Double-sided partially molded sip module

Abstract

A double-sided partially molded SIP module. A semiconductor device has a substrate and a first component disposed above a first surface of the substrate. A connector is disposed above the first surface of the substrate. A first sealant is deposited above the first component, while the connector remains outside the first sealant. A shielding layer is formed above the first sealant, while the connector remains outside the shielding layer. A second component is disposed above a second surface of the substrate. Solder bumps are disposed above the second surface of the substrate. A second sealant is deposited above the second surface of the substrate. An opening is formed through the second sealant to expose the solder bumps. Solder balls are disposed in the openings. The solder balls and solder bumps are reflowed to form a combined solder bump.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to a dual-sided partially molded system-in-a-package (SiP) module and a method of manufacturing the same. BACKGROUND

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic

[0003] One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices generally consume less power, have higher performance, and can be produced more efficiently. Additionally, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end-products. Smaller semiconductor die sizes can be achieved through improvements in front-end processes, resulting in semiconductor dies with smaller, higher-density active and passive components. Back-end processes can result in semiconductor device packages with smaller footprints by improving electrical interconnections and packaging materials.

[0004] System-in-a-package (SiP) modules are a type of semiconductor package that integrates several components in a single package. One method of reducing the footprint of a SiP module is to mount components on both sides of the package substrate. Dual-sided SiP modules allow for more components to be included in a fixed footprint. Market forces are continually pushing SiP modules toward smaller footprints and lower thicknesses. As SiP module sizes are reduced, challenges can arise in packaging components on both sides of the substrate. Accordingly, there is a need for improved dual-sided SiP modules and methods of manufacturing SiP modules that can scale to smaller sizes while maintaining advanced features required by the market. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figures la- lc illustrating a semiconductor wafer having multiple semiconductor dies separated by scribe lanes;

[0006] Figures 2a- 2p illustrating forming a dual-sided SiP module;

[0007] Figures 3a- 3e illustrating an alternative method of forming a dual-sided SiP module; and

[0008] Figure 4a and Figure 4bIntegration of SiP modules into electronic devices is illustrated. DETAILED DESCRIPTION

[0009] In the following description of the drawings, the present application is described in one or more embodiments, wherein like numbers describe similar elements throughout. Although the application is described with reference to the best mode contemplated for carrying out the application's objectives, the application will be appreciated by those of ordinary skill in the art that modifications not only can be practiced but also can be warranted within the spirit and scope of the application, which is defined by the following claims, their full scope intended to embrace any and all equivalents. The term "semiconductor die" as used herein refers to both the singular and the plural of the term and can therefore refer to both a single semiconductor device and multiple semiconductor devices.

[0010] Semiconductor devices are typically fabricated using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form functional electrical circuits. Active electrical components such as transistors and diodes have the ability to control the flow of electrical current. Passive electrical components such as capacitors, inductors, and resistors create a relationship between voltage and current necessary to perform circuit functions.

[0011] Back-end manufacturing refers to the process of cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental protection. To singulate the semiconductor dies, the wafer is scored and broken along non-functional areas of the wafer, known as scribe lines or streets. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed over the semiconductor dies are then connected to contacts within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive adhesive, wirebonds, or other suitable interconnection structures. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, and the functionality of the semiconductor device is made available to other system components.

[0012] Figure laA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material used for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or streets 106. The streets 106 provide cutting regions to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0013] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers and dielectric layers that are formed on the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry can include one or more transistors, diodes and other circuit elements formed within the active surface 110 to implement analog circuits or digital circuits such as digital signal processors (DSPs), power amplifiers, application specific integrated circuits (ASICs), memory or other signal processing circuits. The semiconductor die 104 can also contain IPDs such as inductors, capacitors and resistors for RF signal processing.

[0014] A conductive layer 112 is formed over the active surface 110 using a PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive material. The conductive layer 112 operates as a contact pad electrically connected to the circuitry on the active surface 110.

[0015] A conductive bump material is deposited over the conductive layer 112 using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, combinations thereof, or other suitable conductive material with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable adhesion or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps 114. In one embodiment, the bumps 114 are formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed over the conductive layer 112. The interconnect structure can also use wirebonds, conductive adhesive, stud bumps, micro bumps, or other electrical interconnects.

[0016] In Figure lc The semiconductor wafer 100 is singulated into individual semiconductor dies 104 through the saw lanes 106 using a saw blade or laser cutting tool 118. The individual semiconductor dies 104 can be inspected and electrically tested to identify known good dies (KGD) after singulation.

[0017] Figures 2a- 2p A dual-sided SiP module having semiconductor dies 104 is formed. Figure 2a is a partial cross-sectional view of a panel of SiP devices 150 separated by saw lanes 151 in an early stage of manufacturing. Two SiP devices 150 are illustrated, but hundreds or thousands of SiP devices are typically formed in a single panel using the same steps described herein. A substrate 152 is used as a base to form the SiP modules 150. The substrate 152 includes one or more insulating layers 154 interleaved with one or more conductive layers 156.

[0018] In one embodiment, the insulating layers 154 are core insulating boards with conductive layers 156, such as copper clad laminate substrates, patterned over the top and bottom surfaces. The conductive layers 156 also include conductive vias electrically coupled through the insulating layers 154. The substrate 152 can include any number of conductive and insulating layers interleaved over one another. A solder mask or passivation layer can be formed over either side of the substrate 152. In other embodiments, any suitable type of substrate or leadframe is used for the substrate 152.

[0019] Any components needed to implement the intended functionality of the SiP device 150 are mounted to or disposed above the substrate 152 and electrically connected to the conductive layer 156. The substrate 152 has two major surfaces: a top surface 157 and a bottom surface 159. Components can be mounted to the top surface 157 and the bottom surface 159 in any suitable configuration. In the illustrated embodiment, discrete components 164 (e.g., resistors, capacitors, inductors, transistors, and diodes) are mounted on the top surface 157 using solder paste 166. The solder paste 166 is reflowed between the terminals of the discrete components 164 and contact pads of the conductive layer 156 on the top surface 157. The semiconductor die 104 will be mounted on the bottom surface 159 at a later stage. Alternatively, the semiconductor die 104 or other active components can be mounted on the top surface 157, and discrete components can be mounted on the bottom surface 159 instead of or in addition to the semiconductor die 104.

[0020] In the illustrated embodiment, the semiconductor 104 is a 5G cellular transceiver, and the discrete components 164 form a filter network for millimeter (mm) wave radio frequency (RF) signals used by 5G. A prior art technique for mm-wave 5G is a board-to-board (B2B) connector 170 to ensure signal input and output stability. The B2B connector 170 allows a cable to be connected to the SiP module 150 for direct interconnection with another semiconductor package. After any desired components, including the discrete components 164 and the B2B connector 170, are mounted on the top surface 157, a reflow step is used to melt the solder paste 166 and physically attach the components. A deflux step is optionally used to clean the connections.

[0021] In the fully manufactured SiP module 150, for environmental protection, the discrete components 164 will need to be encapsulated, while the B2B connector 170 will need to be exposed for subsequent connection via a B2B cable. Figure 2b A mold chase 172 is illustrated with a partition for selectively encapsulating the discrete components 164 without covering the B2B connector 170. A mold cavity 174 encloses components to be encapsulated, such as the discrete components 164, and an inlet 175 will allow the mold cavity to be filled with a molding compound. A relief cavity 176 encloses the B2B connector 170. The relief cavity 176 blocks the flow of molding compound onto the B2B connector 170. The walls of the relief cavity 176 substantially seal off the B2B connector 170 from the mold cavity 174, so that the molding compound encapsulates the discrete components 164 without extending to the B2B connector 170.

[0022] Figure 2cThe sealant 180 is shown deposited through inlet 175 to fill mold cavity 174. The sealant 180 flows above, below, and around any component within mold cavity 174. For some components, a separate mold bottom filler may be used to ensure the area between the component and substrate 152 is filled. After filling mold cavity 174 with sealant 180, the sealant is cured if necessary. Any suitable molding process can be used. Sealant 180 can be a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer with or without filler. Sealant 180 is non-conductive, provides structural support, and environmentally protects discrete component 164 from external components and contaminants.

[0023] Figure 2c The illustration shows a cavity package. Other packaging methods are used in other embodiments. As another example, Figure 2d The deposition of sealant 180 is shown via transfer molding using molding groove 182. Inlet 175 is located adjacent to the bottom of substrate 152.

[0024] exist Figure 2e In the process, the molding groove 172 or 182 is removed, leaving a cured sealant 180 above the discrete component 164 in the shape of a molding cavity 174. The B2B connector 170 remains exposed for later use.

[0025] exist Figure 2f In this configuration, the panel of SiP device 150 is flipped so that the bottom surface 159 of substrate 152 is oriented upwards or otherwise made available for processing. The panel can be flipped by transferring it from a first carrier to a second carrier. Semiconductor die 104 is mounted to substrate 152 by using, for example, pick-and-place processes or machines to place the semiconductor die onto the bottom surface 159, and then reflowing the bumps 114 to physically and electrically couple the bumps to the exposed contact pads of conductive layer 156. Solder bumps 184 are formed using any suitable method and any suitable materials, such as those discussed above for bumps 114 on semiconductor die 104. Any other desired electrical components may also be mounted onto the bottom surface 159, such as additional discrete components 164, discrete active components, or integrated circuit dies.

[0026] In one embodiment, after the bumps 184 and die 104 are placed on the bottom surface 159, a reflow step is used to melt the bumps 184 and 114 and physically attach them to the substrate 140. An optional desoldering step cleans the surface.

[0027] exist Figure 2gIn this process, a second sealant 190 is deposited on the bottom surface 159, the semiconductor die 104, and the bump 184 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or another suitable applicator. The sealant 190 can be a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer with or without fillers. The sealant 190 is non-conductive, provides structural support, and environmentally protects the SiP device 150 from external components and contaminants.

[0028] Unlike the top surface 157 with the B2B connector 170, the bottom surface 159 is completely covered by sealant. The sealant 190 deposited above the bottom surface 159 is higher than the back surface 108 of the semiconductor die 104 and also higher than the height of the bump 184 above the bottom surface 159. The back surface 108 of the semiconductor die 104 is covered by sealant 190. The bump 184 is also completely covered by sealant 190.

[0029] exist Figure 2h In this process, a polishing mill 192 is used to planarize the sealant 190 to a desired thickness. The polishing mill 192 removes material from the sealant 190 to reduce its thickness. Optionally, the sealant 190 is thinned until the semiconductor die 104 is exposed. A portion of the semiconductor die 104 may be removed during the planarization process to ensure that the back face 108 of the die is coplanar with the back face of the sealant 190. The bumps 184 remain covered by the sealant 190.

[0030] exist Figure 2i In this embodiment, a laser 194 is used to drill through the sealant 190 to form an opening 196 exposing the bump 184. The laser 194 emits energy as a laser beam that removes material from the sealant 190 wherever it hits the sealant. The laser 194 is mounted to a jig and moves individually over each bump 184 to expose each corresponding bump. In other embodiments, multiple lasers 194 are used in parallel. An opening 196 is formed for each bump 184. In some embodiments, the opening 196 is formed using chemical etching, mechanical drilling, or another suitable means instead of using a laser 194.

[0031] exist Figure 2j In this configuration, solder balls 198 are positioned into openings 196 on bumps 184. The balls 198 may contact the bumps 184 or be held above the bumps 184 by the sidewalls of the openings 196. Any suitable drop or placement mechanism is used to position the balls 198. Each opening 196 has solder balls 198 placed thereon, stacked on or above the corresponding solder bumps 184.

[0032] Figure 2kSolder balls 198 and solder bumps 184 reflowed into a combined solder bump 200 are shown. The solder bump 200 includes solder material for solder bumps 184 and solder balls 198, which are melted into a single piece of solder by heating the solder material to a temperature above the solder melting point. The solder bump 200 comprises a continuous solder structure with a uniform material composition extending from the contact pads of the conductive layer 156 on the bottom surface 159 to the opposing surface of the sealant 190. The bump 200 extends completely through the thickness of the sealant 190. After the bumps 184 and balls 198 are reflowed into the bump 200, an optional desoldering step is performed. A saw blade or laser cutting tool 204 is used along... Figure 21 The saw groove 151 in the middle separates the panel of the SiP module 150 into individual modules to separate the individual modules from each other.

[0033] Figures 2m- 2p A shielding layer is shown formed over the sealant 180. Optionally, the panel may be flipped before or after monomerization to provide access to the upper sealant 180. Alternatively, the shielding layer may be formed as illustrated, but before processing the bottom surface 159 to reduce the number of times the panel is flipped during manufacturing.

[0034] exist Figure 2m In this configuration, a can 210 is disposed on the B2B connector 170 to protect the B2B connector during shielding formation. The can 210 contacts the top surface 157 surrounding the B2B connector 170 to prevent sputtered metal from creating an electrical connection to the B2B connector.

[0035] Figure 2n An alternative to can 210 is shown. The SiP module 150 is disposed over an opening in the thin-film carrier 214, for example, using a pick-and-place process or machine. The SiP module 150 is positioned such that the edge of the SiP module is on the thin-film carrier 214, and solder bumps 200 are within the opening. In other embodiments, bumps 200 may be placed on the thin-film carrier 214. A mask 216 is placed over the end of the SiP module 150 to cover the B2B connector 170. The mask 216 rests on the thin-film carrier 216 surrounding the SiP module 150. The thin-film carrier 216 may include an adhesive to hold the SiP module 150 and the mask 216 in place. The sides of the mask 216, oriented towards the corresponding sealant 180, are shorter to form a lip extending over the substrate 152 between the sealant and the B2B connector 170.

[0036] With the can 210 or mask 216 in place above the B2B connector 170, the shielding layer 212 is formed on Figure 20The upper sealant 180 is placed above the can 210. A shielding layer 212 is conformally formed above the SiP device 150 and completely covers the top and sides of the sealant 180 and the can 210. The shielding layer 212 may physically contact the conductive layer 156 exposed on the sides of the substrate 152 to ground the shielding layer. The shielding layer 212 is formed by spraying, electroplating, sputtering, or any other suitable metal deposition process. The shielding layer 212 may be formed of copper, aluminum, iron, or any other material suitable for EMI shielding. A gap is typically maintained between the shielding layer 212 and the sealant 180 on the can 210 to facilitate subsequent removal of the can.

[0037] In some embodiments, Figure 21 During the monomerization process, the SiP module 150 is disposed on a carrier having an optional heat release or interface layer. The monomerized SiP devices 150 are held on the same carrier for the application of the shielding layer 212. Therefore, during the formation of the shielding layer 212, the space between adjacent SiP devices 150 is equal to the width of the kerf of the cutting tool 204. The thickness of the shielding layer 212 is low enough that the shielding layers of adjacent SiP devices 150 do not contact each other and remain monomerized while encapsulated on the carrier. In other embodiments, the SiP devices 150 are disposed on separate carriers after monomerization and before the formation of the shielding layer 212.

[0038] exist Figure 2p In the process, can 210 or mask 216, along with a portion of shielding layer 212 formed on can or mask, is removed. Shielding layer 212 retains complete coverage of each exposed surface of sealant 180, including the top surface and all four sides. In forming shielding layer 212, all exposed surfaces of sealant 180 are coated with a conductive material. Shielding layer 212 is not formed on B2B connector 170 to leave the connector exposed for subsequent use.

[0039] Figure 2p The SiP module 150 is a completed unit, ready to be packaged and delivered to customers who will integrate the SiP module into larger electronic devices. The SiP module 150 includes a semiconductor die 104, discrete components 164, and any other desired electrical components packaged on two opposing surfaces of a substrate 152. For environmental protection, components on both the top surface 157 and the bottom surface 159 are encapsulated. Components on the top surface 157 are shielded by a shielding layer 212 around the sides and top surface of a sealant 180. Other components on the semiconductor die 104 and the bottom surface 159 also benefit from the shielding layer 212, although the bottom components are not as tightly surrounded by the shielding layer as the discrete components 164.

[0040] B2B connector 170 remains exposed from and outside both sealant 180 and shielding layer 212 for high-speed signal input and output (I / O). Bump 200 also remains exposed for mounting SiP module 150 to a larger substrate and for additional system integration. In a typical scenario, B2B connector 170 is used to transmit high-bandwidth data signals between SiP module 150 and another component, while bump 200 is used to provide power, debug outputs, and other slower data I / O. Bump 200 also provides mechanical connection to the underlying system substrate by reflowing solder material onto the contact pads.

[0041] Figures 3a- 3e An alternative process flow for forming a SiP module 250 with double-sided encapsulation, shielding, and exposure of B2B connectors is shown. Figure 3a In order to be in with Figure 2e The panel begins in a similar state as shown, except that the B2B connector 170 has not yet been mounted onto the substrate 152. Instead, the contact pads 252 are left exposed for later mounting of the B2B connector 170. The molding of the sealant 180 can be done using... Figures 2b- 2d The same molding groove 172 or 182 can be used, or a different mold without the pressure relief cavity 176 can be used. The mold can be solid, instead of having a cavity for the B2B connector 170.

[0042] Figure 3b The diagram illustrates the execution from above. Figures 2f- 2k Following the steps, the SiP module 250 is provided with bumps 200 extending through sealant 190 for mounting to the system substrate. Figure 3c In this configuration, the SiP module 250 is flipped and monolithized via sawtooth 251. A shielding layer 260 is formed above the SiP module 250 in a manner similar to the shielding layer 212 above. The shielding layer 260 is formed to completely cover all top and side surfaces of the sealant 180 and the substrate 152, including the contact pads 252 not covered by the sealant 180.

[0043] exist Figure 3d In this embodiment, laser 262 is used to remove shielding layer 260 from above contact pad 252. In one embodiment, a portion of shielding layer 260 is removed by sputtering stripping via laser ablation. In other embodiments, other types of etching (e.g., chemical or mechanical etching) are used to remove shielding layer 260 from above contact pad 250. Figure 3e In this process, the B2B connector 170 is picked up and placed on the contact pad 252 to electrically connect the B2B connector to the semiconductor die 104, discrete component 164, and any other electrical components mounted on the substrate 152.

[0044] Figure 4aand Figure 4b The illustration shows the integration of the aforementioned SiP module (e.g., SiP module 250 with shielding layer 260) into electronic device 300. Figure 4a The illustration shows a partial cross-section of a SiP module 250 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. Bumps 200 flow back to a conductive layer 304 of the PCB 302 to physically attach and electrically connect the SiP module 250 to the PCB. In other embodiments, thermoforming or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the SiP module 250 and the PCB 302. A semiconductor die 104 is electrically coupled to the conductive layer 304 via a substrate 152 and bumps 200.

[0045] Figure 4b The illustration shows an electronic device 300 including a PCB 302, wherein multiple semiconductor packages are mounted on the surface of the PCB, including a SiP module 250 with a shielding layer 260 and a B2B connector 170. A ribbon cable 312 with a connector 310 is inserted into the B2B connector 170 to electrically couple another device to a component in the SiP module 250. The connector 310 is configured to mate with the B2B connector 170 such that the ribbon cable 312 can conduct electrical signals to and from the SiP module 250. The ribbon cable 312 can be used to connect the SiP module 250 to the PCB 302, another package on the PCB 302, another PCB of the same or different electronic devices, another package on another PCB, another electronic device, test equipment, etc. Other types of cables or conductors, such as coaxial cables or twisted-pair cables, can be used instead of the ribbon cable. The ribbon cable 312 is connected to the semiconductor die 104 and discrete component 164 through a substrate 152.

[0046] Depending on the application, electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages. Electronic device 300 may be a standalone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 300 may be a sub-component of a larger system. For example, electronic device 300 may be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device 300 may also be a graphics card, network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor dies or electrical components.

[0047] exist Figure 4bIn this design, PCB 302 provides a universal substrate for the structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. Trace 304 also provides power and ground connections to the semiconductor package as needed.

[0048] In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to a PCB 302. In other embodiments, the semiconductor device may have only a first-level package, where the die is mechanically and electrically mounted directly to the PCB 302.

[0049] For illustrative purposes, several types of first-level packages, including wire bond packages 346 and flip chips 348, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, connection pad grid array (LGA) 356, multi-chip module (MCM) 358, quad flat no-lead package (QFN) 360, quad flat package 362, and embedded wafer-level ball grid array (eWLB) 364, are shown mounted on PCB 302 together with SiP module 250. Conductive traces 304 electrically couple the various packages and components disposed on PCB 302 to SiP module 250, thereby providing access to components within SiP module 250 to other components on the PCB.

[0050] Depending on system requirements, any combination of semiconductor packages configured with any combination of first and second-level packaging styles, along with other electronic components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can integrate prefabricated components into electronic devices and systems. Because semiconductor packages incorporate complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0051] While one or more embodiments of the invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations can be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a substrate; disposing a first component and a B2B connector over a first surface of the substrate; depositing a first encapsulant over the first component while the B2B connector remains outside of the first encapsulant; forming a solder bump on a second surface of the substrate opposite the first surface; disposing a semiconductor die on the second surface of the substrate; depositing a second encapsulant over the solder bump and semiconductor die, over the second surface of the substrate; backgrinding the second encapsulant until the semiconductor die is exposed from the second encapsulant, wherein the second encapsulant remains fully covering the solder bump after backgrinding; drilling an opening into the second encapsulant to expose the solder bump after backgrinding; disposing a solder ball in the opening; and heating the solder bump and solder ball to reflow the solder bump and solder ball into a combined solder bump; disposing the substrate over a thin film carrier, wherein the second encapsulant is oriented toward the thin film carrier; disposing a mask over the B2B connector, wherein the mask rests on the thin film carrier, and wherein a side of the mask oriented toward the first encapsulant includes a lip extending over the substrate between the encapsulant and the B2B connector; forming a shield layer over the first encapsulant and mask while the substrate remains over the thin film carrier; and removing the mask after forming the shield layer.

2. The method of claim 1, further comprising depositing the first encapsulant into a mold cavity, wherein the first component is within the mold cavity and the B2B connector is outside of the mold cavity.

3. The method of claim 1, further comprising: disposing a third component on the second surface of the substrate; and depositing the second encapsulant over the third component.

4. A method of manufacturing a semiconductor device, comprising: providing a substrate; disposing a first component over a first surface of the substrate; disposing a B2B connector over the first surface of the substrate; depositing a first encapsulant over the first component; forming a shield layer over the first encapsulant; disposing a solder bump over a second surface of the substrate opposite the first surface; depositing a second encapsulant over the second surface of the substrate; forming a first opening through the second encapsulant to expose the solder bump; disposing a solder ball in the first opening; reflowing the solder ball and solder bump into a combined solder bump; disposing the substrate on a thin film carrier, wherein the thin film carrier includes a second opening and the combined solder bump extends into the second opening; disposing a mask over the B2B connector, wherein the mask rests on the thin film carrier; forming a shield layer over the first encapsulant and mask while the substrate remains on the thin film carrier; and removing the mask after forming the shield layer.

5. The method of claim 4, further comprising disposing a semiconductor die over the second surface of the substrate.

6. The method of claim 4, further comprising leaving the B2B connector and a portion of the substrate exposed from the first encapsulant and shield layer. ​ ​ 7. The method of claim 4, wherein removing the mask removes a portion of the shield layer to expose a portion of the substrate.

8. A method of manufacturing a semiconductor device, comprising: providing a substrate; disposing a first component over a first surface of the substrate; disposing a B2B connector over the first surface of the substrate; depositing a first encapsulant over the first component; disposing a solder bump over a second surface of the substrate; depositing a second encapsulant over the solder bump; backgrinding the second encapsulant without exposing the solder bump; after backgrinding, forming an opening by drilling through the second encapsulant to expose the solder bump; disposing a solder ball in the opening; reflowing the solder ball and the solder bump into a combined solder bump; disposing the substrate over a film carrier, wherein the second encapsulant is oriented toward the film carrier; disposing a mask over the B2B connector, wherein the mask rests on the film carrier; forming a shield layer over the first encapsulant and the mask while the substrate remains over the film carrier; and removing the mask after forming the shield layer.

9. The method of claim 8, further comprising disposing a can or mask over the B2B connector while forming the shield layer.

10. The method of claim 8, further comprising leaving a portion of the substrate exposed from the first encapsulant and shield layer.

11. The method of claim 8, further comprising disposing a semiconductor die over the second surface of the substrate.

12. A method of manufacturing a semiconductor device, comprising: providing a substrate; disposing a first component over a first surface of the substrate; disposing a B2B connector over the first surface of the substrate; depositing a first encapsulant over the first component while the B2B connector remains outside of the first encapsulant; disposing a second component over a second surface of the substrate; disposing a solder bump over the second surface of the substrate; depositing a second encapsulant over the second surface of the substrate; forming a first opening through the second encapsulant to expose the solder bump; disposing a solder ball in the first opening; reflowing the solder ball and the solder bump to form a combined solder bump; disposing the substrate over a film carrier, wherein the film carrier includes a second opening and the combined solder bump extends into the second opening; disposing a can or mask over the B2B connector, wherein the can or mask rests on the film carrier and there is a gap between a top of the B2B connector and a top of the can or mask; forming a shield layer over the first encapsulant and the can or mask while the substrate remains on the film carrier; and removing the can or mask after forming the shield layer.

13. The method of claim 12, wherein removing the can or mask removes the entire can or mask.

14. The method of claim 12, further comprising depositing the first encapsulant into a mold cavity, wherein the first component is within the mold cavity and the B2B connector is outside of the mold cavity. ​

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