A highly robust asymmetric bidirectional thyristor electrostatic protection device and its manufacturing method

Abstract

The present invention provides a highly robust asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof, comprising a P-type substrate, an N-type deep well, an N-type well, a P-type well, etc.; a first N-well and a second P+ injection region, a second N-well and a fifth P+ injection region, wherein the device triggering voltage is reduced by highly doped P+ injection and N-well avalanche breakdown; two electrodes of the first P+ injection region and the third N+ injection region are connected together to serve as the cathode of the device; four electrodes of the first N+ injection region, the third P+ injection region, the second N+ injection region, and the fourth P+ injection region are connected together to serve as the anode of the device; while reducing the device triggering voltage, the device utilizes different electrostatic discharge (ESD) discharge paths to achieve bidirectional protection of I / O ports, thereby effectively protecting the chip I / O signal ports that transmit positive and negative levels; the device has the characteristics of low triggering voltage and high failure current, and can be applied to bidirectional ESD protection of I / O ports.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection, and in particular to a highly robust asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing processes and the continuous reduction in device size, electrostatic discharge (ESD) has led to increasingly serious failures in integrated circuit chips and electronic products. According to relevant statistics, the annual losses caused by ESD in the microelectronics field amount to approximately $10 billion. This data highlights the necessity of ESD protection measures for integrated circuit chips and electronic products.

[0003] Compared to other ESD devices, traditional silicon controlled rectifiers (SCRs) offer advantages such as high current discharge capability per unit area and low parasitic capacitance. However, these devices suffer from disadvantages such as excessively high trigger voltages and low holding voltages after the device is triggered. Excessively high trigger voltages prevent the device from promptly protecting the core circuit, while low holding voltages can cause latch-up, rendering the ESD protection device inoperable and unable to guarantee the integrity of signals transmitted through I / O ports.

[0004] Asymmetric bidirectional thyristor devices are improved on the basis of traditional thyristors. They have an asymmetric structural layout. Their working principle is the same as that of traditional unidirectional thyristors. Asymmetric bidirectional thyristors can discharge ESD current from two directions. Figure 1 , its equivalent circuit diagram is shown in Figure 2. When an ESD pulse is applied to the anode of the bidirectional SCR, the N-type deep well and the second P-well form a reverse-biased PN junction. When the ESD pulse voltage is higher than the reverse-biased PN junction avalanche breakdown voltage, the device will generate an avalanche breakdown current, which flows through the second P-well parasitic resistance Rp2. When the voltage across Rp2 is higher than the forward conduction voltage of the vertical NPN transistor, the vertical NPN transistor turns on. After the vertical NPN transistor turns on, it provides base current to the lateral PNP transistor, causing the lateral PNP transistor to turn on. The two transistors provide base current to each other and promote each other to form a positive feedback loop. When the two transistors are fully turned on, they form an SCR path to discharge the ESD current. The bidirectional SCR has a symmetrical structure. When an ESD pulse is applied to the cathode, the N-type deep well and the first P-well form a reverse-biased PN junction avalanche breakdown, causing the PNP transistor and the NPN transistor to turn on successively to discharge static electricity. However, traditional SCRs have the disadvantages of high trigger voltage and low holding voltage. A high trigger voltage will cause the device to fail to meet the design window requirements, and a low holding voltage is prone to latch-up effect. Therefore, it is necessary to lower the trigger voltage to ensure that the device can promptly turn on the protection core circuit when ESD current arrives, and at the same time increase the holding voltage of the bidirectional thyristor to avoid latch-up effect. Summary of the Invention

[0005] In order to solve the above technical problems, the present invention provides a highly robust asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof, and is applied to the ESD protection design of I / O ports with an operating voltage of 0 to 5.5V.

[0006] The invention provides a simple-structured, highly robust asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof.

[0007] To achieve the above-mentioned purpose, the technical solution of the embodiment of the present invention is implemented as follows:

[0008] The present invention provides a highly robust asymmetric bidirectional thyristor electrostatic protection device, comprising a P-type substrate; an N-type deep well is provided in the P-type substrate; a first N-well, a first P-well, a second N-well, and a second P-well are provided above the N-type deep well from left to right; a first P+ injection region is provided in the first N-well; a first N+ injection region and a third P+ injection region are provided in the first P-well; a second N+ injection region and a fourth P+ injection region are provided in the second N-well; a third N+ injection region is provided in the second P-well; a second P+ injection region is provided between the first N-well and the first P-well; a fifth P+ injection region is provided between the second N-well and the second P-well; two electrodes of the first P+ injection region and the third N+ injection region are connected together as the cathode of the device, and four electrodes of the first N+ injection region, the third P+ injection region, the second N+ injection region, and the fourth P+ injection region are connected together as the anode of the device.

[0009] Preferably, a first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type substrate; a second field oxygen isolation region is provided between the right side of the first P+ injection region and the left side of the second P+ injection region; a third field oxygen isolation region is provided between the right side of the second P+ injection region and the left side of the first N+ injection region; a fourth field oxygen isolation region is provided between the right side of the first N+ injection region and the left side of the third P+ injection region; a fifth field oxygen isolation region is provided between the right side of the third P+ injection region and the left side of the second N+ injection region; a sixth field oxygen isolation region is provided between the right side of the second N+ injection region and the left side of the fourth P+ injection region; a seventh field oxygen isolation region is provided between the right side of the fourth P+ injection region and the left side of the fifth P+ injection region; an eighth field oxygen isolation region is provided between the right side of the fifth P+ injection region and the left side of the third N+ injection region; and a ninth field oxygen isolation region is provided between the right side of the third N+ injection region and the right edge of the P-type substrate.

[0010] Preferably, the first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region and the fourth field oxygen isolation region are located on the surface of the first P-well; the left side of the fifth field oxygen isolation region is located on the surface of the first P-well, and the right side of the fifth field oxygen isolation region is located on the surface of the second N-well; the sixth field oxygen isolation region and the seventh field oxygen isolation region are located on the surface of the second N-well; and the eighth field oxygen isolation region and the ninth field oxygen isolation region are located on the surface of the second P-well.

[0011] Preferably, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the fourth P+ injection region, the second N-well, and the second P-well form a PNP-type transistor, and the second N-well, the second P-well, and the third N+ injection region form an NPN-type transistor. When the parasitic PNP and parasitic NPN are turned on, a forward SCR path is formed. When a high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the first P+ injection region, the first N-well, and the first P-type well form a PNP-type transistor, and the first N-well, the first P-well, and the first N+ injection region form an NPN-type transistor. When the parasitic PNP and parasitic NPN are turned on, a reverse SCR path is formed.

[0012] Preferably, when a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection region into the second N-well, the second P-well, and the third N+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the fifth P+ injection region and the second N-well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second N-well. When the voltage drop on the equivalent resistance reaches 0.7V, the longitudinal PNP transistor is turned on and the base current is provided to the lateral NPN transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the forward SCR path is successfully opened. When a high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the first P+ injection region into the first N-well, the first P-well, and the first N+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the second P+ injection region and the first N-well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P-well. When the voltage drop on the equivalent resistance reaches 0.7V, the lateral NPN transistor is turned on and the base current is provided to the vertical PNP transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the reverse SCR path is successfully opened.

[0013] The present invention provides a method for manufacturing a highly robust asymmetric bidirectional thyristor electrostatic protection device, the method comprising:

[0014] Step 1: forming an N-type deep well in a P-type substrate;

[0015] Step 2: Generating a first N-well, a first P-well, a second N-well, and a second P-well above the N-type deep well;

[0016] Step 3: forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, and a ninth field oxygen isolation region in the P-type substrate from left to right;

[0017] Step 4: forming a first P+ injection region in the first N-well from left to right, forming a first N+ injection region and a third P+ injection region in the first P-well from left to right, and forming a second P+ injection region between the contact surface of the first N-well and the first P-well, forming a second N+ injection region and a fourth P+ injection region in the second N-well from left to right, forming a third N+ injection region in the second P-well from left to right, and forming a fifth P+ injection region between the contact surface of the second N-well and the second P-well; and the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ injection region, the right side of the first P+ injection region contacts the left side of the second field oxygen isolation region, the right side of the second field oxygen isolation region contacts the left side of the second P+ injection region, the right side of the second P+ injection region contacts the left side of the third field oxygen isolation region; the right side of the third field oxygen isolation region contacts the left side of the The left side of the first N+ implant region is in contact with the right side of the first N+ implant region, the right side of the fourth field oxygen isolation region is in contact with the left side of the third P+ implant region, the right side of the third P+ implant region is in contact with the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region is in contact with the left side of the second N+ implant region, the right side of the second N+ implant region is in contact with the left side of the sixth field oxygen isolation region, the right side of the sixth field oxygen isolation region is in contact with the left side of the fourth P+ implant region, the right side of the fourth P+ implant region is in contact with the left side of the seventh field oxygen isolation region, the right side of the seventh field oxygen isolation region is in contact with the left side of the fifth P+ implant region, the right side of the fifth P+ implant region is in contact with the left side of the eighth field oxygen isolation region, the right side of the eighth field oxygen isolation region is in contact with the left side of the third N+ implant region, the right side of the third N+ implant region is in contact with the left side of the ninth field oxygen isolation region, and the right side of the ninth field oxygen isolation region is in contact with the right edge of the P-type substrate;

[0018] Step 5: Annealing the first P+ implantation region, the second P+ implantation region, the first N+ implantation region, the third P+ implantation region, the second N+ implantation region, the fourth P+ implantation region, the fifth P+ implantation region, and the third N+ implantation region to eliminate impurity migration in the implantation region;

[0019] Step six: Connect the first N+ injection region, the third P+ injection region, the second N+ injection region, and the fourth P+ injection region together as the anode of the device, and connect the first P+ injection region and the third N+ injection region together as the cathode of the device.

[0020] Preferably, the method further comprises:

[0021] A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, and a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

[0022] The present invention provides a highly robust asymmetric bidirectional thyristor electrostatic protection device and a manufacturing method thereof, which has the following beneficial effects:

[0023] 1. The present invention can reduce the trigger voltage and increase the holding voltage by modifying the device process hierarchy without increasing the device layout area. When an ESD current is applied to the cathode, the first N-well connects to the second P+ injection region, forming an additional conductive path. This conductive path passes through the first P+ injection region, the first N-well, the second P+ injection region, the first P-well, and the first N+ injection region, shunting the main path of the first P+ injection region, the first N-well, the first P-well, and the first N+ injection region to increase the reverse holding voltage. The reverse PN junction formed by the first N-well and the second P+ injection region has a low breakdown voltage, and this structural design can effectively reduce the reverse device trigger voltage. When an ESD current is applied to the anode, the second N-well connects to the fifth P+ injection region, forming an additional conductive path. This conductive path passes through the fourth P+ injection region, the second N-well, the fifth P+ injection region, the second P-well, and the third N+ injection region, shunting the main path of the fourth P+ injection region, the second N-well, the second P-well, and the third N+ injection region to increase the forward holding voltage. The reverse PN junction formed by the second N well and the fifth P+ injection region has a relatively low breakdown voltage. This structural design can effectively reduce the forward trigger voltage of the device.

[0024] 2. The sizes of the first P-well and the second P-well of the present invention are adjustable to increase the distance between the anode and cathode of the device, which can extend the effective length of the discharge current path of the ESD current and thereby increase its equivalent resistance, thereby improving the holding voltage of the device. The N-type deep well can completely isolate the main structure of the thyristor from the P-type substrate, effectively improving the device's anti-leakage capability.

[0025] 3. The size S2 of the first P+ injection region and the fourth P+ injection region in the first N-well and the second N-well of the present invention is adjustable. When S2 is increased, the parasitic PNP tube gain is increased, the positive feedback link is strengthened, and the failure current is improved. Therefore, the failure current of the device will increase with the increase of the size S2. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a cross-sectional view of a currently known bidirectional SCR electrostatic protection device;

[0027] Figure 2This is the equivalent circuit diagram of the currently known bidirectional SCR electrostatic protection device;

[0028] Figure 3 A cross-sectional view of the highly robust asymmetric bidirectional thyristor electrostatic protection device provided by the present invention;

[0029] Figure 4 The equivalent circuit diagram of the highly robust asymmetric bidirectional thyristor electrostatic protection device provided by the present invention;

[0030] Figure 5 This is a simulation diagram of the total current density distribution of the highly robust asymmetric bidirectional thyristor electrostatic protection device provided by the present invention. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0033] like Figure 3 As shown, a highly robust asymmetric bidirectional thyristor electrostatic protection device includes a P-type substrate 101; an N-type deep well 201 is provided in the P-type substrate 101; a first N-well 301, a first P-well 401, a second N-well 302, and a second P-well 402 are provided above the N-type deep well 201 from left to right; a first P+ injection region 501 is provided in the first N-well 301; a first N+ injection region 503 and a third P+ injection region 504 are provided in the first P-well 401; a second N+ injection region 505 and a fourth P+ injection region 506 are provided in the second N-well 302; A third N+ injection region 508 is provided in the second P-well 402; a second P+ injection region 502 is provided between the first N-well 301 and the first P-well 401; a fifth P+ injection region 507 is provided between the second N-well 302 and the second P-well 402; the two electrodes of the first P+ injection region 501 and the third N+ injection region 508 are connected together as the cathode of the device, and the four electrodes of the first N+ injection region 503, the third P+ injection region 504, the second N+ injection region 505 and the fourth P+ injection region 506 are connected together as the anode of the device.

[0034] In one embodiment, a first field oxygen isolation region 601 is provided between the left side of the first P+ injection region 501 and the left edge of the P-type substrate 101; a second field oxygen isolation region 602 is provided between the right side of the first P+ injection region 501 and the left side of the second P+ injection region 502; a third field oxygen isolation region 603 is provided between the right side of the second P+ injection region 502 and the left side of the first N+ injection region 503; a fourth field oxygen isolation region 604 is provided between the right side of the first N+ injection region 503 and the left side of the third P+ injection region 504; a fourth field oxygen isolation region 604 is provided between the right side of the third P+ injection region 504 and the left side of the A fifth field oxygen isolation region 605 is provided on the left side of the second N+ injection region 505; a sixth field oxygen isolation region 606 is provided on the right side of the second N+ injection region 505 and on the left side of the fourth P+ injection region 506; a seventh field oxygen isolation region 607 is provided on the right side of the fourth P+ injection region 506 and on the left side of the fifth P+ injection region 507; an eighth field oxygen isolation region 608 is provided on the right side of the fifth P+ injection region 507 and on the left side of the third N+ injection region 508; and a ninth field oxygen isolation region 609 is provided between the right side of the third N+ injection region 508 and the right edge of the P-type substrate 101.

[0035] In one embodiment, the first field oxygen isolation region 601 and the second field oxygen isolation region 602 are located on the surface of the first N-well 301; the third field oxygen isolation region 603 and the fourth field oxygen isolation region 604 are located on the surface of the first P-well 401; the left side of the fifth field oxygen isolation region 605 is located on the surface of the first P-well 401, and the right side of the fifth field oxygen isolation region 605 is located on the surface of the second N-well 302; the sixth field oxygen isolation region 606 and the seventh field oxygen isolation region 607 are located on the surface of the second N-well 302; the eighth field oxygen isolation region 608 and the ninth field oxygen isolation region 609 are located on the surface of the second P-well 402.

[0036] In one embodiment, if Figure 3 As shown, when a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the fourth P+ injection region 506, the second N-well 302, and the second P-type well 402 form a PNP transistor, and the second N-well 302, the second P-well 402, and the third N+ injection region 508 form an NPN transistor. When the parasitic PNP and parasitic NPN are turned on, a forward SCR path is formed. When a high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the first P+ injection region 501, the first N-well 301, and the first P-well 401 form a PNP transistor, and the first N-well 301, the first P-well 401, and the first N+ injection region 503 form an NPN transistor. When the parasitic PNP and parasitic NPN are turned on, a reverse SCR path is formed.

[0037] When a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection region 506 into the second N-well 302, the second P-well 402, and the third N+ injection region 508. When the ESD current increases to a certain value, the reverse PN junction composed of the fifth P+ injection region 507 and the second N-well 302 undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second N-well 302. The equivalent circuit diagram shows Figure 4 It can be seen that when the equivalent resistance R n When the voltage drop reaches 0.7V, the vertical PNP transistor is turned on and the base current is provided to the lateral NPN transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the forward SCR path performs electrostatic discharge. When the high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the first P+ injection region 501 into the first N well 301, the first P well 401, and the first N+ injection region 503. When the ESD current increases to a certain value, the reverse PN junction composed of the second P+ injection region 502 and the first N well 301 undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P well 401. The equivalent circuit Figure 4 It can be seen that when the equivalent resistance R P When the voltage drop reaches 0.7V, the lateral NPN transistor is turned on and provides base current to the vertical PNP transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the reverse SCR path is used for electrostatic discharge.

[0038] Compared with the traditional bidirectional symmetrical thyristor electrostatic protection device, the present device changes the traditional symmetrical bidirectional thyristor device path. The reverse biased PN junction composed of the fifth P+ injection region 507 and the second N well 302, the second P+ injection region 502 and the first N well 301 enables the device to have a lower trigger voltage. At the same time, the present device has an additional discharge path, which is simulated by the total current density distribution of the device. Figure 5 It can be seen that the current density distribution below the second P+ injection region 502 and the fifth P+ injection region 506 is the densest, indicating that this path is the main discharge path. At the same time, the current is also relatively dense in the N-type deep well 201, indicating that this discharge path is a secondary discharge path. This discharge path can guide the current to flow deep into the device, and can effectively improve the device's holding voltage and failure current.

[0039] The first P-well 401 and the second P-well 402 can increase the distance between the anode and cathode of the device, which can effectively improve the holding voltage of the device. The N-type deep well 201 can completely isolate the main structure of the thyristor from the P-type substrate 101, effectively improving the device's anti-leakage capability.

[0040] The size S2 of the first P+ injection region 501 and the fourth P+ injection region 506 in the first N-well 301 and the second N-well 302 is adjustable. When S2 is increased, the parasitic PNP tube gain is increased, the positive feedback link is strengthened, and the failure current is improved. Therefore, the failure current of the device will increase with the increase of the size S2.

[0041] The embodiment of the present invention further provides a method for manufacturing a highly robust asymmetric bidirectional thyristor electrostatic protection device, comprising the following steps:

[0042] Step 1: forming an N-type deep well 201 in a P-type substrate 101;

[0043] Step 2: forming a first N-well 301, a first P-well 401, a second N-well 302, and a second P-well 402 above the N-type deep well 201;

[0044] Step 3: forming a first field oxygen isolation region 601, a second field oxygen isolation region 602, a third field oxygen isolation region 603, a fourth field oxygen isolation region 604, a fifth field oxygen isolation region 605, a sixth field oxygen isolation region 606, a seventh field oxygen isolation region 607, an eighth field oxygen isolation region 608, and a ninth field oxygen isolation region 609 in the P-type substrate 101 from left to right;

[0045] Step 4: Form a first P+ injection region 501 in the first N-well 301 from left to right, form a first N+ injection region 503 and a third P+ injection region 504 in the first P-well 401 from left to right, and simultaneously form a second P+ injection region 502 between the contact surface of the first N-well 301 and the first P-well 401, form a second N+ injection region 505 and a fourth P+ injection region 506 in the second N-well 302 from left to right, and form a third N+ injection region 508 in the second P-well 402 from left to right, and simultaneously form a second N+ injection region 506 between the second N-well 302 and the first P-well 401. A fifth P+ injection region 507 is formed between the contact surfaces of the second P well 402; and the left side of the first field oxygen isolation region 601 contacts the left edge of the P-type substrate 101, the right side of the first field oxygen isolation region 601 contacts the left side of the first P+ injection region 501, the right side of the first P+ injection region 501 contacts the left side of the second field oxygen isolation region 602, the right side of the second field oxygen isolation region 602 contacts the left side of the second P+ injection region 502, the right side of the second P+ injection region 502 contacts the left side of the third field oxygen isolation region 603; the right side of the third field oxygen isolation region 603 The left side of the first N+ implantation region 503 is in contact with the right side of the first N+ implantation region 503, the left side of the fourth field oxygen isolation region 604 is in contact with the right side of the fourth field oxygen isolation region 604, the left side of the third P+ implantation region 504 is in contact with the right side of the third P+ implantation region 504, the left side of the fifth field oxygen isolation region 605 is in contact with the right side of the fifth field oxygen isolation region 605, the left side of the second N+ implantation region 505 is in contact with the right side of the sixth field oxygen isolation region 606, and the right side of the sixth field oxygen isolation region 606 is in contact with the left side of the fourth P+ implantation region 504. The left side of the fourth P+ implantation region 506 is in contact with the left side of the seventh field oxygen isolation region 607, the right side of the seventh field oxygen isolation region 607 is in contact with the left side of the fifth P+ implantation region 507, the right side of the fifth P+ implantation region 507 is in contact with the left side of the eighth field oxygen isolation region 608, the right side of the eighth field oxygen isolation region 608 is in contact with the left side of the third N+ implantation region 508, the right side of the third N+ implantation region 508 is in contact with the left side of the ninth field oxygen isolation region 609, and the right side of the ninth field oxygen isolation region 609 is in contact with the right edge of the P-type substrate 101;

[0046] Step 5: Annealing the first P+ implantation region 501, the second P+ implantation region 502, the first N+ implantation region 503, the third P+ implantation region 504, the second N+ implantation region 505, the fourth P+ implantation region 506, the fifth P+ implantation region 507, and the third N+ implantation region 508 to eliminate impurity migration in the implantation regions;

[0047] Step six: Connect the first N+ injection region 503, the third P+ injection region 504, the second N+ injection region 505, and the fourth P+ injection region 506 together as the anode of the device, and connect the first P+ injection region 501 and the third N+ injection region 508 together as the cathode of the device.

[0048] Optionally, the method further includes:

[0049] A silicon dioxide film is grown on the P-type substrate 101, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, and a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

[0050] The manufacturing method of the highly robust asymmetric bidirectional thyristor electrostatic protection device of the present invention is simple in process and easy to operate. The asymmetric bidirectional thyristor electrostatic protection device structure produced has a reverse avalanche breakdown surface with a lower breakdown voltage, which can effectively reduce the triggering voltage of the device. At the same time, this design enables the device to have an additional ESD current discharge path, which can effectively increase the device holding voltage. This device can be used in the ESD protection design of I / O ports with a voltage of 0 to 5.5V, and can effectively protect the internal chip from the risk of latch-up. The example device of the present invention adopts a 0.25μm BCDMOS process.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A highly robust asymmetric bidirectional thyristor electrostatic protection device, characterized in that: It comprises a P-type substrate; an N-type deep well is provided in the P-type substrate; Above the N-type deep well, from left to right, there are a first N-well, a first P-well, a second N-well, and a second P-well; a first P+ injection region is provided in the first N-well; a first N+ injection region and a third P+ injection region are provided in the first P-well; a second N+ injection region and a fourth P+ injection region are provided in the second N-well; A third N+ injection region is provided in the second P-well; a second P+ injection region is provided between the first N-well and the first P-well; a fifth P+ injection region is provided between the second N-well and the second P-well; the two electrodes of the first P+ injection region and the third N+ injection region are connected together as the cathode of the device, and the four electrodes of the first N+ injection region, the third P+ injection region, the second N+ injection region and the fourth P+ injection region are connected together as the anode of the device.

2. The highly robust asymmetric bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: A first field oxygen isolation region is provided between the left side of the first P+ injection region and the left edge of the P-type substrate; a second field oxygen isolation region is provided between the right side of the first P+ injection region and the left side of the second P+ injection region; a third field oxygen isolation region is provided between the right side of the second P+ injection region and the left side of the first N+ injection region; a fourth field oxygen isolation region is provided between the right side of the first N+ injection region and the left side of the third P+ injection region; a fifth field oxygen isolation region is provided between the right side of the third P+ injection region and the left side of the second N+ injection region; a sixth field oxygen isolation region is provided between the right side of the second N+ injection region and the left side of the fourth P+ injection region; a seventh field oxygen isolation region is provided between the right side of the fourth P+ injection region and the left side of the fifth P+ injection region; an eighth field oxygen isolation region is provided between the right side of the fifth P+ injection region and the left side of the third N+ injection region; and a ninth field oxygen isolation region is provided between the right side of the third N+ injection region and the right edge of the P-type substrate.

3. The highly robust asymmetric bidirectional thyristor electrostatic protection device according to claim 2, characterized in that: The first field oxygen isolation region and the second field oxygen isolation region are located on the surface of the first N-well; the third field oxygen isolation region and the fourth field oxygen isolation region are located on the surface of the first P-well; the left side of the fifth field oxygen isolation region is located on the surface of the first P-well, and the right side of the fifth field oxygen isolation region is located on the surface of the second N-well; the sixth field oxygen isolation region and the seventh field oxygen isolation region are located on the surface of the second N-well; The eighth field oxygen isolation region and the ninth field oxygen isolation region are located on a surface of the second P-well.

4. The highly robust asymmetric bidirectional thyristor electrostatic protection device according to claim 2, characterized in that: When a high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the fourth P+ injection region, the second N-well, and the second P-well constitute a PNP-type transistor, and the second N-well, the second P-well, and the third N+ injection region constitute an NPN-type transistor. When the parasitic PNP and the parasitic NPN are turned on, a forward SCR path is formed; when a high-voltage ESD pulse reaches the cathode of the device and the anode of the device is connected to a low potential, the first P+ injection region, the first N-well, and the first P-well constitute a PNP-type transistor, and the first N-well, the first P-well, and the first N+ injection region constitute an NPN-type transistor. When the parasitic PNP and the parasitic NPN are turned on, a reverse SCR path is formed.

5. The highly robust asymmetric bidirectional thyristor electrostatic protection device according to claim 1, characterized in that: When a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, and the ESD current flows along the fourth P+ injection region into the second N-well, the second P-well, and the third N+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the fifth P+ injection region and the second N-well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second N-well. When the voltage drop on the equivalent resistance reaches 0.7V, the vertical PNP transistor is turned on and the base current is provided to the lateral NPN transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the forward SCR path is successfully opened; When a high-voltage ESD pulse reaches the cathode of the device, the anode of the device is connected to a low potential, and the ESD current flows along the first P+ injection region into the first N-well, the first P-well, and the first N+ injection region. When the ESD current increases to a certain value, the reverse PN junction formed by the second P+ injection region and the first N-well undergoes avalanche breakdown, generating an avalanche breakdown current and forming a voltage drop on the equivalent resistance of the second P-well. When the voltage drop on the equivalent resistance reaches 0.7V, the lateral NPN transistor is turned on and the base current is provided to the vertical PNP transistor, thereby promoting its conduction, forming a positive feedback effect. At this time, the reverse SCR path is successfully opened.

6. A method for manufacturing a highly robust asymmetric bidirectional thyristor electrostatic protection device, characterized in that: The method comprises: Step 1: forming an N-type deep well in a P-type substrate; Step 2: Generating a first N-well, a first P-well, a second N-well, and a second P-well above the N-type deep well; Step 3: forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, and a ninth field oxygen isolation region in the P-type substrate from left to right; Step 4: forming a first P+ injection region in the first N-well from left to right, forming a first N+ injection region and a third P+ injection region in the first P-well from left to right, and forming a second P+ injection region between the contact surface of the first N-well and the first P-well, forming a second N+ injection region and a fourth P+ injection region in the second N-well from left to right, forming a third N+ injection region in the second P-well from left to right, and forming a fifth P+ injection region between the contact surface of the second N-well and the second P-well; and the left side of the first field oxygen isolation region contacts the left edge of the P-type substrate, the right side of the first field oxygen isolation region contacts the left side of the first P+ injection region, the right side of the first P+ injection region contacts the left side of the second field oxygen isolation region, the right side of the second field oxygen isolation region contacts the left side of the second P+ injection region, the right side of the second P+ injection region contacts the left side of the third field oxygen isolation region; the right side of the third field oxygen isolation region contacts the left side of the The left side of the first N+ implant region is in contact with the right side of the first N+ implant region, the right side of the fourth field oxygen isolation region is in contact with the left side of the third P+ implant region, the right side of the third P+ implant region is in contact with the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region is in contact with the left side of the second N+ implant region, the right side of the second N+ implant region is in contact with the left side of the sixth field oxygen isolation region, the right side of the sixth field oxygen isolation region is in contact with the left side of the fourth P+ implant region, the right side of the fourth P+ implant region is in contact with the left side of the seventh field oxygen isolation region, the right side of the seventh field oxygen isolation region is in contact with the left side of the fifth P+ implant region, the right side of the fifth P+ implant region is in contact with the left side of the eighth field oxygen isolation region, the right side of the eighth field oxygen isolation region is in contact with the left side of the third N+ implant region, the right side of the third N+ implant region is in contact with the left side of the ninth field oxygen isolation region, and the right side of the ninth field oxygen isolation region is in contact with the right edge of the P-type substrate; Step 5: Annealing the first P+ implantation region, the second P+ implantation region, the first N+ implantation region, the third P+ implantation region, the second N+ implantation region, the fourth P+ implantation region, the fifth P+ implantation region, and the third N+ implantation region to eliminate impurity migration in the implantation region; Step six: Connect the first N+ injection region, the third P+ injection region, the second N+ injection region, and the fourth P+ injection region together as the anode of the device, and connect the first P+ injection region and the third N+ injection region together as the cathode of the device.

7. The method for manufacturing a highly robust asymmetric bidirectional thyristor electrostatic protection device according to claim 6, characterized in that: The method also includes: A silicon dioxide film is grown on the P-type substrate, and then a silicon nitride layer is deposited; a photoresist layer is spin-coated on the wafer, and a mask is added to expose and develop it to form an isolation shallow groove; the silicon dioxide, silicon nitride and isolation shallow groove are etched to remove the photoresist layer, and a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is formed, and the silicon nitride layer is removed.

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