MRAM write failure detection and processing method and detection and processing circuit, MRAM

Abstract

The present invention provides a detection and processing method for MRAM write failure, a detection and processing circuit, and an MRAM. The detection and processing method includes: using a write voltage with a voltage value of V1 to write first data to a storage area to be tested of the MRAM; the normal write voltage value of the storage area to be tested during application is V2, and V1 < V2; reading the data stored in the storage area to be tested to obtain second data; comparing the first data and the second data to detect the storage element with write failure in the storage area to be tested. When detecting write failure, the degree of increase in the failure probability of abnormal storage elements with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the relationship curve between WER and write current, thereby detecting more abnormal storage elements with write failure and improving the overall detection coverage of failed storage elements. The detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for detecting and processing MRAM write failures, a detection and processing circuit, and an MRAM. Background Art

[0002] As the demand for low power consumption in chips for various application scenarios, such as automotive electronics and smart homes, becomes increasingly stringent, low-power MRAM (Magnetoresistive Random Access Memory), one of the most critical modules within a chip, is gradually becoming a research hotspot in the industry. The failure rate of MRAM memory cells is an important factor affecting the yield and reliability of MRAM. Failure types of MRAM memory cells include hard failures and soft failures. Hard failures include open circuits of memory cells, short circuits of memory cells, and read failures. Soft failures include write failures. Among them, hard failures are easy to detect, while write failures are random, making it impossible to accurately locate memory cells with a high probability of write failures. The number of memory cells with write failures directly affects the write success rate of MRAM. Existing testing methods mainly use normal write voltage values ​​in actual applications to test MRAM memory cells, resulting in low detection coverage of write failures. Summary of the Invention

[0003] The present invention provides an MRAM write failure detection and processing method, a detection and processing circuit, and an MRAM, so as to improve the overall detection coverage of failed memory cells.

[0004] In a first aspect, the present invention provides a method for detecting and processing an MRAM write failure, the method comprising:

[0005] Step 1: Using a write voltage of V1, write first data into a memory area to be tested of the MRAM; wherein a normal write voltage value of the memory area to be tested during application is V2, and V1<V2;

[0006] Step 2: Read the data stored in the storage area to be tested to obtain second data;

[0007] Step 3: Compare the first data and the second data to detect memory cells with write failures in the memory area to be tested.

[0008] In the above scheme, by reducing the write voltage during the detection of MRAM write failures, the first data is written to the memory area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the memory area to be tested in actual application, so that during the write failure detection process, the failure probability of each memory cell due to write failure is greater than the failure probability of the memory cell at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal memory cells with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal memory cells with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal memory cells with write failures, thereby improving the overall detection coverage of failed memory cells. The above detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible.

[0009] In one specific embodiment, an MRAM includes a main memory area and a redundant memory area, wherein the memory area to be tested is located in the main memory area, and the redundant memory area includes B repair units. Before writing first data to the memory area to be tested of the MRAM, the detection and processing method further includes: dividing the memory area to be tested into a plurality of test units, wherein the number of memory cells in each test unit is the same as the number of memory cells in the repair unit. This facilitates detection of the number of write-failed memory cells in each divided test unit and facilitates subsequent replacement of a test unit with a repair unit.

[0010] In a specific embodiment, writing first data to the storage area under test of the MRAM using a write voltage having a voltage value of V1 includes: writing the first data to each unit under test respectively using a write voltage having a voltage value of V1. Reading the data stored in the storage area under test to obtain second data includes: reading the data stored in each unit under test and obtaining the second data from each unit under test. Comparing the first data and the second data to detect write-failed storage elements in the storage area under test includes: comparing the first data written to each unit under test and the second data obtained from the unit under test to detect write-failed storage elements in each unit under test. By dividing the storage area under test into multiple units under test, the number of storage elements in each unit under test is the same as the number of storage elements in a repair unit in the redundant storage area, thereby facilitating the detection of the number of failed storage elements in each unit under test, and further facilitating redundant repair of units under test with a large number of failed storage elements.

[0011] In a specific embodiment, the detection and processing method further includes:

[0012] Step 4: Count the number of write-failed memory cells in each unit under test, and mark the units under test with the top M write-failed memory cells, where M≤B.

[0013] Step 5: Repeat steps 1 to 4 N times to obtain N×M marked units under test. By marking the units under test with the top M write-failed memory cells in each read / write test and repeating the read / write test N times, N×M marked units under test are obtained. This facilitates analysis of the positional distribution of these marked units under test and the number of marked failed memory cells in each unit under test. This information can then be used for in-depth analysis of manufacturing, yield control, and other aspects.

[0014] In a specific embodiment, the detection and processing method further includes:

[0015] Step 6: From the N×M marked units to be tested, count and mark the units to be tested that rank in the top M in terms of repetition frequency;

[0016] Step 7: Select M repair units from the redundant storage area and perform redundant repair on the M units to be tested marked in step 6.

[0017] By counting and marking the top M test cells with the highest repeat frequency from the N×M marked test cells, and then performing redundant repair on these M test cells, the top M test cells with the highest probability of having write-failed storage elements are detected, thereby improving the accuracy of the detected write-failed test cells. Furthermore, the number of repeated read and write tests (N) can be adjusted for different MRAM capacities and process conditions, providing greater flexibility.

[0018] In a second aspect, the present invention further provides a detection and processing circuit for MRAM write failure, which includes a sending control module, a data generator, a power supply module, a write operation module, a read operation module, and a comparison and verification module arranged in the MRAM. The sending control module is used to demarcate a storage area to be tested from the storage area of ​​the MRAM. The data generator is used to generate first data. The power supply module is used to generate a write voltage with a voltage value of V1, wherein the normal write power supply of the storage area to be tested when applied is V2, and V1 < V2. The write operation module is used to write the first data to the storage area to be tested using a write voltage with a voltage value of V1. The read operation module is used to read the data stored in the storage area to be tested to obtain the second data. The comparison and verification module is used to compare the first data and the second data to detect the storage element with write failure in the storage area to be tested.

[0019] In the above scheme, by reducing the write voltage during the detection of MRAM write failures, the first data is written to the memory area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the memory area to be tested in actual application, so that during the write failure detection process, the failure probability of each memory cell due to write failure is greater than the failure probability of the memory cell at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal memory cells with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal memory cells with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal memory cells with write failures, thereby improving the overall detection coverage of failed memory cells. The above detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible.

[0020] In one specific embodiment, the MRAM includes a primary storage area and a redundant storage area, wherein the redundant storage area includes B repair units. A transmission control module is configured to demarcate a test storage area from the primary storage area and divide the test storage area into multiple test units; the number of memory cells in each test unit is the same as the number of memory cells in the repair unit. This facilitates detection of the number of write-failed memory cells in each test unit and facilitates subsequent replacement of a test unit with a repair unit.

[0021] In a specific embodiment, the write operation module is used to use a write voltage with a voltage value of V1 to write the first data to each unit under test. The read operation module is used to read the data stored in each unit under test and obtain the second data from each unit under test. The comparison and verification module is used to compare the first data written to each unit under test and the second data obtained from the unit under test to detect the write-failed storage element in each unit under test. By dividing the storage area under test into multiple units under test, the number of storage elements in each unit under test is the same as the number of storage elements in a repair unit in the redundant storage area, thereby facilitating the detection of the number of failed storage elements in each unit under test, and further facilitating the redundant repair of the units under test with a large number of failed storage elements.

[0022] In a specific embodiment, the detection and processing circuit further includes a statistical marking module and a redundancy repair module. The statistical marking module is used to count the number of write-failed storage elements in each unit under test and mark the units under test that rank in the top M in terms of the number of write-failed storage elements, where M ≤ B. The sending control module is further used to control the write operation module, the read operation module, the comparison and verification module, and the statistical marking module to repeatedly perform the corresponding operations N times to obtain N×M marked units under test. By marking the units under test that rank in the top M in terms of the number of write-failed storage elements in each read / write test and repeating the read / write test N times, N×M marked units under test are obtained, so as to facilitate analysis of the position distribution of these marked units under test, analysis of the number of marked failed storage elements in each unit under test, and use of this information for in-depth analysis of processing, manufacturing, yield control, and other aspects.

[0023] In a specific embodiment, the statistical marking module is further used to count and mark the top M units to be tested in terms of repetition frequency from the N×M marked units to be tested. The detection processing circuit also includes a redundant repair module, which is used to select M repair units from the redundant storage area and perform redundant repair on the top M units to be tested in terms of repetition frequency. By counting and marking the top M units to be tested in terms of repetition frequency from the N×M marked units to be tested, and then performing redundant repair on these M units to be tested, the top M units to be tested with the highest probability of having write-failed storage elements are detected, thereby improving the accuracy of the detected write-failed units to be tested. The number of repeated read and write tests, N, can be adjusted for MRAMs of different capacities and process conditions, thereby providing greater flexibility.

[0024] In one specific embodiment, the detection processing circuit further includes: an address generator connected to the transmission control module, and an address storage module connected to the statistical marking module. The address generator is configured to generate address information for multiple units under test based on the multiple units under test that have been identified. The address storage module is configured to store the address information for the N×M marked units under test, and further configured to store the address information for the top M units under test ranked by repetition frequency. This facilitates temporary storage of the address information for the units under test and the address information for the screened N×M marked units under test.

[0025] In a specific embodiment, the address storage module is located in the main storage area, and the address storage module and the storage area to be tested are located in different areas. The power supply module is further configured to generate a write voltage with a voltage value of V3, wherein V3>V2. The write operation module is further configured to use a write voltage with a voltage value of V3 to write the address information of the N×M marked units to be tested and the address information of the first M units to be tested ranked by repetition frequency into the address storage module. By using a storage area other than the storage area to be tested in the main storage area as the address storage module, and using a higher write voltage value V3 to write the address information of the N×M marked units to be tested and the address information of the first M units to be tested ranked by repetition frequency into the address storage module, the probability of error in the address information temporarily stored in the address storage module can be reduced.

[0026] In one specific embodiment, the power module includes a Trim value storage module and a power management module. The transmission control module is further configured to configure Trim values ​​for different gears and transmit the configured Trim values ​​to the Trim value storage module. The power management module is configured to read the Trim values ​​from the Trim value storage module and analyze the Trim values ​​to obtain a write voltage of V1 or V3, thereby facilitating configuration of write voltages of different voltage values.

[0027] In a specific embodiment, the address storage module is an SRAM (Static Random-Access Memory), a register or an EEPROM (Electrically Erasable Programmable Read Only Memory), so that different storage media can be flexibly selected according to the storage space in the MRAM.

[0028] In one specific embodiment, the address storage module includes a failed unit address temporary storage module and a repair signature storage module. The failed unit address temporary storage module is configured to store the address information of N×M marked units under test. The statistical marking module is configured to transfer the address information of the units under test ranked in the top M by repetition frequency from the failed unit address temporary storage module to the repair signature storage module, thereby providing additional storage for the address information of the top M units under test ranked in the top M by repetition frequency, thereby facilitating subsequent redundant repair of these top M units under test.

[0029] In a third aspect, the present invention further provides an MRAM comprising a storage area and any of the above-described MRAM write failure detection and processing circuits. By reducing the write voltage during the MRAM write failure detection process, first data is written to the MRAM storage area to be tested at a write voltage value V1 that is lower than the normal write voltage value of the storage area to be tested in actual application. This ensures that, during the write failure detection process, the failure probability of each storage element due to write failure is greater than the failure probability of the storage element at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal storage elements with a long tail in the WER vs. write current curve is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the WER vs. write current curve. This allows for the detection of more abnormal storage elements with write failures, thereby improving the overall detection coverage of failed storage elements. The above-described detection and processing method can be implemented using a simple algorithm circuit and can be more efficiently applied to the screening process. Furthermore, the voltage value V1 can be adjusted for different MRAM capacities and process conditions, thereby providing greater flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A flowchart of a method for detecting and processing an MRAM write failure provided by an embodiment of the present invention;

[0031] Figure 2 is a curve showing the relationship between WER and write current;

[0032] Figure 3 Another WER vs. write current curve;

[0033] Figure 4 A flowchart of another method for detecting and processing MRAM write failures provided by an embodiment of the present invention;

[0034] Figure 5 A flowchart of another method for detecting and processing MRAM write failures provided by an embodiment of the present invention;

[0035] Figure 6 This is the distribution diagram of failed memory cells after 100 write and read tests using normal write voltage;

[0036] Figure 7 The distribution of failed memory cells after 100 write-read tests using a reduced write voltage.

[0037] Figure 8 A schematic diagram of N×M marked address information of units under test and address information of the units under test ranked in the top M in terms of repetition frequency provided by an embodiment of the present invention;

[0038] Figure 9A flowchart of another method for detecting and processing MRAM write failures provided by an embodiment of the present invention;

[0039] Figure 10 A flowchart of another method for detecting and processing MRAM write failures provided by an embodiment of the present invention;

[0040] Figure 11 A circuit block diagram of an MRAM write failure detection and processing device provided by an embodiment of the present invention;

[0041] Figure 12 A circuit block diagram of another MRAM write failure detection and processing device provided by an embodiment of the present invention;

[0042] Figure 13 A circuit block diagram of another MRAM write failure detection and processing device provided by an embodiment of the present invention;

[0043] Figure 14 A circuit block diagram of another MRAM write failure detection and processing device provided by an embodiment of the present invention;

[0044] Figure 15 A circuit block diagram of another MRAM write failure detection and processing device provided by an embodiment of the present invention.

[0045] Reference numerals:

[0046] 10- Transmission control module 11- MRAM storage area 111- Main storage area

[0047] 112-Redundant storage area 21-Data generator 22-Power module

[0048] 221-Trim value storage module 222-Power management module

[0049] 23-Write operation module 24-Read operation module 25-Comparison verification module

[0050] 31-Statistical marking module 32-Redundancy repair module 41-Address generator

[0051] 42-Address storage module 421-Failed unit address temporary storage module

[0052] 422-Fix signature storage module DETAILED DESCRIPTION

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0054] To facilitate understanding of the MRAM write failure detection and processing method provided by the embodiments of the present invention, the following first describes the application scenario of the detection and processing method provided by the embodiments of the present invention. The detection and processing method is applied to the detection process of MRAM write failures. The following is a detailed description of the MRAM write failure detection and processing method with reference to the accompanying drawings.

[0055] refer to Figure 1 The MRAM write failure detection and processing method provided by the embodiment of the present invention includes:

[0056] S10: writing first data into a memory area to be tested of the MRAM using a write voltage having a voltage value of V1; wherein a normal write voltage value of the memory area to be tested during application is V2, and V1<V2;

[0057] S20: Reading data stored in the storage area to be tested to obtain second data;

[0058] S30: Compare the first data and the second data to detect write-failed memory cells in the memory area to be tested.

[0059] In the above scheme, by reducing the write voltage during the detection of MRAM write failures, the first data is written to the memory area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the memory area to be tested in actual application, so that during the write failure detection process, the failure probability of each memory cell due to write failure is greater than the failure probability of the memory cell at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal memory cells with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal memory cells with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal memory cells with write failures, thereby improving the overall detection coverage of failed memory cells. The above detection and processing method can be implemented through a simple algorithm circuit and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible. The following is a detailed introduction to each of the above steps in conjunction with the accompanying drawings.

[0060] First, refer to Figure 1, using a write voltage of V1 to write first data to the memory area under test of the MRAM; wherein the normal write voltage value of the memory area under test during application is V2, and V1 < V2. The write current of the MRAM affects the write failure probability of each memory cell. The larger the write current, the smaller the write failure probability of the memory cell. The write failure probability of the memory cell can be represented by WER. The relationship between WER and write current is as follows:

[0061]

[0062] According to the above formula, we can get Figure 2 The relationship curve between WER and write current is shown. Therefore, in the storage area of ​​MRAM, there will be a certain number of random write failure memory cells every time a write is performed. When the write current is not large enough, the number of random write failure memory cells will increase. In addition, due to process deviations or defects, there is a certain deviation between the WER and write current curves of the memory cells. The WER has a long tail phenomenon, and the write current required by some memory cells is much larger than that of most memory cells, such as Figure 3 The thin solid line curve shown in FIG. 1 shows that this type of memory cell is an abnormal memory cell, and these memory cells can be collectively referred to as write-failed memory cells during the detection process. Figure 3 In the WER and write current relationship curve of normal memory cells shown by the thick solid line in the figure, there is a short tail phenomenon, or even no tail phenomenon. Such memory cells are normal memory cells. Assuming that the write current of the normal write operation of MRAM in application is I1, by reducing the write current to I2, as shown in FIG. Figure 3 As shown, it can be seen that the write failure probability of the storage element will increase at this time, the write failure probability of the normal storage element will increase less or even not increase, but the write failure probability of the abnormal storage element will increase by a large margin (from the write failure probability of 0.2 of the abnormal storage element when the write current is I1, to the write failure probability of 0.5 when the write current is I2), which will cause the number of write failures of the abnormal storage element to increase, and the number of storage elements with write failures will increase. In the MRAM circuit, the write current is generally changed by changing the write voltage. The greater the write voltage, the greater the write current; the smaller the write voltage, the smaller the write current. Therefore, the present application limits the write voltage value V1 when detecting write failure to V2 when the normal write voltage value is applied. When the first data is written to the storage area to be tested of the MRAM using a write voltage of V1, the write failure probability of each storage element will be greater than the failure probability of the storage element at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal storage cells with a longer tail in the WER vs. write current relationship curve is much greater than the degree of increase in the failure probability of normal storage cells with a shorter tail in the WER vs. write current relationship curve. This allows for the detection of more abnormal storage cells with write failures, thereby improving the overall detection coverage of failed storage cells.

[0063] Next, refer to Figure 1 Specifically, the data stored in the storage area to be tested can be read using a normal read voltage during application.

[0064] Next, refer to Figure 1 , comparing the first data with the second data to detect write-failed memory cells in the memory area under test. Because memory cells in the memory area under test may experience random write failures, when the stored data is read from the memory area under test again, the second data obtained may differ from the written first data. Therefore, by analyzing the difference between the first and second data, memory cells with write failures during this read / write test can be detected. By lowering the write voltage during the MRAM write-failure detection process, the first data is written to the memory area under test at a write voltage V1 that is lower than the normal write voltage value of the memory area under test in actual use. This ensures that the write failure probability of each memory cell during the write-failure detection process is greater than the failure probability of the memory cell at the normal write voltage. In particular, the increased failure probability of abnormal memory cells whose WER vs. write current curve exhibits a long tail is much greater than the increased failure probability of normal memory cells whose WER vs. write current curve exhibits a short tail. This allows for the detection of more write-failed memory cells, thereby improving the overall detection coverage of failed memory cells. The above detection and processing method can be implemented using a simple algorithm circuit, and can be applied more efficiently to the screening process. In addition, the voltage value V1 can be adjusted according to different MRAM capacities and process conditions, thus providing greater flexibility.

[0065] Furthermore, the MRAM storage area includes not only a primary storage area but also a redundant storage area. When testing memory cells in the primary storage area, the memory area to be tested can be located in the primary storage area. Of course, when testing memory cells in the redundant storage area, some or all of the memory cells in the redundant storage area become the memory area to be tested. The redundant storage area contains B repair units, where B is a positive integer. Each repair unit serves as a minimum redundant replacement unit during redundant repair, replacing the memory cells in a certain storage area in the primary storage area as a whole, thereby performing redundant repair.

[0066] Before writing the first data into the memory area to be tested of the MRAM using a write voltage with a voltage value of V1, the memory area to be tested may be divided into a plurality of units to be tested, wherein the number of memory cells in each unit to be tested is the same as the number of memory cells in the repair unit, so as to facilitate detection of the number of write-failed memory cells in each divided unit to be tested and facilitate subsequent replacement of a unit to be tested with a repair unit.

[0067] Afterwards, the first data is written to the storage area to be tested of the MRAM. Specifically, a write voltage with a voltage value of V1 can be used to write the first data to each unit to be tested. At this time, the corresponding read operation in step 2 is also slightly different. It is necessary to read the data stored in each unit to be tested and obtain the second data from each unit to be tested. The corresponding comparison of the first data and the second data in step 3 is also slightly different. It is necessary to compare the first data written to each unit to be tested and the second data obtained from the unit to be tested to detect the write-failed storage elements in each unit to be tested. By dividing the storage area to be tested into multiple units to be tested, the number of storage elements in each unit to be tested is the same as the number of storage elements in a repair unit in the redundant storage area, thereby facilitating the detection of the number of failed storage elements in each unit to be tested, and further facilitating the redundant repair of the units to be tested with a large number of failed storage elements.

[0068] In addition, reference Figure 4 and Figure 5 After step 3, the detection and processing method may further include the following steps:

[0069] Step 4: Count the number of write-failed memory cells in each unit under test, and mark the units under test with the top M write-failed memory cells, where M≤B.

[0070] Step 5: Repeat steps 1 to 4 N times to obtain N×M marked units to be tested.

[0071] By marking the top M units under test with the most failed memory cells in each read / write test and repeating the read / write test N times, N×M marked units under test are obtained, so as to analyze the position distribution of these marked units under test, analyze the number of marked failed memory cells in each unit under test, and use this information for in-depth analysis of processing, manufacturing, yield control, etc.

[0072] Continue to refer Figure 4 , the detection method may further comprise the following steps:

[0073] Step 6: From the N×M marked units to be tested, count and mark the units to be tested that rank in the top M in terms of repetition frequency;

[0074] Step 7: Select M repair units from the redundant storage area and perform redundant repair on the M units to be tested marked in step 6.

[0075] By counting and marking the top M test cells with the highest repeat frequency from the N×M marked test cells, and then performing redundant repair on these M test cells, the top M test cells with the highest probability of having write-failed storage elements are detected, thereby improving the accuracy of the detected write-failed test cells. Furthermore, the number of repeated read and write tests (N) can be adjusted for different MRAM capacities and process conditions, providing greater flexibility.

[0076] That is, steps 4 to 7 above adopt a multiple read and write test method, taking advantage of the fact that the write failure probability of abnormal memory cells is higher than that of normal memory cells in the above write failure test method, so that abnormal memory cells with a high write failure probability can be more easily revealed. Assuming that the WER of each memory cell in the storage area of ​​the MRAM is the same and does not affect each other, the number of memory cell failures and the number of corresponding memory cells conform to the Poisson distribution. For example, after N = 100 tests, the expected value λ is as follows:

[0077] λ=WER*100

[0078] The expected value λ can be substituted into the following Poisson distribution formula to obtain the ideal distribution of failed memory elements in 100 tests of the memory area to be tested:

[0079]

[0080] like Figure 6 The distribution of failed memory cells after 100 write-read tests using normal write voltage is shown in Figure 1. Figure 7 This is the distribution of failed memory cells after 100 write-read tests using a reduced write voltage. By first counting the number of write failures (x, fail count) for each memory cell, and then counting the number of memory cells with the same fail count, we get (y, bitcount). The solid lines marked with "*" are the simulation results of write-failed memory cells in an ideal memory area under test, while the solid lines marked with "○" are the statistical results of the number of write-failed memory cells and the number of memory cells in the actual memory area under test. Comparison Figure 6 and Figure 7 It can be found that the frequency of fail bits increases significantly after the write voltage is reduced, so that the above-mentioned method can significantly improve the overall detection coverage of failed memory cells.

[0081] In step 4 above, by marking the top M units under test with the largest number of write-failed memory cells, where M ≤ B, some or all of the repair units in the redundant memory area can be used to replace some of the units under test in the memory area under test for redundant repair. Alternatively, marking the top M units under test with the largest number of write-failed memory cells can be accomplished by storing the address information of these M units under test.

[0082] Correspondingly, in step 5, steps 1 to 4 are repeated N times to obtain N×M marked units to be tested. Alternatively, the address information of the N×M marked units to be tested can be stored to obtain the following: Figure 8 The N×M address information array shown. Figure 8 As shown, the address information of the first M units under test obtained in the first test may be A1, A2, A3, A4, ...; the address information of the first M units under test obtained in the second test may be A2, A1, A5, A4, ...; the address information of the first M units under test obtained in the third test may be A1, A5, A2, A3, ...; ...; the address information of the first M units under test obtained in the Nth test may be .... Thus, N×M marked address information of units under test are obtained.

[0083] In the above step 6, when counting and marking the top M units to be tested in terms of repetition frequency from the N×M marked units to be tested, the address information of the top M units to be tested in terms of repetition frequency can be selected from the address information of the aforementioned N×M marked units to be tested, and the address information of the top M units to be tested in terms of repetition frequency that has been counted is transferred to the storage device, thereby achieving the statistical marking of the top M units to be tested in terms of repetition frequency.

[0084] In addition, when storing the address information of the N×M marked units under test and the address information of the units under test ranked first by repetition frequency, reference is made to Figure 9 A temporary storage area can be selected as an address storage module to store the address information. The address storage module can be an SRAM, a register, an EEPROM, etc., so that different storage media can be flexibly selected according to the storage space in the MRAM.

[0085] refer to Figure 10 , the address storage module can also be located in the main storage area of ​​the MRAM, but the address storage module and the storage area to be tested are located in different areas, so that the MRAM can be used as the address storage module 42. Of course, the address storage module can also be an area in the main storage area that has undergone a write failure test. At this time, when writing these address information into the address storage module of the main storage area of ​​the MRAM, a write voltage with a voltage value of V3 can be used to write the address information of the N×M marked cells to be tested and the address information of the top M cells to be tested in terms of repetition frequency into the address storage module, where V3>V2. By using a storage area other than the storage area to be tested in the main storage area as the address storage module and using a higher write voltage value V3 to write the address information of the N×M marked cells to be tested and the address information of the top M cells to be tested in terms of repetition frequency into the address storage module, the error probability of the address information temporarily stored in the address storage module can be reduced.

[0086] refer to Figure 4 、 Figure 9 and Figure 10 In step 7, M repair cells can be selected from the redundant storage area to perform redundant repair on the M test cells marked in step 6. Specifically, the address information of the top M test cells with the highest repetition frequency stored in step 6 can be used to replace these top M test cells with M repair cells from the redundant storage area, thereby achieving redundant repair. This method marks the top M test cells with the highest number of write-failed storage elements during each read / write test, and repeats the read / write test N times to obtain N×M marked test cells. From these N×M marked test cells, the top M test cells with the highest repetition frequency are counted and marked, and redundant repair is then performed on these M test cells to detect the top M test cells with the highest probability of having the highest number of write-failed storage elements, thereby improving the accuracy of the detected write-failed test cells. Furthermore, the number of repeated read / write tests (N) can be adjusted for different MRAM capacities and process conditions, providing greater flexibility.

[0087] The detection and processing method shown in each of the above embodiments, by reducing the write voltage during the detection of MRAM write failures, writes the first data to the storage area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the storage area to be tested in actual application, so that during the write failure detection process, the failure probability of each storage element due to write failure is greater than the failure probability of the storage element at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal storage elements with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal storage elements with write failures, thereby improving the overall detection coverage of failed storage elements. The above detection and processing method can realize detection through a simple algorithm circuit and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible.

[0088] In addition, the embodiment of the present invention also provides a detection and processing circuit for MRAM write failure, referring to Figure 11The detection processing circuit includes a sending control module 10, a data generator 21, a power module 22, a write operation module 23, a read operation module 24, and a comparison and verification module 25, which are arranged in the MRAM. Among them, the sending control module 10 is used to demarcate the storage area to be tested from the storage area of ​​the MRAM. The data generator 21 is used to generate first data. The power module 22 is used to generate a write voltage with a voltage value of V1, wherein the normal write power supply of the storage area to be tested when in use is V2, and V1<V2. The write operation module 23 is used to use the write voltage with a voltage value of V1 to write the first data to the storage area to be tested. The read operation module 24 is used to read the data stored in the storage area to be tested to obtain the second data. The comparison and verification module 25 is used to compare the first data and the second data to detect the storage element with write failure in the storage area to be tested.

[0089] In the above scheme, by reducing the write voltage during the detection of MRAM write failures, the first data is written to the memory area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the memory area to be tested in actual application, so that during the write failure detection process, the failure probability of each memory cell due to write failure is greater than the failure probability of the memory cell at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal memory cells with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal memory cells with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal memory cells with write failures, thereby improving the overall detection coverage of failed memory cells. The above detection and processing method can be implemented through a simple algorithm circuit and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible. The following is a detailed introduction to the above circuit modules in conjunction with the accompanying drawings.

[0090] When setting up the transmission control module 10, the transmission control module 10 serves as the core control module for implementing detection. It can receive external input information and control the operation of the data generator 21, the power module 22, the write operation module 23, the read operation module 24, and the comparison and verification module 25. A configurable information input module can be provided in the MRAM as the MRAM's overall input port for receiving external configurable information. The configurable information input module is connected to the transmission control module 10 to forward configuration information to the transmission control module 10.

[0091] refer to Figure 11 and Figure 12, the MRAM storage area 11 includes a main storage area 111 and a redundant storage area 112. When the sending control module 10 demarcates the storage area to be tested from the storage area of ​​the MRAM, the sending control module 10 can demarcate the storage area to be tested from the main storage area 111 of the MRAM, or can demarcate the storage area to be tested from the redundant storage area 112. Among them, the redundant storage area 112 can include B repair units. When the sending control module 10 demarcates the storage area to be tested from the main storage area 111, it can first demarcate the storage area to be tested, and then divide the storage area to be tested into multiple units to be tested; the number of storage elements in each unit to be tested is the same as the number of storage elements in the repair unit, so as to facilitate the detection of the number of write-failed storage elements in each divided unit to be tested, and at the same time facilitate the subsequent replacement of a certain unit to be tested with a repair unit. At this time, the write operation module 23 needs to use a write voltage with a voltage value of V1 to write the first data to each unit to be tested respectively. The read operation module 24 needs to read the data stored in each unit to be tested and obtain the second data from each unit to be tested. The comparison and verification module 25 needs to compare the first data written into each unit to be tested and the second data obtained from the unit to be tested to detect the write-failed storage element in each unit to be tested. By dividing the storage area to be tested into multiple units to be tested, the number of storage elements in each unit to be tested is the same as the number of storage elements in a repair unit of the redundant storage area 112, thereby facilitating the detection of the number of failed storage elements in each unit to be tested, and further facilitating the redundant repair of the units to be tested with a large number of failed storage elements. The specific detection process is described in the aforementioned detection and processing method section and will not be repeated here.

[0092] In addition, reference Figure 12 The detection and processing circuit may further include a statistical marking module 31 and a redundancy repair module 32. The statistical marking module 31 may be used to count the number of write-failed storage elements in each unit under test and mark the units under test with the top M write-failed storage elements, where M ≤ B. The sending control module 10 may also be used to control the write operation module 23, the read operation module 24, the comparison and verification module 25, and the statistical marking module 31 to repeatedly perform corresponding operations N times to obtain N×M marked units under test. By marking the top M write-failed storage elements in each read / write test and repeating the read / write test N times, N×M marked units under test are obtained, so as to facilitate analysis of the position distribution of these marked units under test, analysis of the number of marked failed storage elements in each unit under test, and use of this information for in-depth analysis of manufacturing, yield control, and the like.

[0093] Of course, the statistical marking module 31 can also be used to count and mark the top M units to be tested in terms of repetition frequency from the N×M marked units to be tested. Figure 12The detection and processing circuit can further include a redundant repair module 32, which can also be used to select M repair units from the redundant storage area 112 and perform redundant repair on the test units ranked in the top M in terms of repetition frequency. By marking the test units ranked in the top M in terms of the number of write-failed storage elements in each read and write test, and repeating the read and write test N times, N×M marked test units are obtained; then, from the N×M marked test units, the test units ranked in the top M in terms of repetition frequency are counted and marked, and then redundant repair is performed on these M test units to detect the top M test units with the highest probability of the number of write-failed storage elements, thereby improving the accuracy of the detected write-failed test units. The number of repeated read and write tests N can be adjusted for different MRAM capacities and process conditions, thereby providing greater flexibility. The specific implementation method is described in the aforementioned detection and processing method section and will not be repeated here.

[0094] In addition, reference Figure 13 , the detection processing circuit may also include: an address generator 41 connected to the sending control module 10, and an address storage module 42 connected to the statistical marking module 31. Among them, the address generator 41 is used to generate address information of multiple units to be tested based on the multiple units to be tested that have been delineated. The address storage module 42 is used to store the address information of N×M marked units to be tested, and is also used to store the address information of the top M units to be tested with the highest repetition frequency. This is to facilitate the temporary storage of the address information of the units to be tested, as well as the address information of the screened N×M marked units to be tested. For the specific address information storage and statistics of the units to be tested, please refer to the description of the aforementioned method part, which will not be repeated here. An address decoder may also be provided in the MRAM, and the address decoder may be connected to circuit modules such as the read operation module 24, the write operation module 23 and the sending control module 10 to decode the address information.

[0095] When specifically determining the address storage module 42, the address storage module 42 can be SRAM, register, EFUSE, etc., so that different storage media can be flexibly selected according to the storage space in the MRAM. Figure 10The address storage module 42 can also be located in the main storage area, but the address storage module and the storage area to be tested are located in different areas, so that the MRAM can be used as the address storage module 42. Of course, the address storage module 42 can also be an area in the main storage area that has undergone write failure testing. In this case, the power supply module 22 can also be used to generate a write voltage with a voltage value of V3, where V3>V2. When writing this address information into the address storage module 42 of the main storage area 111 of the MRAM, the write operation module 23 can use a write voltage value of V3 to write the address information of the N×M marked cells to be tested and the address information of the top M cells to be tested ranked by repetition frequency into the address storage module 42. By using a storage area other than the storage area to be tested in the main storage area 111 as the address storage module 42 and using a higher write voltage value V3 to write the address information of the N×M marked cells to be tested and the address information of the top M cells to be tested ranked by repetition frequency into the address storage module 42, the error probability of the address information temporarily stored in the address storage module 42 can be reduced.

[0096] In addition, when setting the address storage module 42, refer to Figure 14 The address storage module 42 may include a failed unit address temporary storage module 421 and a repair signature storage module 422. The failed unit address temporary storage module 421 is configured to store the address information of N×M marked units under test. The statistical marking module 31 is configured to transfer the address information of the units under test ranked in the top M in terms of repetition frequency from the failed unit address temporary storage module 421 to the repair signature storage module 422, thereby providing additional storage for the address information of the units under test ranked in the top M in terms of repetition frequency, thereby facilitating subsequent redundant repair of the top M units under test.

[0097] When setting up the power module 22, refer to Figure 15 The power module 22 includes a Trim value storage module 221 and a power management module 222. The transmission control module 10 is further configured to configure the Trim values ​​for different gears and send the configured Trim values ​​to the Trim value storage module 221. Specifically, the transmission control module 10 can send the configured Trim values ​​to the Trim value storage module 221 via the Trim value sending module. The Trim value storage module 221 can be a register, or a storage medium such as SRAM, EFUSE, EEPROM, or OTP. The power management module 222 is configured to read the Trim value in the Trim value storage module 221 and parse the Trim value to obtain a write voltage with a voltage value of V1 or V3. This facilitates configuration of write voltages with different voltage values.

[0098] By reducing the write voltage during the detection of MRAM write failures, the first data is written to the memory area to be tested of the MRAM at a write voltage value V1 that is smaller than the normal write voltage value of the memory area to be tested in actual application, so that during the write failure detection process, the failure probability of each memory cell due to write failure is greater than the failure probability of the memory cell at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal memory cells with a long tail in the relationship curve between WER and write current is much greater than the degree of increase in the failure probability of normal memory cells with a short tail in the relationship curve between WER and write current, thereby being able to detect more abnormal memory cells with write failures, thereby improving the overall detection coverage of failed memory cells. The above-mentioned detection and processing method can realize detection through a simple algorithm circuit, and can be more efficiently applied to the screening process. In addition, the voltage value V1 can be adjusted for MRAMs of different capacities and process conditions, thereby making it more flexible.

[0099] In addition, an embodiment of the present invention further provides an MRAM, comprising a storage area and any of the above-described MRAM write failure detection and processing circuits. By reducing the write voltage during the MRAM write failure detection process, first data is written to the MRAM storage area to be tested at a write voltage value V1 that is lower than the normal write voltage value of the storage area to be tested in actual application. This ensures that, during the write failure detection process, the failure probability of each storage element due to write failure is greater than the failure probability of the storage element at the normal write voltage. In particular, the degree of increase in the failure probability of abnormal storage elements with a long tail in the WER vs. write current curve is much greater than the degree of increase in the failure probability of normal storage elements with a short tail in the WER vs. write current curve. This allows for the detection of more abnormal storage elements with write failures, thereby improving the overall detection coverage of failed storage elements. The above-described detection and processing method can be implemented using a simple algorithm circuit and can be more efficiently applied to the screening process. Furthermore, the voltage value V1 can be adjusted for different MRAM capacities and process conditions, thereby providing greater flexibility.

[0100] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for detecting and processing MRAM write failures, characterized in that: include: Step 1: writing first data into the memory area to be tested of the MRAM using a write voltage of voltage V1; wherein a normal write voltage value of the memory area to be tested during application is V2, and V1<V2; Step 2: Reading the data stored in the storage area to be tested to obtain second data; Step 3: Compare the first data and the second data to detect write-failed memory cells in the storage area to be tested.

2. The detection and processing method according to claim 1, wherein: The MRAM includes a main storage area and a redundant storage area, the storage area to be tested is located in the main storage area, and the redundant storage area includes B repair units; Before writing the first data into the storage area to be tested of the MRAM, the detection processing method further includes: The storage area to be tested is divided into a plurality of units to be tested, and the number of storage elements in each unit to be tested is the same as the number of storage elements in the repair unit.

3. The detection and processing method according to claim 2, wherein: The step of writing first data into the memory area to be tested of the MRAM by using a write voltage having a voltage value of V1 includes: Using a write voltage with a voltage value of V1, write the first data into each unit to be tested; The reading out of the data stored in the storage area to be tested to obtain the second data comprises: reading out the data stored in each unit to be tested to obtain the second data from each unit to be tested; The comparing the first data and the second data to detect the write-failed storage elements in the storage area to be tested includes: comparing the first data written into each unit to be tested and the second data obtained from the unit to be tested to detect the write-failed storage elements in each unit to be tested.

4. The detection and processing method according to claim 2, wherein: Also includes: Step 4: Count the number of write-failed memory cells in each unit under test, and mark the units under test with the top M write-failed memory cells, where M≤B. Step 5: Repeat steps 1 to 4 for N times to obtain N×M marked units to be tested.

5. The detection and processing method according to claim 4, wherein: Also includes: Step 6: From the N×M marked units to be tested, count and mark the units to be tested that rank in the top M in terms of repetition frequency; Step 7: Select M repair units from the redundant storage area, and perform redundant repair on the M units to be tested marked in step 6.

6. A detection and processing circuit for MRAM write failure, characterized in that: It includes a sending control module, a data generator, a power supply module, a write operation module, a read operation module and a comparison and verification module arranged in the MRAM; wherein, The sending control module is used to demarcate a storage area to be tested from the storage area of ​​the MRAM; The data generator is used to generate first data; The power supply module is used to generate a write voltage with a voltage value of V1; wherein the normal write voltage value of the storage area to be tested during application is V2, and V1<V2; The write operation module is used to write the first data into the storage area to be tested by using the write voltage with the voltage value V1; The read operation module is used to read the data stored in the storage area to be tested to obtain second data; The comparison and verification module is used to compare the first data and the second data, and detect the storage elements with write failures in the storage area to be tested.

7. The detection processing circuit according to claim 6, wherein: The MRAM includes a main storage area and a redundant storage area, and the redundant storage area includes B repair units; The sending control module is used to demarcate the storage area to be tested from the main storage area, and divide the storage area to be tested into a plurality of units to be tested; The number of storage elements in each unit to be tested is the same as the number of storage elements in the repair unit.

8. The detection processing circuit according to claim 7, wherein: The write operation module is used to write the first data into each unit under test respectively using the write voltage with the voltage value V1; The read operation module is used to read the data stored in each unit under test and obtain second data from each unit under test; The comparison and verification module is used to compare the first data written into each unit under test and the second data obtained from the unit under test, and detect the memory cell with write failure in each unit under test.

9. The detection processing circuit according to claim 7, wherein: Also includes: A statistical marking module is used to count the number of write-failed storage elements in each unit under test and mark the units under test with the number of write-failed storage elements ranking in the top M; where M≤B; The sending control module is further used to control the write operation module, the read operation module, the comparison and verification module and the statistical marking module to repeatedly perform corresponding operations N times to obtain N×M marked units under test.

10. The detection processing circuit according to claim 9, wherein: The statistical marking module is further configured to count and mark the first M units to be tested in terms of repetition frequency from the N×M marked units to be tested; The detection processing circuit further includes: a redundant repair module, configured to select M repair units from the redundant storage area and perform redundant repair on the units to be tested that are ranked in the top M in terms of repetition frequency.

11. The detection processing circuit according to claim 10, wherein: Also includes: an address generator connected to the sending control module, the address generator being configured to generate address information of the plurality of units under test according to the plurality of units under test that are demarcated; The address storage module connected to the statistical marking module is used to store the address information of the N×M marked units to be tested; and is also used to store the address information of the first M units to be tested ranked by repetition frequency.

12. The detection processing circuit according to claim 11, wherein: The address storage module is located in the main storage area, and the address storage module and the storage area to be tested are located in different areas; The power supply module is further configured to generate a write voltage having a voltage value of V3; wherein V3>V2; The write operation module is further configured to write the address information of the N×M marked units under test and the address information of the first M units under test ranked by repetition frequency into the address storage module using the write voltage V3.

13. The detection processing circuit according to claim 12, wherein: The power supply module includes a Trim value storage module and a power management module; The sending control module is further configured to configure the Trim values ​​of different gears and send the configured Trim values ​​to the Trim value storage module; The power management module is used to read the Trim value in the Trim value storage module and parse the Trim value to obtain the write voltage whose voltage value is V1 or V3.

14. The detection processing circuit according to claim 11, wherein: The address storage module is an SRAM, a register or an EEPROM.

15. The detection processing circuit according to claim 11, wherein: The address storage module includes a failure unit address temporary storage module and a repair signature storage module; Wherein, the failed unit address temporary storage module is used to store the address information of the N×M marked units to be tested; The statistical marking module is used to transfer the address information of the units to be tested that are ranked in the top M in terms of repetition frequency from the failed unit address temporary storage module to the repair signature storage module.

16. An MRAM, characterized in that: include: Storage area; The MRAM write failure detection and processing circuit according to any one of claims 6 to 15.

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