A CS pin voltage release circuit for a switching power supply control chip

Abstract

The present invention discloses a voltage release circuit for the CS pin of a switching power supply control chip. This circuit modulates the input waveform at the current sampling pin of the PWM switching power supply control chip, converting an input triangular wave with a non-zero amplitude and a low rising slope into a post-peak sawtooth wave with a zero amplitude and a large rising slope. After this modulation step, the PWM switching power supply has lower design requirements for the RC filter parameters of the current sampling circuit, preventing control loop instability caused by RC filter circuit parameter drift due to long-term use of the power supply. This circuit also improves the control loop stability margin and enhances anti-interference capabilities.

Description

Technical Field

[0001] The present invention belongs to the field of switch control technology and relates to a CS pin voltage release circuit for a switching power supply control chip. Specifically, the present invention is a circuit for enhancing the stability of an existing PWM switching power supply control loop and reducing the requirements for RC filtering parameters in a current sampling circuit. Background Art

[0002] Currently, most forward and flyback switching power supplies use a single-output control chip similar to the UC1842 as the main controller. This type of control chip uses a current-mode control method, employing a voltage + current dual-loop control scheme: the voltage loop serves as the outer control loop, and the current loop serves as the inner control loop. The current control strategy employs cycle-by-cycle current limiting. The main operating principle is that the output voltage, after voltage division and filtering, is combined with a preset voltage reference and fed into a voltage error amplifier. The amplifier's output serves as the reference input for the current control loop. The other input to the current control loop is the current signal sampled at the chip's CS pin. When the current signal amplitude exceeds the reference input, the PWM output signal is shut off for the current cycle until it is restarted in the next cycle. The current signal sampled at the CS pin has a low amplitude and a low rising slope, making it susceptible to interference from the voltage cycle switching signal. This can cause erroneous operation, such as premature shutdown of the PWM output signal, and further lead to instability in the power supply control loop.

[0003] To prevent the clutter interference signal generated by the power circuit from entering the control circuit, the resistance value in the RC filter circuit is usually several hundred ohms to one thousand ohms. Therefore, when the PWM signal is turned off, the voltage on the capacitor in the RC filter circuit cannot drop to 0V, resulting in the current sampling signal on the CS pin starting at a value other than 0V when the next PWM signal is turned on. When the external interference signal is superimposed on the current sampling signal, it can easily exceed the input given signal of the current loop, causing the PWM output signal to be turned off. Summary of the Invention

[0004] (1) Purpose of the invention

[0005] The purpose of the present invention is to provide a CS pin voltage release circuit for a switching power supply control chip, which solves the problem of unstable power supply control loop in the background art by optimizing the waveform of the CS pin sampling voltage.

[0006] (2) Technical solution

[0007] In order to solve the above technical problems, the present invention provides a CS pin voltage release circuit for a switching power supply control chip. The switching power supply control chip includes a voltage error amplifier, a resistor 1R, a resistor 2R, a current comparator, a logic circuit, and a reference voltage source. The output end of the voltage error amplifier is connected to one end of the resistor 2R, the other end of the resistor 2R is connected to one end of the resistor 1R and the positive input terminal of the current comparator, the other end of the resistor 1R is grounded, the output end of the current comparator is connected to the input end of the logic circuit, the output end of the logic circuit is the PWM control signal output pin Pin6_PWM of the switching power supply control chip, the negative input terminal of the current comparator is the current feedback signal pin Pin3_CS of the switching power supply control chip, that is, the CS pin, and one end of the reference voltage source serves as the reference voltage pin Pin8 of the switching power supply control chip; a discharge circuit is provided near the CS pin. When the PWM signal is turned off, the voltage on the CS pin is reduced to 0V by releasing residual energy. When the PWM signal of the next cycle is turned on, the discharge circuit is turned off, and the current sampling signal on the CS pin gradually increases from 0V until the amplitude is the same as the given signal amplitude of the current loop, and then the PWM signal is turned off.

[0008] The voltage release circuit includes a resistor R1, a capacitor C1, a resistor Rs, and an N-channel MOS transistor Q1. Resistor Rs is connected between the source of the N-channel MOS transistor Q1 and ground, converting the current signal flowing through the MOS transistor into a voltage signal. This signal is then sent to the current feedback signal pin Pin3_CS through an RC filter circuit consisting of resistor R1 and capacitor C1. The gate of the N-channel MOS transistor Q1 is connected to the PWM control signal output pin Pin6_PWM, and the drain of the N-channel MOS transistor Q1 is connected to the inductor T1.

[0009] The discharge circuit includes a PNP transistor V1, an N-channel MOS transistor Q2, and a resistor R2. The emitter of the PNP transistor V1 is connected to the reference voltage pin Pin8, the base is connected to the PWM control signal output pin Pin6_PWM, and the collector is connected to the gate G of the N-channel MOS transistor Q2. The drain of the N-channel MOS transistor Q2 is connected to the current feedback signal pin Pin3_CS, and the source is connected to ground. The resistor R2 is connected between the gate and source of the MOS transistor Q2.

[0010] Among them, when the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a high level, the PNP transistor V1 is turned on, and the current flowing through the resistor Rs gradually increases; the PNP transistor V1 is turned off, the gate of the N-channel MOS transistor Q2 is at a low level, and the N-channel MOS transistor Q2 is in the off state. The amplitude of the current signal on the capacitor C1 gradually increases until the amplitude reaches the given voltage amplitude of the current loop input, and the PWM control signal output becomes low.

[0011] Among them, when the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a low level, the PNP transistor V1 is turned off, and the current flowing through the resistor Rs is zero. At this time, the PNP transistor V1 is turned on, the gate of the N-channel MOS transistor Q2 is high, the N-channel MOS transistor Q2 is in the on state, and the current signal on the capacitor C1 is released to zero level.

[0012] The signal on the CS pin is a trailing sawtooth wave with an initial amplitude of 0V and a subsequent rising edge.

[0013] Among them, the amplitude of the current sampling signal is significantly different from the amplitude of the current loop given signal, so that the interference signal is not enough to reach the amplitude of the current loop given signal after being superimposed on the current sampling signal, and will not trigger the shutdown of the PWM signal.

[0014] Among them, among the control signal output by Pin6_PWM, the current loop given control signal and the current signal fed back by the Pin3_CS pin, when Pin6_PWM outputs a high level, the voltage amplitude of the current signal of the Pin3_CS pin gradually increases until the voltage amplitude is equal to the current loop given control signal, and the control signal output by Pin6_PWM becomes a low level.

[0015] When the control signal output by Pin6_PWM becomes low level, the current signal fed back by the Pin3_CS pin drops to zero level synchronously.

[0016] (3) Beneficial effects

[0017] The above technical solution provides a CS pin voltage release circuit for a switching power supply control chip. When the CS pin voltage release circuit is provided on the periphery of the switching power supply control chip, the design requirements for the RC filter parameters of the current sampling circuit are reduced. This also prevents the RC filter parameters of the current sampling circuit from drifting due to long-term use of the power supply, which can lead to unstable control loops. This improves the control loop's stability margin and anti-interference capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the schematic diagram of the voltage release circuit of the CS pin of the switching power supply control chip;

[0019] Figure 2 It corresponds to Figure 1 The control signal timing diagram is as follows. DETAILED DESCRIPTION

[0020] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0021] In the voltage release circuit of the CS pin of the switching power supply control chip of the present invention, a discharge circuit is provided near the CS pin of the switching power supply control chip. When the PWM signal is turned off, the residual energy on the capacitor in the RC filter circuit is released, so that the voltage on the CS pin is reduced to 0V. When the PWM signal of the next cycle is turned on, the discharge circuit is closed, and the current sampling signal on the CS pin gradually rises from 0V until the amplitude reaches the same as the given signal amplitude of the current loop, and then the PWM signal is turned off.

[0022] like Figure 2 As shown, the switching power supply control chip includes a voltage error amplifier, a resistor 1R, a resistor 2R, a current comparator, a logic circuit and a reference voltage source. The output end of the voltage error amplifier is connected to one end of the resistor 2R, the other end of the resistor 2R is connected to one end of the resistor 1R and the positive input of the current comparator, the other end of the resistor 1R is grounded, the output end of the current comparator is connected to the input end of the logic circuit, the output end of the logic circuit is the PWM control signal output pin Pin6_PWM of the switching power supply control chip, the negative input end of the current comparator is the current feedback signal pin Pin3_CS of the switching power supply control chip, and one end of the reference voltage source serves as the reference voltage pin Pin8 of the switching power supply control chip.

[0023] The voltage release circuit includes resistor R1, capacitor C1, resistor Rs, and N-channel MOS transistor Q1. Resistor Rs is connected between the source of N-channel MOS transistor Q1 and ground, converting the current signal flowing through the MOS transistor into a voltage signal. This signal is sent to the current feedback signal pin Pin3_CS, also known as the CS pin, through the RC filter circuit composed of resistor R1 and capacitor C1. The gate of N-channel MOS transistor Q1 is connected to the PWM control signal output pin Pin6_PWM, and the drain of N-channel MOS transistor Q1 is connected to inductor T1.

[0024] The discharge circuit includes a PNP transistor V1, an N-channel MOS transistor Q2, and a resistor R2. The emitter of the PNP transistor V1 is connected to the reference voltage pin Pin8, the base is connected to the PWM control signal output pin Pin6_PWM, and the collector is connected to the gate G of the N-channel MOS transistor Q2. The drain of the N-channel MOS transistor Q2 is connected to the current feedback signal pin Pin3_CS, and the source is connected to ground. The resistor R2 is connected between the gate and source of the MOS transistor Q2.

[0025] When the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a high level, the PNP transistor V1 is turned on, and the current flowing through the resistor Rs gradually increases; the PNP transistor V1 is turned off, the gate of the N-channel MOS transistor Q2 is at a low level, and the N-channel MOS transistor Q2 is in the off state. The amplitude of the current signal on the capacitor C1 gradually increases until the amplitude reaches the given voltage amplitude of the current loop input, and the PWM control signal output becomes low.

[0026] When the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a low level, the PNP transistor V1 is turned off, and the current flowing through the resistor Rs is zero. At this time, the PNP transistor V1 is turned on, the gate of the N-channel MOS transistor Q2 is high, the N-channel MOS transistor Q2 is in the on state, and the current signal on the capacitor C1 is released to zero level.

[0027] In this embodiment, the signal on the CS pin is a post-peak sawtooth waveform with an initial amplitude of 0V and a steep rising slope. Because the amplitude of the current sampling signal differs significantly from the amplitude of the current loop reference signal, the interference signal superimposed on the current sampling signal is insufficient to reach the amplitude of the current loop reference signal and thus does not trigger the PWM signal to shut down.

[0028] When Pin6_PWM of the switching power supply control chip outputs a high level, MOS transistor Q1 is turned on, and current passes through sampling resistor Rs and is converted into a voltage signal. This sampling signal enters Pin3_CS of the switching power supply control chip after passing through the RC filter circuit composed of resistor R1 and capacitor C1. When the voltage release circuit is not set, Pin3_CS is a high-impedance input pin. Due to the presence of the RC filter circuit, the voltage clock on Pin3_CS cannot drop to 0V. In addition, the voltage amplitude on Pin3_CS when MOS transistor Q1 is turned on and off is relatively small. When the interference signal is superimposed on the sampling signal on Pin3_CS, it is easy to malfunction, causing Pin6_PWM to be incorrectly shut down.

[0029] like Figure 2 As shown in the figure, the timing diagram of the control signal output by Pin6_PWM, the current loop given control signal and the current signal fed back by the Pin3_CS pin is shown. When Pin6_PWM outputs a high level, the voltage amplitude of the current signal of the Pin3_CS pin gradually increases until the voltage amplitude is equal to the current loop given control signal, and the control signal output by Pin6_PWM becomes a low level. The main difference between whether or not there is a CS pin voltage release circuit for the switching power supply control chip is whether the current signal fed back by the Pin3_CS pin can quickly drop to zero level when the control signal output by Pin6_PWM becomes a low level. Figure 2It can be seen that the starting value of the current signal in each switching cycle is zero level, which can tolerate the superposition of large interference signals and will not cause the output signal of Pin6_PWM to be incorrectly shut down.

[0030] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A CS pin voltage release circuit for a switching power supply control chip, characterized in that: The switching power supply control chip includes a voltage error amplifier, a resistor 1R, a resistor 2R, a current comparator, a logic circuit and a reference voltage source. The output end of the voltage error amplifier is connected to one end of the resistor 2R, the other end of the resistor 2R is connected to one end of the resistor 1R and the positive input of the current comparator, the other end of the resistor 1R is grounded, the output end of the current comparator is connected to the input end of the logic circuit, the output end of the logic circuit is the PWM control signal output pin Pin6_PWM of the switching power supply control chip, the negative input end of the current comparator is the current feedback signal pin Pin3_CS of the switching power supply control chip, that is, the CS pin, and one end of the reference voltage source serves as the reference voltage pin Pin8 of the switching power supply control chip; a discharge circuit is set near the CS pin. When the PWM signal is turned off, the voltage on the CS pin is reduced to 0V by releasing the residual energy. When the PWM signal of the next cycle is turned on, the discharge circuit is turned off, and the current sampling signal on the CS pin gradually rises from 0V until the amplitude is the same as the given signal amplitude of the current loop, and then the PWM signal is turned off; The voltage release circuit includes a resistor R1, a capacitor C1, a resistor Rs, and an N-channel MOS transistor Q1. The resistor Rs is connected between the source of the N-channel MOS transistor Q1 and ground, converting the current signal flowing through the MOS transistor into a voltage signal. The voltage signal is sent to the current feedback signal pin Pin3_CS through an RC filter circuit composed of the resistor R1 and the capacitor C1. The gate of the N-channel MOS transistor Q1 is connected to the PWM control signal output pin Pin6_PWM, and the drain of the N-channel MOS transistor Q1 is connected to the inductor T1. The discharge circuit includes a PNP transistor V1, an N-channel MOS transistor Q2, and a resistor R2. The emitter of the PNP transistor V1 is connected to the reference voltage pin Pin8, the base is connected to the PWM control signal output pin Pin6_PWM, and the collector is connected to the gate G of the N-channel MOS transistor Q2; the drain of the N-channel MOS transistor Q2 is connected to the current feedback signal pin Pin3_CS, and the source is connected to ground. The resistor R2 is connected between the gate and source of the MOS transistor Q2.

2. The CS pin voltage release circuit of the switching power supply control chip according to claim 1, characterized in that: When the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a high level, the PNP transistor V1 is turned on, and the current flowing through the resistor Rs gradually increases; the PNP transistor V1 is turned off, the gate of the N-channel MOS transistor Q2 is at a low level, and the N-channel MOS transistor Q2 is in the off state. The amplitude of the current signal on the capacitor C1 gradually increases until the amplitude reaches the given voltage amplitude of the current loop input, and the PWM control signal output becomes low.

3. The CS pin voltage release circuit of the switching power supply control chip according to claim 2, characterized in that: When the PWM control signal output pin Pin6_PWM of the switching power supply control chip outputs a low level, the PNP transistor V1 is turned off, and the current flowing through the resistor Rs is zero. At this time, the PNP transistor V1 is turned on, the gate of the N-channel MOS transistor Q2 is high, the N-channel MOS transistor Q2 is in the on state, and the current signal on the capacitor C1 is released to zero level.

4. The CS pin voltage release circuit of the switching power supply control chip according to claim 3, characterized in that: The signal on the CS pin is a trailing sawtooth wave with an initial amplitude of 0V and a subsequent rising edge.

5. The CS pin voltage release circuit of the switching power supply control chip according to claim 4, characterized in that: The current sampling signal amplitude differs greatly from the current loop given signal amplitude, so that the interference signal superimposed on the current sampling signal is insufficient to reach the current loop given signal amplitude, and will not trigger the shutdown of the PWM signal.

6. The CS pin voltage release circuit of the switching power supply control chip according to claim 5, characterized in that: Among the control signal output by Pin6_PWM, the current loop given control signal and the current signal fed back by the Pin3_CS pin, when Pin6_PWM outputs a high level, the voltage amplitude of the current signal of the Pin3_CS pin gradually increases until the voltage amplitude is equal to the current loop given control signal, and the control signal output by Pin6_PWM becomes a low level.

7. The CS pin voltage release circuit of the switching power supply control chip according to claim 6, characterized in that: When the control signal output by Pin6_PWM becomes low level, the current signal fed back by the Pin3_CS pin drops to zero level synchronously.

8. Application of the CS pin voltage release circuit of a switching power supply control chip according to any one of claims 1 to 7 in the field of switch control technology.

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