Wafer loading platform

Abstract

A wafer carrier has a high heat dissipation capacity and is not prone to damage. The wafer carrier (10) has a low manufacturing cost. The wafer carrier (10) comprises: a ceramic substrate (20) having a wafer carrier surface (22a) on its upper surface and an electrode (26) built therein; a cooling substrate (30) having a coolant flow path (38) formed therein; and a metal bonding layer (40) bonding the lower surface of the ceramic substrate (20) and the upper surface of the cooling substrate (30). The cooling substrate (30) comprises: a top substrate (81) made of a metal matrix composite material or a low thermal expansion metal material, constituting the top of the coolant flow path (38); a grooved substrate (83) made of a ceramic material having the same main component as the ceramic substrate (20), having a flow path groove (88) on its upper surface constituting the bottom and side walls of the coolant flow path (38); and a metal top bonding layer (82) bonding the lower surface of the top substrate (81) and the upper surface of the grooved substrate (83).

Description

Technical Field

[0001] The present invention relates to a wafer placing table. Background Art

[0002] In the past, a wafer carrier is known, which is obtained by bonding a ceramic substrate such as alumina implanted with an electrode for electrostatic adsorption and a cooling substrate containing a metal such as aluminum by means of a resin layer (for example, refer to patent document 1). According to this wafer carrier, the influence of the thermal expansion difference between the ceramic substrate and the cooling substrate can be alleviated by the resin layer. A wafer carrier is also known in which a ceramic substrate and a cooling substrate having a coolant flow path are bonded by using a metal bonding layer instead of a resin layer (for example, patent documents 2 and 3). The metal bonding layer has a higher thermal conductivity than the resin layer, and therefore can achieve the heat removal capacity required when processing the wafer using high-power plasma. On the other hand, the metal bonding layer has a larger Young's modulus and lower stress relaxation than the resin layer, and therefore can hardly alleviate the influence of the thermal expansion difference between the ceramic substrate and the cooling substrate. In patent documents 2 and 3, in order to make it less likely to be damaged due to the thermal expansion difference, a metal matrix composite material (MMC) having a smaller difference in thermal expansion coefficient with the ceramic substrate is used as the material of the cooling substrate.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 4-287344

[0006] Patent Document 2: Japanese Patent No. 5666748

[0007] Patent Document 3: Japanese Patent No. 5666749 Summary of the invention

[0008] However, MMC is more expensive than metals such as aluminum, and the cost of forming a coolant flow path is high due to its difficult processing, so the manufacturing cost of the wafer carrier is sometimes increased. In addition, it is also considered to use a low thermal expansion metal material with a small difference in thermal expansion coefficient with the ceramic substrate to replace MMC, but the low thermal expansion metal material is also expensive, and the cost of forming a coolant flow path is high due to its difficult processing, so the manufacturing cost of the wafer carrier is sometimes increased.

[0009] The present invention has been made to solve the above-mentioned problems, and its main object is to reduce the manufacturing cost of a wafer placement table that has a high heat dissipation capability and is less prone to damage.

[0010] The first wafer stage of the present invention comprises:

[0011] A ceramic substrate having a wafer placement surface on an upper surface and having electrodes built therein;

[0012] a cooling substrate having a refrigerant flow path formed therein; and

[0013] a metal bonding layer bonding the lower surface of the ceramic substrate and the upper surface of the cooling substrate,

[0014] The cooling substrate comprises: a top substrate made of a metal-based composite material or a low thermal expansion metal material, which constitutes the top of the refrigerant flow path; a grooved substrate made of a ceramic material whose main component is the same as that of the ceramic substrate, and flow grooves constituting the bottom and side walls of the refrigerant flow path are arranged on the upper surface of the grooved substrate; and a metal top bonding layer, which bonds the lower surface of the top substrate and the upper surface of the grooved substrate.

[0015] In the first chip carrier of the present invention, the top substrate of the cooling substrate adopts MMC or a low thermal expansion metal material, and the grooved substrate adopts a ceramic material that is relatively cheap and can form flow grooves at a relatively low cost using near-net forming technology. Therefore, the manufacturing cost of the chip carrier can be reduced. In addition, as the bonding layer between the ceramic substrate-top substrate and the top substrate-grooved substrate, a bonding layer made of metal with high thermal conductivity is used instead of a resin layer with low thermal conductivity. Therefore, the ability to take away heat from the chip (heat dissipation ability) is higher. In addition, the main component of the ceramic material constituting the grooved substrate is the same as the main component of the ceramic material constituting the ceramic substrate, so the absolute value of the difference in linear thermal expansion coefficient between the grooved substrate and the ceramic substrate is small. Therefore, the absolute value of the difference in linear thermal expansion coefficient between the ceramic substrate, the top substrate and the grooved substrate is small, and even if the stress relaxation of the bonding layer is low, it is not easy to cause problems.

[0016] It should be noted that in this specification, the low thermal expansion metal material refers to a metal material having a linear thermal expansion coefficient of 10×10 -6 / K or less metal material, preferably 9.0×10 -6 / K or less, more preferably 8.0×10 -6 / K or less. In addition, in this specification, the linear thermal expansion coefficient obtained by measuring the length at 40°C and 400°C is referred to as the linear thermal expansion coefficient of 40-400°C. In addition, in this specification, the main component refers to: a component that occupies more than 50% by mass of the total components included, preferably more than 70% by mass, and more preferably more than 90% by mass. In addition, in this specification, up and down, left and right, front and back, etc. are sometimes used to describe the present invention, but up and down, left and right, front and back are just relative positional relationships. Therefore, when the orientation of the chip carrier is changed, sometimes up and down becomes left and right, and left and right becomes up and down, and this situation is also included in the technical scope of the present invention.

[0017] The first wafer stage of the present invention may be: the absolute value of the difference in linear thermal expansion coefficient between the metal matrix composite material or low thermal expansion metal material constituting the top substrate and the ceramic material constituting the grooved substrate and the ceramic material constituting the ceramic substrate at 40 to 400°C is 1.5×10 -6 / K or less. According to this, even if the stress relaxation property of the bonding layer is low, problems are less likely to occur.

[0018] The first wafer stage of the present invention may be such that the ceramic material constituting the ceramic substrate is alumina, and the ceramic material constituting the grooved substrate is alumina having a purity lower than that of the alumina constituting the ceramic substrate. Thus, the grooved substrate can be manufactured at a lower cost.

[0019] The second wafer stage of the present invention comprises:

[0020] A ceramic substrate having a wafer placement surface on an upper surface and having electrodes built therein;

[0021] a cooling substrate having a refrigerant flow path formed therein; and

[0022] a metal bonding layer bonding the lower surface of the ceramic substrate and the upper surface of the cooling substrate,

[0023] The cooling substrate comprises: a top substrate made of a metal-based composite material or a low-thermal expansion metal material, which constitutes the top of the refrigerant flow path; a perforated substrate made of a ceramic material whose main component is the same as that of the ceramic substrate, and the flow path holes constituting the side walls of the refrigerant flow path pass through in the up and down directions; a bottom substrate, which constitutes the bottom of the refrigerant flow path; a metal top bonding layer, which bonds the lower surface of the top substrate and the upper surface of the perforated substrate; and a bottom bonding layer, which bonds the lower surface of the perforated substrate and the upper surface of the bottom substrate.

[0024] In the second wafer carrier of the present invention, the top substrate of the cooling substrate adopts MMC or low thermal expansion metal material, and on the other hand, the perforated substrate adopts a ceramic material that is relatively cheap and can form flow path holes at a relatively low cost using near-net forming technology. Therefore, the manufacturing cost of the wafer carrier can be reduced. In addition, as the bonding layer between the ceramic substrate-top substrate and the top substrate-perforated substrate, a metal bonding layer with high thermal conductivity is adopted instead of a resin layer with low thermal conductivity. Therefore, the ability to take away heat from the wafer (heat dissipation ability) is higher. In addition, the main component of the ceramic material constituting the perforated substrate is the same as the main component of the ceramic material constituting the ceramic substrate, so the absolute value of the difference in linear thermal expansion coefficient between the perforated substrate and the ceramic substrate is small. Therefore, the absolute value of the difference in linear thermal expansion coefficient between the ceramic substrate, the top substrate and the perforated substrate is small, and even if the stress relaxation of the bonding layer is low, it is not easy to cause problems.

[0025] The second wafer carrier of the present invention can be: the bottom substrate is made of a metal-based composite material or a low thermal expansion metal material, and the bottom bonding layer is made of metal. Accordingly, the absolute value of the difference in linear thermal expansion coefficient between the material constituting the ceramic substrate and the material constituting the bottom substrate is small, so the influence of the difference in linear thermal expansion coefficient between the ceramic substrate and the top substrate and the perforated substrate, and the influence of the difference in linear thermal expansion coefficient between the top substrate, the perforated substrate and the bottom substrate are eliminated, and the warping or breakage of the wafer carrier 10 can be suppressed. Therefore, the degree of freedom of the material constituting the top substrate and the perforated substrate is improved. In addition, since the perforated substrate and the bottom substrate are bonded with a metal bonding layer, the perforated substrate and the bottom substrate can be bonded at the same time as the ceramic substrate and the top substrate are bonded, and the top substrate and the perforated substrate are bonded, so that the wafer carrier can be manufactured efficiently.

[0026] The second wafer stage of the present invention may be: the absolute value of the difference in linear thermal expansion coefficient between the metal matrix composite material or low thermal expansion metal material constituting the top substrate and the ceramic material constituting the perforated substrate and the ceramic material constituting the ceramic substrate at 40 to 400°C is 1.5×10 -6 / K or less. According to this, even if the stress relaxation property of the bonding layer is low, problems are less likely to occur.

[0027] The second wafer stage of the present invention may be such that the ceramic material constituting the ceramic substrate is alumina, and the ceramic material constituting the perforated substrate is alumina having a purity lower than that of the alumina constituting the ceramic substrate. Thus, the perforated substrate can be manufactured at a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a longitudinal cross-sectional view of the wafer stage 10 installed in the chamber 94 .

[0029] Figure 2 It is a plan view of the wafer stage 10 .

[0030] Figure 3 This is a cross-sectional view when the wafer stage 10 is cut along the upper surface of the grooved substrate 83 and viewed from above.

[0031] Figure 4 It is a manufacturing process diagram of the wafer placement table 10.

[0032] Figure 5 It is a longitudinal cross-sectional view of the wafer placement table 210 .

[0033] Figure 6 It is a longitudinal sectional view of another embodiment of the wafer stage 10 .

[0034] Explanation of symbols

[0035] 10 wafer mounting table, 20 ceramic substrate, 22 central portion, 22a wafer mounting surface, 24 outer peripheral portion, 24a focusing ring mounting surface, 26 wafer adsorption electrode, 27 hole, 30 cooling substrate, 32 inner peripheral portion, 34 outer peripheral portion, 38 coolant flow path, 38a inlet, 38b outlet, 40 metal bonding layer, 42 insulating film, 52 wafer adsorption DC power supply, 53 low pass filter, 54 power supply terminal, 55 insulating tube, 62 RF power supply, 63 high pass filter, 64 power supply terminal, 66 through hole, 70 fastening member, 70a inner peripheral Step surface, 72 bolts, 78 focusing ring, 81 top substrate, 82 top bonding layer, 83 grooved substrate, 88 flow groove, 94 chamber, 96 setting plate, 98 nozzle, 110 joint, 120 ceramic sintered body, 130 MMC / ceramic block, 131, 132 through holes, 140 metal bonding layer, 181 MMC circular plate component, 182 top bonding layer, 183 grooved circular plate component, 210 wafer placement table, 230 cooling substrate, 283 perforated substrate, 284 bottom bonding layer, 285 bottom substrate, 288 flow hole. DETAILED DESCRIPTION

[0036] [First embodiment]

[0037] Hereinafter, a wafer stage 10 according to a first embodiment of the present invention will be described with reference to the drawings. Figure 1 1 is a longitudinal cross-sectional view of the wafer stage 10 provided in the chamber 94 (a cross-sectional view when cut along a plane including the central axis of the wafer stage 10). Figure 2 is a plan view of the wafer stage 10, Figure 3 This is a cross-sectional view when the wafer stage 10 is cut along the upper surface of the grooved substrate 83 as viewed from above. In the present specification, "to" indicating a numerical range is used to mean that the numerical values ​​described before and after it are included as the lower limit and the upper limit.

[0038] The wafer stage 10 is a member used when CVD or etching is performed on a wafer W using plasma, and is fixed to a mounting plate 96 provided inside a chamber 94 for semiconductor processes. The wafer stage 10 includes a ceramic substrate 20 , a cooling substrate 30 , and a metal bonding layer 40 .

[0039] The ceramic substrate 20 has an outer peripheral portion 24 having an annular focus ring placement surface 24a on the outer periphery of a central portion 22 having a circular wafer placement surface 22a. Hereinafter, the focus ring is sometimes abbreviated as "FR". A wafer W is placed on the wafer placement surface 22a, and a focus ring 78 is placed on the FR placement surface 24a. The ceramic substrate 20 is formed of a ceramic material represented by aluminum oxide, aluminum nitride, etc. The FR placement surface 24a is lowered by one level relative to the wafer placement surface 22a.

[0040] The central portion 22 of the ceramic substrate 20 has a built-in chip adsorption electrode 26 on the side close to the chip placement surface 22a. The chip adsorption electrode 26 is formed of a material containing, for example, W, Mo, WC, MoC, etc. The chip adsorption electrode 26 is a disk-shaped or mesh-shaped monopolar electrostatic electrode. The layer on the upper side of the chip adsorption electrode 26 in the ceramic substrate 20 functions as a dielectric layer. A chip adsorption DC power supply 52 is connected to the chip adsorption electrode 26 via a power supply terminal 54. The power supply terminal 54 is configured to pass through an insulating tube 55 configured in a through hole that penetrates the cooling substrate 30 and the metal bonding layer 40 in the up-down direction, and reach the chip adsorption electrode 26 from the lower surface of the ceramic substrate 20. A low-pass filter (LPF) 53 is provided between the chip adsorption DC power supply 52 and the chip adsorption electrode 26.

[0041] The cooling substrate 30 is a disk member having a diameter larger than that of the ceramic substrate 20, and has an inner peripheral portion 32 on which the ceramic substrate 20 is arranged, and an outer peripheral portion 34 extending relative to the outer periphery of the ceramic substrate 20. The cooling substrate 30 includes a top substrate 81, a grooved substrate 83, and a top bonding layer 82. The cooling substrate 30 has a coolant flow path 38 inside for circulating a coolant. The coolant flow path 38 is provided in a spiral shape from an inlet 38a to an outlet 38b ( Figure 3 The inlet 38a and the outlet 38b of the coolant flow path 38 penetrate the grooved substrate 83 in the up-down direction and are open at the bottom surface of the coolant flow path 38. The inlet 38a and the outlet 38b of the coolant flow path 38 are connected to a coolant cooling device (not shown). The coolant discharged from the outlet 38b is adjusted in temperature by the coolant cooling device and then returns to the inlet 38a to be supplied to the coolant flow path 38.

[0042] The top substrate 81 is a disk component made of a metal matrix composite material (MMC). The top substrate 81 constitutes the top of the coolant flow path 38. The absolute value of the difference in linear thermal expansion coefficient at 40 to 400°C between the MMC used for the top substrate 81 and the ceramic material used for the ceramic substrate 20 is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, more preferably 0.5×10 -6 / K or less. Examples of MMC include materials containing Si, SiC and Ti, materials obtained by impregnating a SiC porous body with Al and / or Si, and the like. The material containing Si, SiC and Ti is referred to as SiSiCTi, the material obtained by impregnating a SiC porous body with Al is referred to as AlSiC, and the material obtained by impregnating a SiC porous body is referred to as SiSiC. When the ceramic substrate 20 is an alumina substrate, the MMC used for the top substrate 81 is preferably AlSiC, SiSiCTi, or the like. For the linear thermal expansion coefficient of 40 to 400°C, alumina is 7.2×10 -6 / K, AlSiC (SiC75%) is 7.8×10 -6 / K,SiSiCTi is 7.3×10 -6 / K. When the ceramic substrate 20 is an aluminum nitride substrate, the MMC used for the top substrate 81 is preferably AlSiC, SiSiC, or the like. The linear thermal expansion coefficient of aluminum nitride at 40 to 400°C is 4.6×10 -6 / K, AlSiC (SiC85%) is 5.6×10 -6 / K. The top substrate 81 also functions as a high frequency (RF) electrode for plasma generation together with the metal bonding layer 40 and the metal top bonding layer 82. The power supply terminal 64 is arranged to pass through the through hole 66 that penetrates the grooved substrate 83 and the top bonding layer 82 in the up-down direction and reaches the lower surface of the top substrate 81. A high pass filter (HPF) 63 is arranged between the top substrate 81 and the RF power supply 62.

[0043] The grooved substrate 83 is a circular plate component made of ceramic material. Figure 3As shown, the upper surface of the grooved substrate 83 is provided with a flow path groove 88 constituting the bottom and side wall of the coolant flow path 38. The main component of the ceramic material used for the grooved substrate 83 is the same as the main component of the ceramic material used for the ceramic substrate 20. The main component refers to: a component that occupies more than 50% by mass of the total components contained, preferably more than 70% by mass, and more preferably more than 90% by mass. The absolute value of the difference in linear thermal expansion coefficient between ceramic materials with the same main component is small. The ceramic material constituting the grooved substrate 83 can be a material with the same main component as the main component of the ceramic material constituting the ceramic substrate 20 and low purity. For example, the ceramic substrate 20 can adopt alumina with higher purity (for example, alumina with more than 99%) from the viewpoint of improving the electrical properties as a dielectric layer, and the grooved substrate 83 can adopt alumina with lower purity (for example, alumina with 95%) from the viewpoint of improving mechanical properties such as toughness and reducing costs. Compared with materials with higher purity, materials with lower purity can contain more glass such as SiO2. The absolute value of the difference in linear thermal expansion coefficient between the ceramic material used for the grooved substrate 83 and the ceramic material used for the ceramic substrate 20 at 40 to 400° C. is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, more preferably 0.5×10 -6 The absolute value of the difference in linear thermal expansion coefficient between the ceramic material used for the grooved substrate 83 and the MMC used for the top substrate 81 at 40 to 400°C is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, more preferably 0.5×10 -6 / K or less.

[0044] The top bonding layer 82 is a metal bonding layer that bonds the lower surface of the top substrate 81 and the upper surface of the grooved substrate 83. The top bonding layer 82 can be, for example, a layer formed of solder or metal brazing. The top bonding layer 82 is formed using, for example, TCB (Thermal compression bonding). TCB refers to a well-known method of sandwiching a metal bonding material between two parts to be bonded and press-bonding the two parts under a state where the metal bonding material is heated to a temperature below the solidus temperature of the metal bonding material. The material of the top bonding layer 82 can be the same as the material of the metal bonding layer 40.

[0045] The metal bonding layer 40 bonds the lower surface of the ceramic substrate 20 and the upper surface of the cooling substrate 30. The metal bonding layer 40 may be, for example, a layer formed of solder or brazing metal. The metal bonding layer 40 is formed using, for example, TCB.

[0046] The side surface of the outer peripheral portion 24 of the ceramic substrate 20, the outer periphery of the metal bonding layer 40, and the side surface of the cooling substrate 30 are covered with an insulating film 42. Examples of the insulating film 42 include a thermal sprayed film of aluminum oxide, yttrium trioxide, and the like.

[0047] The wafer stage 10 is provided with a fastening member 70, which is mounted on a setting plate 96 provided inside the chamber 94. The fastening member 70 is an annular member having a substantially inverted L-shaped cross section, and has an inner peripheral step surface 70a. The wafer stage 10 and the setting plate 96 are integrated by the fastening member 70. In a state where the inner peripheral step surface 70a of the fastening member 70 is placed on the outer peripheral portion 34 of the cooling substrate 30 of the wafer stage 10, a bolt 72 is inserted from the upper surface of the fastening member 70 and screwed into a screw hole provided on the upper surface of the setting plate 96. The bolt 72 is installed at a plurality of locations (e.g., 8 locations, 12 locations) provided at equal intervals along the circumferential direction of the fastening member 70. The fastening member 70 and the bolt 72 may be made of an insulating material or a conductive material (metal, etc.).

[0048] Next, use Figure 4 , a manufacturing example of the wafer placement table 10 is described. Figure 4 1 is a manufacturing process diagram of the wafer stage 10. First, a ceramic powder compact is hot-pressed and fired to produce a disk-shaped ceramic sintered body 120 ( Figure 4 (A)). The ceramic sintered body 120 has a wafer adsorption electrode 26 built therein. Next, a hole 27 is provided from the lower surface of the ceramic sintered body 120 to the wafer adsorption electrode 26 ( Figure 4 (B)), insert the power supply terminal 54 into the hole 27, and join the power supply terminal 54 and the chip adsorption electrode 26 ( Figure 4 (C)).

[0049] At the same time, an MMC disk member 181 and a grooved disk member 183 made of a ceramic material and having flow path grooves 88 formed on the upper surface are manufactured. Figure 4 (D)). Next, a through hole 131 is formed in the MMC disk component 181, through holes 132 and 66 are formed in the grooved disk component 183, and an inlet 38a and an outlet 38b are formed in the grooved disk component 183. The power supply terminal 64 is connected to the lower surface of the MMC disk component 181 at a position opposite to the through hole 66. Figure 4(E)). When the ceramic sintered body 120 is made of alumina, the MMC disc component 181 is preferably made of SiSiCTi or AlSiC. This is because the thermal expansion coefficient of alumina is roughly the same as the thermal expansion coefficient of SiSiCTi and AlSiC. In addition, when the ceramic sintered body 120 is made of alumina, the grooved disc component 183 is preferably made of alumina with a lower purity than the ceramic sintered body 120. The grooved disc component 183 can be manufactured using, for example, near-net forming technology.

[0050] The SiSiCTi disc component can be made, for example, as follows. First, silicon carbide, metal Si and metal Ti are mixed to make a powder mixture. Next, the obtained powder mixture is formed into a disc-shaped molded body by uniaxial pressure forming, and the molded body is hot-pressed and sintered in an inert atmosphere to obtain a SiSiCTi disc component.

[0051] When the grooved circular plate component 183 is manufactured by using near-net forming technology, it can be manufactured as follows, for example. That is, a plurality of ceramic green sheets are stacked to manufacture a molded body of a predetermined shape such as the shape of the grooved substrate 83 after firing, and the molded body is fired at normal pressure, thereby obtaining the grooved substrate 83. It should be noted that the molded body can also be manufactured by die casting, and can also be manufactured by 3D printing using photoforming or the like. In addition, the molded body can also be manufactured as follows, that is, after manufacturing a grooveless circular plate molded body, a groove corresponding to the flow path groove 88 is formed by cutting or the like.

[0052] Next, metal bonding materials are respectively arranged on the upper surface of the MMC disc component 181 and the upper surface of the grooved disc component 183. Necessary through holes are pre-set in each metal bonding material. Then, the power supply terminal 64 of the MMC disc component 181 is inserted into the through hole 66 of the grooved disc component 183, and the MMC disc component 181 is placed on the metal bonding material arranged on the upper surface of the grooved disc component 183. Furthermore, the power supply terminal 54 of the ceramic sintered body 120 is inserted into the through hole 131 of the MMC disc component 181 and the through hole 132 of the grooved disc component 183, and the ceramic sintered body 120 is placed on the metal bonding material arranged on the upper surface of the MMC disc component 181. Accordingly, a stacked body is obtained by stacking the grooved disc component 183, the metal bonding material, the MMC disc component 181, the metal bonding material and the ceramic sintered body 120 in sequence from the bottom. The laminate is heated and pressurized (TCB) to obtain a bonded body 110 ( Figure 4(F)). The joint body 110 is obtained by joining the ceramic sintered body 120 to the upper surface of the MMC / ceramic block 130 which is the basis of the cooling substrate 30 by means of a metal bonding layer 140. The MMC / ceramic block 130 is obtained by joining the MMC disc part 181 and the grooved disc part 183 by means of a metal top bonding layer 182. The MMC / ceramic block 130 has a coolant flow path 38 inside.

[0053] TCB is performed, for example, as follows. That is, the stack is pressurized and joined at a temperature below the solidus temperature of the metal bonding material (for example, a temperature above the solidus temperature minus 20°C and below the solidus temperature), and then returned to room temperature. Accordingly, the metal bonding material becomes a metal bonding layer. As the metal bonding material at this time, Al-Mg bonding materials and Al-Si-Mg bonding materials can be used. For example, when TCB is performed using an Al-Si-Mg bonding material, the stack is pressurized in a heated state under a vacuum atmosphere. The metal bonding material preferably uses a metal bonding material with a thickness of about 100 μm.

[0054] Next, the periphery of the ceramic sintered body 120 is cut to form a step, thereby producing a ceramic substrate 20 having a central portion 22 and a peripheral portion 24. In addition, as necessary, the peripheries of the metal bonding layer 140 and the MMC / ceramic block 130 are cut to produce a metal bonding layer 40 and a cooling substrate 30. At this time, the peripheral portion 34 of the cooling substrate 30 is extended relative to the periphery of the ceramic substrate 20. In addition, an insulating tube 55 for inserting the power supply terminal 54 is arranged in the through holes 131, 132, the hole of the metal bonding layer 40, and the hole of the top bonding layer 82. Furthermore, ceramic powder is sprayed on the side of the peripheral portion 24 of the ceramic substrate 20, the periphery of the metal bonding layer 40, and the side of the cooling substrate 30, thereby forming an insulating film 42 ( Figure 4 (G)). Thus, the wafer placement table 10 is obtained.

[0055] Next, use Figure 1 , an example of using the wafer stage 10 is described. As described above, the wafer stage 10 is fixed to the setting plate 96 of the chamber 94 by the fastening member 70. A shower head 98 is arranged on the top surface of the chamber 94 to release the process gas into the chamber 94 from a plurality of gas injection holes.

[0056] A focus ring 78 is placed on the FR placement surface 24a of the wafer placement table 10, and a disc-shaped wafer W is placed on the wafer placement surface 22a. The focus ring 78 has a step along the inner circumference of the upper end so that it does not interfere with the wafer W. In this state, a DC voltage of the wafer adsorption DC power supply 52 is applied to the wafer adsorption electrode 26, so that the wafer W is adsorbed on the wafer placement surface 22a. Then, the interior of the chamber 94 is set to a predetermined vacuum atmosphere (or a reduced pressure atmosphere), and while supplying a process gas from the shower head 98, an RF voltage from the RF power supply 62 is applied to the top substrate 81. As a result, plasma is generated between the wafer W and the shower head 98. Then, CVD film formation or etching is performed on the wafer W using this plasma. It should be noted that the focus ring 78 is also consumed along with the plasma processing of the wafer W. However, since the focus ring 78 is thicker than the wafer W, the focus ring 78 is replaced after a plurality of wafers W are processed.

[0057] In the wafer carrier 10 of the first embodiment described above, the top substrate 81 of the cooling substrate 30 adopts MMC, and the grooved substrate 83 adopts a ceramic material that is relatively cheap and can form the flow path groove 88 at a low cost using near-net forming technology. Therefore, the manufacturing cost of the wafer carrier can be reduced. In addition, as the bonding layer between the ceramic substrate 20-top substrate 81 and the top substrate 81-grooved substrate 83, a metal bonding layer with high thermal conductivity is used instead of a resin layer with low thermal conductivity. Therefore, the heat dissipation capacity is high. In addition, since the main component of the ceramic material constituting the grooved substrate 83 is the same as the main component of the ceramic material constituting the ceramic substrate 20, the absolute value of the difference in linear thermal expansion coefficient between the grooved substrate 83 and the ceramic substrate 20 is small. Therefore, the absolute value of the difference in linear thermal expansion coefficient between the ceramic substrate 20, the top substrate 81 and the grooved substrate 83 is small, and even if the stress relaxation property of the bonding layer is low, it is not easy to cause problems.

[0058] In addition, the top substrate 81 of the cooling substrate 30, which is arranged in a portion where thermal stress is easily generated when the chip W is processed using high-power plasma (the portion higher than the coolant flow path 38), adopts MMC whose toughness is higher than that of ceramic materials. Therefore, even if thermal stress is generated, the chip carrier 10 is not easily damaged.

[0059] In addition, since MMC has conductivity, the top substrate 81 can also be used as an RF electrode, and there is no need to prepare an RF electrode separately. In addition, since the metal bonding layer 40 and the top bonding layer 82 are made of metal, these bonding layers can also be used as RF electrodes.

[0060] In the wafer stage 10, if the absolute values ​​of the differences in linear thermal expansion coefficients between the ceramic material constituting the ceramic substrate 20, the MMC constituting the top substrate 81, and the ceramic material constituting the grooved substrate 83 are all 1.5×10 -6 / K or less, even if the stress relaxation property of the bonding layer is low, problems are less likely to occur.

[0061] In addition, if the absolute value of the difference in linear thermal expansion coefficient between the ceramic material constituting the ceramic substrate 20 and the ceramic material constituting the grooved substrate 83 is small, the influence of the difference in linear thermal expansion coefficient between the ceramic substrate 20 and the top substrate 81 and the influence of the difference in linear thermal expansion coefficient between the top substrate 81 and the grooved substrate 83 are eliminated, and it is possible to suppress warping or damage of the wafer stage 10. Therefore, the degree of freedom of the material constituting the top substrate 81 is improved.

[0062] [Second embodiment]

[0063] Hereinafter, a wafer stage 210 according to a second embodiment of the present invention will be described with reference to the drawings. Figure 5 It is a longitudinal cross-sectional view of the wafer placement table 210 . Figure 5 In the present invention, the same components as those in the first embodiment are denoted by the same reference numerals.

[0064] The wafer stage 210 is a member used in the same manner as the wafer stage 10 . The wafer stage 210 includes a ceramic substrate 20 , a cooling substrate 230 , and a metal bonding layer 40 .

[0065] The cooling substrate 230 is a disk member having a diameter larger than that of the ceramic substrate 20. The cooling substrate 230 includes: a top substrate 81, a perforated substrate 283, a bottom substrate 285, a top bonding layer 82, and a bottom bonding layer 284. The cooling substrate 230 includes a coolant flow path 38 for coolant circulation inside. The inlet 38a and the outlet 38b of the coolant flow path 38 penetrate the bottom substrate 285 in the up-down direction and are open at the bottom surface of the coolant flow path 38.

[0066] The perforated substrate 283 is a disc member made of a ceramic material. In the perforated substrate 283, the flow path hole 288 constituting the side wall of the coolant flow path 38 is penetrated in the up-down direction. The details of the ceramic material used for the perforated substrate 283 are the same as the ceramic material used for the grooved substrate 83. The perforated substrate 283 can be manufactured using a near-net-shape forming technology.

[0067] The bottom substrate 285 is a circular plate component made of MMC. The bottom substrate 285 constitutes the bottom of the refrigerant flow path 38. The details of the MMC used for the bottom substrate 285 are the same as those of the MMC used for the top substrate 81. The MMC used for the bottom substrate 285 preferably has the same main component as the main component of the MMC used for the top substrate 81, but the main component may be different. The material of the MMC used for the bottom substrate 285 may be the same as that of the MMC used for the top substrate 81. The absolute value of the difference in linear thermal expansion coefficient at 40 to 400°C between the MMC used for the bottom substrate 285 and the ceramic material used for the ceramic substrate 20 is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, more preferably 0.5×10 -6 / K or less.

[0068] The bottom bonding layer 284 is a metal bonding layer that bonds the bottom surface of the perforated substrate 283 and the top surface of the bottom substrate 285. The bottom bonding layer 284 may be, for example, a layer formed of solder or metal brazing material. The bottom bonding layer 284 is formed using, for example, TCB. The material of the bottom bonding layer 284 may be the same as the material of at least one of the metal bonding layer 40 and the top bonding layer 82.

[0069] The wafer stage 210 may be configured as follows, for example: Figure 4 The wafer placing table 10 is manufactured according to a manufacturing example. Figure 4 The steps (A) to (C) are the same as those in the manufacturing example of the wafer stage 10 . Figure 4 In the process (D), an MMC disc component for the top, a perforated disc component made of ceramic material, and an MMC disc component for the bottom are made instead of making the MMC disc component 181 and the grooved disc component 183. The two MMC disc components are made according to the MMC disc component 181, and the perforated disc component is made according to the grooved disc component 183. Then, according to Figure 4 In step (E), through holes are formed in each of the two MMC disk components and the perforated disk component. Figure 4 Step (F) is to prepare a laminated body by stacking the bottom MMC disc component, the metal bonding material, the perforated disc component, the metal bonding material, the top MMC disc component, the metal bonding material, and the ceramic sintered body in order from the bottom, and the laminated body is bonded by TCB to prepare a bonded body. Finally, according to Figure 4 In step (G), cutting is performed to arrange the insulating tube 55 and form the insulating film 42. Thus, the wafer placement table 210 is obtained.

[0070] In the wafer carrier 210 of the second embodiment described above, the top substrate 81 of the cooling substrate 230 adopts MMC, and the perforated substrate 283 adopts a ceramic material that is relatively cheap and can form the flow path hole 288 at a low cost using near-net forming technology. Therefore, the manufacturing cost of the wafer carrier can be reduced. In addition, as the bonding layer between the ceramic substrate 20-top substrate 81 and the top substrate 81-perforated substrate 283, a metal bonding layer with high thermal conductivity is used instead of a resin layer with low thermal conductivity. Therefore, the heat dissipation capacity is high. In addition, since the main component of the ceramic material constituting the perforated substrate 283 is the same as the main component of the ceramic material constituting the ceramic substrate 20, the absolute value of the difference in linear thermal expansion coefficient between the perforated substrate 283 and the ceramic substrate 20 is small. Therefore, the absolute value of the difference in linear thermal expansion coefficient between the ceramic substrate 20, the top substrate 81 and the perforated substrate 283 is small, and even if the stress relaxation of the bonding layer is low, it is not easy to cause problems.

[0071] In addition, the top substrate 81 of the cooling substrate 230, which is arranged at a portion where thermal stress is easily generated when the wafer W is processed using high-power plasma, uses MMC having toughness higher than that of ceramic materials. Therefore, even if thermal stress is generated, the wafer placement table 210 is not easily damaged.

[0072] In addition, since MMC has conductivity, the top substrate 81 can also be used as an RF electrode, and there is no need to prepare an RF electrode separately. In addition, since the metal bonding layer 40, the top bonding layer 82 and the bottom bonding layer 284 are made of metal, these bonding layers can also be used as RF electrodes. It should be noted that the bottom substrate 285 made of MMC can also be used as an RF electrode.

[0073] Furthermore, the bottom substrate 285 is made of MMC, and the absolute value of the difference in linear thermal expansion coefficient between the bottom substrate 285 and the ceramic material constituting the ceramic substrate 20 is small, so the influence of the difference in linear thermal expansion coefficient between the ceramic substrate 20 and the top substrate 81 and the perforated substrate 283, and the influence of the difference in linear thermal expansion coefficient between the top substrate 81, the perforated substrate 283 and the bottom substrate 285 are eliminated, and the warping or damage of the wafer stage 210 can be suppressed. Therefore, the degree of freedom of the material constituting the top substrate 81 and the perforated substrate 283 is improved.

[0074] Furthermore, since the perforated substrate 283 and the bottom substrate 285 are bonded together using a metal bottom bonding layer 284, the perforated substrate 283 and the bottom substrate 285 can be bonded together at the same time as the ceramic substrate 20 and the top substrate 81 are bonded together, and the top substrate 81 and the perforated substrate 283 are bonded together, thereby enabling the chip carrier 210 to be manufactured efficiently.

[0075] It should be noted that the bottom substrate 285 has little effect on the heat dissipation capacity, and therefore, it can be bonded using a resin layer or the like. Therefore, the bottom substrate 285 may not be made of MMC, and may be made of, for example, a high thermal expansion metal (such as aluminum) with a relatively large linear thermal expansion coefficient, or may be made of ceramics, or may be made of resin. In addition, the bottom bonding layer 284 may not be made of metal, and may be made of, for example, resin.

[0076] In the wafer stage 210, if the absolute values ​​of the differences in linear thermal expansion coefficients between the ceramic material constituting the ceramic substrate 20, the MMC constituting the top substrate 81, and the ceramic material constituting the through-hole substrate 283 are all 1.5×10 -6 / K or less, even if the stress relaxation property of the bonding layer is low, it is less likely to cause problems. In addition, if the absolute values ​​of the differences in linear thermal expansion coefficients between the MMCs constituting the bottom substrate 285 and each other are all 1.5×10 -6 / K or less, even if the stress relaxation property of the bonding layer is low, problems are less likely to occur.

[0077] It should be noted that the present invention is not limited to the above-described embodiment and can be implemented in various forms as long as they fall within the technical scope of the present invention.

[0078] For example, in the wafer stage 10 of the first embodiment, a hole penetrating the wafer stage 10 may be provided so as to reach from the lower surface of the cooling substrate 30 to the wafer stage 22a. Examples of such holes include a gas supply hole for supplying a heat-conducting gas (e.g., He gas) to the back side of the wafer W, and a lift pin hole for inserting a lift pin for moving the wafer W up and down relative to the wafer stage 22a. The heat-conducting gas is supplied to a space formed by a plurality of small protrusions (not shown) provided on the wafer stage 22a (supporting the wafer W) and the wafer W. The lift pin holes are provided at three locations when the wafer W is supported by, for example, three lift pins. Similarly, the wafer stage 210 of the second embodiment may be provided with a gas supply hole, a lift pin hole, and the like.

[0079] In the wafer placement table 10 of the first embodiment described above, the cooling substrate 30 is a disk member without a step. However, it may be Figure 6 The upper surface of the outer peripheral portion 34 is lowered by one level relative to the upper surface of the inner peripheral portion 32 to form a stepped disc member. Figure 6 In the embodiment, although a step is provided on the periphery of the grooved substrate 83, the position of the step is not particularly limited, and a step may be provided on the periphery of the top substrate 81. The wafer stage 210 of the second embodiment is similar, and a step may be provided on the periphery of one or more of the top substrate 81, the perforated substrate 283, and the bottom substrate 285.

[0080] In the wafer stage 10 of the first embodiment described above, the top substrate 81 is made of MMC, but it may be made of a low thermal expansion metal material. In this case, the low thermal expansion metal material is preferably a metal material with high toughness and conductivity, as with MMC. In addition, the absolute value of the difference in linear thermal expansion coefficient between the low thermal expansion metal material and the ceramic material used for the ceramic substrate 20 at 40 to 400°C is preferably 1.5×10 -6 / K or less. Examples of low thermal expansion metal materials include molybdenum, tungsten, etc. For example, when the ceramic substrate 20 is an aluminum nitride substrate, the top substrate made of a low thermal expansion metal material may be a molybdenum substrate. For the linear thermal expansion coefficient of 40 to 400°C, aluminum nitride is 4.6×10 -6 / K, molybdenum is 5.6×10 -6 / K. Similarly, the wafer stage 210 of the second embodiment can also make the top substrate 81 made of a low thermal expansion metal material. In this case, the bottom substrate 285 can also be made of a low thermal expansion metal material. In addition, in the wafer stage 210 of the second embodiment, one of the top substrate 81 and the bottom substrate 285 can be made of MMC, and the other can be made of a low thermal expansion metal material.

[0081] In the first and second embodiments described above, a chip adsorption electrode 26 is built into the central portion 22 of the ceramic substrate 20. However, an RF electrode for plasma generation may be built in instead of the chip adsorption electrode 26, or an RF electrode for plasma generation may be built in in addition to the chip adsorption electrode 26. In this case, a high-frequency power supply is connected to the RF electrode instead of the top substrate 81. In addition, a focusing ring (FR) adsorption electrode may be built in the outer peripheral portion 24 of the ceramic substrate 20. In this case, a DC power supply is connected to the FR adsorption electrode. In addition, a heater electrode (resistive heating element) may be built into the ceramic substrate 20. In this case, the heater power supply is connected to the heater electrode. In this way, the ceramic substrate 20 may have one layer of electrodes built in, or may have two or more layers of electrodes built in.

[0082] In the first and second embodiments described above, the refrigerant flow path 38 is arranged in a spiral shape from the inlet 38a to the outlet 38b, but the planar shape of the refrigerant flow path 38 is not particularly limited. In addition, a plurality of refrigerant flow paths 38 may be provided. In addition, the cross section of the refrigerant flow path 38 is rectangular, but the cross-sectional shape of the refrigerant flow path 38 is not particularly limited. For example, the upper corner in the cross section of the refrigerant flow path 38 may be a curved surface (R surface). Accordingly, cracks can be prevented from being generated starting from the upper corner in the cross section of the refrigerant flow path. In this case, the curved surface may be provided on the top substrate 81.

[0083] In the first embodiment described above, Figure 4The ceramic sintered body 120 of (A) is produced by hot pressing a molded body of ceramic powder, but the molded body at this time may be produced by laminating a plurality of tape-cast molded bodies, may be produced by die casting, or may be produced by compacting ceramic powder. The same is true for the second embodiment.

[0084] In the first embodiment described above, the grooved disc member 183 having the flow path groove 88 is manufactured, and then the through holes 132, 66, the inlet 38a, and the outlet 38b are formed. However, the grooved disc member 183 having the through holes 132, 66, the inlet 38a, and the outlet 38b may be manufactured by using a near-net-shape forming technique. The same is true in the second embodiment.

Claims

1. A wafer loading platform, wherein: have: A ceramic substrate having a wafer placement surface on an upper surface and having electrodes built therein; a cooling substrate having a refrigerant flow path formed therein; and a metal bonding layer bonding the lower surface of the ceramic substrate and the upper surface of the cooling substrate, The cooling substrate comprises: a top substrate made of a metal-based composite material or a low thermal expansion metal material, which constitutes the top of the refrigerant flow path; a grooved substrate made of a ceramic material whose main component is the same as that of the ceramic substrate, and flow grooves constituting the bottom and side walls of the refrigerant flow path are arranged on the upper surface of the grooved substrate; and a metal top bonding layer, which bonds the lower surface of the top substrate and the upper surface of the grooved substrate.

2. The wafer stage according to claim 1, wherein: The absolute value of the difference in linear thermal expansion coefficient between the metal matrix composite material or low thermal expansion metal material constituting the top substrate and the ceramic material constituting the grooved substrate and the ceramic material constituting the ceramic substrate at 40 to 400°C is 1.5×10 -6 / below K.

3. The wafer stage according to claim 1 or 2, wherein: The ceramic material constituting the ceramic substrate is alumina, and the ceramic material constituting the grooved substrate is alumina having a purity lower than that of the alumina constituting the ceramic substrate.

4. A wafer loading platform, wherein: have: A ceramic substrate having a wafer placement surface on an upper surface and having electrodes built therein; a cooling substrate having a refrigerant flow path formed therein; and a metal bonding layer bonding the lower surface of the ceramic substrate and the upper surface of the cooling substrate, The cooling substrate comprises: a top substrate made of a metal-based composite material or a low-thermal expansion metal material, which constitutes the top of the refrigerant flow path; a perforated substrate made of a ceramic material having the same main component as the main component of the ceramic substrate, and the flow path holes constituting the side walls of the refrigerant flow path penetrate in the up-down direction; a bottom substrate, which constitutes the bottom of the refrigerant flow path; a metal top bonding layer, which bonds the lower surface of the top substrate and the upper surface of the perforated substrate; and a bottom bonding layer bonding the lower surface of the perforated substrate and the upper surface of the bottom substrate.

5. The wafer stage according to claim 4, wherein: The bottom substrate is made of a metal-based composite material or a low thermal expansion metal material, and the bottom bonding layer is made of metal.

6. The wafer stage according to claim 4 or 5, wherein: The absolute value of the difference in linear thermal expansion coefficient between the metal matrix composite material or low thermal expansion metal material constituting the top substrate and the ceramic material constituting the perforated substrate and the ceramic material constituting the ceramic substrate at 40 to 400°C is 1.5×10 -6 / below K.

7. The wafer stage according to claim 4 or 5, wherein: The ceramic material constituting the ceramic substrate is alumina, and the ceramic material constituting the perforated substrate is alumina having a purity lower than that of the alumina constituting the ceramic substrate.

8. The wafer stage according to claim 6, wherein: The ceramic material constituting the ceramic substrate is alumina, and the ceramic material constituting the perforated substrate is alumina having a purity lower than that of the alumina constituting the ceramic substrate.

Images