FPGA-based asynchronous sampling method, device, storage medium and system

Abstract

The application discloses an asynchronous sampling method and device based on FPGA, a storage medium and a system. The application compares real data with monitoring data continuously to obtain the phase position of a sampling clock edge relative to a real data bit, and adjusts the position of the clock edge in the data bit to an optimal sampling position in real time, so that the timing performance is improved, and the timing convergence pressure is reduced.

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