Multi-channel CMOS image synchronous transmission integration method and system thereof

Abstract

The present application relates to the technical field of space wide area imaging, and particularly relates to a multi-channel CMOS image synchronous transmission integration method and system; in the present application, a high-precision time code, a us pulse synchronization signal and a delay shooting instruction are sent by a master control unit, the high-precision time code and the us pulse synchronization signal are sent to CMOS board A, CMOS board B, CMOS board C and CMOS board D of a detector module by an imaging control board, self-keeping is carried out according to the high-precision time code and the us pulse synchronization signal, so that the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are synchronously driven and shot, channel data monitoring modules record image data receiving delay information of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D, so that effective detection images are integrated, and the effective detection images after integration are output by image packetization by the detector module.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of space wide area imaging technology, in particular to a multi-channel CMOS image synchronous transmission integration method and system. BACKGROUND

[0002] Space targets mainly refer to all on-orbit spacecraft and space debris beyond 100km from the surface of the earth, which specifically includes space stations, artificial satellites, asteroids and debris caused by space target impact.

[0003] With the increasing number of space launch projects, the number and types of space targets have also increased a lot, which has increased the security risks for the safe and orderly operation of spacecraft in orbit. With the complex space environment, countries are working hard to develop space target imaging systems.

[0004] The traditional method of the current space target imaging system mainly uses a smaller instantaneous field of view to scan and detect the entire space domain, so the search update rate is slow, and it cannot meet the needs of simultaneous observation of multiple targets and rapid identification of new targets and dynamic targets. SUMMARY

[0005] The technical problem solved by the present application is to provide a multi-channel CMOS image synchronous transmission integration method, which sends a high-precision time code, a us pulse synchronization signal and a delay shooting instruction from the master control unit, sends the high-precision time code and the us pulse synchronization signal to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module by the imaging control board, and drives and shoots the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D synchronously according to the high-precision time code and the us pulse synchronization signal, monitors the synchronous image data and records the image data reception delay information of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D by the channel data monitoring module, thereby integrating effective detection images, and outputs the integrated effective detection images by the detector module.

[0006] To solve the above technical problems, one technical solution adopted by the present application is to provide a multi-channel CMOS image synchronous transmission integration method, which comprises the following steps:

[0007] Step S1, the master unit sends high-precision time code, the imaging control board sends the high-precision time code to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; at the same time, the master unit also sends the us pulse synchronization signal, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the CMOS board A, CMOS board B, CMOS board C and CMOS board D are synchronously driven;

[0008] Step S2, the master unit sends the delay shooting instruction, and the imaging control board sends the delay shooting instruction to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D are self-protected, so that the CMOS board A, CMOS board B, CMOS board C and CMOS board D are synchronously shot;

[0009] Step S3, the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module output images for synchronous data transmission;

[0010] Step S4, the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module synchronously send image data to the imaging control board, the imaging control board receives the synchronous image data, monitors the synchronous image data, and records the image data reception delay information of the CMOS board A, CMOS board B, CMOS board C and CMOS board D, the imaging control board sends the image data reception delay information to the master unit, the master unit sends the image data permission delay time to the imaging control board, and the imaging control board judges the validity of the image data of the CMOS board A, CMOS board B, CMOS board C and CMOS board D through the image data permission delay time;

[0011] Step S5, the imaging control board integrates the valid detection image, and the detector module outputs the integrated valid detection image in image packet.

[0012] As an improvement of the present application, in step S1, the main control unit sends a high-precision time code to the communication module b in the imaging control board, and the imaging control board sends the high-precision time code to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the communication unit 1, the communication unit 2, the communication unit 3 and the communication unit 4 respectively; at the same time, the main control unit sends a us pulse synchronization signal to the synchronization unit c, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the synchronization unit 1, the synchronization unit 2, the synchronization unit 3 and the synchronization unit 4 respectively; the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the four-way signals of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are synchronously driven.

[0013] As a further improvement of the present application, in step S2, the main control unit sends a delay shooting instruction to the communication module b in the imaging control board, and the imaging control board sends the delay shooting instruction to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the communication unit 1, the communication unit 2, the communication unit 3 and the communication unit 4 respectively; the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the four-way signals of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are synchronously driven.

[0014] As a further improvement of the present application, in step S3, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module respectively transmit image data to the data transmission unit 1, the data transmission unit 2, the data transmission unit 3 and the data transmission unit 4 in the imaging control board, and the imaging control board transmits the image data to the main control unit through the data transmission unit a.

[0015] As a further improvement of the present application, in step S3, the data transmission unit 1, the data transmission unit 2, the data transmission unit 3, the data transmission unit 4 and the data transmission unit a all adopt 120Mhz same frequency clock.

[0016] As a further improvement of the present application, in step S3, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D output image adopt the transmission mechanism of sending 1 row of image data and waiting for 3 rows of image data.

[0017] As a further improvement of the present application, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are all provided with a CMOS1 detector and a CMOS2 detector.

[0018] As a further improvement of the present application, in step S4, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module synchronously send image data to the imaging control board through the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four, the imaging control board receives the synchronous image data of the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four through the receiving module one, the receiving module two, the receiving module three and the receiving module four respectively and monitors the detector data validity through the channel data monitoring module, the channel data monitoring module records the image data receiving delay information of the CMOS1 detector and the CMOS2 detector on the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D through the counter respectively, then the channel data monitoring module sends the synchronous delay information of the CMOS1 detector and the CMOS2 detector of the CMOS board A, the CMOS1 detector and the CMOS2 detector of the CMOS board B, the CMOS1 detector and the CMOS2 detector of the CMOS board C and the CMOS1 detector and the CMOS2 detector of the CMOS board D to the host unit through the communication module via the communication unit b, the host unit feeds back the sending four-way image data allowed delay time to the channel data monitoring module to the communication module through the communication unit b, and the channel data monitoring module judges the validity of the image data of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D through the image data allowed delay time.

[0019] A multi-channel CMOS image synchronous transmission integrated system, comprising:

[0020] A host unit for sending high-precision time code and us pulse synchronization signal for control;

[0021] An imaging control board for receiving the high-precision time code and the us pulse synchronization signal sent by the host unit and sending the high-precision time code and the us pulse synchronization signal to the detector module;

[0022] A detector module comprising a CMOS board A, a CMOS board B, a CMOS board C and a CMOS board D for detection.

[0023] As a further improvement of the present application, the imaging control board comprises: a data transmission unit one for receiving image data of CMOS board A, a data transmission unit two for receiving image data of CMOS board B, a data transmission unit three for receiving image data of CMOS board C, a data transmission unit four for receiving image data of CMOS board D, a data transmission unit a for transmitting image data of the imaging control board to the master control unit, a sending module for sending image data, a communication unit one for sending high-precision time code to CMOS board A, a communication unit two for sending high-precision time code to CMOS board B, a communication unit three for sending high-precision time code to CMOS board C, a communication unit four for sending high-precision time code to CMOS board D, a communication module for sending and receiving signal instructions, a synchronization unit one for sending us pulse synchronization signals to CMOS board A, a synchronization unit two for sending us pulse synchronization signals to CMOS board B, a synchronization unit three for sending us pulse synchronization signals to CMOS board C, a synchronization unit four for sending us pulse synchronization signals to CMOS board D, a receiving module one for receiving synchronization image data of the data transmission unit one, a receiving module two for receiving synchronization image data of the data transmission unit two, a receiving module three for receiving synchronization image data of the data transmission unit three, a receiving module four for receiving synchronization image data of the data transmission unit four, and a channel data monitoring module for monitoring the validity of the detector data.

[0024] The present application has the following advantages: compared with the prior art, the master control unit of the present application sends high-precision time code, us pulse synchronization signals and delay shooting instructions, the imaging control board sends the high-precision time code and the us pulse synchronization signals to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module, and the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are driven and shot synchronously according to the high-precision time code and the us pulse synchronization signals, the channel data monitoring module monitors the synchronization image data and records the image data reception delay information detected by the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D, so as to integrate the effective detection image, and the detector module outputs the integrated effective detection image in the form of image packet. BRIEF DESCRIPTION OF DRAWINGS

[0025] Fig. 1 The step block diagram of the multi-channel CMOS image synchronous transmission integration method of the present application;

[0026] Fig. 2 The image data transmission integration structure block diagram of the present application;

[0027] Fig. 3 The image data transmission integration timing diagram of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and do not limit the present application.

[0029] In recent years, array cameras have been applied in space target detection, which has the advantages of expanding the field of view and high detection capability; the present application proposes a multi-channel CMOS image synchronous transmission integration method and system for multi-detector array imaging system, which is easy to realize in embedded software and has important significance for practical engineering project application.

[0030] Please refer to Figs. 1 to 3 The multi-channel CMOS image synchronous transmission integration method of the present application comprises the following steps:

[0031] Step S1, the master control unit sends a high-precision time code, and the imaging control board sends the high-precision time code to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; at the same time, the master control unit also sends a us pulse synchronization signal, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the CMOS board A, CMOS board B, CMOS board C and CMOS board D are synchronously driven;

[0032] Step S2, the master control unit sends a delay shooting instruction, and the imaging control board sends the delay shooting instruction to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module are self-protected, so that the CMOS board A, CMOS board B, CMOS board C and CMOS board D are synchronously shot;

[0033] Step S3, the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module output images for synchronous data transmission line synchronous transmission;

[0034] Step S4, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module synchronously send image data to the imaging control board, the imaging control board receives and monitors the synchronous image data and records the image data receiving delay information detected by the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D, the imaging control board sends the image data receiving delay information to the main control unit, the main control unit sends the image data allowable delay time to the imaging control board, and the imaging control board judges the validity of the image data of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D through the image data allowable delay time;

[0035] Step S5, the imaging control board integrates the valid detection image, and the detector module outputs the integrated valid detection image in image groups.

[0036] In the application, the main control unit sends a high-precision time code, a us pulse synchronization signal and a delay shooting instruction, the imaging control board sends the high-precision time code and the us pulse synchronization signal to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are self-protected according to the high-precision time code and the us pulse synchronization signal, so as to be synchronously driven and shot, the channel data monitoring module monitors the synchronous image data and records the image data receiving delay information detected by the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D, so as to integrate the valid detection image, and the detector module outputs the integrated valid detection image in image groups.

[0037] In the application, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are respectively provided with two detectors of CMOS1 and CMOS2, the two detectors of CMOS1 and CMOS2 are domestic devices GSENSE6060 high-resolution CMOS image sensors, the synchronization unit C, the synchronization unit one, the synchronization unit two, the synchronization unit three and the synchronization unit four are realized by RS422, the data transmission unit a, the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four are realized by domestic devices JSR2711, the clock of the data transmission unit a, the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four is 120Mhz, and the single-frame image transmission time of the camera is better than 3s.

[0038] In the application, the integration transmission of the images of four non-homologous crystal oscillator circuit boards is realized without cache, the clock of the image output of the four detector circuit boards is 120Mhz, the image output clock of the imaging control board after integration is also 120Mhz, and the integration is carried out according to the timing. Fig. 3

[0039] ​Wherein, in step S1, the main control unit sends high-precision time code to the communication module b in the imaging control board, and the imaging control board sends the high-precision time code to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module through the communication unit one, communication unit two, communication unit three and communication unit four respectively; at the same time, the main control unit sends the us pulse synchronization signal to the synchronization unit c, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module through the synchronization unit one, synchronization unit two, synchronization unit three and synchronization unit four respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the four-way signal of the CMOS board A, CMOS board B, CMOS board C and CMOS board D is synchronously driven.

[0040] In step S2, the main control unit sends a delay shooting instruction to the communication module b in the imaging control board, and the imaging control board sends the delay shooting instruction to the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module through the communication unit one, communication unit two, communication unit three and communication unit four respectively; the CMOS board A, CMOS board B, CMOS board C and CMOS board D are self-protected, so that the CMOS board A, CMOS board B, CMOS board C and CMOS board D are synchronously shot; since the imaging control board has no cache, the output images of the four non-homogeneous crystal oscillator detector boards need to be synchronized, so that the image integration can output the images in sequence, and the synchronization unit is used to transmit the synchronization pulse signal; at the same time, the CMOS board A, CMOS board B, CMOS board C and CMOS board D receive the time code sent by the main control unit, and the CMOS board A, CMOS board B, CMOS board C and CMOS board D are self-protected according to the synchronization signal and the time code, so that each detector board has the same time, and the CMOS board A, CMOS board B, CMOS board C and CMOS board D realize synchronous data transmission, synchronous shooting and synchronous driving according to the time.

[0041] In step S3, the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module respectively transmit image data to the data transmission unit one, data transmission unit two, data transmission unit three and data transmission unit four in the imaging control board, and the imaging control board transmits the image data to the main control unit through the data transmission unit a; the data transmission unit one, data transmission unit two, data transmission unit three, data transmission unit four and data transmission unit a all adopt 120Mhz same frequency clock; the transmission mechanism of the CMOS board A, CMOS board B, CMOS board C and CMOS board D outputting image data is that one row of image data is sent and three rows of image data are waited.

[0042] In the present application, CMOS board A, CMOS board B, CMOS board C and CMOS board D are provided with CMOS1 detector and CMOS2 detector.

[0043] In step S4, the CMOS board A, CMOS board B, CMOS board C and CMOS board D of the detector module synchronously send image data to the imaging control board through the data transmission unit one, data transmission unit two, data transmission unit three and data transmission unit four, the imaging control board receives the synchronous image data of the data transmission unit one, data transmission unit two, data transmission unit three and data transmission unit four through the receiving module one, receiving module two, receiving module three and receiving module four respectively, and monitors the detector data validity through the channel data monitoring module, the channel data monitoring module records the image data receiving delay information of the CMOS1 detector and CMOS2 detector on the CMOS board A, CMOS board B, CMOS board C and CMOS board D through the counter respectively, then the channel data monitoring module sends the synchronous delay information of the CMOS1 detector and CMOS2 detector of the CMOS board A, CMOS1 detector and CMOS2 detector of the CMOS board B, CMOS1 detector and CMOS2 detector of the CMOS board C, and CMOS1 detector and CMOS2 detector of the CMOS board D to the main control unit through the communication module via the communication unit b, the main control unit feeds back the sending four-way image data allowable delay time to the channel data monitoring module through the communication unit b to the communication module, the channel data monitoring module judges the validity of the image data of the CMOS board A, CMOS board B, CMOS board C and CMOS board D through the image data allowable delay time; when the data delay information of a certain way exceeds the threshold value, it is considered that the detector of this way is abnormal, and the channel data monitoring module adopts the fifo buffer unit based on the ping-pong structure.

[0044] The imaging control board has no cache, and can be designed to save circuit cost. Since the space device is relatively high in price, the imaging control board requires the CMOS board A, CMOS board B, CMOS board C and CMOS board D to output image synchronous data transmission line synchronization (synchronization of four CMOS boards is realized by high-precision time code self-keeping time, that is, the four CMOS boards output the first row, the second row, … at the same time); if the image synchronization of the four CMOS boards is particularly good, they will reach the imaging control board together (as shown in Fig. 3 If the CMOS board B is broken and cannot output image data, the channel monitoring module will wait for one row of image time, and when there is no image in this channel, it will start to read the image of the next circuit board. For example, at this time, the original order 1234 becomes 134, but the imaging control board still waits for one row of time when judging the missing 2.

[0045] In step S5, the imaging control board sequentially outputs images according to the CMOS1 detector of the CMOS board A, the CMOS1 detector of the CMOS board B, the CMOS1 detector of the CMOS board C, the CMOS1 detector of the CMOS board D, the CMOS2 detector of the CMOS board A, the CMOS2 detector of the CMOS board B, the CMOS2 detector of the CMOS board C, and the CMOS2 detector of the CMOS board D. When it is identified in the channel data monitoring module in step S4 that an abnormality occurs in a certain piece of detector, the imaging control board discards the image output of the piece of detector, and the output images of other detectors are sequentially outputted.

[0046] An embodiment of the present application includes the following steps:

[0047] Step one: synchronous driving, the master control unit sends a high-precision time code to the communication module b, and the imaging control board sends the high-precision time code to the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D through the communication unit one, the communication unit two, the communication unit three, and the communication unit four; the master control unit sends a us pulse synchronization signal to the synchronization unit c, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D through the synchronization unit one, the synchronization unit two, the synchronization unit, and the synchronization unit four; the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D perform self-keeping time according to the high-precision time code and the us pulse synchronization signal, and realize the synchronous driving function of the 8 pieces of CMOS detectors of the 4 CMOS boards.

[0048] Step two: synchronous shooting: the master control unit sends a delay shooting instruction to the communication module b, and the imaging control board sends the delay shooting instruction to the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D through the communication unit one, the communication unit two, the communication unit three, and the communication unit four, and then the master control unit completes the synchronous shooting of the 8 pieces of CMOS detectors of the 4 CMOS boards through the self-keeping time function in step one.

[0049] Step three: synchronous data transmission line synchronization: since the 4 CMOS boards have 4 data transmission units for outputting image data, the 4 data transmission units include the data transmission unit one, the data transmission unit two, the data transmission unit three, and the data transmission unit four, and the imaging control board has only one data transmission unit a for external interface, and the 5 data transmission units adopt a 120Mhz same frequency clock, therefore, the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D are respectively designed with SDRAM cache units, the CMOS board A, the CMOS board B, the CMOS board C, and the CMOS board D adopt a transmission mechanism of sending 1 row of image data and waiting for 3 rows of image data for outputting image, and synchronous data transmission line synchronization is realized through the self-keeping time function in step one.

[0050] Step four: channel data monitoring and detector bad patch identification: CMOS board A, CMOS board B, CMOS board C and CMOS board D synchronously send image data to the imaging control board through the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four, the imaging control board receives the synchronous image data of the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four through the receiving module one, the receiving module two, the receiving module three and the receiving module four, and monitors the validity of the detector data through the channel data monitoring module, the channel data monitoring module is a fifo buffer unit based on the ping-pong structure, the image data receiving delay information of the two CMOS1 and CMOS2 detectors on the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D is recorded through the counter respectively, then the channel data monitoring module sends the synchronous delay information of the CMOS board A-CMOS1 and CMOS2, the CMOS board B-CMOS1 and CMOS2, the CMOS board C-CMOS1 and CMOS2 and the CMOS board D-CMOS1 and CMOS2 to the host unit through the communication module; the host unit can send the four-way image data allowable delay time to the channel data monitoring module through the communication module; the channel data monitoring module judges the validity of the four-way eight-piece image data through the image data allowable delay time, and considers that the detector of the detector board is abnormal when the data delay information exceeds the threshold.

[0051] Step five: image integration and detector image packet output: two detectors are arranged on the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D, the imaging control board outputs images in the order of CMOS board A-CMOS1 detector, CMOS board B-CMOS1 detector, CMOS board C-CMOS1 detector, CMOS board D-CMOS1 detector, CMOS board A-CMOS2 detector, CMOS board B-CMOS2 detector, CMOS board C-CMOS2 detector and CMOS board D-CMOS2 detector, when it is identified in step four that an abnormality occurs in a certain piece of detector, the imaging control board discards the image output of the piece of detector, and the order of the image output of the other detectors remains unchanged.

[0052] The application also provides a multi-channel CMOS image synchronous transmission integration system, comprising:

[0053] A host unit is used for sending high-precision time code and us pulse synchronization signals for control;

[0054] An imaging control board is used for receiving the high-precision time code and the us pulse synchronization signals sent by the host unit and sending the high-precision time code and the us pulse synchronization signals to the detector module;

[0055] The detector module comprises a CMOS plate A, a CMOS plate B, a CMOS plate C and a CMOS plate D for detection.

[0056] The CMOS plate A, the CMOS plate B, the CMOS plate C and the CMOS plate D are each provided with a CMOS1 detector and a CMOS2 detector.

[0057] The imaging control board comprises:

[0058] The first data transmission unit is configured to receive image data of the CMOS plate A.

[0059] The second data transmission unit is configured to receive image data of the CMOS plate B.

[0060] The third data transmission unit is configured to receive image data of the CMOS plate C.

[0061] The fourth data transmission unit is configured to receive image data of the CMOS plate D.

[0062] The data transmission unit a is configured to transmit image data of the imaging control board to the main control unit.

[0063] The sending module is configured to send image data.

[0064] The first communication unit is configured to send a high-precision time code to the CMOS plate A.

[0065] The second communication unit is configured to send a high-precision time code to the CMOS plate B.

[0066] The third communication unit is configured to send a high-precision time code to the CMOS plate C.

[0067] The fourth communication unit is configured to send a high-precision time code to the CMOS plate D.

[0068] The communication module is configured to send and receive signal instructions.

[0069] The first synchronization unit is configured to send a us pulse synchronization signal to the CMOS plate A.

[0070] The second synchronization unit is configured to send a us pulse synchronization signal to the CMOS plate B.

[0071] The third synchronization unit is configured to send a us pulse synchronization signal to the CMOS plate C.

[0072] The fourth synchronization unit is configured to send a us pulse synchronization signal to the CMOS plate D.

[0073] The first receiving module is configured to receive synchronized image data of the first data transmission unit.

[0074] The second receiving module is configured to receive synchronized image data of the second data transmission unit.

[0075] a third receiving module, configured to receive the synchronous image data of the third data transmission unit;

[0076] a fourth receiving module, configured to receive the synchronous image data of the fourth data transmission unit;

[0077] a channel data monitoring module, configured to monitor the validity of the detector data.

[0078] The present application realizes the synchronous shooting of multiple detectors and the high-speed transmission of images downstream, and the transmission time of a single frame of image is less than 3s, which has practical application value.

[0079] The above merely describes the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent flow transformation made by using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for multi-lane CMOS image synchronous transmission integration, characterized in that, Comprise the following steps: Step S1, the master unit sends high-precision time code, the imaging control board sends the high-precision time code to the CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module respectively;The master unit also sends the us pulse synchronization signal, and the imaging control board sends the us pulse synchronization signal to the CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module respectively;The CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module are synchronized by high-precision time code and us pulse synchronization signal and are driven synchronously; Step S2, the master unit sends the delay shooting instruction, and the imaging control board sends the delay shooting instruction to the CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module respectively;The CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module are synchronized by self-keeping and are synchronously photographed; Step S3, the CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module output image and are synchronously transmitted; Step S4, the CMOS board A, CMOS board B, CMOS board C, CMOS board D of detector module synchronously send image data to the imaging control board, and the imaging control board receives synchronous image data and monitors synchronous image data and records the image data reception delay information of CMOS board A, CMOS board B, CMOS board C, CMOS board D detection, and the imaging control board sends the image data reception delay information to the master unit, and the master unit sends the image data permission delay time to the imaging control board, and the imaging control board judges the validity of the image data of CMOS board A, CMOS board B, CMOS board C, CMOS board D through the image data permission delay time; Step S5, the imaging control board integrates effective detection image, and the detector module outputs the integrated effective detection image in image packet; In step S1, the main control unit sends a high-precision time code to the communication module b in the imaging control board, which sends the high-precision time code to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the communication unit one, the communication unit two, the communication unit three and the communication unit four respectively; meanwhile, the main control unit sends a us pulse synchronization signal to the synchronization unit c, which sends the us pulse synchronization signal to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the synchronization unit one, the synchronization unit two, the synchronization unit three and the synchronization unit four respectively; the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module are self-protected according to the high-precision time code and the us pulse synchronization signal, so that the four-way signal of the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D is synchronously driven. The imaging control board has no cache, and needs four non-homogeneous crystal oscillator CMOS boards to output image synchronization, so as to realize image integration and output image in sequence; the four synchronization units of the imaging control board are used for transmitting the us pulse synchronization signal respectively, and the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D receive the high-precision time code sent by the main control unit; when the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are self-protected according to the us pulse synchronization signal and the high-precision time code, it is equivalent that each CMOS board has the same time; the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D realize synchronous data transmission, synchronous shooting and synchronous driving according to the time.

2. The method of claim 1, wherein the method further comprises: In step S2, the main control unit sends a delay shooting instruction to the communication module b in the imaging control board, which sends the delay shooting instruction to the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module through the communication unit one, the communication unit two, the communication unit three and the communication unit four respectively; the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module are self-protected, so that the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D are synchronously shot.

3. The method of claim 2, wherein the method further comprises: In step S3, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D of the detector module transmit image data to the data transmission unit one, the data transmission unit two, the data transmission unit three and the data transmission unit four in the imaging control board respectively, and the imaging control board transmits the image data to the main control unit through the data transmission unit a.

4. The method of claim 3, wherein the method further comprises: In step S3, the data transmission unit one, the data transmission unit two, the data transmission unit three, the data transmission unit four and the data transmission unit a all adopt 120Mhz same frequency clock.

5. The method of claim 4, wherein the method further comprises: In step S3, the CMOS board A, the CMOS board B, the CMOS board C and the CMOS board D output image adopt the transmission mechanism of sending 1 row of image data and waiting for 3 rows of image data.

6. The method of claim 5, wherein the method further comprises: CMOS board A, CMOS board B, CMOS board C, CMOS board D are provided with CMOS1 detector and CMOS2 detector.

7. The method of claim 6, wherein the method further comprises: In step S4, the CMOS board A, CMOS board B, CMOS board C, CMOS board D of the detector module synchronously send image data to the imaging control board through the data transmission unit one, data transmission unit two, data transmission unit three and data transmission unit four, the imaging control board receives the synchronous image data of the data transmission unit one, data transmission unit two, data transmission unit three and data transmission unit four through the receiving module one, receiving module two, receiving module three and receiving module four respectively, and monitors the detector data validity through the channel data monitoring module, the channel data monitoring module records the image data receiving delay information of the CMOS1 detector and CMOS2 detector on the CMOS board A, CMOS board B, CMOS board C and CMOS board D through the counter respectively, then the channel data monitoring module sends the synchronous delay information of the CMOS1 detector and CMOS2 detector of the CMOS board A, the CMOS1 detector and CMOS2 detector of the CMOS board B, the CMOS1 detector and CMOS2 detector of the CMOS board C, the CMOS1 detector and CMOS2 detector of the CMOS board D to the main control unit through the communication module via the communication unit b, the main control unit feeds back the four-way image data allowed delay time to the channel data monitoring module through the communication unit b to the communication module, and the channel data monitoring module judges the validity of the image data of the CMOS board A, CMOS board B, CMOS board C and CMOS board D through the image data allowed delay time.

8. A multi-lane CMOS image synchronous transmission integration system, characterized in that, The multi-channel CMOS image synchronous transmission integration method according to any one of claims 1 to 7 is adopted; The multi-channel CMOS image synchronous transmission integration system comprises: The main control unit is used for sending high-precision time code and us pulse synchronization signal for control; The imaging control board is used for receiving the high-precision time code and us pulse synchronization signal sent by the main control unit and sending the high-precision time code and us pulse synchronization signal to the detector module; The detector module comprises CMOS board A, CMOS board B, CMOS board C and CMOS board D for detection.

9. The integrated system of claim 8, wherein, The imaging control board comprises: a data transmission unit one for receiving image data of the CMOS board A, a data transmission unit two for receiving image data of the CMOS board B, a data transmission unit three for receiving image data of the CMOS board C, a data transmission unit four for receiving image data of the CMOS board D, a data transmission unit a for transmitting image data of the imaging control board to a host unit, a sending module for sending image data, a communication unit one for sending high-precision time code to the CMOS board A, a communication unit two for sending high-precision time code to the CMOS board B, a communication unit three for sending high-precision time code to the CMOS board C, a communication unit four for sending high-precision time code to the CMOS board D, a communication module for sending and receiving signal instructions, a synchronization unit one for sending a us pulse synchronization signal to the CMOS board A, a synchronization unit two for sending a us pulse synchronization signal to the CMOS board B, a synchronization unit three for sending a us pulse synchronization signal to the CMOS board C, a synchronization unit four for sending a us pulse synchronization signal to the CMOS board D, a receiving module one for receiving synchronization image data of the data transmission unit one, a receiving module two for receiving synchronization image data of the data transmission unit two, a receiving module three for receiving synchronization image data of the data transmission unit three, a receiving module four for receiving synchronization image data of the data transmission unit four, and a channel data monitoring module for monitoring the validity of the detector data.

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