A PCB with a loss test area and a design method and a use method thereof
By changing the differential traces to single-ended traces in the loss test area of the PCB board, the problems of large space occupation and high cost in the existing technology are solved, and higher material utilization and test accuracy are achieved.
Patent Information
- Application Number
- CN202211736319.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-31
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2042-12-31
AI Technical Summary
In the existing design of loss test areas on PCB boards, the traces and vias for differential signals occupy a large amount of space, which affects the utilization rate of the board material and increases costs. At the same time, the reduction in test samples leads to a decrease in accuracy.
The differential traces in the loss test area were changed to single-ended traces. The loss data of the differential transmission line was obtained through the single-ended test line. The differential vias that occupy a large area were removed to preserve the test accuracy.
Without compromising test accuracy, the size of the loss test area was reduced, costs were lowered, and the utilization rate of the board material was improved.
Smart Images
Figure CN116170937B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of PCB signal integrity testing technology, specifically relating to a PCB board with a loss test area, its design method, and its usage method. Background Technology
[0002] As digital signal rates increase, signal integrity design becomes increasingly important. Only by optimizing the design of various factors that cause distortion in high-speed signals can the accurate transmission of information be guaranteed. Factors causing signal distortion mainly include crosstalk between signal networks and reflection and loss caused by the signal transmission medium itself. Because the transmission path has equivalent series and parallel resistances, there will inevitably be some energy loss when the signal is transmitted through this medium. Furthermore, since high-frequency components suffer greater loss than low-frequency components, this often leads to rising-side degradation, causing a series of signal integrity problems such as inter-symbol interference (ISI) and eye diagram collapse.
[0003] In server products, high-speed signals have high frequencies; for example, PCIe signals can reach up to 16GHz. To avoid severe signal distortion, energy loss during PCB transmission is significant. To address this, PCBs are typically optimized and upgraded using boards with lower dissipation factors to effectively reduce losses and ensure accurate signal transmission to the receiver. While lower dissipation factors result in less signal loss, they also increase costs. Therefore, PCB selection must meet signal loss requirements while avoiding resource waste due to overly optimized boards. Critical design places higher demands on the process stability of PCB manufacturers. To prevent losses from fluctuating due to manufacturing processes and failing to meet loss specifications, PCB loss monitoring is necessary, leading to the development of PCB loss testing areas, or coupons.
[0004] Monitoring PCB material loss using the PCB loss test area coupon involves designing a trace with the same impedance as the PCB on the coupon board and obtaining loss data for this trace at different frequencies.
[0005] To improve anti-interference capabilities, high-speed signals commonly employ differential mode. This involves applying two signals of equal amplitude but opposite direction to two transmission lines with equal line width and fixed spacing, known as differential transmission lines. After transmitting the same distance to the receiving end, the two signals are compared to obtain the differential signal voltage, thus achieving differential signal transmission. To obtain loss data for high-speed signals in differential transmission lines, a loss test area (coupon) is typically designed at the edge of the PCB board. The dimensions of the traces on the coupon board are identical to those on the PCB board, meaning the line width and spacing are the same. Differential vias are added at both ends of the traces. To accurately obtain the trace loss, de-embedding is necessary. Therefore, the coupon board typically uses multiple sets of test lines; for example, three different trace lengths are usually used to test three sets of trace loss data.
[0006] Because PCBs are usually cut from a large piece of material, they need to be properly spliced together to increase the utilization rate of the material. The remaining material after cutting the PCB will be used to make the coupon board. The existing coupon design requires three sets of differential signal lines and three pairs of differential vias, which takes up a lot of space, increases the difficulty of splicing, and may even affect the utilization rate of the material, resulting in increased costs.
[0007] To avoid increasing costs, the current approach to reducing board utilization by changing the wiring from 3 sets to 2 sets when coupons affect board utilization is to address the issue. While this ensures board utilization, it reduces the number of test samples, lowers the accuracy of the results, and prevents its widespread application.
[0008] This is a shortcoming of the existing technology. Therefore, it is very necessary to provide a PCB board with a loss test area and its design and usage methods to address the above-mentioned defects in the existing technology. Summary of the Invention
[0009] The existing PCB boards use differential signals for high-speed signals, and the coupon board design has three sets of loss lines and differential vias, which occupy a lot of space, increase the difficulty of board assembly, affect the utilization rate of the board material, and cause increased costs. The present invention provides a PCB board with a loss test area, as well as its design method and usage method, to solve the above technical problems.
[0010] In a first aspect, the present invention provides a PCB board with a loss test area, comprising a PCB board, the surface of the PCB board having a main board area and a loss test area, the main board area being disposed in the middle of the surface of the PCB board, and the loss test area being disposed at the outer edge of the main board area.
[0011] The main layout area of the PCB board is equipped with pairs of differential transmission lines;
[0012] The two differential transmission lines in a pair have the same line width and a fixed line spacing;
[0013] The loss test area is equipped with a preset number and preset length of single-ended test lines, and the line width of the single-ended test lines is the same as that of the differential transmission lines.
[0014] Each single-ended test lead has a via at both ends;
[0015] The length difference between different single-ended test lines is greater than the set length threshold.
[0016] Furthermore, three single-ended test leads are provided on the loss test area, with lengths of 2 inches, 5 inches, and 10 inches, respectively. These three single-ended test leads are used to de-embed the loss.
[0017] Furthermore, the single-ended test line in the loss test area is connected to a loss tester;
[0018] The loss tester is connected to a probe via a cable;
[0019] The via of the single-ended test lead is connected to the probe of the loss tester;
[0020] The loss tester reads the loss values of the single-ended test line at different frequency signal lines, thereby calculating the loss value of the differential transmission line. The loss tester acquires loss data for each single-ended test line at different frequencies.
[0021] Secondly, the present invention provides a PCB board design method with a loss testing area, the specific steps of which are as follows:
[0022] S 1. Verify that the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal;
[0023] S 2. Change the differential test lines in the original PCB board's loss test area to single-ended test lines, thereby reducing the size of the original PCB board's loss test area.
[0024] Furthermore, the specific steps of step S1 are as follows:
[0025] S 11. According to the S-parameter theory, a transmission signal line and upper and lower reference planes equidistant from the transmission signal line are preset to form a four-port transmission line;
[0026] S 12. The loss generated by the signal transmission from port P1 to port P2 is defined as S21, the loss generated by the transmission from port P3 to port P4 is defined as S43, the far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23.
[0027] S 13. The differential loss S generated after the differential signals input from ports P1 and P3 reach ports P2 and P4. DD21 Represented as:
[0028] S DD21 =0.5×(S) 21 +S 43 -S 41 -S 23 );
[0029] S 14.S 41 and S 23 The magnitude is calculated based on the far-end crosstalk factor (FEXT) between transmission lines, and the formula for calculating the far-end crosstalk factor (FEXT) is:
[0030]
[0031] Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L Capacitance and inductance per unit length along the signal path;
[0032] S 15. The preset signal transmission line is a symmetrical strip line. Since the medium around the signal transmission line is homogeneous and uniform, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same, that is, C_ml / C_L-L_ml / L_L=0. The far-end crosstalk coefficient FEXT is determined to be 0, that is, there is no far-end crosstalk.
[0033] S16. Since S41 and S23 are both 0, the differential calculation formula for differential signal transmission lines can be simplified to:
[0034] S DD21 =0.5×(S) 21 +S 43 );
[0035] S 16. Furthermore, according to the original loss test area coupon, the differential test lines are all symmetrical. Symmetrical differential test lines all have S21 = S43, therefore S DD21 =S 21 =S 43 ;
[0036] S 17. When the PCB stack-up is set to symmetrical striplines, the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal.
[0037] Furthermore, the specific steps of step S2 are as follows:
[0038] S 21. Locate each pair of differential test lines in the loss test area of the original PCB board;
[0039] S 22. Delete one differential test line and its corresponding via from each pair of differential test lines, and keep one differential test line and its single-ended via as a single-ended test line.
[0040] Thirdly, the present invention provides a method for using a PCB board with a loss testing area based on the first aspect described above, comprising the following steps:
[0041] SS 1. Connect the loss tester to each single-ended test line in sequence and obtain the loss value of each single-ended test line at different frequencies;
[0042] SS2. Based on the loss value of each single-ended test line at different frequencies, calculate the loss per unit length of the trace, and then calculate the loss value of the differential transmission line at different frequencies.
[0043] Furthermore, the specific steps of step SS 1 are as follows:
[0044] SS 11. Connect the loss tester to the 2-inch single-ended test line through the probe of the corresponding cable, and read the set frequency loss value of the 2-inch single-ended test line as S1.
[0045] SS 12. Connect the loss tester to the 5-inch single-ended test cable through the probe of the corresponding cable, and read the set frequency loss value of the 5-inch single-ended test cable as S 2.
[0046] SS 13. Connect the loss tester to the 10-inch single-ended test line through the corresponding cable probe, and read the set frequency loss value of the 10-inch single-ended test line as S3.
[0047] Furthermore, the specific steps of step SS 2 are as follows:
[0048] SS21. Calculate the 3-inch single-ended test line loss value by subtracting the 5-inch single-ended test line loss value S2 from the 2-inch single-ended test line loss value S1.
[0049] SS22. Calculate the loss value of the 5-inch single-ended test line by subtracting the loss value S3 of the 10-inch single-ended test line from the loss value S2 of the 5-inch single-ended test line.
[0050] SS23. Calculate the loss per unit length of trace at a given frequency.
[0051] SS24. Calculate the loss value of the differential transmission line using the loss S per unit length of trace at a set frequency.
[0052] Furthermore, the specific steps of step SS 24 are as follows:
[0053] SS241. Obtain the length Ninch of the differential transmission line under test;
[0054] SS242. Calculate the loss value of this differential transmission line.
[0055] The beneficial effects of this invention are as follows:
[0056] The PCB board with loss test area provided by this invention, along with its design and usage methods, changes the differential trace test lines of the loss test area coupon board to single-ended trace test lines without affecting test accuracy, and also eliminates the differential vias that occupy a large area, effectively reducing the size of the loss coupon board and helping to reduce costs.
[0057] Furthermore, the design principle of this invention is reliable, the structure is simple, and it has a very wide range of application prospects.
[0058] Therefore, it is evident that the present invention has outstanding substantive features and significant progress compared with the prior art, and the beneficial effects of its implementation are also obvious. Attached Figure Description
[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0060] Figure 1 This is a schematic diagram of the PCB board structure with a loss testing area according to the present invention.
[0061] Figure 2 This is a schematic diagram illustrating the principle of verifying that the differential signal loss in the loss test area of a PCB board is equal to the loss of its single-ended trace.
[0062] Figure 3 This is a schematic diagram of the PCB board design method with a loss test area according to the present invention.
[0063] Figure 4 This is a schematic diagram of the process for using a PCB board with a loss testing area according to the present invention.
[0064] In the diagram, 1-PCB board; 2-Main board area; 3-Loss test area; 4-Differential transmission line; 5-Single-ended test line. Detailed Implementation
[0065] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.
[0066] Example 1:
[0067] like Figure 1 As shown, the present invention provides a PCB board with a loss test area, including a PCB board 1. The surface of the PCB board 1 has a main board area 2 and a loss test area 3. The main board area 2 is located in the middle of the surface of the PCB board 1, and the loss test area 3 is located at the outer edge of the main board area 2.
[0068] The main layout area 2 of PCB board 1 is equipped with pairs of differential transmission lines 4;
[0069] The two differential transmission lines 4 in a pair have the same line width and a fixed line spacing;
[0070] The loss test area 3 is equipped with a preset number and preset length of single-ended test lines 5, and the line width of the single-ended test lines 5 is the same as the line width of the differential transmission line 4.
[0071] Each single-ended test lead 5 has a via at both ends;
[0072] The length difference of different single-ended test lines 5 is greater than the set length threshold.
[0073] The PCB board with a loss test area provided by this invention changes the differential trace test lines of the loss test area coupon board to single-ended trace test lines without affecting the test accuracy, and also removes the differential vias that occupy a large area, effectively reducing the size of the loss coupon board and helping to reduce costs.
[0074] Example 2:
[0075] like Figure 1 As shown, the present invention provides a PCB board with a loss test area, including a PCB board 1. The surface of the PCB board 1 has a main board area 2 and a loss test area 3. The main board area 2 is located in the middle of the surface of the PCB board 1, and the loss test area 3 is located at the outer edge of the main board area 2.
[0076] The main layout area 2 of PCB board 1 is equipped with pairs of differential transmission lines 4;
[0077] The two differential transmission lines 4 in a pair have the same line width and a fixed line spacing;
[0078] The loss test area 3 is equipped with a preset number and preset length of single-ended test lines 5, and the line width of the single-ended test lines 5 is the same as the line width of the differential transmission line 4.
[0079] Each single-ended test lead 5 has a via at both ends;
[0080] The length difference of different single-ended test lines 5 is greater than the set length threshold.
[0081] Three single-ended test lines 5 are set on the loss test area 3, and the lengths of the three single-ended test lines are 2 inches, 5 inches and 10 inches respectively;
[0082] The single-ended test line 5 in the loss test area 3 is connected to a loss tester;
[0083] The loss tester is connected to a probe via a cable;
[0084] The via of single-ended test lead 5 is connected to the probe of the loss tester;
[0085] The loss tester reads the loss value of the single-ended test line 5 at different frequency signal lines, and then calculates the loss value of the differential transmission line 4.
[0086] In the above embodiment 2, the loss data tested by the loss tester is the sum of the loss of the trace, via, probe and cable. In order to accurately obtain the loss of the trace, the via, probe and cable need to be de-embedded. Therefore, there is more than one single-ended test line on the loss area coupon board. Usually, three lengths of traces of 2 / 5 / 10 inches are used.
[0087] Using a loss tester, the loss data S1, S2, and S3 of 2 / 5 / 10-inch traces were measured respectively. S2-S1 represents the loss of a 3-inch trace, and S3-S2 represents the loss of a 5-inch trace. The loss per unit length of trace, S, can be expressed as:
[0088]
[0089] In the above embodiment 2, the differential transmission line 4 can be located on the same PCB layer or on different PCB layers. Taking PCIe signal as an example, the industry standard for differential trace impedance is 85 ohms. Based on the stack-up structure of the PCB board, the trace width W and trace spacing P of the 85 ohm PCB differential transmission line can be calculated using impedance calculation software. Except for densely traced areas such as BGA, the PCIe differential signal traces on the board should all follow the size requirements of W and P. The single-ended test line 6 of the loss test area 3 also has a trace width of W.
[0090] like Figure 2Taking the four-port transmission line shown as an example, the signal loss from port P1 to port P2 is defined as S21, and the signal loss from port P3 to port P4 is defined as S43. The far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23. Then, the differential loss S generated by the differential signals input from ports P1 and P3 to ports P2 and P4 is S23. DD21 It can be represented as:
[0091] S DD21 =0.5×(S) 21 +S 43 -S 41 -S 23 )
[0092] S 41 and S 23 The magnitude depends on the far-end crosstalk coefficient FEXT between transmission lines, which is calculated using the following formula:
[0093]
[0094] Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L For example, the capacitance and inductance per unit length along the signal path. Figure 2 The symmetrical stripline shown has a homogeneous and uniformly distributed dielectric surrounding the signal transmission line. In this case, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same. Therefore, the far-end crosstalk coefficient FEXT is 0, and thus there is no far-end crosstalk.
[0095] At this point, both S41 and S23 are 0, and the differential calculation formula for the differential signal can be simplified to:
[0096] S DD21 =0.5×(S) 21 +S 43 )
[0097] Furthermore, because the differential test lines in the original loss test area coupon are all symmetrical, and symmetrical differential test lines all have S... 21 =S 43 Therefore S DD21 =S 21 =S 43 ;
[0098] As can be seen from the above derivation process, when the PCB stack-up is designed as follows... Figure 2When the symmetrical stripline is shown, the differential signal loss of the original loss test area coupon is equal to the loss of its single-ended trace. Therefore, in order to reduce the size of the loss test area coupon, we change the differential transmission line to a single-ended trace and obtain the loss data of the differential transmission line on the PCB by the loss of the single-ended test line.
[0099] Since the loss of a single-ended test line can represent the loss of a differential transmission line, the three sets of differential test lines on the loss test area coupon board were changed to three single-ended test lines. The corresponding six pairs of differential vias were also changed to six differential vias. This not only avoids reducing the number of test line sets but also preserves the original test accuracy. This achieves the reduction of the size of the loss test area coupon board, ensuring the utilization rate of PCB materials, and without reducing test accuracy.
[0100] Example 3:
[0101] like Figure 3 As shown, this invention provides a PCB board design method with a loss testing area, the specific steps of which are as follows:
[0102] S 1. Verify that the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal;
[0103] S2. Change the differential test lines in the original PCB board's loss test area to single-ended test lines, thereby reducing the size of the original PCB board's loss test area.
[0104] The PCB design method with a loss test area provided by this invention changes the differential trace test lines of the loss test area coupon board to single-ended trace test lines without affecting the test accuracy, and also removes the differential vias that occupy a large area, effectively reducing the size of the loss coupon board and helping to reduce costs.
[0105] Example 4:
[0106] like Figure 3 As shown, this invention provides a PCB board design method with a loss testing area, the specific steps of which are as follows:
[0107] S 1. Verify that the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal;
[0108] The specific steps of step S1 are as follows:
[0109] S 11. According to the S-parameter theory, a transmission signal line and upper and lower reference planes equidistant from the transmission signal line are preset to form a four-port transmission line;
[0110] S 12. The loss generated by the signal transmission from port P1 to port P2 is defined as S21, the loss generated by the transmission from port P3 to port P4 is defined as S43, the far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23.
[0111] S 13. The differential loss S generated after the differential signals input from ports P1 and P3 reach ports P2 and P4. DD21 Represented as:
[0112] S DD21 =0.5×(S) 21 +S 43 -S 41 -S 23 );
[0113] S 14.S 41 and S 23 The magnitude is calculated based on the far-end crosstalk factor (FEXT) between transmission lines, and the formula for calculating the far-end crosstalk factor (FEXT) is:
[0114]
[0115] Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L Capacitance and inductance per unit length along the signal path;
[0116] S 15. The preset signal transmission line is a symmetrical strip line. Since the medium around the signal transmission line is homogeneous and uniform, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same, that is, C_ml / C_L-L_ml / L_L=0. The far-end crosstalk coefficient FEXT is determined to be 0, that is, there is no far-end crosstalk.
[0117] S16. Since S41 and S23 are both 0, the differential calculation formula for differential signal transmission lines can be simplified to:
[0118] S DD21 =0.5×(S) 21 +S 43 );
[0119] S 16. Furthermore, according to the original loss test area coupon, the differential test lines are all symmetrical. Symmetrical differential test lines all have S21 = S43, therefore S DD21 =S 21 =S 43 ;
[0120] S 17. When the PCB stack-up is set to symmetrical stripline, the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal.
[0121] S2. Change the differential test lines in the original PCB board's loss test area to single-ended test lines, reducing the size of the original PCB board's loss test area; the specific steps of step S2 are as follows:
[0122] S21. Locate each pair of differential test lines in the loss test area of the original PCB board;
[0123] S22. Delete one differential test line and its corresponding via from each pair of differential test lines, and keep one differential test line and its single-ended via as a single-ended test line.
[0124] In the above embodiment 4, the loss data tested by the loss tester is the sum of the loss of the trace, via, probe and cable. In order to accurately obtain the loss of the trace, the via, probe and cable need to be de-embedded. Therefore, there is more than one single-ended test line on the loss area coupon board. Usually, three lengths of traces of 2 / 5 / 10 inches are used.
[0125] Using a loss meter to test the loss data S1, S2, and S3 of 2 / 5 / 10 inch traces respectively, S2-S1 represents the loss of a 3-inch trace, and S3-S2 represents the loss of a 5-inch trace. The loss S per unit length of trace can be expressed as:
[0126]
[0127] In the above embodiment 4, the differential transmission line 4 can be located on the same PCB layer or on different PCB layers. Taking PCIe signal as an example, the industry standard for differential trace impedance is 85 ohms. Based on the stack-up structure of the PCB board, the trace width W and trace spacing P of the 85 ohm PCB differential transmission line can be calculated using impedance calculation software. Except for densely traced areas such as BGA, the PCIe differential signal traces on the board should all follow the size requirements of W and P. The single-ended test line 6 of the loss test area 3 also has a trace width of W.
[0128] like Figure 2 Taking the four-port signal transmission line shown as an example, the signal loss from port P1 to port P2 is defined as S21, and the signal loss from port P3 to port P4 is defined as S43. The far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23. Then, the differential loss S generated after the differential signals input from ports P1 and P3 reach ports P2 and P4 is S23. DD21 It can be represented as:
[0129] S DD21 =0.5×(S) 21 +S 43 -S 41 -S 23 )
[0130] S 41 and S 23 The magnitude depends on the far-end crosstalk coefficient FEXT between transmission lines, which is calculated using the following formula:
[0131]
[0132] Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L For example, the capacitance and inductance per unit length along the signal path. Figure 2 The signal transmission line shown is a symmetrical stripline. The medium surrounding the signal transmission line is homogeneous and uniformly distributed. In this case, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same. Therefore, the far-end crosstalk coefficient FEXT is 0, and thus there is no far-end crosstalk.
[0133] At this point, both S41 and S23 are 0, and the differential calculation formula for the differential signal can be simplified to:
[0134] S DD21 =0.5×(S) 21 +S 43 )
[0135] Furthermore, because the differential test lines in the original loss test area coupon are all symmetrical, each pair of symmetrical differential test lines has S 21 =S 43 Therefore S DD21 =S 21 =S 43 ;
[0136] As can be seen from the above derivation process, when the PCB stack-up is designed as follows... Figure 2 When the symmetrical stripline is shown, the differential signal loss in the original differential transmission line is equal to the loss of its single-ended trace. Therefore, in order to reduce the size of the loss test area, we change the differential transmission line to a single-ended trace and obtain the loss data of the differential transmission line on the PCB by the loss of the single-ended test line.
[0137] Since the loss of a single-ended test line can represent the loss of a differential transmission line, the three sets of differential test lines on the loss test area coupon board were changed to three single-ended test lines. The corresponding six pairs of differential vias were also changed to six differential vias. This not only avoids reducing the number of test line sets but also preserves the original test accuracy. This achieves the reduction of the size of the loss test area coupon board, ensuring the utilization rate of PCB materials, and without reducing test accuracy.
[0138] Example 5:
[0139] like Figure 4 As shown, the present invention provides a method for using a PCB board with a loss test area based on Embodiment 1 or Embodiment 2, comprising the following steps:
[0140] SS 1. Connect the loss tester to each single-ended test line in sequence and obtain the loss value of each single-ended test line at different frequencies;
[0141] SS2. Based on the loss value of each single-ended test line at different frequencies, calculate the loss per unit length of the trace, and then calculate the loss value of the differential transmission line at different frequencies.
[0142] The PCB board usage method with loss test area provided by this invention changes the differential trace test lines of the loss test area coupon board to single-ended trace test lines without affecting the test accuracy, and also removes the differential vias that occupy a large area, effectively reducing the size of the loss coupon board and helping to reduce costs.
[0143] Example 6:
[0144] like Figure 4 As shown, the present invention provides a method for using a PCB board with a loss testing area, comprising the following steps:
[0145] SS 1. Connect the loss tester to each single-ended test line in sequence and obtain the loss value of each single-ended test line at different frequencies; the specific steps of step SS 1 are as follows:
[0146] SS 11. Connect the loss tester to the 2-inch single-ended test line through the probe of the corresponding cable, and read the set frequency loss value of the 2-inch single-ended test line as S1.
[0147] SS 12. Connect the loss tester to the 5-inch single-ended test cable through the probe of the corresponding cable, and read the set frequency loss value of the 5-inch single-ended test cable as S 2.
[0148] SS 13. Connect the loss tester to the 10-inch single-ended test line through the probe of the corresponding cable, and read the set frequency loss value of the 10-inch single-ended test line as S3.
[0149] SS2. Based on the loss values of each single-ended test line at different frequencies, calculate the loss per unit length of the trace, and then calculate the loss value of the differential transmission line at different frequencies; the specific steps of step SS2 are as follows:
[0150] SS21. Calculate the 3-inch single-ended test line loss value by subtracting the 5-inch single-ended test line loss value S2 from the 2-inch single-ended test line loss value S1.
[0151] SS22. Calculate the loss value of the 5-inch single-ended test line by subtracting the loss value S3 of the 10-inch single-ended test line from the loss value S2 of the 5-inch single-ended test line.
[0152] SS23. Calculate the loss per unit length of trace at a given frequency.
[0153] SS24. Calculate the loss value of the differential transmission line using the loss S per unit length of trace at a set frequency.
[0154] In the above embodiment 6, the differential transmission line 4 can be located on the same PCB layer or on different PCB layers. Taking PC I e signal as an example, the industry standard for differential trace impedance is 85 ohms. Based on the stack-up structure of the PCB board, the trace width W and trace spacing P of the 85 ohm PCB differential transmission line can be calculated using impedance calculation software. Except for densely traced areas such as BGA, the PC I e differential signal traces on the board should all follow the size requirements of W and P. The trace width of the single-ended test line 6 in the loss test area 3 is also W.
[0155] like Figure 2 Taking the four-port signal transmission line shown as an example, the signal loss from port P1 to port P2 is defined as S21, and the signal loss from port P3 to port P4 is defined as S43. The far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23. Then, the differential loss S generated after the differential signals input from ports P1 and P3 reach ports P2 and P4 is S23. DD21 It can be represented as:
[0156] S DD21 =0.5×(S) 21 +S 43 -S 41 -S 23 )
[0157] S 41 and S 23 The magnitude depends on the far-end crosstalk coefficient FEXT between transmission lines, which is calculated using the following formula:
[0158]
[0159] Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L For example, the capacitance and inductance per unit length along the signal path. Figure 2 The signal transmission line shown is a symmetrical stripline. The medium surrounding the signal transmission line is homogeneous and uniformly distributed. In this case, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same. Therefore, the far-end crosstalk coefficient FEXT is 0, and thus there is no far-end crosstalk.
[0160] At this point, both S41 and S23 are 0, and the differential calculation formula for the differential signal can be simplified to:
[0161] S DD21 =0.5×(S) 21 +S 43 )
[0162] Furthermore, because the differential test lines in the original loss test area coupon are all symmetrical, each pair of symmetrical differential test lines has S 21 =S 43 Therefore S DD21 =S 21 =S 43 ;
[0163] As can be seen from the above derivation process, when the PCB stack-up is designed as follows... Figure 2 When the symmetrical stripline is shown, the differential signal loss in the original differential transmission line is equal to the loss of its single-ended trace. Therefore, in order to reduce the size of the loss test area, we change the differential transmission line to a single-ended trace and obtain the loss data of the differential transmission line on the PCB by the loss of the single-ended test line.
[0164] Since the loss of a single-ended test line can represent the loss of a differential transmission line, the three sets of differential test lines on the loss test area coupon board were changed to three single-ended test lines. The corresponding six pairs of differential vias were also changed to six differential vias. This not only avoids reducing the number of test line sets but also preserves the original test accuracy. This achieves the reduction of the size of the loss test area coupon board, ensuring the utilization rate of PCB materials, and without reducing test accuracy.
[0165] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the invention should also be covered within the protection scope of the invention. Therefore, the protection scope of the invention should be determined by the scope of the claims.
Claims
1. A PCB board with a loss testing area, characterized in that, This includes a PCB board, which has a main board layout area and a loss testing area. The main board layout area is located in the middle of the PCB board, and the loss testing area is located at the outer edge of the main board layout area. The main layout area of the PCB board is equipped with pairs of differential transmission lines; The two differential transmission lines in a pair have the same line width and a fixed line spacing; The loss test area is equipped with a preset number and preset length of single-ended test lines, and the line width of the single-ended test lines is the same as that of the differential transmission lines. Each single-ended test lead has a via at both ends; The length difference between different single-ended test lines is greater than the set length threshold. Three single-ended test leads are set up in the loss test area; The single-ended test line in the loss test area is connected to a loss tester; The loss tester is connected to a probe via a cable; The via of the single-ended test lead is connected to the probe of the loss tester; The loss tester reads the loss value of the single-ended test line at different frequency signal lines, and then calculates the loss value of the differential transmission line. Modify the differential trace test lines on the coupon board in the loss test area to single-ended trace test lines.
2. The PCB board with a loss testing area as described in claim 1, characterized in that, The three single-ended test leads have lengths of 2 inches, 5 inches, and 10 inches, respectively.
3. A PCB board design method with a loss testing area, characterized in that, The specific steps are as follows: S1. Verify that the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal; S2. Change the differential test lines in the original PCB board's loss test area to single-ended test lines, thereby reducing the size of the original PCB board's loss test area; The specific steps of step S1 are as follows: S11. According to the S-parameter theory, a transmission signal line and upper and lower reference planes equidistant from the transmission signal line are preset to form a four-port transmission line; S12. The loss generated by the transmission of the preset signal from port P1 to port P2 is defined as S21, the loss generated by the transmission from port P3 to port P4 is defined as S43, the far-end crosstalk generated by the input signal from port P1 at port P4 is S41, and the far-end crosstalk generated by the input signal from port P3 at port P2 is S23. S13. The differential loss S generated after the differential signals input from ports P1 and P3 reach ports P2 and P4. DD21 Represented as: ； S14. S 41 and S 23 The magnitude is calculated based on the far-end crosstalk factor (FEXT) between transmission lines, and the formula for calculating the far-end crosstalk factor (FEXT) is: Where Len represents the differential trace length, RT is the signal rise time, v represents the signal transmission speed, and C... ml and L ml For mutual capacitance and mutual inductance per unit length between transmission lines, C L and L L Capacitance and inductance per unit length along the signal path; S15. The preset signal transmission line is a symmetrical strip line. Since the medium around the signal transmission line is homogeneous and uniform, the relative coupling capacitance and relative coupling inductance between the traces are exactly the same, that is, C_ml / C_L -L_ml / L_L = 0. The far-end crosstalk coefficient FEXT is determined to be 0, that is, there is no far-end crosstalk. S16. Since S41 and S23 are both 0, the differential calculation formula for differential signal transmission lines can be simplified to: ； S16. Furthermore, according to the original loss test area coupon, the differential test lines are all symmetrical. Symmetrical differential test lines all have S21 = S43, therefore... ; S17. When the PCB stack-up is set to symmetrical striplines, the differential signal loss in the loss test area of the PCB board is equal to the loss of the single-ended trace of the differential signal.
4. The PCB board design method with a loss testing area as described in claim 3, characterized in that, The specific steps of step S2 are as follows: S21. Locate each pair of differential test lines in the loss test area of the original PCB board; S22. Delete one differential test line and its corresponding via from each pair of differential test lines, and keep one differential test line and its single-ended via as a single-ended test line.
5. A method of using a PCB board with a loss testing area based on any one of claims 1-2, characterized in that, Includes the following steps: SS1. Connect the loss tester to each single-ended test line in sequence and obtain the loss value of each single-ended test line at different frequencies. SS2. Based on the loss value of each single-ended test line at different frequencies, calculate the loss per unit length of the trace, and then calculate the loss value of the differential transmission line at different frequencies.
6. The method of using a PCB board with a loss testing area as described in claim 5, characterized in that, The specific steps for step SS1 are as follows: SS11. Connect the loss tester to the 2-inch single-ended test cable through the probe of the corresponding cable, and read the set frequency loss value of the 2-inch single-ended test cable as S1. SS12. Connect the loss tester to the 5-inch single-ended test cable through the probe of the corresponding cable, and read the set frequency loss value of the 5-inch single-ended test cable as S2. SS13. Connect the loss tester to the 10-inch single-ended test cable via the corresponding cable probe, and read the set frequency loss value of the 10-inch single-ended test cable as S3.
7. The method of using a PCB board with a loss testing area as described in claim 6, characterized in that, The specific steps for step SS2 are as follows: SS21. Calculate the loss value of a 3-inch single-ended test line by subtracting the loss value S2 of a 5-inch single-ended test line from the loss value S1 of a 2-inch single-ended test line. SS22. Calculate the loss value of the 5-inch single-ended test line by subtracting the loss value S3 of the 10-inch single-ended test line from the loss value S2 of the 5-inch single-ended test line. SS23. Calculate the loss S per unit length of trace at a given frequency. ; SS24. Calculate the loss value of the differential transmission line using the loss S per unit length of trace at a set frequency.
8. The method of using a PCB board with a loss testing area as described in claim 7, characterized in that, The specific steps for step SS24 are as follows: SS241. Obtain the length N inch of the differential transmission line to be tested; SS242. Calculate the total loss of this differential transmission line, S_total = N. .
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