Method for reducing epitaxial resistance
By forming an ion-doped epitaxial layer on the source and drain regions of the PMOS region and performing thermal annealing, the problem of high epitaxial resistance of PMOS affecting device performance was solved, and the performance of PMOS devices was improved.
Patent Information
- Application Number
- CN202310150236.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-21
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2043-02-21
AI Technical Summary
In the FDSOI device process, the epitaxial resistance of PMOS is relatively large, which affects the Idsat and Ioff performance of the device. Furthermore, the boron doping concentration in PMOS is not easy to increase, which limits its performance.
By forming an ion-doped epitaxial layer on the source and drain regions of the PMOS region and performing rapid thermal annealing, the doped ions diffuse to the bottom of the sidewalls. Combined with photolithography and etching, the sidewalls are formed, thereby reducing the channel resistance from the source and drain regions to the gate edge.
The reduced epitaxial resistance of the PMOS improved the Idsat and Ioff performance of the device, thus enhancing the overall performance of the device.
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Figure CN116207047B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for reducing epitaxial resistance. Background Technology
[0002] In current FDSOI (fully depleted silicon-on-insulator) device manufacturing processes, after the sidewall process is completed, the source and drain regions of PMOS or NMOS are epitaxially grown. Because the channel is undoped, the source and drain regions are P- or B-doped Si or SiGe.
[0003] Since the source and drain regions are grown epitaxially, the distance between the source / drain regions and the gate is increased to reduce leakage current from the source / drain regions to the gate. However, this increases the channel resistance from the source / drain regions to the gate edge, affecting the Idsat (saturation current) - Ioff (off-state current) performance. Furthermore, compared to NMOS, it is more difficult to increase the boron doping concentration in PMOS, resulting in higher epitaxial resistance; therefore, the performance of PMOS is significantly affected.
[0004] To solve the above problems, a novel method for reducing epitaxial resistance is needed. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for reducing epitaxial resistance, which solves the problem that in the prior art, the source and drain regions are grown epitaxially. In order to reduce the leakage current from the source and drain regions to the gate, the distance between the source and drain regions and the gate is increased, which increases the channel resistance from the source and drain regions to the gate edge, affecting the Idsat (saturation current) - Ioff (off-state current) performance. Compared with NMOS, it is not easy to increase the boron doping concentration in PMOS, resulting in high epitaxial resistance and greatly affecting the performance of PMOS.
[0006] To achieve the above and other related objectives, the present invention provides a method for reducing epitaxial resistance, comprising:
[0007] Step 1: Provide a semiconductor structure, wherein the semiconductor structure includes at least: a source / drain region and a gate stack in an NMOS region; a source / drain region and a gate stack in a PMOS region; and a first protective layer covers the source / drain region and the gate.
[0008] Step 2: Use photolithography and etching to open the first protective layer on the PMOS region to form the first sidewall located on the sidewall of the gate stack;
[0009] Step 3: Form an ion-doped first epitaxial layer and a first cap layer on the source / drain region of the PMOS region;
[0010] Step four, rapid thermal annealing treatment is performed on the source-drain region of the PMOS region, so that the doping ions in the first epitaxial layer diffuse to the first epitaxial layer at the bottom of the side wall;
[0011] Step five, the remaining first protective layer is removed, then a second protective layer covering the NMOS region and the PMOS region is formed, then the second protective layer on the NMOS region is opened by using photoetching and etching, a second epitaxial layer doped with ions and a second cap layer on the second epitaxial layer are formed on the source-drain region of the NMOS region, and then the remaining second protective layer is removed.
[0012] Preferably, the PMOS region in step one comprises an N-type silicon substrate, an oxide layer on the N-type silicon substrate, a first silicon layer on the oxide layer, a gate stack of the PMOS region on the first silicon layer, and source-drain regions of the PMOS region on both sides of the gate of the PMOS region respectively; the NMOS region comprises a P-type substrate, an oxide layer on the P-type substrate, a second silicon layer on the oxide layer, a gate stack of the NMOS region on the second silicon layer, and source-drain regions of the NMOS region on both sides of the gate stack of the NMOS region respectively.
[0013] Preferably, the first silicon layer in step one is a germanium-silicon layer.
[0014] Preferably, the second silicon layer in step one is a single-crystal silicon layer.
[0015] Preferably, the P-type silicon substrate of the NMOS region in step one is implanted with B ions; and the N-type silicon substrate of the PMOS region is doped with P ions.
[0016] Preferably, the stack in step one is composed of a first gate oxide layer, a high-K dielectric layer, an isolation layer, a gate polysilicon layer, a gate nitride layer, and a second gate oxide layer, which are stacked in order from bottom to top.
[0017] Preferably, a second side wall is further formed on the sidewall of the stack in step one.
[0018] Preferably, the material of the second side wall in step one is silicon oxynitride.
[0019] Preferably, the materials of the first and second protective layers in steps two and five are silicon dioxide or silicon nitride.
[0020] Preferably, the first epitaxial layer in step three is a germanium-silicon epitaxial layer.
[0021] Preferably, the ions doped on the source-drain region of the PMOS region in step three are B ions.
[0022] Preferably, the material of the first cap layer in step three is silicon.
[0023] Preferably, the material of the first cap layer in step three is silicon germanium, and the concentration of germanium in the first cap layer is lower than that in the first epitaxial layer.
[0024] Preferably, the second epitaxial layer in step five is a silicon epitaxial layer.
[0025] Preferably, the material of the second epitaxial layer in step five is silicon.
[0026] Preferably, the ions implanted on the source-drain region on the NMOS region in step five are P ions.
[0027] As mentioned above, the method for reducing the epitaxial resistance of the present application has the following beneficial effects:
[0028] The present application reduces the channel resistance of the PMOS source-drain region to the gate edge, and improves the Idsat (saturation current) and Ioff (off-state current) performance of the device. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1A shows a semiconductor structure of the present application;
[0030] Figure 1B shows an epitaxial layer for forming a PMOS region of the present application;
[0031] Figure 1C shows a semiconductor structure after annealing of the present application;
[0032] Figure 1D shows an epitaxial layer for forming a NMOS region of the present application;
[0033] Figure 1E shows a semiconductor structure after removing the second protective layer of the present application;
[0034] Figure 2 shows a process flow of the present application. DETAILED DESCRIPTION
[0035] The above embodiments of the present application are described with reference to the specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from the above description. The present application can be implemented or applied in other different embodiments, and the details in the description can be modified or changed based on different views and applications without departing from the spirit of the present application.
[0036] Please refer to Figure 2The application provides a method for reducing epitaxial resistance, comprising the following steps:
[0037] Step one, please refer to Figure 1A , a semiconductor structure is provided, and the semiconductor structure at least comprises: source-drain regions and gate stacks 2 of an NMOS region, source-drain regions and gate stacks 2 of a PMOS region; the source-drain regions and the gate stacks 2 are covered with a first protective layer 1;
[0038] In the embodiment of the application, the semiconductor structure in step one is formed on a silicon-on-insulator (SOI) structure, the PMOS region comprises an N-type silicon substrate, an oxide layer 5 located on the N-type silicon substrate, a first silicon layer 4 located on the oxide layer 5, the material of the oxide layer 5 is generally silicon dioxide, the gate stack 2 of the PMOS region is located on the first silicon layer 4, and the source-drain regions of the PMOS region are respectively located on the two sides of the gate of the PMOS region; the NMOS region comprises a P-type substrate, an oxide layer 5 located on the P-type substrate, a second silicon layer 6 located on the oxide layer 5, the gate stack 2 of the NMOS region is located on the second silicon layer 6, and the source-drain regions of the NMOS region are respectively located on the two sides of the gate stack 2 of the NMOS region. The N-type silicon substrate and the P-type silicon substrate can be formed by ion implantation on a silicon substrate 7.
[0039] In the embodiment of the application, the first silicon layer 4 in step one is a germanium-silicon layer, which is a silicon-on-insulator structure on the PMOS region.
[0040] In the embodiment of the application, the second silicon layer 6 in step one is a single-crystal silicon layer, which is a silicon-on-insulator structure on the NMOS region.
[0041] In the embodiment of the application, B ions are implanted in the P-type silicon substrate of the NMOS region in step one; P ions are implanted in the N-type silicon substrate of the PMOS region. It should be noted that the type of the implanted ions can be adjusted according to actual process requirements, for example, ions of the same group as B ions or P ions.
[0042] In the embodiment of the application, the semiconductor structure in step one is a FDSOI (fully depleted SOI) device, and the stack is composed of a first gate oxide layer, a high-K dielectric layer, an isolation layer, a gate polysilicon layer, a gate nitride layer and a second gate oxide layer stacked from bottom to top. The materials of the first and second gate oxide layers can be silicon dioxide, the material of the high-K dielectric layer can be HfO, and the material of the gate nitride layer can be silicon nitride.
[0043] In the embodiment of the application, a second side wall 3 is further formed on the side wall of the stack in step one.
[0044] In the embodiment of the application, the material of the second side wall 3 in step one is silicon oxynitride.
[0045] Step two, open the first protective layer 1 on the PMOS region by lithography and etching, i.e. form a photoresist layer covering the semiconductor structure on the substrate, then open the photoresist layer by lithography to expose the first protective layer 1 on the PMOS region, and then etch the exposed first protective layer 1 by dry etching to form a first sidewall on the sidewall of the gate stack 2, forming a structure as shown in Figure 1B
[0046] In the embodiment of the present application, the material of the first protective layer 1 in step two is silicon dioxide or silicon nitride.
[0047] Step three, form a first epitaxial layer 8 on the source-drain region of the PMOS region and a first cap layer (not shown in the figure) on the first epitaxial layer 8, the first epitaxial layer 8 can be formed by a vapor phase epitaxy method;
[0048] In the embodiment of the present application, the first epitaxial layer 8 in step three is a germanium-silicon epitaxial layer.
[0049] In the embodiment of the present application, the ion doped on the source-drain region of the PMOS region in step three is a B ion, i.e. the first epitaxial layer 8 is doped with a B ion. The type of the ion can also be adjusted according to the actual process requirements, for example, an ion of the same group as the B ion.
[0050] In the embodiment of the present application, the material of the first cap layer in step three is silicon.
[0051] In the embodiment of the present application, the material of the first cap layer in step three is a germanium-silicon layer, and the concentration of germanium in the first cap layer is lower than the concentration of germanium in the first epitaxial layer 8, i.e. after forming a germanium-silicon epitaxial layer on the source-drain region of the PMOS region, a germanium-silicon layer with a lower concentration of germanium than the germanium-silicon epitaxial layer is formed on the germanium-silicon epitaxial layer.
[0052] Step four, perform rapid thermal annealing on the source-drain region of the PMOS region to diffuse the doped ions in the first epitaxial layer 8 to the region of the first epitaxial layer 8 at the bottom of the sidewall, forming a structure as shown in Figure 1C
[0053] Step five, the remaining first protective layer 1 is removed, which can be removed by wet etching, and then a second protective layer is formed covering the NMOS region and the PMOS region, and then the second protective layer on the NMOS region is opened by using photoetch and etching, i.e. a photoresist layer covering the semiconductor structure is formed on the substrate, and then the photoresist layer is opened by photoetching so that the second protective layer on the NMOS region is exposed, and the exposed second protective layer is etched by dry etching to form a second side wall 3 on the side wall of the gate stack 2, and then an ion-doped second epitaxial layer 9 on the source-drain region of the NMOS region and a second cap layer (not shown in the figure) on the second epitaxial layer 9 are formed, and a structure as shown in Figure 1D is formed, and the forming method can be chemical vapor deposition.
[0054] In the embodiment of the present application, the material of the second protective layer in step five is silicon dioxide or silicon nitride.
[0055] In the embodiment of the present application, the second epitaxial layer 9 in step five is a silicon epitaxial layer.
[0056] In the embodiment of the present application, the material of the second cap layer in step five is silicon.
[0057] In the embodiment of the present application, the ion doped on the source-drain region of the NMOS region in step five is P ion. The type of the ion can also be adjusted according to the actual process requirements, such as the ion of the same group as P ion.
[0058] It should be noted that the drawings provided in the embodiment only schematically illustrate the basic concept of the present application, and the drawings only show the components related to the present application, not the number, shape and size of the components when actually implemented. The type, number and proportion of each component when actually implemented can be arbitrarily changed, and the layout type of the components can also be more complex.
[0059] In summary, the present application reduces the channel resistance of the PMOS source-drain region to the gate edge, and improves the Idsat (saturation current) and Ioff (off-state current) performance of the device. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0060] The above embodiment only exemplarily illustrates the principle and effect of the present application, and is not used to limit the present application. Any person skilled in the art can modify or change the above embodiment without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of reducing epitaxial resistance, comprising: At least comprising: Step one, providing a semiconductor structure, at least comprising: source-drain regions and gate stacks of NMOS region; source-drain regions and gate stacks of PMOS region; the source-drain regions and the gate are covered with a first protective layer; Step two, using lithography and etching to open the first protective layer on the PMOS region to form a first sidewall on the sidewall of the gate stack; Step three, forming an ion-doped first epitaxial layer on the source-drain regions of the PMOS region and a first cap layer on the first epitaxial layer; Step four, performing rapid thermal annealing on the source-drain regions of the PMOS region, so that the doped ions in the first epitaxial layer diffuse to the first epitaxial layer at the bottom of the sidewall; Step five, removing the remaining first protective layer, then forming a second protective layer covering the NMOS region and the PMOS region, then using lithography and etching to open the second protective layer on the NMOS region, forming an ion-doped second epitaxial layer on the source-drain regions of the NMOS region and a second cap layer on the second epitaxial layer, and then removing the remaining second protective layer.
2. The method of reducing epilayer resistance of claim 1, wherein: The PMOS region in step one comprises an N-type silicon substrate, an oxide layer on the N-type silicon substrate, a first silicon layer on the oxide layer, and the gate stack of the PMOS region is on the first silicon layer, and the source-drain regions of the PMOS region are respectively on both sides of the gate of the PMOS region; The NMOS region comprises a P-type substrate, an oxide layer on the P-type substrate, a second silicon layer on the oxide layer, and the gate stack of the NMOS region is on the second silicon layer, and the source-drain regions of the NMOS region are respectively on both sides of the gate stack of the NMOS region.
3. The method of reducing epilayer resistance of claim 2, wherein: The first silicon layer in step one is a germanium-silicon layer.
4. The method of reducing epilayer resistance of claim 2, wherein: The second silicon layer in step one is a single-crystal silicon layer.
5. The method of reducing epilayer resistance of claim 2, wherein: The P-type silicon substrate of the NMOS region in step one is implanted with B ions; the N-type silicon substrate of the PMOS region is implanted with P ions.
6. The method of reducing epilayer resistance of claim 1, wherein: The stack in step one is composed of a first gate oxide layer, a high-K dielectric layer, a separation layer, a gate polysilicon layer, a gate nitride layer, and a second gate oxide layer, stacked in order from bottom to top.
7. The method of reducing epilayer resistance of claim 6, wherein: A second sidewall is also formed on the sidewall of the stack in step one.
8. The method of reducing epilayer resistance of claim 7, wherein: The material of the second sidewall in step one is silicon oxynitride.
9. The method of reducing epilayer resistance of claim 1, wherein: The materials of the first and second protective layers in steps two and five are silicon dioxide or silicon nitride.
10. The method of reducing epilayer resistance of claim 1, wherein: The first epitaxial layer in step three is a germanium-silicon epitaxial layer.
11. The method of reducing epilayer resistance of claim 1, wherein: The doped ions on the source-drain regions of the PMOS region in step three are B ions.
12. The method of reducing epilayer resistance of claim 1, wherein: The material of the first cap layer in step three is silicon.
13. The method of reducing epilayer resistance of claim 10, wherein: The material of the first cap layer in step three is germanium-silicon, and the concentration of germanium in the first cap layer is lower than that in the first epitaxial layer.
14. The method of reducing epilayer resistance of claim 1, wherein: The second epitaxial layer in step five is a silicon epitaxial layer.
15. The method of reducing epilayer resistance of claim 1, wherein: The material of the second epitaxial layer in step five is silicon.
16. The method of reducing epilayer resistance of claim 1, wherein: The doped ions on the source-drain regions of the NMOS region in step five are P ions.
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