A method for fabricating a metal interconnect

Abstract

The present invention relates to a method for fabricating metal interconnects. The method includes: (1) providing a substrate and forming a material layer on the upper surface of the substrate; (2) forming a metal layer on the upper surface of the material layer and forming an etching barrier layer on the upper surface of the metal layer; (3) etching the metal layer outside the etching barrier layer by a dry etching process to form a thin metal layer; (4) passivating the thin metal layer by a passivation process to form a passivation layer; (5) etching the passivation layer by a wet etching process; (6) removing the etching barrier layer to leave an interconnect layer. This method can reduce the damage to the target substrate material during the dry etching process, maintain the intrinsic properties of the material, is beneficial to improving the electrical properties of the fabricated devices, and expands the application scope of metal interconnects in fragile materials such as two-dimensional materials, organic semiconductors, and perovskites.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a method for fabricating metal interconnects. Background Art

[0002] The method for fabricating metal interconnects is an important part of semiconductor processes because the devices in an integrated circuit must be connected through the interconnects in the backend process to form a circuit. Currently, on silicon devices, common metal interconnects include aluminum, copper, tungsten, etc. For metals such as copper and tungsten that are difficult to etch, the dual damascene process is generally used, while for the fabrication method of mature aluminum metal interconnects, wet etching process or dry etching process is used.

[0003] The wet etching process is a commonly used etching process in semiconductors. The wet etching has high efficiency, high etching selectivity, and is relatively gentle on the substrate material, and will not damage the substrate material. However, wet etching is isotropic etching, and lateral etching will cause problems such as pattern deformation or over-etching.

[0004] The dry etching process can etch the metal or material on the substrate to form the desired shape. Dry etching is anisotropic etching, and the volatiles of the dry etching of the metal are taken away by the exhaust system without residual contamination. Currently, the dry etching process has been maturely applied to semiconductor processes, such as the various dry etching processes of aluminum metal mentioned in "Approaches for patterning of aluminum" (Frank, WE.

[0005] MICROELECTRONIC ENGINEERING. 1997. 33(1 - 4), pp. 85 - 100). And Chinese Patent CN108109996B uses the dry etching process to selectively etch the passivation layer to form plug holes.

[0006] However, for fragile two-dimensional materials, organic semiconductors, perovskites, etc., the dry etching process will damage the structure of the substrate material to a certain extent, thereby affecting the performance of the substrate material, especially having a greater impact on two-dimensional materials with atomic-level thickness. The high-energy etching gas will directly damage the two-dimensional material, resulting in device failure. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a method for fabricating metal interconnects to overcome the defect that the dry etching process used in the prior art to fabricate metal interconnects will damage the substrate material.

[0008] The present invention provides a method for fabricating metal interconnects, including:

[0009] (1) Providing a substrate and forming a material layer on the upper surface of the substrate;

[0010] (2) A metal layer is formed on the upper surface of the material layer, and an etch stop layer is formed in the area where metal interconnect lines are required on the upper surface of the metal layer;

[0011] (3) The metal layer outside the etch stop layer is etched using a dry etching process to form a thin metal layer;

[0012] (4) The thin metal layer is passivated using a passivation process to form a passivation layer;

[0013] (5) The passivation layer is selectively etched using a wet etching process;

[0014] (6) The etch stop layer is removed, leaving an interconnect layer.

[0015] Preferably, in step (1), the substrate is a rigid substrate or a flexible substrate.

[0016] Preferably, the rigid substrate includes one or more of a germanium layer, a silicon layer, a germanium-silicon layer, a silicon carbide layer, a copper layer, a nickel layer, a ceramic layer, and a glass layer.

[0017] Preferably, the flexible substrate includes one or more of polyvinyl alcohol, polyester, polyimide, polyethylene naphthalate glycol, paper, and textile materials.

[0018] Preferably, in step (1), the material layer includes one or more of a two-dimensional material, an organic semiconductor, and a perovskite.

[0019] Preferably, the two-dimensional material includes one or more of graphene, molybdenum disulfide, tungsten diselenide, and hexagonal boron nitride.

[0020] Preferably, the organic semiconductor includes one or more of cyanine, phthalocyanine, polyaniline, and polypyrrole.

[0021] Preferably, the perovskite includes one or more of calcium titanate, lanthanum manganite, and methylammonium lead iodide.

[0022] Preferably, the formation method of the material layer in step (1) includes one or more of physical vapor deposition, chemical vapor deposition, epitaxial growth, redox method, and assisted transfer method.

[0023] Preferably, in step (2), the metal layer includes one or more of aluminum, iron, chromium, titanium, molybdenum, tungsten, magnesium, antimony, and tellurium.

[0024] Preferably, the formation method of the metal layer in step (2) includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0025] Preferably, the physical vapor deposition method includes one or more of thermal evaporation method, electron beam evaporation method, and magnetron sputtering method.

[0026] Preferably, the chemical vapor deposition method includes plasma enhanced chemical vapor deposition method.

[0027] Preferably, the atomic layer deposition method includes plasma enhanced atomic layer deposition method.

[0028] Preferably, the formation method of the etching barrier layer in step (2) includes one or more of ultraviolet photoresist, electron beam photoresist, and hard mask process.

[0029] Preferably, the ultraviolet photoresist includes one or more of ultraviolet positive photoresist S1800 series, ultraviolet negative photoresist SU-8 series, and ultraviolet photoresist reversal AZ5214.

[0030] Preferably, the electron beam photoresist includes electron beam positive photoresist PMMA and / or electron beam negative photoresist HSQ.

[0031] Preferably, the hard mask process includes one or more of metal nickel mask, metal chromium mask, titanium nitride mask, silicon nitride mask, and silicon dioxide mask.

[0032] The above-mentioned etching barrier layer materials can be selected and adjusted according to the etching rate and etching film thickness to meet the requirements of different thickness metal interconnects.

[0033] Preferably, the dry etching process in step (3) includes one or more of ion beam etching, reactive ion etching, and inductively coupled plasma etching.

[0034] Preferably, the gas source of the ion beam etching is one or two of helium He and argon Ar.

[0035] Preferably, the reactive ion etching and inductively coupled plasma etching need to select different gas sources according to different metals to be etched.

[0036] Preferably, the thickness of the thin metal layer in step (3) is 10 - 20 nm.

[0037] Preferably, the passivation process in step (4) includes one or more of natural oxidation process, anodic oxidation process, and chemical passivation process.

[0038] Preferably, the natural oxidation process can change process conditions such as temperature, pressure, and oxygen concentration according to requirements.

[0039] Preferably, the anodic oxidation process can change process conditions such as electrolyte, applied current, and cathode plate according to requirements.

[0040] Preferably, the chemical passivation process can select corresponding gas phase or liquid phase acid-base passivation solution according to different metals.

[0041] Preferably, the passivation layer in step (4) comprises one or more of aluminum oxide, antimony oxide and tellurium oxide.

[0042] Preferably, in step (4), the thickness of the passivation layer is 10-20 nm.

[0043] Preferably, in the step (5), the wet etching process uses tetramethylammonium hydroxide TMAH as an etching solution, and silicate H2SiO3 as a corrosion inhibitor. TMAH is a strong alkaline solution, which can react with aluminum oxide to form metaaluminate, which is easily soluble in water and therefore easy to remove, and TMAH does not react with the substrate 1, the material layer 2, and the etching barrier layer 4. The silicate colloid formed by adding an appropriate amount of silicate to the solution can react with the surface of the aluminum metal to form aluminosilicate, which is deposited on the surface of the aluminum metal to prevent further corrosion.

[0044] When the pH value of the TMAH solution containing silicate is less than or equal to 12.5, the solution will selectively corrode the passivation layer (such as aluminum oxide), with a maximum corrosion rate of 13.8 nm / min, and a maximum selectivity ratio of the passivation layer to the metal layer (such as aluminum metal) of 1.6. If the pH value of the TMAH solution containing silicate is greater than 12.5, the solution will rapidly corrode aluminum oxide and aluminum metal.

[0045] Preferably, in step (6), the etching stop layer is removed by using one or more of an organic solvent, an inorganic solvent, and ultrasonic cleaning.

[0046] Preferably, the organic solvent includes one or more of propylene glycol methyl ether acetate (PGMEA), methyl isobutyl ketone (MIBK), N-methyl pyrrolidone (NMP), and acetone.

[0047] Preferably, the inorganic solvent includes one or more of hydrofluoric acid (HF) and buffered hydrofluoric acid (BHF).

[0048] The above-mentioned etching stop layer removal method is mainly determined by the selected etching stop layer, and different etching stop layers require different removal methods.

[0049] The present invention prepares metal interconnects by dry etching and wet etching. First, a metal layer (such as an aluminum electrode layer) is deposited on the upper surface of a material layer (such as graphene) of a substrate (such as a germanium-based substrate), and an etching stop layer is formed by methods such as electron beam negative photoresist exposure and development. Then, dry etching is performed on the area outside the etching stop layer by methods such as ion beam etching to thin the metal layer to a thickness of 10 nm. Next, a passivation process is used, such as placing it in an atmospheric environment at normal temperature and pressure to allow the thin aluminum metal to naturally oxidize to form aluminum oxide. After that, an etching solution with a selectivity ratio, that is, a low-concentration TMAH solution with the pH value adjusted by adding silica colloid, is used to selectively etch the passivation layer (such as aluminum oxide). Finally, the etching stop layer is removed using an organic or inorganic solvent to achieve the purpose of preparing an aluminum interconnect layer on the upper surface of the material layer of the substrate.

[0050] Beneficial effects

[0051] The present invention can conveniently fabricate metal interconnects on a target substrate. While obtaining metal lines with steep edges, it reduces the damage to the target substrate material during the dry etching process, maintains the intrinsic properties of the material, is beneficial to improving the electrical properties of the fabricated devices, and expands the application scope of metal interconnects in fragile materials such as two-dimensional materials, organic semiconductors, and perovskites. Therefore, the present invention effectively avoids the disadvantages of fragile materials in the device fabrication process, improves the stability and reliability of device fabrication, and has high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 is a process flow chart (steps S1 - S8) of the method for preparing metal interconnects of the present invention.

[0053] Figure 2 is a schematic structural diagram of a substrate provided by the present invention.

[0054] Figure 3 is a schematic structural diagram of forming a material layer on the upper surface of the substrate according to the present invention.

[0055] Figure 4 is a schematic structural diagram of forming a metal layer on the upper surface of the material layer according to the present invention.

[0056] Figure 5 is a schematic structural diagram of forming an etching stop layer on the upper surface of the metal layer according to the present invention.

[0057] Figure 6 is a schematic structural diagram of forming a thin metal layer by dry etching the metal layer outside the etching stop layer using a dry etching process according to the present invention.

[0058] Figure 7 is a schematic structural diagram of passivating the thin metal layer to form a passivation layer using a passivation process according to the present invention.

[0059] Figure 8 This is a schematic structural diagram of etching the passivation layer by the wet etching process of the present invention.

[0060] Figure 9 This is a schematic structural diagram of removing the etching barrier layer and leaving the interconnect layer of the present invention.

[0061] The above Figures 2 - 9 In the above, the digital markings are explained as follows:

[0062] 1 is the substrate, 2 is the material layer, 3 is the metal layer, 4 is the etching barrier layer, 5 is the thin metal layer, 6 is the passivation layer, and 7 is the interconnect layer. Specific embodiments

[0063] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0064] Embodiment 1

[0065] Please refer to Figures 1 to 9 . It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0066] A method for preparing metal interconnects is provided in this embodiment. Please refer to Figure 1 , which includes the following steps:

[0067] S1: Provide a substrate;

[0068] S2: Form a material layer on the upper surface of the substrate;

[0069] S3: Form a metal layer on the upper surface of the material layer;

[0070] S4: Form an etching barrier layer on the upper surface of the metal layer;

[0071] S5: Etch the metal layer outside the etching barrier layer by a dry etching process to form a thin metal layer;

[0072] S6: Passivate the thin metal layer by a passivation process to form a passivation layer;

[0073] S7: Selectively etch the passivated aluminum layer by a wet etching process;

[0074] S8: Remove the etching barrier layer, leaving the interconnect layer.

[0075] As Figure 2 shown, in this embodiment, a germanium layer rigid substrate is used in step S1.

[0076] As Figure 3 shown, in this embodiment, chemical vapor deposition is used to grow a single-layer graphene on the surface of the germanium layer substrate in step S2.

[0077] As Figure 4 shown, in this embodiment, electron beam evaporation is used to deposit 160 nm of metallic aluminum on the upper surface of the graphene layer in step S3.

[0078] As Figure 5 shown, in this embodiment, electron beam negative photoresist HSQ is used for exposure and development to form amorphous silicon dioxide as an etching barrier layer on the upper surface of the metallic aluminum in step S4.

[0079] As Figure 6 shown, in this embodiment, ion beam etching using argon as a gas source is used to remove the aluminum metal outside the etching barrier layer in step S5. Experimental measurements show that under the conditions of an ion beam etching voltage of 400 V, an argon gas flow rate of 6 sccm, a substrate temperature of 7 °C, and an etching angle of 0°, the etching rate of metallic aluminum is 25 nm / min, and the etching rate of amorphous silicon dioxide is 42 nm / min. By ion beam etching the metallic aluminum for 6 minutes, a 10-nm thin layer of aluminum metal layer is formed to ensure that the thin layer of aluminum metal layer can be completely oxidized in the next step.

[0080] As Figure 7 shown, in this embodiment, a natural oxidation process is carried out under the atmosphere conditions of normal temperature and normal pressure in step S6. Through natural oxidation, it is ensured that the 10-nm thin layer of aluminum metal can be completely formed into an aluminum oxide layer.

[0081] As Figure 8As shown, in this embodiment, in step S7, by adding 0.5 mol / L nanoscale silica colloid to 2.36% TMAH solution, the pH value of the solution can be adjusted to 12.5, thereby forming a selective etchant that can rapidly oxidize aluminum and react slowly with the substrate 1, the material layer 2, the etch stop layer 4, and the interconnect layer 7, and removing the passivation layer 6. The corrosion rate of this etchant on aluminum oxide at 25°C is 13.8 nm / min, the corrosion rate on the interconnect layer 7 is 12 nm / min, and it hardly corrodes the substrate 1, the material layer 2, and the etch stop layer 4. When the pH of the etchant solution is equal to 12.3, the etch selectivity between aluminum oxide and aluminum metal can reach 1.6. In this embodiment, the thickness of the passivation layer is 10 nm. In the experiment, the sample was immersed in the etchant for 1 minute to remove the aluminum oxide layer, and there was only 12 nm of lateral corrosion on the aluminum metal under the etch stop layer, which did not affect the electrical performance of the metal interconnects in the order of hundreds of nanometers in this embodiment.

[0082] As Figure 9 shown, in this embodiment, in step S8, NMP organic solvent is used. By immersing in the NMP solution at 80°C for 12 hours, the etch stop layer 4 formed by the electron beam positive photoresist is removed. The interconnect layer 7 is insoluble in the organic solvent, and the etch stop layer 4 is soluble in the organic solvent. The interconnect layer 7 remains on the upper surface of the material layer 2 after the etch stop layer 4 is removed. In another embodiment, BHF inorganic solvent is used to remove the etch stop layer 4 formed by the electron beam negative photoresist. The interconnect layer 7 is slightly soluble in the inorganic solvent, and the etch stop layer 4 is soluble in the inorganic solvent. By immersing in the BHF solution at 25°C for 5 seconds to remove the etch stop layer, the interconnect layer 7 remains on the upper surface of the material layer 2 after the barrier layer 4 is removed. Through Raman testing of the single-layer graphene on the substrate surface, it can be known that the D / G of the graphene prepared by using the method of this patent is 0.30, while the D / G of the metal interconnects prepared on the graphene only by dry etching is 1.04. For graphene, the smaller the D / G, the smaller the defects in the graphene. There is even a large area where the Raman signal of graphene cannot be measured, proving that the graphene is damaged by the high-energy plasma of dry etching. It can be seen that the preparation method of this patent causes less damage to the material layer and can better retain the material properties of the material layer.

[0083] The above embodiments only exemplify the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a metal interconnect line, comprising: (1) providing a substrate and forming a material layer on the upper surface of the substrate; (2) forming a metal layer on the upper surface of the material layer and forming an etching barrier layer in the region where the metal interconnect line is required on the upper surface of the metal layer; (3) etching the metal layer outside the etching barrier layer by a dry etching process to form a thin metal layer; (4) passivating the thin metal layer by a passivation process to form a passivation layer; (5) selectively etching the passivation layer by a wet etching process; (6) removing the etching barrier layer to leave an interconnect line layer.

2. The preparation method according to claim 1, characterized in that, In the step (1), the substrate is a rigid substrate or a flexible substrate; the rigid substrate includes one or more of a germanium layer, a silicon layer, a germanium-silicon layer, a silicon carbide layer, a copper layer, a nickel layer, a ceramic layer, and a glass layer; the flexible substrate includes one or more of polyvinyl alcohol, polyester, polyimide, polyethylene naphthalate glycol ester, paper, and textile materials.

3. The preparation method according to claim 1, wherein In the step (1), the material layer includes one or more of two-dimensional materials, organic semiconductors, and perovskites; the forming method of the material layer includes one or more of physical vapor deposition, chemical vapor deposition, epitaxial growth, redox method, and assisted transfer method.

4. The preparation method according to claim 1, characterized in that, In the step (2), the metal layer includes one or more of aluminum, iron, chromium, titanium, molybdenum, tungsten, magnesium, antimony, and tellurium; the forming method of the metal layer includes one or more of physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

5. The preparation method according to claim 1, characterized in that, In the step (2), the forming manner of the etching barrier layer includes one or more of ultraviolet photoresist, electron beam photoresist, and hard mask process; the ultraviolet photoresist includes one or more of ultraviolet positive photoresist, ultraviolet negative photoresist, and ultraviolet photoresist reversal film; The electron beam photoresist includes electron beam positive photoresist and / or electron beam negative photoresist; the hard mask process includes one or more of metal nickel mask, metal chromium mask, titanium nitride mask, silicon nitride mask, and silicon dioxide mask.

6. The preparation method according to claim 1, characterized in that, In the step (3), the dry etching process includes one or more of ion beam etching, reactive ion etching, and inductively coupled plasma etching; the gas source of the ion beam etching is one or both of helium He and argon Ar; the thickness of the thin metal layer is 10-20 nm.

7. The preparation method according to claim 1, characterized in that, In the step (4), the passivation process includes one or more of natural oxidation process, anodic oxidation process, and chemical passivation process; the passivation layer includes one or more of aluminum oxide, antimony oxide, and tellurium oxide.

8. The preparation method according to claim 1, characterized in that, In the step (5), the wet etching process uses tetramethylammonium hydroxide TMAH as the etching solution and silicic acid H2SiO3 as the corrosion inhibitor, and the pH value of the solution is less than or equal to 12.

5.

9. The preparation method according to claim 1, wherein In the step (6), the etching barrier layer is removed by one or more of organic solvents, inorganic solvents, and ultrasonic cleaning.

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