Current-biased tunable qubits

Abstract

Techniques for designing, generating, and utilizing current-biased tunable qubits are presented. The qubit device can include a first Josephson junction (JJ) positioned along a first current path of the device, and a second JJ and a third JJ coupled in series along a second current path parallel to the first current path, wherein the second and third JJs facilitate controlling the frequency of the device. The first JJ can be larger in area than each of the second and third JJs, wherein the current split ratio between the first and second current paths can thereby be increased. The device can include a capacitor having a first terminal associated with the second and third JJs and a second terminal associated with ground. Alternatively, a high-kinetic inductance line can be used in the first current path instead of the JJ.

Description

Technical Field

[0001] The present disclosure relates to quantum circuits, and more particularly to current-biased tunable qubits. Summary of the Invention

[0002] The following is an overview presented to provide a basic understanding of one or more embodiments of the disclosed subject matter. This overview is not intended to identify key or critical elements or to delineate any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, structures, methods, apparatus, and / or computer program products are presented that can facilitate the creation, design, and / or utilization of current-biased tunable qubits.

[0003] According to an embodiment, a device may include a first Josephson junction positioned along a first current path of the device. The device may also include a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path.

[0004] Another embodiment relates to a method that may include forming a first Josephson junction along a first current path of a device. The method may also include forming a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device that is parallel to the first current path.

[0005] Further embodiments relate to a qubit device that may include a high kinetic inductance line positioned along a first current path of the device, wherein the high kinetic inductance line has a kinetic inductance level that satisfies a defined threshold kinetic inductance level. The qubit device may also include a first Josephson junction and a second Josephson junction coupled in series along a second current path of the device in parallel with the first current path.

[0006] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] This patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.

[0008] Figure 1 A diagram illustrating an exemplary, non-limiting apparatus that can be used to provide desired current bias frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter.

[0009] Figure 2 Graphs depicting example graphs of frequency (eg, qubit frequency) of the device as a function of current according to various aspects and embodiments of the disclosed subject matter.

[0010] Figure 3 Graphs depicting example graphs of inductance of a device as a function of current are depicted in accordance with aspects and embodiments of the disclosed subject matter.

[0011] Figures 4 to 7 A chart depicting example graphs of corresponding design curves for devices (e.g., current-biased frequency-tunable qubit devices) with first, second, and third Josephson junctions of different sizes according to various aspects and embodiments of the disclosed subject matter.

[0012] Figure 8 Diagrams are shown of example apparatus that can be used to provide desired current bias frequency tuning and that can employ low-pass filters and / or current shunts to facilitate reducing housing sensitivity to electrical noise and Purcell losses, in accordance with various aspects and embodiments of the disclosed subject matter.

[0013] Figure 9 Illustrations are presented of example graphs of qubit frequency of a device as a function of input current for different embodiments in which the device includes a low-pass filter component and a current shunt component, includes only a current shunt component, or does not include a low-pass filter component or a current shunt component.

[0014] Figure 10 Graphs are presented of example graphs of the detuning of a device as a function of input current in various embodiments where the device includes a low pass filter component and a current shunt component, includes only a current shunt component, or does not include a low pass filter component or a current shunt component.

[0015] Figure 11 Graphs are presented of example graphs of T1 Purcell bound as a function of input current for devices that, in various embodiments, include a low pass filter component and a shunt component, include only a shunt component, or include no low pass filter component or shunt component.

[0016] Figure 12 The desired frequency of a device as a function of input current is presented in accordance with aspects and embodiments of the disclosed subject matter. .

[0017] Figure 13Diagrams of example devices are shown that can be used to provide desired current bias frequency tuning and whose geometry can be desirably modified to have desirably low mutual inductance and also desirably reduced sensitivity to noise, in accordance with aspects and embodiments of the disclosed subject matter.

[0018] Figure 14 According to various aspects and embodiments of the disclosed subject matter, illustrations of example graphs of flux noise of a device (e.g., a current bias frequency tunable device) as a function of spatial dimension Y of a circuit loop of the device for various values ​​of the spatial dimension X of the circuit loop and a width of a first current path of the device.

[0019] Figure 15-17 Presented are diagrams of corresponding simulated example graphs of cross capacitance between input charge islands, capacitor charge islands, and ground charge islands of an example device for different spatial dimensions X and Y of the device, in accordance with various aspects and embodiments of the disclosed subject matter.

[0020] Figure 18-20 Presented are graphs of example plots from corresponding simulations of self-resonant frequencies of corresponding Josephson junction assemblies as a function of dimension Y for different sizes of spatial dimension X of a device according to various aspects and embodiments of the disclosed subject matter.

[0021] Figure 21

[0014] An illustration of an exemplary, non-limiting apparatus that can employ a high-kinetic inductor line in conjunction with a Josephson junction to facilitate desirable frequency tuning of a current bias is presented in accordance with various aspects and embodiments of the disclosed subject matter.

[0022] Figure 22 Graphs depicting example graphs of frequency (eg, qubit frequency) of the device as a function of current according to various aspects and embodiments of the disclosed subject matter.

[0023] Figure 23 According to various aspects and embodiments of the disclosed subject matter, a flow chart is shown of an exemplary, non-limiting method for forming an apparatus that can be used to provide desired current bias frequency tuning.

[0024] Figure 24 In accordance with various aspects and embodiments of the disclosed subject matter, a flowchart is depicted of an example, non-limiting method for forming a low-pass filter component and / or a current shunt component on a device that can be used to provide desired current bias frequency tuning to facilitate reducing the device's sensitivity to noise and Purcell losses.

[0025] Figure 25A flow chart illustrating an example, non-limiting method for modifying or configuring the geometry of a circuit of a device that can be used to provide desired current bias frequency tuning so as to reduce the device's sensitivity to noise and have a desired low mutual inductance, in accordance with various aspects and embodiments of the disclosed subject matter.

[0026] Figure 26 A flow chart depicts an exemplary, non-limiting method for forming a device that can employ high kinetic inductance lines in conjunction with Josephson junctions to facilitate frequency tuning of a desirable current bias, according to various aspects and embodiments of the disclosed subject matter.

[0027] Figure 27 A block diagram illustrating an example non-limiting operating environment that can facilitate one or more embodiments described herein is shown. DETAILED DESCRIPTION

[0028] The following detailed description is illustrative only and is not intended to limit the embodiments and / or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any explicit or implicit information presented in the previous background or overview section or the detailed description section.

[0029] One or more embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used throughout to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that, in various circumstances, one or more embodiments may be practiced without these specific details.

[0030] Frequency-tunable qubit devices can be useful and desirable in many quantum computing architectures. For example, frequency-tunable qubit devices can be used for parametric operations or as tunable coupling devices. For frequency-tunable qubit devices, it can be desirable (e.g., ideal or optimal) to have low loss and high coherence.

[0031] There are frequency tunable devices based on superconducting quantum interference devices (SQUIDs), which can be tuned using magnetic fields generated on-chip or with external coils. While tunable qubit devices using magnetic field-tuned SQUIDs are possible, these devices can be deficient in many respects, as they can suffer from undesirable general flux noise and / or magnetic crosstalk, and / or can require relatively high and undesirable current levels (e.g., about 1 milliampere (mA)) in order to operate.

[0032] Thus, it would be desirable to have a frequency tunable device that is not subject to these and / or other drawbacks. For example, it would be desirable to create, implement, or develop a desirably designed current-controlled qubit (e.g., a current-controlled coupler) that can have higher performance and can be more efficient (e.g., by utilizing or requiring less current to achieve a desired tuning range or a tuning range similar to that of a SQUID-based frequency tunable device), is desirably compact, and is less sensitive to flux noise and magnetic crosstalk.

[0033] To this end, various embodiments described herein relate to techniques for designing, creating, and / or utilizing current-biased, frequency-tunable qubits. In some embodiments, a device (e.g., a qubit device) may include a first Josephson junction positioned along a first current path of the device, and second and third Josephson junctions that may be coupled in series along a second current path parallel to the first current path, wherein the second and third Josephson junctions may facilitate controlling the frequency of the device. In certain embodiments, the device may be a transmon qubit device. There may also be a first inductive component (e.g., a first wiring having a first inductance) positioned along the first current path and a second inductive component (e.g., a second wiring having a second inductance) positioned along the second current path. The device may also include a capacitor component (e.g., a capacitor) having a first terminal associated with the second and third Josephson junctions and a second terminal associated with a ground of the device.

[0034] In some embodiments, the area of ​​the first Josephson junction can be larger (e.g., significantly larger) than each of the second and third Josephson junctions, wherein the current splitting ratio between the first current path and the second current path can be increased based at least in part on the area of ​​the first Josephson junction being larger than the areas of the second and third Josephson junctions. The frequency of the device can be controlled based at least in part on the amount of current applied to the device and the arrangement of the second and third Josephson junctions relative to the first Josephson junction.

[0035] Alternatively (or additionally), in other embodiments, a device may have a high kinetic inductance line in the first current path instead of (or in addition to) a Josephson junction. For example, a device (e.g., a qubit device) may include a high kinetic inductance line positioned along the first current path of the device, wherein the high kinetic inductance line may have a kinetic inductance level that may meet a defined threshold kinetic inductance level. The device may also include a first Josephson junction and a second Josephson junction that may be coupled in series along a second current path of the device in parallel with the first current path. The first Josephson junction and the second Josephson junction may facilitate tuning the frequency of the device.

[0036] There may also be a first inductive component (e.g., a first wiring having a first inductance (in addition to the inductance of the high-kinetic inductor line) positioned along the first current path, and a second inductive component (e.g., a second wiring having a second inductance) positioned along the second current path. The device may also include a capacitor component (e.g., a capacitor) having a first terminal associated with the first and second Josephson junctions and a second terminal associated with the ground of the device.

[0037] The frequency of the qubit device can be adjusted based at least in part on the magnitude of the current applied to the device and the arrangement of the first and second Josephson junctions relative to the high kinetic inductor wiring. The current split ratio between the first and second current paths can be based at least in part on the relationship between the high kinetic inductor wiring, the first Josephson junction, and the second Josephson junction.

[0038] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the drawings.

[0039] Figure 1 A diagram illustrating an example, non-limiting apparatus 100 that can be used to provide desired (e.g., enhanced, suitable, acceptable, or optimal) frequency tuning of current biasing, in accordance with various aspects and embodiments of the disclosed subject matter. In some embodiments, apparatus 100 can be a qubit device (e.g., a qubit device with tunable frequency of current biasing), such as, for example, a transporter qubit device.

[0040] The device 100 may include a first Josephson junction component 102 (JJ1) that may be positioned along a first current path 104 that may have a first current (I1) (e.g., when current is supplied to the device 100). The first current path 104 may also include a first inductive component 106 that may be associated with the first Josephson junction component 102. The first inductive component 106 may be or include a first wiring of a desired conductive material, wherein the first inductive component 106 may have a first level of inductance (L1). A Josephson junction may be a quantum mechanical device that may include two superconducting components (e.g., superconducting electrodes) that may be separated from each other by a relatively thin barrier (e.g., a barrier formed of a non-superconducting or insulating material), wherein the barrier may be or include, for example, a relatively thin insulating tunnel barrier, a desired metallic material, a semiconductor, or a desired magnetic material (e.g., a ferromagnet).

[0041] The device 100 may also include a second Josephson junction assembly 108 (JJ2) and a third Josephson junction assembly 110 (JJ3) that can be coupled in series along a second current path 112 in parallel with the first current path 104, wherein the second current path 112 can have a second current (I2) (e.g., when current is supplied to the device 100), and wherein the second Josephson junction assembly 108 and the third Josephson junction assembly 110 can facilitate controlling the frequency of the device 100, as described more fully herein. For example, when a current source (e.g., a current generator assembly) is used to control (e.g., adjust or tune) the frequency of the device 100 (e.g., the qubit frequency) and to control the second Josephson junction assembly 108 and the third Josephson junction assembly 110, to the current source, the second Josephson junction assembly 108 and the third Josephson junction assembly 110 can be connected in series with each other in the second current path 112. That is, from the perspective of the current source, the second Josephson junction assembly 108 and the third Josephson junction assembly 110 can be connected in series with each other. The second current path 112 may further include a second inductive component 114 that may be associated with the second Josephson junction component 108 and the third Josephson junction component 110. The second inductive component 114 may be or include a second wiring of a desired conductive material, wherein the second inductive component 114 may have a second level of inductance (L2). The first level of inductance of the first inductive component 106 may include, for example, the self-inductance or effective inductance of the first inductive component 106 (e.g., the self-inductance or effective inductance of the first wiring), and the second level of inductive component 114 may include, for example, the self-inductance or effective inductance of the second inductive component 114 (e.g., the self-inductance or effective inductance of the second wiring).

[0042] The apparatus 100 may also include a capacitor component 116 (e.g., a capacitor) having a first terminal associated with (e.g., connected to) the second Josephson junction component 108 and the third Josephson junction component 110 (e.g., connected to the second current path between the second Josephson junction component 108 and the third Josephson junction component 110), and a second terminal that may be associated with (e.g., connected to) a ground 118 of the apparatus 100. When considering the second Josephson junction component 108 and the third Josephson junction component 110 from the perspective of the capacitor component 116 (e.g., a qubit capacitor) of the apparatus 100, the second Josephson junction component 108 and the third Josephson junction component 110 may appear to be in parallel with respect to the capacitor component 116, although, again from the perspective of the current source, the second Josephson junction component 108 and the third Josephson junction component 110 may be coupled in series with each other in the second current path 112. In one non-limiting example, capacitor component 116 may be 60 femtofarads (fF), although capacitors having another desired capacitance greater than or less than 60 fF may be utilized in device 100 as needed or appropriate.

[0043] The device 100 may also include a current generator assembly 120 (e.g., a current pulse generator) that can generate a desired current having a desired current level (e.g., a current pulse having a desired pulse form). The current generator assembly 120 can apply or supply a desired current bias to a circuit loop (e.g., a superconducting circuit loop) that includes the first current path 104 and the second current path 112 to facilitate tuning of the frequency of the control device 100, wherein a first portion of the current can flow through the first current path 104 and a second portion of the current can flow through the second current path 112, based at least in part on the corresponding sizes (e.g., corresponding areas) of the first Josephson junction assembly 102 associated with the first current path 104 and the second Josephson junction assembly 108 and the third Josephson junction assembly 110 associated with the second current path 112. When corresponding portions of current flow through the first current path 104 and the second current path 112, the corresponding portions of the current can be used to change corresponding phase differences across the Josephson junctions (e.g., 102, 108, and 110), where the phase differences (e.g., superconducting phase differences) across the corresponding Josephson junctions can be represented as δ1 for the first Josephson junction component 102, δ2 for the second Josephson junction component 108, and δ3 for the third Josephson junction component 110, respectively. When the phase differences of the Josephson junctions change, the inductance (e.g., the amount or level of inductance) of the Josephson junctions can change accordingly.

[0044] In some embodiments, the first Josephson junction assembly 102 can be larger (e.g., significantly larger) in area than each of the second Josephson junction assembly 108 and the third Josephson junction assembly 110. For example, the first area of ​​the first Josephson junction assembly 102 can be approximately 100 times larger, or greater than or less than 100 times (e.g., 50 times larger, 60 times larger, 70 times larger, ..., 110 times larger, 120 times larger, ...) than the second area of ​​the second Josephson junction assembly 108 and the third area of ​​the third Josephson junction assembly 110, as desired. In some embodiments, the sizes of the second Josephson junction assembly 108 and the third Josephson junction assembly 110 can be the same, but, if and as desired, in other embodiments, the sizes of the second Josephson junction assembly 108 and the third Josephson junction assembly 110 can be different from each other.

[0045] The current split ratio (e.g., I2 / I1) between the first current path 104 and the second current path 112 can be increased based at least in part on the first Josephson junction assembly 102 being larger in area than the second Josephson junction assembly 108 and the third Josephson junction assembly 110. The frequency of the device 100 can be controlled (e.g., managed, adjusted, modified, or tuned) based at least in part on the amount of current applied to the apparatus 100 by the current generator assembly 120, the arrangement of the second Josephson junction assembly 108 and the third Josephson junction assembly 110 relative to the first Josephson junction assembly 102, and the size (e.g., area) of the first Josephson junction assembly 102 relative to (e.g., compared to) the size of the second Josephson junction assembly 108 and the third Josephson junction assembly 110.

[0046] Notably and desirably, the apparatus 100 can be a current-controlled, frequency-tunable device and can utilize three Josephson junctions (e.g., first, second, and third Josephson junction components 102, 108, and 110) as arranged in the circuit of the apparatus 100, the inductance of which can be varied using an applied current through the Josephson junction (e.g., provided from the current generator component 120), where I = I = I C sinδ, and where, for the Josephson junction (L JJ ) can be determined, for example, in Eq. (1) as follows:

[0047]

[0048] However, conventional tunable qubit or coupler devices employing Josephson junctions use magnetic fields generated from current lines to tune the qubit frequency, and the current loop is electrically isolated from the circuits containing the Josephson junctions and is coupled to or associated with the circuits containing the Josephson junctions only through mutual inductance from the magnetic field generated by the current loop. There is no direct current path from the current bias to the Josephson junctions. In such conventional tunable qubit or coupler devices, a magnetic field (e.g., flux passing through the SQUID loop) can change the difference in the phases of the Josephson junctions and, therefore, change the Josephson junction inductance, thereby allowing the qubit frequency to be changed. That is, in such conventional tunable qubit or coupler devices, a magnetic field (e.g., flux passing through the SQUID loop) controls the phase difference associated with the Josephson junction inductance, which can be used to tune the qubit or coupler frequency.

[0049] In contrast, the disclosed subject matter, including device 100 (e.g., a current-controlled frequency-tunable device), does not necessarily use magnetic fields generated from current lines to tune the qubit frequency. Instead, the disclosed subject matter (e.g., device 100) can utilize current applied through a Josephson junction (e.g., first, second, or third Josephson junction components 102, 108, or 110) (e.g., current provided from current generator component 120) to change the inductance of the Josephson junction and facilitate achieving desirable (e.g., enhanced, suitable, acceptable, or optimal) tuning of the device's frequency, as described more fully herein.

[0050] See briefly Figure 2 and 3 (Together with Figure 1 ), Figure 2 a graph depicting an example graph 200 of frequency (e.g., qubit frequency) of device 100 in gigahertz (GHz) versus current in microamperes (A) according to various aspects and embodiments of the disclosed subject matter, and Figure 3 A graph 300 depicts an example of a graph of the inductance of the device 100 in nanohenries (nH) as a function of the current in microamperes. In a non-limiting example, the area of ​​the first Josephson junction assembly 102 may be approximately 100 times the area of ​​the second Josephson junction assembly 108 and the third Josephson junction assembly 110. For the second Josephson junction assembly 108 and the third Josephson junction assembly 110, the current I C2 can be 20 nanoamperes (nA) and the current I C3 The current I associated with the first Josephson junction component 102 may be 20 nA. C1The first inductance level (L1) and the second inductance level (L2) may each be 12 picohenry (pH). By arranging and dimensioning the first Josephson junction assembly 102 relative to the second and third Josephson junction assembly 108, 110, as described herein, the first Josephson junction assembly 102 may facilitate (e.g., enable) a desirable increase in the current splitting ratio (I2 / I1), which may provide a desirable current biasing effect of the second and third Josephson junction assembly 108, 110. For example, the first Josephson junction assembly 102 may be desirably used to increase the current splitting ratio (I2 / I1), and a majority of the tuning effect of the device 100 (e.g., a tuning effect of the current biasing) may be partially attributable to (e.g., may occur in) the second and third Josephson junction assembly 108, 110.

[0051] exist Figure 2 In the graph 200, the current I in In graph 202 of current as a function of frequency, it can be observed that for 10% tuning from a desired frequency point (e.g., a sweet spot frequency, such as approximately 6.65 GHz at 0.0 μA), device 100 (e.g., a current-biased qubit device) can involve the use of only approximately 1.85 μA. In contrast, a typical field-based device (e.g., a magnetic field-tuned transmission device) may require significantly more current (e.g., up to 34 μA) to achieve 10% tuning from a desired frequency point (e.g., an ideal point frequency). The ideal point frequency may be the top of the curve of curve 202, or may be at another desired frequency.

[0052] about Figure 3 Graph 300 may include a graph 302 of the inductance of the first Josephson junction assembly 102 as a function of the current of the device 100. Graph 300 may also include graphs 304 and 306 of the corresponding inductances of the second Josephson junction assembly 108 and the third Josephson junction assembly 110 as a function of the current of the device 100 (wherein, in graph 300, graph 304 and graph 306 overlap, or at least substantially overlap, one another so that graph 304 and graph 306 appear substantially as if they were a single graph line).

[0053] In graph 300, it can be observed from curve 302 that the inductance of the first Josephson junction assembly 102 can be close to 0.5 nH (e.g., can be in a range between approximately 0.15 nH and approximately 0.9 nH) over a current range from -2.0 μA to 2.0 μA. It can also be observed from graphs 304 and 306 that the inductances of the second and third Josephson junction assemblies 108 and 110 can be the same, or at least substantially the same, and can be relatively higher than the inductance of the first Josephson junction assembly 102, and can vary more over the current range than the inductance of the first Josephson junction assembly 102. For example, the inductances of the second and third Josephson junction assemblies 108 and 110 can each be approximately 17.0 nH at 0.0 μA and can gradually increase to approximately 22.0 nH when the current changes from 0.0 μA to 2.0 μA or from 0.0 μA to -2.0 μA.

[0054] The following analysis of the device 100 may provide further details regarding the three Josephson junction couplers of the device 100. The first inductance level (L1) and the second inductance level (L2) may be the geometric inductances of the two branches of the circuit of the device 100. In equations (2) and (3), respectively, the fluxes (Φ1 and Φ2) of the circuit of the device 100 due to the first current (I1) and the second current (I2) may be determined as follows:

[0055]

[0056]

[0057] Here, M may be the mutual inductance between two branches of the circuit of the apparatus 100 , and wherein M may generally be smaller than the first level of inductance ( L1 ) and the second level of inductance ( L2 ).

[0058] The total flux (Φ) of the circuit of the device 100 T ) can be determined from the following equation (4):

[0059]

[0060] where the two branches of the circuit give opposite signs of the flux, and where Φ ext Can represent external flux.

[0061] Since the phase condition set from a single value:

[0062]

[0063]

[0064] Wherein, δ1 may represent the phase associated with the first Josephson junction component 102, δ2 may represent the phase associated with the second Josephson junction component 108, δ3 may represent the phase associated with the third Josephson junction component 110, and n may be a desired (e.g., arbitrary) integer value.

[0065] By using the Josephson junction current relation (assuming it is below the critical current of the device) and Kirchhoff's current law (KCL), from equations (4), (5), and (6), it follows that:

[0066]

[0067]

[0068]

[0069] Among them, I in may be an input (eg, source) current that may be provided by the current generator assembly 120, where may be the critical current of the first Josephson junction component 102, where may be the critical current of the second Josephson junction component 108, and wherein It can be the critical current of the third Josephson junction component 110. According to equation (9), it can be in Values ​​solves I2 numerically and / or graphically.

[0070] See also Figure 4-7 (Together with Figure 1 ), Figure 4-7 A plurality of example graphs 400, 500, 600, and 700 of corresponding design curves for devices (e.g., current-biased frequency-tunable qubit devices) of different sizes for first, second, and third Josephson junction assemblies are depicted according to various aspects and embodiments of the disclosed subject matter. The tuning range and sensitivity of device 100 can be modified (e.g., changed) by adjusting the sizes of first Josephson junction assembly 102, second Josephson junction assembly 108, and third Josephson junction assembly 110. In this regard, for Figures 4 to 7 Graphs 400, 500, 600, and 700, I c = r x 20 nA where IC can be the critical current of the Josephson junction and the particular value of r for a particular Josephson junction can be related to the size of that particular Josephson junction. The size of the second Josephson junction component 108 and the third Josephson junction component 110 is only increased up to 5 (e.g., r2 = 5 and / or r3 = 5) to avoid undesirable capacitive loading of the qubit capacitor (e.g., capacitor component 116). It should be noted that in Figure 4-7 In the corresponding graphs 400, 500, 600, and 700, the qubit capacitance has been varied up to approximately 400 fF to allow the maximum qubit frequency to be maintained at approximately 6 GHz across all of the graphs 400, 500, 600, and 700. Furthermore, the Josephson junction capacitance (e.g., 2 fF / 20 nA) is accounted for in all of the models depicted in graphs 400, 500, 600, and 700. A desired tuning range or desired frequency can be determined based at least in part on a design curve (e.g., graphs 400, 500, 600, or 700, or other design curves that can be derived from the disclosed subject matter).

[0071] Figure 4 According to various aspects and embodiments of the disclosed subject matter, given different values ​​(e.g., size values) for r1 of the first Josephson junction assembly 102, when the values ​​of r2 of the second Josephson junction assembly 108 and r3 of the third Josephson junction assembly 110 are each set to 1, the current I in 4 is an illustration of an example graph 400 of design curves for the frequency (e.g., qubit frequency) of device 100 as a function of . In graph 400 , the value of r1 can range from 1 to 100, with r2 and r3 each equal to 1. Graph 400 shows a curve 402 for r1=1, a curve 404 for r1=5, a curve 406 for r1=10, a curve 408 for r1=25, a curve 410 for r1=50, and a curve 412 for r1=100.

[0072] Figure 5 According to various aspects and embodiments of the disclosed subject matter, for different values ​​of r1 of the first Josephson junction assembly 102, when the value of r2 of the second Josephson junction assembly 108 is set to 1 and the value of r3 of the third Josephson junction assembly 110 is set to 5, as the current I in Graph 500 shows an example graph of a design curve of the frequency (e.g., qubit frequency) of device 100 as a function of . Graph 500 shows a plot 502 for r1=1, a plot 504 for r1=5, a plot 506 for r1=10, a plot 508 for r1=25, a plot 510 for r1=50, and a plot 512 for r1=100.

[0073] Figure 6 Depicted are the frequency of the device 100 (e.g., qubit frequency) as a function of the current I when the value of r2 of the second Josephson junction assembly 108 is set to 5 and the value of r3 of the third Josephson junction assembly 110 is set to 1 for different values ​​of r1 of the first Josephson junction assembly 102 according to various aspects and embodiments of the disclosed subject matter. inGraph 600 shows a curve 602 for r1=1, a curve 604 for r1=5, a curve 606 for r1=10, a curve 608 for r1=25, a curve 610 for r1=50, and a curve 612 for r1=100.

[0074] Figure 7 According to various aspects and embodiments of the disclosed subject matter, different values ​​of r1 for the first Josephson junction assembly 102 are given. When the values ​​of r2 for the second Josephson junction assembly 108 r3 of the third Josephson junction assembly 110 are all set to 5, the frequency of the device 100 (e.g., the qubit frequency) is used as the current I in Graph 700 shows a curve 702 for r1=1, a curve 704 for r1=5, a curve 706 for r1=10, a curve 708 for r1=25, a curve 710 for r1=50, and a curve 712 for r1=100.

[0075] As can be observed from the corresponding graphs of graphs 400, 500, 600, and 700, reducing the size of the first Josephson junction assembly 102 (e.g., by reducing the value of r1) can provide an even further increase in the I2 / I1 ratio, which can provide more frequency tuning range for the qubit device. However, when the first Josephson junction assembly 102 is selected to have an area approximately 100 times larger than the second Josephson junction assembly 108 and the third Josephson junction assembly 110, the first Josephson junction assembly 102 can still desirably increase the current splitting ratio (e.g., I2 / I1 ratio) of the device 100 and provide a desirable frequency tuning range for the device 100.

[0076] In some cases, device 100 may potentially be sensitive to Purcell losses and electrical noise, which may be undesirable. In some embodiments, to facilitate reducing the sensitivity of a device (e.g., a current-biased qubit device), a low-pass filter and / or a current shunt may be utilized, which may desirably (e.g., appropriately, acceptably, or optimally) reduce the sensitivity of the device to Purcell losses and electrical noise.

[0077] In this regard, Figure 8According to various aspects and embodiments of the disclosed subject matter, a diagram is provided of an example apparatus 800 (e.g., an example circuit for an apparatus) that can be used to provide desirable (e.g., enhanced, suitable, acceptable, or optimal) frequency tuning of a current bias and can employ a low-pass filter and / or a current shunt to facilitate reducing the sensitivity of apparatus 800 to electrical noise and Purcell losses. In some embodiments, apparatus 800 can be a qubit device (e.g., a current-biased frequency-tunable qubit device), such as a transporter qubit device. Apparatus 800 can include a first Josephson junction component 102 (JJ1), which can be positioned along a first current path 104, which can have a first current (I1). First current path 104 can also include a first inductive component 106, which can be associated with first Josephson junction component 102. First inductive component 106 can be or include a first wiring of a desired conductive material, wherein first inductive component 106 can have a first level of inductance (L1).

[0078] The device 800 may also include a second Josephson junction component 108 (JJ2) and a third Josephson junction component 110 (JJ3), which may be coupled in series with the first current path 104 in parallel along a second current path 112, wherein the second current path 112 may have a second current (I2), and wherein the second Josephson junction component 108 and the third Josephson junction component 110 may facilitate controlling the frequency of the device 800, as described more fully herein. The second current path 112 may also include a second inductive component 114, which may be associated with the second Josephson junction component 108 and the third Josephson junction component 110. The second inductive component 114 may be or may include a second wiring of a desired conductive material, wherein the second inductive component 114 may have a second level of inductance (L2).

[0079] The apparatus 800 may also include a capacitor assembly 116, which may have a first terminal associated with the second Josephson junction assembly 108 and the third Josephson junction assembly 110, and a second terminal associated with a ground 118 of the apparatus 800. The apparatus 800 may also include a current generator assembly 120, which may generate a desired current having a desired current level (e.g., a current pulse having a desired pulse form).

[0080] In some embodiments, the first Josephson junction assembly 102 can be larger in area (e.g., 100 times larger, or 100 times larger or less than 100 times) than each of the second Josephson junction assembly 108 and the third Josephson junction assembly 110. The current split ratio (e.g., I2 / I1) between the first current path 104 and the second current path 112 can be increased based at least in part on the first Josephson junction assembly 102 being larger in area than the second Josephson junction assembly 108 and the third Josephson junction assembly 110. The frequency of the device 800 can be controlled at least in part based on the amount of current applied to the device 800 by the current generator assembly 120, the arrangement of the second Josephson junction assembly 108 and the third Josephson junction assembly 110 relative to the first Josephson junction assembly 102, and the size (e.g., area) of the first Josephson junction assembly 102 relative to (e.g., compared to) the size of the second Josephson junction assembly 108 and the third Josephson junction assembly 110.

[0081] In certain embodiments, the apparatus 800 may include a low-pass filter component 802, whose input may be associated with (e.g., connected to) the output of the current generator component 120, and whose output may be associated with the first current path 104 and the second current path 112 (e.g., a node in the circuit associated with the first current path 104 and the second current path 112). In some embodiments, the low-pass filter component 802 may be a 1.4 GHz low-pass filter, but in other embodiments, the low-pass filter component 802 may be designed and configured to have a low-pass cutoff frequency higher or lower than 1.4 GHz, as desired. The low-pass filter assembly 802 may include a capacitor assembly 804 and an inductor assembly 806, wherein the inductor assembly 806 may be connected in series with and between the current generator assembly 120 and the load (e.g., the Josephson junction assemblies 102, 108, and 110, and the capacitor assembly 116), and the capacitor assembly 804 may be connected in parallel with the current generator assembly 120 and the load, with a first terminal connected to the current generator assembly 120 and the inductor assembly 806 and a second terminal connected to the ground 118. In an exemplary embodiment, the capacitor assembly 804 may have a capacitance of 1.5 picofarads (pF), and the inductor assembly 806 may have an inductance of 8 nH, although in other embodiments, the capacitor assembly 804 may have a capacitance greater than or less than 1.5 pF, and / or the inductor assembly 806 may have an inductance greater than or less than 8 nH, as desired.

[0082] In some embodiments, additionally or alternatively, the apparatus 800 can include a current separator component 808 that can be connected at a first terminal to the inductor component 806, the first current path 104, and the second current path 112, and can be connected at a second terminal to the ground 118. The current shunt component 808 can shunt (e.g., divide) current flowing from the output of the low-pass filter component 802 to the first current path 104 and the second current path 112 to divert some of the current to a ground plane (e.g., the ground 118) via the current shunt component 808. In certain embodiments, the shunt component 808 can include an inductor component that can have a desired inductance, such as 12 pH, or another desired inductance greater than or less than 12 pH. According to different embodiments, the current shunt component 808 can be on-chip (e.g., an integrated circuit (IC) chip) with the other components of the device 800, or the current shunt component 808 can be off-chip (e.g., located on an IC chip separate from all or some of the other components of the device 800), but without losses so as not to introduce additional and undesirable noise into the device 800.

[0083] Quantum Circuit Analyzer Tool (QuCAT) modeling of the example device 800 may illustrate certain features of the device 800. QuCAT may be used to derive Hamiltonians for the circuits of the device 800. As described herein, the model of the circuit may include low-pass filter components and current shunt components. See briefly Figure 9 and 10 (Together with Figure 8 ), Figure 9 The qubit frequency of the example apparatus 800 is presented as a function of the input (e.g., source) current (I in ) is an illustration of an example graph 900 of a function of ). Figure 10 An example graph 1000 is presented of the detuning performance (in megahertz (MHz)) of an example device 800 as a function of input current in various embodiments where the device includes a low pass filter component 802 and a current shunt component 808, includes only a current shunt component 808, or does not include a low pass filter component 802 or a current shunt component 808.

[0084] about Figure 9 , which may include the qubit frequency (in GHz) of the example device 800 when the device 800 does not include the low-pass filter component 802 or the current splitter component 808 as the input current (I inGraph 900 also includes a graph 902 of qubit frequency as a function of input current (in μA). Graph 900 may also include a graph 904 of qubit frequency as a function of input current for example device 800 when device 800 includes both low-pass filter component 802 and current shunt component 808. Graph 900 may further include a graph 906 of qubit frequency as a function of input current for example device 800 when device 800 includes only current shunt component 808. (Note that curve 904 and curve 906 substantially overlap one another, so that, as a result, curve 904 and curve 906 appear substantially as if they were a single line in graph 900.) For analytical modeling, there may be desirable good agreement in qubit frequency versus source current.

[0085] about Figure 10 , which may include the detuning performance (in MHz) of the example device 800 when the device 800 does not include the low-pass filter component 802 or the current shunt component 808 as a function of the input current (I in Graph 1000 also includes a graph 1002 showing the detuning of example device 800 as a function of input current (in μA). Graph 1000 also includes a graph 1004 showing the detuning of example device 800 as a function of input current when device 800 includes both low-pass filter component 802 and current shunt component 808. Graph 1000 also includes a graph 1006 showing the detuning of example device 800 as a function of input current when device 800 includes only current shunt component 808. (Note that plot 1004 and plot 1006 substantially overlap one another, and thus, as a result, plot 1004 and plot 1006 appear as essentially a single line in graph 1000.)

[0086] QuCAT modeling can also be used to examine current noise and Purcell losses in qubit devices. Current noise in qubit devices can induce relaxation, which can be described by the fluctuation dissipation theorem and can be given by equation (10) as follows:

[0087]

[0088] To facilitate digital assessment, QuCAT for relatively small changes in current. Evaluating this numerically, it is found that It is therefore observed that there is no current noise induced relaxation, and therefore the current cannot excite the qubit device.

[0089] The Purcell loss of a device such as device 800 (e.g., a qubit device) can be determined using admittance formalism or directly from QuCAT (e.g., for a device with a low-pass filter component and a current shunt component, T1 > 3 milliseconds (ms)). Figure 11 (Together with Figure 8 ), Figure 11 The T1Purcell limit of the exemplary device 800 is presented as a function of the input (e.g., source) current (I in ). Graph 1100 may include a plot 1102 of the T1 Purcell limit of the example device 800 as a function of input current (in μA) when the device 800 does not include the low-pass filter component 802 or the current shunt component 808. Graph 1100 may also include a plot 1104 of the T1 Purcell limit of the example device 800 as a function of input current when the device 800 includes both the low-pass filter component 802 and the current shunt component 808. Graph 1100 may further include a plot 1106 of the T1 Purcell limit of the example device 800 as a function of input current when the device 800 includes only the current shunt component 808.

[0090] The Johnson noise sensitivity of device 800 can also be examined. Since, as desired, only a relatively small amount of current (e.g., a few μA) will typically be used for frequency tuning of device 800, additional attenuation can be added compared to a conventional qubit. Assuming a 5 volt (V) and approximately 100 mA arbitrary waveform generator (AWG) is provided, if and as desired, device 800 can attenuate 100 decibels (dB) and still have 10 μA available for frequency tuning.

[0091] For example, if there is 20dB of attenuation on the 4K, 1K, and 100mK boards for the example device 800, the noise current may be (Johnson Current Noise), where K may be temperature in Kelvin, where mK may be milliKelvin, and where pA may be picoamperes.

[0092] To facilitate examining the sensitivity and power spectral density noise of a qubit device, the following equations, such as Equations 11, 12, and 13, may be utilized as follows:

[0093]

[0094]

[0095]

[0096] in, may be a desired frequency point (eg, an ideal point frequency), D may be the sensitivity of the apparatus 800, and wherein S I can be the power spectral density noise of device 800. For a qubit device detuned by 10% from a desired frequency point (e.g., an ideal point frequency), (for current controlled devices, such as device 800), and (For magnetic field controlled devices, such as magnetic field tuned transmission devices), where μs can be microseconds.

[0097] If and as desired, in some embodiments, the sensitivity of device 800 can be reduced by design and / or by adding a current shunt (e.g., current shunt assembly 808) (as described herein) that can divert a desired amount of current to the ground plane. For example, diverting the current by a factor of 10 in device 800 (e.g., by design and / or current shunt assembly 808) can reduce the sensitivity D by 10 and reduce the power spectral noise S by 10. I Lowering 100, this gives While also providing the desired suppression of Purcell losses, as described herein.

[0098] When examining changes in qubit frequency with respect to relatively small flux changes, one can is estimated as a function of input current with different amounts of universal flux noise, for example, using equation (14) as follows:

[0099]

[0100] In certain embodiments, further improvements can be achieved, for example, by making a relatively small perimeter loop with a relatively wide wiring segment connecting the Josephson junctions (e.g., first, second, or third Josephson junction assemblies 102, 108, or 110) and a relatively small hole to accept the flux, which can also desirably make the qubit device (e.g., device 800) less sensitive to ambient fields as well.

[0101] Briefly turn to Figure 12 (Together with Figure 8 ), Figure 12 An example apparatus 800 is presented according to aspects and embodiments of the disclosed subject matter as an input (eg, source) current (I in ) is the expected frequency of the function Graph 1200 shows an example graph of a frequency (eg, an ideal point frequency or other desired frequency). Graph 1200 may include a graph of a frequency (eg, an ideal point frequency or other desired frequency) when A=10 -5 At Φ0, the expected frequency of the example device 800 is A plot 1202 of (eg, ideal point frequency or other desired frequency) in seconds (s) as a function of input current in μA. The graph 1200 may include the desired frequency of the example apparatus 800. A plot 1204 of frequency (eg, ideal point frequency or other desired frequency) as a function of input current (in μA).

[0102] According to various embodiments of the disclosed subject matter, the flux noise sensitivity and mutual inductance of a qubit device (e.g., device 100 or device 800) can desirably be reduced by the geometry of the device's components. Because the qubit device does not require magnetic field tuning or sufficiently large mutual inductance, the geometry of the qubit device can be modified to have relatively small (e.g., very small) mutual inductance and also reduce sensitivity to flux noise.

[0103] Steering Figure 13 , Figure 13 According to various aspects and embodiments of the disclosed subject matter, a diagram of an example apparatus 1300 is shown that can be used to provide desired (e.g., enhanced, suitable, acceptable, or optimal) current bias frequency tuning and whose geometry can be desirably modified to have desirably low mutual inductance and also desirably reduced sensitivity to noise (e.g., flux and / or other noise). Example apparatus 1300 can be, for example, a current-biased qubit device. In some embodiments, example apparatus 1300 can be a current-biased transmission qubit device. Apparatus 1300 is illustrated with a first view 1302 of apparatus 1300 and a second view 1304 (e.g., an exploded or magnified view) of a portion of apparatus 1300 including a Josephson junction.

[0104] Device 1300 may include a first Josephson junction component 1306 (JJ1), a second Josephson junction component 1308 (JJ2), a third Josephson junction component 1310 (JJ3), a capacitor component 1312 (e.g., a qubit capacitor), a ground plane 1314 (e.g., ground), and an input 1316. The respective components (e.g., 1306, 1308, 1310, 1312, 1314, and 1316) may be arranged in a circuit relative to each other, such as described herein with respect to Figure 1For example, a first Josephson junction component 1306 can be positioned along a first current path 1318 that can have a first current (I1) (e.g., when a current is applied via an input 1316, such as via a current generator component). The first current path 104 can also include a first inductive component ( Figure 13 13). The first inductive component may be or may include a first wiring of a desired conductive material, wherein the first inductive component may have a first level of inductance (L1). The second Josephson junction component 1308 and the third Josephson junction component 1310 may be coupled in series along a second current path 1320, which may be in parallel with the first current path 1318, wherein the second current path 1320 may have a second current (I2). The second current path 1320 may include a second inductive component ( Figure 13 13). The second inductive component may be or include a second wiring of a desired conductive material, wherein the second inductive component may have a second level of inductance (L2). The capacitor component 1312 may have a first terminal associated with the second Josephson junction component 1308 and the third Josephson junction component 1310 (e.g., connected to a second current path 1320 therebetween), and a second terminal that may be associated with (e.g., connected to) the ground plane 1314.

[0105] Geometric features of the device 1300 may include a width 1322 (W) of the first current path 1318 (e.g., a first wiring of the first current path 1318) and the first Josephson junction assembly 1306, as well as dimensions X1324 and Y1326 of a space 1328 defined (e.g., surrounded) by the first current path 1318, the second current path 1320, the first Josephson junction assembly 1306, the second Josephson junction assembly 1308, the third Josephson junction assembly 1310, and a pad 1330 associated with the capacitor assembly 1312 (e.g., a pad or capacitor charge island that can be connected to the capacitor assembly 1312).

[0106] According to various embodiments of the disclosed subject matter, the dimensions X1324 and / or Y1326 of the width 1322 (W) and / or the space 1328 (e.g., the space of the circuit loop of the device 1300) of the first current path 1318 and the associated first Josephson junction assembly 1306 can be designed, modified, or adjusted to enable the device 1300 to have a desirably small (e.g., very small) mutual inductance (e.g., reduced mutual inductance) and / or also a desirably reduced sensitivity to flux noise.

[0107] In this regard, it may be useful to examine certain geometric design points related to flux noise. The mathematical relationship between the flux, flux noise, dimension W 1322, and dimensions X 1324 and Y 1326 of space 1328 may be given, for example, by the following example equation (15):

[0108]

[0109] where m = μ b (Bohr magneton), σ=10 16 m -2 (surface spin density), λ = 40 nm, and b = 120 nm (thickness).

[0110] In this regard, in accordance with various aspects and embodiments of the disclosed subject matter, reference is briefly made to Figure 14 (as well as Figure 13 ), Figure 14 An example graph 1400 of flux noise of a device as a function of dimension Y 1326 (e.g., dimension Y of the circuit loop of the device) of space 1328 is presented for different values ​​of dimension X 1324 (e.g., dimension X of the circuit loop of the device) and dimension W 1322 (e.g., width of the first current path of the device) of space 1328. Example graph 1400 may include flux noise of a device (e.g., device 1300) when X = 24 micrometers (μm), Y = 24 μm, and W = 10.2 μm. 1326 for a device (e.g., device 1300) when X=30 μm and W=10.2 μm. Example graph 1400 may include a plot 1404 of flux noise as a function of dimension Y 1326 for a device (e.g., device 1300) when X=30 μm and W=10.2 μm. Example graph 1400 may also include a plot 1406 of flux noise as a function of dimension Y 1326 for a device (e.g., device 1300) when X=20 μm and W=10.2 μm, and a plot 1408 of flux noise as a function of dimension Y 1326 for a device (e.g., device 1300). Example graph 1400 may further include a plot 1410 of flux noise for a conventional magnetic field-based qubit or coupler device when X=24 μm, Y=24 μm, and W=1.2 μm.

[0111] As can be observed from graph 1400, the flux noise of example device 1300 can be significantly lower than the flux noise of conventional qubit devices. As can also be observed from graph 1400, the flux noise of device 1300 can be modified (e.g., reduced) by modifying (e.g., reducing (or increasing) the size of) the dimensions X 1324 and / or Y 1326 of space 1328 of device 1300 and / or the dimension W 1322 of device 1300. For example, as the size of dimension X 1324 of space 1328 is reduced, the flux noise of device 1300 can be reduced, and as the size of dimension Y 1326 of space 1328 is reduced (and / or the size of dimension W 1322 is increased), the flux noise of device 1300 can be reduced.

[0112] Regarding the design of the qubit device, there may be certain constraints on the design geometry. For example, a constraint on the size of more favorable (e.g., improved or increased) flux noise reduction (e.g., smaller loop size and larger width) for the qubit device may be cross capacitance, such as, for example, the cross capacitance between the input charge island (1) 1332 and the capacitor charge island (2) 1330 (e.g., pad 1330), the cross capacitance between the input charge island (1) 1332 and the ground charge island (3) 1334, and the cross capacitance between the capacitor charge island (2) 1330 and the ground charge island (3) 1334. This may be limited by the capacitance that does not change the resonant frequency of the Josephson junction (e.g., first, second, and / or third Josephson junction components 1306, 1308, and / or 1310).

[0113] The simulation of Q3D can enable the determination of the cross capacitance between the input charge island (1) 1332, the capacitor charge island (2) 1330 and the ground charge island (3) 1334. In this regard, a brief reference is made to Figure 15-17 (as well as Figure 13 ), Figure 15-17 Graphs of example graphs of corresponding simulations of cross-capacitance between input charge islands (1) 1332, capacitor charge islands (2) 1330, and ground charge islands (3) 1334 for different dimensions X and Y of a space 1328 of a device in accordance with various aspects and embodiments of the disclosed subject matter are presented. Figure 15 A diagram depicts an example graph 1500 of a corresponding simulation of the cross capacitance between an input charge island (1) 1332 and a capacitor charge island (2) 1330 for different sizes of dimension Y of dimension X of a space 1328 of a device according to various aspects and embodiments of the disclosed subject matter. The example graph 1500 may include the input charge island (1) 1332 and the capacitor charge island (2) 1330 (C 12) between the cross capacitance (in fF) as a function of size Y, where size X = 10 μm. The example graph 1500 may also include the cross capacitance C as a function of size Y for size X = 15 μm. 12 Plot 1504 of the cross capacitance C as a function of dimension Y for dimension X = 20 μm 12 Plot 1506 of the cross capacitance C as a function of dimension Y for dimension X = 25 μm 12 Plot 1508 of, and the cross capacitance C as a function of dimension Y for dimension X=30 μm 12 Drawing 1510.

[0114] Figure 16 Graph of an example graph 1600 illustrating corresponding simulations of cross capacitance between input charge islands (1) 1332 and ground charge islands (3) 1334 as a function of dimension Y for different sizes of dimension X of space 1328 of a device in accordance with various aspects and embodiments of the disclosed subject matter. Example graph 1600 may include cross capacitance (C) between input charge islands (1) 1332 and ground charge islands (3) 1334 as a function of dimension Y for dimension X = 10 μm. 13 ) (in fF) is plotted 1602. The example graph 1600 may also include the cross capacitance C as a function of dimension Y for dimension X=15 μm. 13 Plot 1604 of the cross capacitance C as a function of dimension Y for dimension X = 20 μm 13 Plot 1606 of the cross capacitance C as a function of dimension Y for dimension X=25 μm 13 Plot 1608 of, and the cross capacitance C as a function of dimension Y for dimension X=30 μm 13 Drawing of 1610.

[0115] Figure 17 According to aspects and embodiments of the disclosed subject matter, an example graph 1700 is provided of corresponding simulations of cross capacitance between capacitor charge island (2) 1330 and ground charge island (3) 1334 as a function of dimension Y for different sizes of dimension X of space 1328 of a device. The example graph 1700 may include cross capacitance (C 23 ) as a function of dimension Y, where dimension X=10 μm. The example graph 1700 may also include a graph of the cross-capacitance C as a function of dimension Y for dimension X=15 μm. 23 Plot 1704 of the cross capacitance C as a function of dimension Y for dimension X=20 μm 23Plot 1706 of the cross capacitance C as a function of dimension Y for dimension X=25 μm 23 Plot 1708 of , and the cross capacitance C as a function of dimension Y for dimension X=30 μm 23 Drawing of 1710.

[0116] Simulations of the self-resonant frequency of the corresponding Josephson junction components due to cross capacitance in the range from X=30μm and Y=15μm to X=10μm and Y=0.1μm can also be performed and examined. Even when the X and Y dimensions are reduced to X=10μm and Y=0.1μm in the range of X=30μm and Y=15μm, the Figure 18-20 In the following graphs of , it can be observed that the self-resonant frequencies arising from the corresponding Josephson junction components due to the cross capacitance are still acceptable for qubit devices, as these self-resonant frequencies can typically be at or above about 20 GHz. Figure 18-20 (as well as Figure 13 ), Figure 18-20 Presented are graphs of example plots of self-resonant frequencies from corresponding Josephson junction assemblies as a function of corresponding simulations of dimension Y for different sizes of dimension X of space 1328 of a device, according to various aspects and embodiments of the disclosed subject matter. Figure 18 Graphs of simulated example graphs 1800 of the self-resonant frequency from the first Josephson junction assembly 1306 (JJ1) as a function of dimension Y for different sizes of dimension X of the space 1328 of the apparatus are presented in accordance with various aspects and embodiments of the disclosed subject matter. The exemplary graphs 1800 may include a plot 1802 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X = 10 μm, a plot 1804 of the self-resonant frequency from JJ1 as a function of dimension Y when dimension X = 15 μm, a plot 1806 of the self-resonant frequency from JJ1 as a function of dimension Y when dimension X = 20 μm, a plot 1808 of the self-resonant frequency from JJ1 as a function of dimension Y when dimension X = 25 μm, and a plot 1810 of the self-resonant frequency from JJ1 as a function of dimension Y when dimension X = 30 μm.

[0117] Figure 19According to various aspects and embodiments of the disclosed subject matter, diagrams of example graphs 1900 from simulations of the self-resonant frequency of the second Josephson junction assembly 1308 (JJ2) as a function of dimension Y for different sizes of dimension X of the space 1328 of the apparatus are presented. Exemplary graphs 1900 may include a plot 1902 of the self-resonant frequency from JJ2 as a function of dimension Y when dimension X = 10 μm, a plot 1904 of the self-resonant frequency from JJ2 as a function of dimension Y when dimension X = 15 μm, a plot 1906 of the self-resonant frequency from JJ2 as a function of dimension Y when dimension X = 20 μm, a plot 1908 of the self-resonant frequency from JJ2 as a function of dimension Y when dimension X = 25 μm, and a plot 1910 of the self-resonant frequency from JJ2 as a function of dimension Y when dimension X = 30 μm.

[0118] Figure 20 Depicted are diagrams of example graphs 2000 of the self-resonant frequency of the third Josephson junction assembly 1310 (JJ3) as a function of dimension Y for different sizes of dimension X of the space 1328 of the device, according to various aspects and embodiments of the disclosed subject matter. The exemplary graphs 2000 may include a plot 2002 of the self-resonant frequency from JJ3 as a function of dimension Y when dimension X = 10 μm, a plot 2004 of the self-resonant frequency from JJ3 as a function of dimension Y when dimension X = 15 μm, a plot 2006 of the self-resonant frequency from JJ3 as a function of dimension Y when dimension X = 20 μm, a plot 2008 of the self-resonant frequency from JJ3 as a function of dimension Y when dimension X = 25 μm, and a plot 2010 of the self-resonant frequency from JJ3 as a function of dimension Y when dimension X = 30 μm.

[0119] Steering Figure 21 , Figure 21 A diagram of an exemplary, non-limiting device 2100 is shown that can employ a high-kinetic inductance line in conjunction with a Josephson junction to facilitate desirable (e.g., enhanced, suitable, acceptable, or optimal) frequency tuning of a current bias, according to various aspects and embodiments of the disclosed subject matter. In some embodiments, the Josephson junction of the first current path (e.g., first Josephson junction component 102 of device 100) can be replaced with a high-kinetic inductance line formed from a desired high-kinetic inductance material. In some embodiments, device 2100 can be a qubit device (e.g., a qubit device with frequency tunable current bias), such as, for example, an emitter qubit device.

[0120] The device 2100 may include a high-kinetic inductor line 2102 that may be positioned along a first current path 2104 that may have a first current (I1) (eg, when current is supplied to the device 2100). The high-kinetic inductor line 2102 may have an inductance (L k ), which can be based at least in part on how high the high kinetic inductance of line 2102 is and the dimensions of high kinetic inductance line 2102. High kinetic inductance line 2102 can have a kinetic inductance level that meets (e.g., is sufficiently high; meets or exceeds) a defined threshold kinetic inductance level, where the defined threshold kinetic inductance level can indicate whether line 2102 has a kinetic inductance level that is high enough to be considered a high kinetic inductance line. In some embodiments, the defined threshold kinetic inductance level can be 1 nH / μm, but it should be understood and appreciated that in other embodiments, the defined threshold kinetic inductance level can be greater than or less than 1 nH / μm. In some embodiments, high kinetic inductance line 2102 can be formed from a desired superconducting material (e.g., niobium nitride, titanium niobium nitride, or other desired superconducting material) that meets the defined threshold kinetic inductance level. First current path 2104 can also include a first inductive component 2106, which can be associated with high kinetic inductance line 2102. The first inductive component 106 may be or may include a first wiring of a desired conductive material (or may be a portion of the high-kinetic inductor line 2102), wherein the first inductive component 2106 may have a first level of inductance (L1). The first level of inductance of the first inductive component 2106 may be relatively small (e.g., very small or negligible) compared to the inductance of the high-kinetic inductor line 2102.

[0121] The apparatus 2100 may further include a first Josephson junction assembly 2108 (at Figure 21 and the second Josephson junction assembly 2110 (identified as JJ2 in Figure 212100 ), which can be coupled in series along a second current path 2112 in parallel with the first current path 2104, wherein the second current path 2112 can have a second current (I2) (e.g., when current is supplied to the device 2100), and wherein the first Josephson junction component 2108 and the second Josephson junction component 2110 can facilitate controlling the frequency of the device 2100, as described more fully herein. The second current path 2112 can also include a second inductive component 2114, which can be associated with the first Josephson junction component 2108 and the second Josephson junction component 2110. The second inductive component 2114 can be or include a second wiring of a desired conductive material, wherein the second inductive component 2114 can have a second level of inductance (L2). The first inductance level of the first inductance component 2106 may include, for example, the self-inductance or effective inductance of the first inductance component 2106 (for example, the self-inductance or effective inductance of the first wiring), and the second inductance level of the second inductance component 2114 may include, for example, the self-inductance or effective inductance of the second inductance component 2114 (for example, the self-inductance or effective inductance of the second wiring).

[0122] The device 2100 may also include a capacitor assembly 2116 (e.g., a capacitor) having a first terminal associated with the first Josephson junction assembly 2108 and the second Josephson junction assembly 2110 (e.g., connected to the second current path 2112 therebetween) and a second terminal associated with (e.g., connected to) a ground 2118 of the device 2100. In one non-limiting example, the capacitor assembly 2116 may be 65 fF, although capacitors having another desired capacitance greater than or less than 65 fF may be utilized in the device 2100 as desired or appropriate. The device 2100 may also include a current generator assembly 2120 that may generate a desired current having a desired current level (e.g., a current pulse having a desired pulse form), wherein the current may be supplied or applied to the first current path 2104 and the second current path 2112.

[0123] The current split ratio (e.g., I2 / I1) between the first current path 2104 and the second current path 2112 can be determined or modified (e.g., increased (or decreased)) based at least in part on a characteristic (e.g., high kinetic inductance) of the high kinetic inductance line 2102 relative to the area of ​​the first Josephson junction assembly 2108 and the area of ​​the second Josephson junction assembly 2110. The frequency of the device 2100 can be controlled (e.g., managed, adjusted, modified, or tuned) based at least in part on the amount of current applied to the device 2100 by the current generator assembly 2120, the amount of kinetic inductance of the high kinetic inductance line 2102, the size (e.g., area) of the first Josephson junction assembly 2108 and the second Josephson junction assembly 2110, and / or the arrangement of the high kinetic inductance line 2102 relative to the first Josephson junction assembly 2108 and the second Josephson junction assembly 2110.

[0124] Figure 21 The device 2100 having a high dynamic inductance line 2102 is in the device 2100 (instead of Figure 1 The analysis of the first Josephson junction component 102 of the device 100 can be relatively similar to Figure 1 The analysis of device 100, as described herein, may be performed except that there may be differences in the analysis, which may include, for example, a phase difference across the high kinetic inductance line 2102, and the kinetic inductance does not have an associated magnetic flux contribution (e.g., similar to the first Josephson junction component 102 of device 100).

[0125] Due to the conditions of the unification of the phase δ as considered in equation (16):

[0126]

[0127] in, may represent the phase of the high dynamics inductor line 2102, δ2 may represent the phase of the first Josephson junction component 2108, δ3 may represent the phase of the second Josephson junction component 2110, and Φ ext Can represent external flux.

[0128] For the Josephson junction current relation (assuming below critical current) and KCL, starting from equation (16), in equation (17), it follows that:

[0129]

[0130] Among them, I in may be an input (eg, source) current that may be provided by the current generator component 2120. According to equation (17), for different I in Values ​​Solve I2 numerically and / or graphically.

[0131] Briefly refer to Figure 22 (Together with Figure 21 ), Figure 22 The frequency (e.g., qubit frequency) of the device 2100 according to various aspects and embodiments of the disclosed subject matter is depicted as a function of the current I in 2200 is a graph of an example graph of a function of . In a non-limiting example, the current I associated with the first Josephson junction component 2108 C2 The current I 20 may be 20 nanoamperes (nA) and associated with the second Josephson junction component 2110. C3 The current I associated with the high dynamics inductor line 2102 may be 20 nA. in =I2 can be 2000 nA. The capacitance of capacitor component 2116 can be 65 fF. The inductance levels of the first inductance level (L1) and the second inductance level (L2) can each be 12 pH. By having a high kinetic inductance and arranged relative to the first Josephson junction component 2108 and the second Josephson junction component 2110, as described herein, the high kinetic inductance line 2102 can facilitate (e.g., enable) a desirable increase in the current splitting ratio (I2 / I1), which can provide a desirable current biasing effect of the first Josephson junction component 2108 and the second Josephson junction component 2110. For example, the high kinetic inductance line 2102 can be desirably used to increase the current splitting ratio (I2 / I1), and a majority of the tuning effect of the device 2100 (e.g., the tuning effect of the current biasing) can be partially attributed to (e.g., can occur in) the first Josephson junction component 2108 and the second Josephson junction component 2110.

[0132] exist Figure 22 From the graph 2202 of frequency (in GHz) as a function of current (in μA) for device 2100, it can be observed that for a 10% tuning from a desired frequency point (e.g., an ideal point frequency, such as approximately 6.9 GHz at 0.0 μA), device 100 (e.g., a current-biased qubit device) can involve the use of only approximately 2.3 μA. In contrast, a typical field-based device (e.g., a magnetic field-based Xmon coupler device) may require significantly more current (e.g., up to 34 μA) to achieve a 10% tuning from a desired frequency point (e.g., an ideal point frequency). As can also be observed, Figure 22 The plot 2202 of the device 2100 having the high kinetic inductance line 2102 in the first current path 2104 may be substantially similar to Figure 2FIG. 2 is a drawing 202 of a device 100 having a first Josephson junction assembly 102 in a first current path 104 .

[0133] In some embodiments, although not Figure 21 As shown in FIG, the apparatus 2100 may include a low-pass filter component (eg, low-pass filter component 802) and / or a shunt component (eg, shunt component 808) that is similar to the embodiment of the present invention. Figure 8 The device 2100 may be the same or similar to the device 800 described above to help reduce the undesirable sensitivity of the device 2100 to noise (e.g., current noise, flux noise, or Johnson noise) and / or Purcell loss. In some embodiments, the device 2100 may also have its geometry (e.g., dimensions W, X, and / or Y) designed or modified (e.g., adjusted) to Figure 13 The same or similar methods as described for the apparatus 1300 may be used to facilitate reducing noise sensitivity and / or mutual inductance of the apparatus 2100.

[0134] Notably and desirably, the device 2100 can be a current-controlled frequency-tunable device and can utilize a high-kinetic inductor line 2102 and two Josephson junctions (e.g., first and second Josephson junction components 2108 and 2110) as arranged in the circuit of the device 2100, and the inductance of the Josephson junction can be changed using a current applied through the Josephson junction (e.g., supplied from the current generator component 2120) or the inductance of the high-kinetic inductor line can be changed through the high-kinetic inductor line.

[0135] However, conventional tunable qubit or coupler devices use magnetic fields generated from current lines to tune the qubit frequency. In such conventional tunable qubit or coupler devices, a magnetic field (e.g., flux through the SQUID loop) can change the difference in the phases of the Josephson junctions, and thus change the Josephson junction inductance, and thus can allow for changes in the qubit frequency. The disclosed subject matter, including device 2100 (e.g., a current-controlled frequency tunable device), does not necessarily use magnetic fields generated from current lines to tune the qubit frequency, as the disclosed subject matter (e.g., device 2100) can utilize current applied through a Josephson junction (e.g., first or second Josephson junction assembly 2108 or 2110) (e.g., supplied from current generator assembly 2120) to change the inductance of the Josephson junction, or through a high-kinetic inductance line to change the inductance of the high-kinetic inductance line, and facilitate achieving the desired tuning of the device frequency, such as described more fully herein.

[0136] Devices (e.g., device 100, device 800, device 1300, and device 2100), which can be current-biased frequency-tunable qubit devices, as described herein, can be desirably enhanced and reliable frequency or flux-tunable devices, can have desirably fast tunable gates and tunable qubits to facilitate avoiding undesirable frequency conflicts and dispersion interactions (e.g., ZZ interactions), and can also mitigate, reduce, or minimize magnetic crosstalk and flux noise, which can be desirable because magnetic crosstalk and flux noise can undesirably limit the gate fidelity of qubit devices. In addition to flux-based schemes, devices (e.g., device 100, device 800, device 1300, and device 2100) can also be useful tools for designing tunable elements.

[0137] The devices described herein (e.g., device 100, device 800, device 1300, and device 2100) can be used in multi-qubit systems using flux-controlled tunable elements (e.g., couplers or qubits). These devices (e.g., device 100, device 800, device 1300, and device 2100) can also help reduce power dissipation (e.g., heating) in cables or attenuators as the number of qubits is scaled up in qubit-based systems. With the low (e.g., very low) currents desired in the devices described herein (e.g., device 100, device 800, device 1300, and device 2100), the current biasing schemes (e.g., designs) and techniques of the disclosed subject matter as described herein with respect to such devices can also reduce the complexity associated with having to meet or comply with applicable requirements or constraints (e.g., design constraints) for cryogenic electronics and hardware designed to drive and control flux-tunable qubits. Devices (e.g., device 100, device 800, device 1300, and device 2100) and current biasing schemes (e.g., designs) and techniques (as described herein) may be employed (e.g., may be suitable or desirable for employment) in the field of quantum circuits and computing as desirable techniques for achieving frequency tunability of qubits.

[0138] These systems and / or devices have been (or will be) described herein with respect to the interactions between several components. It will be understood that such systems and components may include those components or subcomponents specified therein, some specified components or subcomponents, and / or additional components. Subcomponents may also be implemented as components that are communicatively coupled to other components, rather than being included within a parent component. In addition, one or more components and / or subcomponents may be combined into a single component that provides aggregate functionality. These components may also interact with one or more other components, which are not specifically described herein for the sake of brevity, but are known to those skilled in the art.

[0139] Figure 23 A flow chart of an example non-limiting method 2300 for forming an apparatus that can be used to provide desired (e.g., enhanced, suitable, acceptable, or optimal) current bias frequency tuning is presented according to various aspects and embodiments of the disclosed subject matter. The method 2300 can be performed by, for example, a system (e.g., a computer system) that includes or is operatively coupled to a processor component and a memory. For the sake of brevity, repetitive descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted.

[0140] At 2302, a first Josephson junction assembly can be formed along a first current path of a device. At 2304, a second Josephson junction assembly and a third Josephson junction assembly can be formed on the device, wherein the second and third Josephson junction assemblies can be coupled in series along a second current path of the device that is parallel to the first current path. For example, the system can form the first Josephson junction assembly along the first current path and can form a second Josephson junction assembly and a third Josephson junction assembly, wherein the second and third Josephson junction assemblies can be coupled in series along a second current path that is parallel to the first current path of the device. The first current path can be associated with a first inductive component having a first inductance, and the second current path can be associated with a second inductive component having a second inductance.

[0141] At 2306, a capacitor assembly including a first terminal and a second terminal can be formed, wherein the first terminal can be associated with the second current path, and wherein the second terminal can be associated with a ground of the device. The capacitor assembly (e.g., a capacitor) can have a desired capacitance, such as described herein. In certain embodiments, the system can form or place the capacitor assembly on the device and can connect the first terminal to the second current path, such as between the second Josephson junction assembly and the third Josephson junction assembly, and can connect the second terminal to ground.

[0142] At 2308, a current generator assembly can be formed on the device, wherein the current generator assembly can supply desired currents to the first current path and the second current path of the device. In certain embodiments, the system can form or place (e.g., insert) the current generator assembly on the device, wherein an output of the current generator assembly can be associated with (e.g., directly or indirectly connected to) the first current path and the second current path of the device.

[0143] In some embodiments, method 2300 may continue to reference point A, where Figure 24Method 2400 may continue from reference point A. In certain embodiments, method 2300 may continue to reference point B, wherein: Figure 25 Method 2500 may continue from reference point B.

[0144] Figure 24 A flowchart of an example non-limiting method 2400 for forming a low pass filter component and / or a shunt component on a device is depicted according to various aspects and embodiments of the disclosed subject matter, the components of which can be used to provide desirable (e.g., enhanced, suitable, acceptable, or optimal) current bias frequency tuning to facilitate reducing the sensitivity of the device to noise (e.g., flux and / or other noise) and Purcell losses. The method 2300 can be performed by, for example, a system (e.g., a computer system) that includes or is operatively coupled to a processor component and a memory. For the sake of brevity, repetitive descriptions of similar elements employed in other embodiments described herein are omitted or can be omitted. In some embodiments, the method 2400 can be performed from Figure 23 Method 2300 starts at reference point A.

[0145] At 2402, a low-pass filter component can be formed on a device, wherein an input of the low-pass filter component can be associated with an output of a current generator component of the device, and an output of the low-pass filter component can be associated with a first current path and a second current path of the device. The system can form or place (e.g., insert) the low-pass filter component on the device, wherein an input (e.g., an input port) of the low-pass filter component can be associated with (e.g., connected to) an output of the current generator component, and an output of the low-pass filter component can be associated with the first current path and the second current path of the device (e.g., nodes in a circuit associated with the first current path and the second current path). The low-pass filter component can be structured and can include components such as those described more fully herein (e.g., an inductor component and a capacitor component).

[0146] At 2404, a current shunt assembly can be formed on the device, wherein the current shunt assembly can be associated with the first current path and the second current path to facilitate shunting current output from the current generator assembly. In some embodiments, in addition or alternatively (e.g., in addition to or in place of the low-pass filter assembly), the system can form or place the current shunt assembly on the device such that the current shunt assembly can be associated with the first current path and the second current path to facilitate shunting current output from the current generator assembly (e.g., diverting some current to a ground plane of the device). For example, the system can connect a first terminal of the current shunt assembly to the first current path, the second current path, and / or the low-pass filter assembly, and can connect a second terminal of the current shunt assembly to a ground of the device (e.g., a ground plane). The current shunt assembly can be constructed and can include components such as those described more fully herein (e.g., an inductor assembly).

[0147] Figure 25 According to various aspects and embodiments of the disclosed subject matter, a flow chart of an exemplary, non-limiting method 2500 for modifying or configuring the geometry of a circuit of a device is shown, which can be used to provide a desired (e.g., enhanced, suitable, acceptable, or optimal) frequency tuning of a current bias to facilitate reducing the device's sensitivity to noise and having a desired low mutual inductance is shown. The method 2500 can be performed by, for example, a system (e.g., a computer system) that includes or is operatively coupled to a processor component and a memory. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted. In certain embodiments, the method 2500 can be performed from Figure 23 Method 2300 starts at reference point B.

[0148] At 2502, with respect to a space associated with a circuit loop of a device, where such space may be defined by a first current path, a second current path, a first Josephson junction component, a second Josephson junction component, a third Josephson junction component, and a pad associated with a capacitor component, a first dimension (e.g., an X dimension) and / or a second dimension (e.g., a Y dimension) of the space and / or a third dimension (e.g., a W dimension) of a width of the first current path may be modified to facilitate reducing sensitivity of the device to noise and having a desired low mutual inductance for the device. For example, in conjunction with the design or formation of the circuit of the device, including a first current path, a second current path, a first Josephson junction component, a second Josephson junction component, a third Josephson junction component, a capacitor component, a current generator component, and a ground, with respect to the space associated with the circuit loop of the device, the system can design, determine, modify (e.g., adjust), or select a first dimension (e.g., X dimension) and / or a second dimension (e.g., Y dimension) of the space associated with the circuit loop, and / or a third dimension (e.g., W dimension) of the width of the first current path to facilitate reducing the device's sensitivity to noise and having a desired low mutual inductance for the device.

[0149] Figure 26 A flow chart of an exemplary non-limiting method 2600 for forming a device that can employ a high-kinetic inductor line in conjunction with a Josephson junction to facilitate desirable (e.g., enhanced, suitable, acceptable, or optimal) frequency tuning of a current bias is depicted according to various aspects and embodiments of the disclosed subject matter. Method 2600 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to a processor assembly and a memory. For the sake of brevity, repetitive descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted.

[0150] At 2602, a high kinetic inductance wiring may be formed along a first current path of a device, wherein the high kinetic inductance wiring may have a kinetic inductance level that may meet a defined threshold kinetic inductance level. At 2604, a first Josephson junction assembly and a second Josephson junction assembly may be formed on the device, wherein the first Josephson junction assembly and the second Josephson junction assembly may be coupled in series along a second current path of the assembly that is parallel to the first current path. For example, the system may form the high kinetic inductance wiring along the first current path, wherein the high kinetic inductance wiring may have a kinetic inductance level that may meet a defined threshold kinetic inductance level (e.g., the kinetic inductance level may be sufficiently high to meet or exceed a defined threshold high kinetic inductance level, wherein the defined threshold high kinetic inductance level may indicate that the kinetic inductance level has a sufficiently high value). The system may also form the first Josephson junction assembly and the second Josephson junction assembly, wherein the first Josephson junction assembly and the second Josephson junction assembly may be coupled in series along the second current path that is parallel to the first current path of the device. The first current path may also be associated with a first inductive component having a first inductance, and the second current path may be associated with a second inductive component having a second inductance.

[0151] At 2606, a capacitor assembly including a first terminal and a second terminal may be formed, wherein the first terminal may be associated with the second current path, and wherein the second terminal may be associated with a ground of the device. The capacitor assembly may have a desired capacitance, such as described herein. In certain embodiments, the system may form or place (e.g., insert) the capacitor assembly on the device, and may connect the first terminal to the second current path, such as between the first Josephson junction assembly and the second Josephson junction assembly, and may connect the second terminal of the capacitor assembly to the ground.

[0152] At 2608, a current generator assembly can be formed on the device, wherein the current generator assembly can supply desired currents to the first current path and the second current path of the device. In certain embodiments, the system can form or place (e.g., insert) the current generator assembly on the device, wherein an output of the current generator assembly can be associated with (e.g., directly or indirectly connected to) the first current path and the second current path of the device.

[0153] In some embodiments, method 2600 may proceed to reference point A, where: Figure 24 Method 2400 can be performed from reference point A.

[0154] For simplicity of explanation, these methods and / or computer-implemented methods are depicted and described as a series of actions. It should be understood and appreciated that disclosed subject matter is not limited by the order of the actions shown and / or actions, and for example actions can occur in different orders and / or simultaneously, and occur together with other actions not presented and described herein. In addition, not all actions shown are necessary for realizing the computer-implemented methods according to disclosed subject matter. In addition, it will be understood and appreciated by those skilled in the art that computer-implemented methods may alternatively be represented as a series of interrelated states via state diagrams or events. In addition, it should also be understood that the computer-implemented methods disclosed hereinafter and throughout this specification can be stored on goods so that such computer-implemented methods are transmitted and transferred to a computer. As used herein, the term goods is intended to encompass a computer program accessible from any computer-readable device or storage medium.

[0155] To provide context for various aspects of the disclosed subject matter, Figure 27 The following discussion is intended to provide a general description of a suitable environment in which aspects of the disclosed subject matter may be implemented. Figure 27 A block diagram of an example non-limiting operating environment that can facilitate one or more embodiments described herein is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted or may be omitted. Figure 27A suitable operating environment 2700 for implementing various aspects of the present disclosure may also include a computer 2712. The computer 2712 may also include a processing unit 2714, a system memory 2716, and a system bus 2718. The system bus 2718 couples system components, including but not limited to the system memory 2716, to the processing unit 2714. The processing unit 2714 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be used as the processing unit 2714. The system bus 2718 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI). System memory 2716 may also include volatile memory 2720 and non-volatile memory 2722. A basic input / output system (BIOS), which contains basic routines for transferring information between elements within computer 2712, such as during startup, is stored in non-volatile memory 2722. By way of example, and not limitation, non-volatile memory 2722 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 2720 may also include random access memory (RAM) that acts as external cache memory. By way of illustration, and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0156] The computer 2712 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 27For example, disk storage 2724 is shown. Disk storage 2724 may also include, but is not limited to, devices such as a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 2724 may also include, alone or in combination with other storage media, storage media including, but not limited to, an optical disk drive, such as a compact disk ROM device (CD-ROM), a CD recordable drive (CD-R drive), a CD rewritable drive (CD-RW drive), or a digital versatile disk ROM drive (DVD-ROM). To facilitate connection of disk storage 2724 to system bus 2718, a removable or non-removable interface, such as interface 2726, is typically used. Figure 27 Also depicted is software that acts as an intermediary between a user and the basic computer resources described in the appropriate operating environment 2700. Such software may also include, for example, an operating system 2728. Operating system 2728, which may be stored on disk storage 2724, is used to control and allocate resources of computer 2712. System applications 2730 utilize operating system 2728's management of resources through program modules 2732 and program data 2734, which are stored, for example, in system memory 2716 or on disk storage 2724. It should be understood that the present disclosure may be implemented using different operating systems or combinations of operating systems. A user enters commands or information into computer 2712 via input device 2736. Input device 2736 includes, but is not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to processing unit 2714 via system bus 2718 via interface port(s) 2738. Interface port 2738 includes, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device 2740 uses some of the same type of ports as input device 2736. Thus, for example, a USB port can be used to provide input to computer 2712, and output information from computer 2712 to output device 2740. Output adapter 2742 is provided to illustrate that, in addition to other output devices 2740, there are also some output devices 2740 that require special adapters, such as monitors, speakers, and printers. As an illustration and not limitation, output adapter 2742 includes a video and sound card that provides a connection method between output device 2740 and system bus 2718. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 2744.

[0157] Computer 2712 can operate in a networked environment using logical connections to one or more remote computers, such as remote computer 2744. Remote computer 2744 can be a computer, server, router, network PC, workstation, microprocessor-based appliance, peer device, or other public network node, and can generally include many or all of the elements described with respect to computer 2712. For the sake of simplicity, memory storage device 2746 is described only with respect to remote computer 2744. Remote computer 2744 is logically connected to computer 2712 via network interface 2748, and then physically connected via communication connection 2750. Network interface 2748 includes wired and / or wireless communication networks, such as a local area network (LAN), a wide area network (WAN), a cellular network, and the like. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, and the like. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variations, packet-switched networks, and Digital Subscriber Lines (DSL). The communication connection 2750 refers to the hardware / software used to connect the network interface 2748 to the system bus 2718. Although the communication connection 2750 is shown internal to the computer 2712 for clarity, it can also be external to the computer 2712. For exemplary purposes only, the hardware / software used to connect to the network interface 2748 can also include internal and external technologies, such as modems, including conventional telephone-grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

[0158] One or more embodiments can be systems, methods, devices and / or computer program products at any possible degree of technical detail integration. A computer program product can include a computer-readable storage medium (or multiple media) having a computer-readable program instruction for causing a processor to execute the aspects of one or more embodiments. A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium can be, for example but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media can include the following: a portable computer disk, a hard disk, a RAM, a ROM, an erasable programmable read-only memory (EPROM or flash memory), an SRAM, a portable CD-ROM, a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card, or a groove with a raised structure of instructions recorded thereon, and any suitable combination thereof. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0159] The computer-readable program instructions described herein can be downloaded to the corresponding computing / processing device from a computer-readable storage medium via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network, and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in the corresponding computing / processing device. The computer-readable program instructions for performing the operation of the disclosed subject matter can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Smalltalk, C++, etc.) and procedural programming languages ​​(e.g., "C" programming languages ​​or similar programming languages). The computer-readable program instructions can be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., using an internet service provider via the internet). In certain embodiments, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can perform computer-readable program instructions by personalizing the electronic circuit using state information of the computer-readable program instructions to perform various aspects of the disclosed subject matter.

[0160] Aspects of the disclosed subject matter are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams and the combination of the blocks in the flowcharts and / or block diagrams can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that the instructions executed by the processor of the computer or other programmable data processing device create a method for implementing the function / action specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored in a computer-readable storage medium, which enables a computer, a programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium having instructions stored therein includes an article of manufacture comprising instructions for implementing the function / action specified in one or more blocks of the flowcharts and / or block diagrams. Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational actions are performed on the computer, other programmable apparatus, or other device to produce computer-implemented processing, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in the flowchart and / or block diagram or multiple boxes.

[0161] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions and operations of the systems, methods and computer program products according to the different embodiments of the disclosed subject matter. To this end, each box in the flowchart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the box may not occur in the order marked in the figure. For example, depending on the functions involved, the two boxes shown in succession may be executed substantially simultaneously, or the boxes may sometimes be executed in the opposite order. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0162] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on a computer and / or a computer, it will be appreciated by those skilled in the art that the present disclosure may also be implemented in combination with other program modules. Typically, a program module includes routines, programs, components, data structures, etc. that perform specific tasks and / or implement specific abstract data types. In addition, it will be appreciated by those skilled in the art that the computer-implemented methods disclosed herein may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, small computing devices, mainframe computers and computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronic devices, etc. The aspects shown may also be implemented in a distributed computing environment, where tasks are performed by remote processing devices linked via a communication network. However, some (if not all) aspects of the present invention may be practiced on stand-alone computers. In a distributed computing environment, program modules may be located in local and remote memory storage devices.

[0163] As used in this application, the terms "component", "system", "platform", "interface" and the like may refer to and / or may include computer-related entities or entities related to an operating machine having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and / or a computer running on a processor. As an illustration, both an application running on a server and a server may be components. One or more components may reside within a process and / or a thread of execution, and a component may be located on one computer and / or distributed between two or more computers. In another example, the corresponding component may be executed from different computer-readable media having different data structures stored thereon. Components may communicate via local and / or remote processes, such as according to a signal having one or more data packets (e.g., data from a component interacting with another component in a local system, a distributed system, and / or data from a component interacting with other systems across a network such as the Internet via the signal). As another example, a component may be a device having a specific function provided by a mechanical component operated by an electrical or electronic circuit, which is operated by a software or firmware application executed by a processor. In such cases, the processor may be internal or external to the device and may execute at least a portion of a software or firmware application. As another example, the component may be a device that provides a specific functionality through electronic components without mechanical components, where the electronic components may include a processor or other means to execute the software or firmware that at least partially imparts the functionality of the electronic components. In one aspect, the component may emulate the electronic component via, for example, a virtual machine within a cloud computing system.

[0164] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. In addition, the articles "a" and "an" as used in the subject specification and drawings should generally be interpreted to mean "one or more" unless otherwise specified or clear from the context to point to the singular form. As used herein, the terms "example" and / or "exemplary" are used to indicate use as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited to such examples. In addition, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as superior or preferred over other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0165] As used in this specification, the term "processor" may refer to substantially any computational processing unit or device, including but not limited to a single-core processor; a single processor with software multi-threaded execution capability; a multi-core processor; a multi-core processor with software multi-threaded execution capability; a multi-core processor with hardware multi-threading technology; a parallel platform; and a parallel platform with distributed shared memory. In addition, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. Further, the processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, in order to optimize space usage or enhance the performance of user devices. The processor may also be implemented as a combination of computational processing units. In this disclosure, terms such as "storage," "memory," "data storage," "data storage," "database," and substantially any other information storage component related to the operation and functionality of a component are used to refer to a "memory component," an entity embodied in "memory," or a component that includes memory. It should be understood that the memory and / or memory components described herein can be volatile memory or non-volatile memory, or can include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory can include ROM, PROM, EPROM, EEPROM, flash memory, or non-volatile RAM (e.g., FeRAM). Volatile memory can include, for example, RAM that can act as external cache memory. By way of illustration, and not limitation, RAM is available in many forms, such as SRAM, DRAM, SDRAM, DDRSDRAM, ESDRAM, SLDRAM, DRRAM, DRDRAM, and RDRAM. Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but are not limited to, these and any other suitable types of memory.

[0166] What has been described above only includes examples of systems and computer-implemented methods. Of course, for the purposes of describing the present disclosure, it is not possible to describe every conceivable combination of components or computer-implemented method, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. In addition, to the extent that the terms "including," "having," "having," and the like are used in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in a manner similar to the term "comprising" in that "comprising" is interpreted as inclusive when used as a transition word in the claims. The descriptions of different embodiments have been presented for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to one of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable one of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: a first Josephson junction positioned along a first current path of the device; as well as a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path, wherein the first Josephson junction is larger in area than the second Josephson junction and the third Josephson junction, and wherein a current splitting ratio between the first current path and the second current path is increased based on the first Josephson junction being larger in area than the second Josephson junction and the third Josephson junction.

2. The device according to claim 1, wherein The device is a qubit device.

3. The device according to claim 1, wherein: The device is a transport sub-qubit device.

4. The device according to claim 1, wherein: The device is a current-biased tunable qubit.

5. The device according to any one of the preceding claims 1 to 4, further comprising: A current generator component applies current to the device, wherein the frequency of the device is controlled based on an amount of the current applied to the device by the current generator component and an arrangement of the second and third Josephson junctions relative to the first Josephson junction.

6. The device according to any one of the preceding claims 1 to 4, further comprising: a first inductive component positioned along the first current path; a second inductive component positioned along the second current path; as well as A capacitor assembly includes a first terminal and a second terminal, wherein the first terminal is associated with the second and third Josephson junctions, and wherein the second terminal is associated with a ground for the device.

7. The device according to any one of the preceding claims 1 to 4, further comprising: a low-pass filter component that applies a low-pass filter to the current, wherein at least a portion of the filtered current output from the low-pass filter component is supplied to the first current path and the second current path, and wherein the low-pass filter is associated with a defined threshold frequency that indicates a cut-off frequency of the low-pass filter; and A current shunt assembly diverts another portion of the filtered current output to a ground of the device.

8. A method comprising: forming a first Josephson junction along a first current path of the device; as well as forming a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path, wherein the first Josephson junction has an area larger than each of the second Josephson junction and the third Josephson junction, and wherein a current splitting ratio between the first current path and the second current path is increased based on the first Josephson junction being larger in area than the second Josephson junction and the third Josephson junction.

9. The method according to claim 8, wherein: The device is a qubit device.

10. The method according to claim 9, wherein: The qubit device is a transport sub-qubit device.

11. The method according to any one of the preceding claims 8 to 10, further comprising: A current is applied to the device, wherein the frequency of the device is tuned based on a level of the current applied to the device and an arrangement of the second and third Josephson junctions relative to the first Josephson junction.

12. The method according to any one of the preceding claims 8 to 10, wherein: The first current path is associated with a first wiring having a first inductance level, and wherein the second current path is associated with a second wiring having a second inductance level.

13. The method according to any one of the preceding claims 8 to 10, further comprising: A capacitor is formed including a first terminal and a second terminal, wherein the first terminal is associated with the second current path, and wherein the second terminal is associated with a ground of the device.

14. A qubit device comprising: a high kinetic inductance line positioned along a first current path of the device, wherein the high kinetic inductance line has a kinetic inductance level that satisfies a defined threshold kinetic inductance level; as well as and a first and a second Josephson junction coupled in series along a second current path of the device, the second current path being in parallel with the first current path, wherein the first and second Josephson junctions facilitate adjusting a frequency of the qubit device, and wherein the frequency of the qubit device is adjusted based on an amount of current applied to the qubit device and an arrangement of the first and second Josephson junctions relative to the high kinetic inductor line.

15. The qubit device of claim 14, wherein the qubit device is a transport sub-qubit device.

16. The qubit device of claim 14, wherein a current splitting ratio between the first current path and the second current path is based on a relationship between the high kinetic inductance line, the first Josephson junction, and the second Josephson junction.

17. The qubit device of any preceding claim 14-16, further comprising: a first inductive component positioned along the first current path; a second inductive component positioned along the second current path; as well as A capacitor assembly includes a first terminal and a second terminal, wherein the first terminal is associated with the second current path, and wherein the second terminal is associated with a ground for the qubit device.

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