Junction termination structure and method of manufacturing the same, semiconductor device

Abstract

The application provides a junction termination structure and a preparation method thereof and a semiconductor device. The junction termination structure comprises a cell region and a termination region located at the periphery of the cell region. The junction termination structure comprises a substrate with a first conductivity type, an epitaxial layer with the first conductivity type located above the substrate, and a plurality of annular grooves located in the epitaxial layer. The plurality of annular grooves are located in the termination region and surround the cell region, comprising first-type annular grooves and second-type annular grooves, and each annular groove is provided with a polysilicon structure and a first insulating layer covering the bottom wall and the side wall of the annular groove; the first-type annular groove is further provided with a second insulating layer and a conductive structure, two polysilicon structures are arranged in the first-type annular groove, the two polysilicon structures are located on the opposite sides of the conductive structure, and the second insulating layer is located between the polysilicon structure and the conductive structure. At least one annular groove close to the cell region is the first-type annular groove, and the conductive structure in the at least one first-type annular groove is configured to be connected to zero potential when the junction termination structure is reversely broken down.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a junction termination structure, its fabrication method, and a semiconductor device. Background Technology

[0002] In the field of power electronics, power semiconductor devices serve as core control components, and their characteristics play a crucial role in the performance of power systems. Among these, the junction termination structure is a key structural feature of power semiconductor devices.

[0003] Currently, power semiconductor devices, such as junction termination devices, exhibit instability during reverse breakdown, leading to abnormal reverse breakdown of junction termination devices. Summary of the Invention

[0004] A first aspect of this application provides a junction termination structure. The junction termination structure includes a cell region and a termination region located on the periphery of the cell region; the junction termination structure includes:

[0005] Substrate having a first conductivity type;

[0006] An epitaxial layer having a first conductivity type is located on the substrate;

[0007] The epitaxial layer contains a plurality of annular grooves located in the termination region and surrounding the cell region. The plurality of annular grooves include a first type of annular groove and a second type of annular groove. Each annular groove contains a polysilicon structure and a first insulating layer covering the bottom and sidewalls of the annular groove. The first type of annular groove also contains a second insulating layer and a conductive structure. Two polysilicon structures are located on opposite sides of the conductive structure within the first type of annular groove. The second insulating layer is located between the polysilicon structure and the conductive structure. At least one annular groove near the cell region is a first type of annular groove, and the conductive structure within at least one of the first type of annular grooves is configured such that the junction termination structure is connected to zero potential during reverse breakdown.

[0008] In one embodiment, the number of the first type of annular groove is one; or...

[0009] When there are two or more of the first type of annular grooves, the distance between each of the first type of annular grooves and the cell region is less than the distance between the second type of annular groove and the cell region; the conductive structure in the first type of annular groove with the smallest distance from the cell region is configured such that the junction termination structure is connected to zero potential during reverse breakdown.

[0010] In one embodiment, the junction termination structure further includes a gate and a source, and the conductive structure is electrically connected to the gate or the source.

[0011] In one embodiment, the junction termination structure further includes a field-limiting ring having a second conductivity type located below the first type of annular groove.

[0012] In one embodiment, the junction termination structure further includes a gate polysilicon located in the epitaxial layer; the polysilicon structure is made of the same material as the gate polysilicon.

[0013] In one embodiment, the width of the first type of annular groove is greater than the width of the second type of annular groove.

[0014] A second aspect of this application provides a semiconductor device, the semiconductor device including the junction termination structure described above.

[0015] A third aspect of this application provides a method for preparing a junction terminal structure, the junction terminal structure comprising a cell region and a terminal region located on the periphery of the cell region; the preparation method includes:

[0016] Provide a substrate having a first conductivity type;

[0017] An epitaxial layer having a first conductivity type is formed on the substrate;

[0018] A plurality of annular grooves are formed in the epitaxial layer surrounding the cell region, the plurality of annular grooves being located in the terminal region; the plurality of annular grooves include a first type of annular groove and a second type of annular groove; at least one annular groove near the cell region is a first type of annular groove.

[0019] Within the first type of annular groove, a first insulating layer, two polysilicon structures, a second insulating layer, and a conductive structure are sequentially formed, covering the sidewalls and bottom wall of the first type of annular groove; the two polysilicon structures are located on opposite sides of the conductive structure, and the second insulating layer is located between the polysilicon structure and the conductive structure; at least one of the conductive structures is configured such that the junction termination structure is connected to zero potential during reverse breakdown; within the second type of annular groove, the first insulating layer and the polysilicon structure are sequentially formed, covering the sidewalls and bottom wall of the second type of annular groove.

[0020] In one embodiment, after forming the two polysilicon structures within the first type of annular groove and before forming the conductive structure within the first type of annular groove, the method for preparing the junction termination structure further includes:

[0021] A field-limiting ring with a second conductivity type is simultaneously formed below the first type of annular groove and between adjacent annular grooves.

[0022] In one embodiment, the fabrication method includes: forming a gate polysilicon in the epitaxial layer;

[0023] The step of forming the gate polysilicon in the epitaxial layer is performed simultaneously with the step of forming the polysilicon structure.

[0024] In one embodiment, the fabrication method includes: forming a gate and a source;

[0025] The conductive structure is electrically connected to the gate or the source.

[0026] The main technical effects achieved by the embodiments of this application are:

[0027] The junction termination structure, its fabrication method, and semiconductor device provided in this application embodiment, since at least one annular groove near the cell region is a first type of annular groove, and the conductive structure in at least one first type of annular groove is connected to zero potential when the junction termination structure undergoes reverse breakdown, can make the potential distribution in the termination region more dispersed, thereby effectively reducing the breakdown voltage and breakdown electric field borne by the first insulating layer of the first type of annular groove, improving the problem of electric field and potential concentration at the first insulating layer in the first type of annular groove, improving the working stability of the junction termination structure during reverse breakdown, and ensuring normal operation of the junction termination structure during reverse breakdown. Attached Figure Description

[0028] Figure 1 This is a partial cross-sectional view of a terminal structure provided in an exemplary embodiment of this application;

[0029] Figure 2 This is a partial top view of a terminal structure provided in an exemplary embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the electric field line distribution of a junction terminal structure during reverse breakdown;

[0031] Figure 4 This is a schematic diagram of the electric field line distribution of the junction termination structure provided in an exemplary embodiment of this application during reverse breakdown;

[0032] Figure 5 This is a flowchart illustrating a method for preparing a terminal structure according to an exemplary embodiment of this application;

[0033] Figure 6 This is a partial cross-sectional view of the first intermediate structure of the terminal structure provided in an exemplary embodiment of this application;

[0034] Figure 7 This is a partial cross-sectional view of the second intermediate structure of the terminal structure provided in an exemplary embodiment of this application;

[0035] Figure 8 This is a partial cross-sectional view of the third intermediate structure of the terminal structure provided in an exemplary embodiment of this application;

[0036] Figure 9 This is a partial cross-sectional view of the fourth intermediate structure of the terminal structure provided in an exemplary embodiment of this application;

[0037] Figure 10 This is a partial cross-sectional view of the fifth intermediate structure of the terminal structure provided in an exemplary embodiment of this application;

[0038] Figure 11 This is a partial cross-sectional view of the sixth intermediate structure of the terminal structure provided in an exemplary embodiment of this application. Specific Implementation

[0039] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0040] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0041] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0042] As described in the background section, existing junction termination structures exhibit instability during reverse breakdown, leading to abnormal reverse breakdown in junction-terminated devices. The junction termination structure contains a dielectric layer and a polysilicon structure within the trench near the cell region. The inventors have discovered that during reverse breakdown, the electric field and potential concentrate at the dielectric layer location within the trench near the cell region. As the rated voltage of the junction termination structure increases, it becomes prone to reverse breakdown instability, affecting its reverse breakdown performance.

[0043] This application provides a junction terminal structure and its preparation method, which can solve the above-mentioned technical problems. The following describes some embodiments of this application in detail with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0044] In this embodiment, for ease of description, the direction from the substrate to the epitaxial layer is defined as "up," and the direction from the epitaxial layer to the substrate is defined as "down," thus determining the up and down directions. It is easy to understand that different direction definitions do not affect the actual operation of the process or the actual form of the product.

[0045] Figure 1 and Figure 2 This is a partial structural diagram of the terminal structure provided in an embodiment of this application. See also... Figure 1 and Figure 2 The junction terminal structure includes a cell region 101 and a terminal region 102 located on the periphery of the cell region 101. The terminal region 102 surrounds the cell region 101.

[0046] The junction termination structure includes a substrate 10 having a first conductivity type, an epitaxial layer 20 having the first conductivity type located on the substrate 10, and a plurality of annular grooves 21 located in the epitaxial layer 20. The substrate 10 and the epitaxial layer 20 are located in the cell region 101 and the termination region 102, respectively. The plurality of annular grooves 21 are located in the termination region 102 and surround the cell region 101. The plurality of annular grooves 21 include a first type of annular groove 211 and a second type of annular groove 212. Each of the annular grooves 21 is provided with a polysilicon structure 32 and a first insulating layer 42 covering the bottom wall and sidewalls of the annular groove 21. The first type of annular groove 211 is also provided with a second insulating layer 43 and a conductive structure 33. Two of the polysilicon structures 32 are provided in the first type of annular groove 211, and the two polysilicon structures 32 are located on opposite sides of the conductive structure 33. The second insulating layer 43 is located between the polysilicon structure 32 and the conductive structure 33. At least one annular groove 21 near the cell region 101 is a first type of annular groove 211, and the conductive structure 33 within at least one first type of annular groove 211 is configured such that the junction termination structure is connected to zero potential during reverse breakdown.

[0047] The junction termination structure provided in this application embodiment, by setting at least one annular groove 21 near the cell region 101 as a first type of annular groove 211, and the conductive structure 33 in at least one first type of annular groove 211 is connected to zero potential when the junction termination structure is reversed, can make the potential distribution of the termination region 102 more dispersed, thereby effectively reducing the breakdown voltage and breakdown electric field borne by the first insulating layer 42 in the first type of annular groove 211, improving the problem of electric field and potential concentration at the first insulating layer 42 in the first type of annular groove 211, and improving the working stability of the junction termination structure during reverse breakdown.

[0048] In one embodiment, such as Figure 1 and Figure 2 As shown, the junction termination structure further includes a gate polysilicon 31, a source 52, a drain 53, and a gate 51. Figure 2 Middle boundary line 511 is the boundary line of gate 51, and the portion between the two boundary lines 511 is gate 51; boundary line 512 is the boundary of source 52. Figure 2 Only one boundary of the source 52 is shown in the diagram. The junction termination structure also includes a body region having a first conductivity type and a source region having a second conductivity type, the body region and the source region being located in the cell region. The source 52 is at least partially located above and in contact with the source region. The gate polysilicon 31 is located in the epitaxial layer 20. The gate 51 is electrically connected to the gate polysilicon 31. The gate 51 and the source 52 may be located on the side of the epitaxial layer 20 away from the substrate 10, and the drain 53 is located on the side of the substrate 10 away from the epitaxial layer 20.

[0049] In one embodiment, the gate 51 is made of the same material as the source 52 and is formed in the same process step. This arrangement helps to simplify the fabrication process of the junction termination structure.

[0050] In one embodiment, such as Figure 1 and Figure 2 As shown, the junction termination structure further includes a dielectric material layer 70 located on the side of the epitaxial layer 20 facing away from the substrate 10. The source electrode 52 is electrically connected to the source region through a via on the dielectric material layer. In some embodiments, the material of the dielectric material layer 70 is silicon dioxide, silicon nitride, etc. The gate electrode 51 and the source electrode 52 are located on the surface of the dielectric material layer 70 facing away from the substrate 10.

[0051] In one embodiment, the dielectric material layer 70 includes a first dielectric layer 71, a second dielectric layer 72, and a third dielectric layer 73. The thickness of the first dielectric layer 71 and the thickness of the second dielectric layer 72 are both less than the thickness of the third dielectric layer 73.

[0052] In one embodiment, the junction termination structure further includes a stop region located around the termination region 102.

[0053] In one embodiment, such as Figure 1 and Figure 2 As shown, there is only one of the first type of annular groove 211. When there is only one first type of annular groove 211, the conductive structure 33 within the first type of annular groove 211 is configured to be connected to zero potential during reverse breakdown of the junction termination structure. This configuration can improve the problem of unstable operation of the junction termination structure during reverse breakdown and also avoid the problem of increasing the size of the junction termination structure due to a large number of first type of annular grooves 211.

[0054] In another embodiment, when there are two or more of the first type of annular grooves 211, the distance between each of the first type of annular grooves 211 and the cell region 101 is smaller than the distance between the second type of annular groove 212 and the cell region 101. The conductive structure 33 in the first type of annular groove 211 with the smallest distance from the cell region 101 is configured to be connected to zero potential during reverse breakdown of the junction termination structure. By configuring the conductive structure 33 in the first type of annular groove 211 with the smallest distance from the cell region 101 to be connected to zero potential during reverse breakdown of the junction termination structure, the electric field and potential distribution in the termination region of the junction termination structure can be made more uniform more effectively, which helps to improve the working stability of the junction termination structure during reverse breakdown.

[0055] In one embodiment, such as Figure 1 As shown, the junction termination structure also includes a gate polysilicon 31 located in the epitaxial layer 20; the polysilicon structure 32 is made of the same material as the gate polysilicon 31 and is formed in the same process step. Thus, the polysilicon structure 32 and the gate polysilicon 31 can be formed in the same process step, which helps simplify the fabrication process of the junction termination structure.

[0056] In some embodiments, the materials of the polysilicon structure 32 and the gate polysilicon 31 may both be polysilicon materials.

[0057] In some embodiments, the material of the conductive structure 33 may also be polycrystalline silicon.

[0058] In one embodiment, such as Figure 1 As shown, the conductive structure 33 is electrically connected to the gate 51 to achieve zero potential for the conductive structure 33 during reverse breakdown of the junction termination structure. During reverse breakdown of the junction termination structure, the gate and source are short-circuited and both are at zero potential, while the drain is at a high potential. Therefore, by electrically connecting the conductive structure 33 to the gate 51 or the source, the conductive structure 33 can be made to reach zero potential during reverse breakdown of the junction termination structure. Electrically connecting the conductive structure 33 to the gate 51 is relatively simple and easy to implement.

[0059] Specifically, the gate 51 is electrically connected to the conductive structure 33 through a via formed in the dielectric layer 70. In other embodiments, the conductive structure 33 may be electrically connected to the source.

[0060] In another embodiment, the conductive structure 33 is electrically connected to the source 52, so that the conductive structure 33 is at zero potential during the reverse breakdown of the junction termination structure. During the reverse breakdown of the junction termination structure, the gate and source are short-circuited and both are at zero potential, while the drain is at a high potential. Therefore, the conductive structure 33 is electrically connected to the source 52, which enables the conductive structure 33 to be at zero potential during the reverse breakdown of the junction termination structure.

[0061] In one embodiment, the epitaxial layer 20 further includes a trench 22, with the gate polysilicon 31 located within the trench 22. A gate insulating layer 41, covering the sidewalls and bottom wall of the trench 22, is provided within the trench 22, insulating the epitaxial layer 20 from the gate polysilicon 31. The trench 22 and the annular trench 21 are formed in the same process step.

[0062] In one embodiment, the gate insulating layer 41 in the trench 22, the first insulating layer 42 in the annular trench 21, and the first dielectric layer 71 are made of the same material and are formed simultaneously in the same process step. This helps to simplify the fabrication process of the junction termination structure.

[0063] In one embodiment, the second dielectric layer 72 and the second insulating layer 43 are made of the same material and can be formed simultaneously in the same process step.

[0064] In one embodiment, the gate insulating layer 41, the first insulating layer 42, and the second insulating layer 43 may be made of materials such as silicon dioxide.

[0065] In one embodiment, such as Figure 1 As shown, the junction termination structure also includes a field-limiting ring 60 with a second conductivity type located below the first type of annular groove 211. The field-limiting ring 60 is annular and surrounds the cell region 101. By setting the field-limiting ring 60 below the first type of annular groove 211, the junction depth of the junction termination structure can be increased, thereby making the potential distribution of the junction termination structure more uniform during reverse breakdown and improving the working stability of the junction termination structure during reverse breakdown.

[0066] In one embodiment, the junction termination structure further includes a field limiting ring 60 of a second conductivity type located between two adjacent annular grooves 21, and a field limiting ring 60 of a second conductivity type located between a first type of annular groove 211 and a trench 22. The field limiting ring 60 located between two adjacent annular grooves 21 includes a field limiting ring 60 located between two adjacent second type annular grooves 212, and a field limiting ring 60 located between a first type annular groove 211 and an adjacent second type annular groove 212. When the number of first type annular grooves 211 is two or more, the field limiting ring 60 located between two adjacent annular grooves 21 also includes a field limiting ring 60 located between two adjacent first type annular grooves 211.

[0067] In some embodiments, the field limiting ring 60 located between adjacent annular grooves 21, the field limiting ring 60 located between the first type of annular groove 211 and the groove 22, and the field limiting ring 60 located below the first type of annular groove 211 are formed simultaneously in the same process step. This arrangement helps to simplify the fabrication process of the junction termination structure.

[0068] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. That is, the substrate 10 is an N-type substrate, the epitaxial layer 20 is an N-type epitaxial layer, the field confinement ring 60 is P-type doped, the body region is N-type doped, and the source region is P-type doped.

[0069] In one embodiment, the doping concentration of the epitaxial layer 20 is less than the doping concentration of the substrate 10, and the doping concentration of the body region is greater than the doping concentration of the source region.

[0070] In one embodiment, the width of the first type of annular groove 211 is greater than the width of the second type of annular groove 212. This arrangement helps to set a conductive structure within the first type of annular groove.

[0071] Preferably, the width of the first type of annular groove 211 is greater than the thickness of the polycrystalline silicon material deposited twice (the dimension of the polycrystalline silicon material in the direction from the substrate to the epitaxial layer). This setting avoids the first type of annular groove 211 being too narrow, which could cause the two polycrystalline silicon structures 32 to become connected and difficult to separate when forming the polycrystalline silicon structure.

[0072] Figure 3 This is a schematic diagram of the electric field line distribution of a junction termination structure during reverse breakdown. Figure 4 This is a schematic diagram of the electric field line distribution of the junction termination structure provided in this application during reverse breakdown. Figure 3 It can be seen that, Figure 3In the junction termination structure shown, the annular groove 212' near the cell region only contains an insulating layer 42' covering the bottom and side walls of the annular groove 212' and a polycrystalline silicon structure 32'. During reverse breakdown, the electric field lines at the insulating layer 42' are concentrated. Figure 4 It can be seen that the junction termination structure provided in this application provides a relatively uniform electric field line distribution during reverse breakdown, which improves the problem of concentrated electric field line distribution at the first insulating layer 42 within the first type of annular groove 211 near the cell region. It is understood that the junction termination structure provided in this application can make the potential distribution in the termination region 102 more dispersed during reverse breakdown, thereby improving the operational stability of the junction termination structure during reverse breakdown.

[0073] This application also provides a method for preparing a junction terminal structure. For example... Figure 1 and Figure 2 As shown, the junction terminal structure includes a cell region 101 and a terminal region 102 located on the periphery of the cell region 101. Figure 5 As shown, the method for preparing the junction terminal structure includes the following steps 110 to 140. Each step will be described below.

[0074] In step 110, a substrate having a first conductivity type is provided.

[0075] In step 120, an epitaxial layer having a first conductivity type is formed on the substrate.

[0076] In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0077] In one embodiment of this application, an N-type doped semiconductor can be used as a substrate 10, and an epitaxial layer 20 can be formed by depositing an N-type semiconductor on the substrate 10 through an epitaxial growth method.

[0078] In step 130, a plurality of annular grooves surrounding the cell region are formed in the epitaxial layer, the plurality of annular grooves being located in the terminal region; the plurality of annular grooves include a first type of annular groove and a second type of annular groove; at least one annular groove close to the cell region is a first type of annular groove.

[0079] In one embodiment, an annular groove 21 can be formed in the epitaxial layer 20 by photolithography and etching techniques.

[0080] Step 130 yields the following result: Figure 6 The first intermediate structure shown. (As shown) Figure 6 As shown, the annular groove 21 includes a first type of annular groove 211 and a second type of annular groove 212, wherein the width of the first type of annular groove 211 is greater than the width of the second type of annular groove 212. When the annular groove 21 is formed in step 130, the trench 22 is also formed simultaneously.

[0081] In step 140, a first insulating layer, two polysilicon structures, a second insulating layer, and a conductive structure are sequentially formed within the first type of annular groove, covering the sidewalls and bottom wall of the first type of annular groove; the two polysilicon structures are located on opposite sides of the conductive structure, and the second insulating layer is located between the polysilicon structure and the conductive structure; at least one of the conductive structures is configured such that the junction termination structure is connected to zero potential during reverse breakdown; the first insulating layer and the polysilicon structure are sequentially formed within the second type of annular groove, covering the sidewalls and bottom wall of the second type of annular groove.

[0082] Figure 1 and Figure 2 In the illustrated embodiment, the number of the first type of annular groove 211 is one. When the number of the first type of annular groove 211 is one, the conductive structure 33 within the first type of annular groove 211 is configured to be connected to zero potential during reverse breakdown of the junction termination structure. In other embodiments, the number of the first type of annular groove 211 may be two or more, and the distance between each of the first type of annular groove 211 and the cell region 101 is less than the distance between the second type of annular groove 212 and the cell region 101; wherein the conductive structure 33 within the first type of annular groove 211 with the smallest distance from the cell region 101 is configured to be connected to zero potential during reverse breakdown of the junction termination structure.

[0083] In one embodiment, step 140 may include the following process:

[0084] First, a first insulating layer covering the sidewalls and bottom wall of the first type of annular groove is formed sequentially in the first type of annular groove, and a first insulating layer covering the sidewalls and bottom wall of the second type of annular groove is formed sequentially in the second type of annular groove.

[0085] This step yields the following result: Figure 7 The second intermediate structure shown. (As shown) Figure 7 As shown, the first insulating layer 42 in the first type of annular trench 211 covers the bottom wall and sidewalls of the first type of annular trench 211, and the first insulating layer 42 in the second type of annular trench 212 covers the bottom wall and sidewalls of the second type of annular trench 212. The gate insulating layer 41 in the trench 22 is formed simultaneously with the first insulating layer 42. The materials of the first insulating layer 42 and the gate insulating layer 41 can be silicon oxide. The first insulating layer 42 and the gate insulating layer 41 can be formed by oxidation deposition or thermal oxidation deposition. When forming the first insulating layer 42, a first dielectric layer 71 is simultaneously formed on the surface of the epitaxial layer facing away from the substrate.

[0086] Subsequently, a polycrystalline silicon structure is formed within the first type of annular groove and the second type of annular groove.

[0087] This step yields the following result: Figure 8 The third intermediate structure shown. (As shown in the image) Figure 8 As shown, two oppositely arranged polysilicon structures 32 are formed in the first type of annular groove 211. The polysilicon structures are located inside the first insulating layer 42, and the two polysilicon structures 32 are spaced apart. A polysilicon structure 32 is formed in the second type of annular groove 212. The polysilicon structure 32 fills the gap between the portions of the first insulating layer 42 located on both sides of the second type of annular groove 212.

[0088] In one embodiment, the method for fabricating the junction termination structure further includes: forming a gate polysilicon in the epitaxial layer. In some embodiments, the material of the gate polysilicon and the material of the polysilicon structure are both polysilicon; the step of forming the gate polysilicon in the epitaxial layer and the step of forming the polysilicon structure can be performed simultaneously. This helps to simplify the fabrication process. Figure 8 As shown, a gate polysilicon 31 is formed in the trench 22 while the polysilicon structure 32 is being formed.

[0089] In one embodiment, the gate polysilicon 31 and the polysilicon structure 32 can be formed by depositing polysilicon material and etching technology.

[0090] In one embodiment, after the two polysilicon structures are formed in the first type of annular groove and before the conductive structure is formed in the first type of annular groove, step 140 may further include the following step: simultaneously forming a field-limiting ring having a second conductivity type below the first type of annular groove and between adjacent annular grooves.

[0091] This step yields the following result: Figure 9 The fourth intermediate structure is shown. (As shown in the image.) Figure 9 As shown, when field limiting rings 60 are formed below the first type of annular groove 211 and between adjacent annular grooves 21, field limiting rings 60 are simultaneously formed between the first type of annular groove 211 and the trench 22. A second insulating layer 43 is formed inside the first type of annular groove 211, covering the sidewalls of the two polysilicon structures 32, and the second insulating layers 43 located on the sidewalls of the two polysilicon structures 32 are spaced apart.

[0092] In this step, a P-type field limiting ring 60 can be formed in the epitaxial layer 20 by implanting impurities and then annealing. During the annealing process after impurity implantation, a second insulating layer 43 covering the sidewalls of the polysilicon structure 32 is formed within the first type of annular groove 211. While forming the second insulating layer 43, a second dielectric layer 72 is simultaneously formed on the surface of the first dielectric layer 71 facing away from the substrate.

[0093] Subsequently, a conductive structure is formed within the first type of annular groove.

[0094] This step yields the following result: Figure 10 The fifth intermediate structure is shown. (As shown in the image.) Figure 10 As shown, the conductive structure 33 is located in the gap between the second insulating layers 43.

[0095] In one embodiment, the conductive structure is made of polycrystalline silicon, and the conductive structure 33 can be formed by depositing polycrystalline silicon and etching.

[0096] In one embodiment, after step 140, the method for fabricating the junction termination structure further includes: forming a third dielectric layer on the surface of the epitaxial layer facing away from the substrate, thereby obtaining a dielectric material layer comprising a first dielectric layer, a second dielectric layer, and a third dielectric layer. This step yields a structure as follows: Figure 11 The sixth intermediate structure is shown. (As shown in the image.) Figure 11 As shown, the dielectric material layer 70 includes a first dielectric layer 71, a second dielectric layer 72, and a third dielectric layer 73. The third dielectric layer 73 covers the surface of the epitaxial layer 20 as projected onto the substrate 10. The third dielectric layer 73 can be formed on the epitaxial layer 20 using an oxidation deposition process or a thermal oxidation deposition process.

[0097] In one embodiment, before forming a dielectric layer on the surface of the epitaxial layer away from the substrate, the method for fabricating the junction termination structure further includes: forming a body region having a first conductivity type and a source region having a second conductivity type in the epitaxial layer, wherein the body region and the source region are located in the cell region.

[0098] In one embodiment, after forming a dielectric layer on the surface of the epitaxial layer away from the substrate, the method for fabricating the junction termination structure further includes: forming a gate, a source, and a drain. This step yields a structure as shown below. Figure 1 and Figure 2 The terminal structure shown. Figure 1 and Figure 2 As shown, the source 52 and gate 51 are located on the side of the dielectric layer 70 away from the substrate 10, and the drain 53 is located on the side of the substrate 10 away from the epitaxial layer 20. The source 52 can be electrically connected to the source region through a via formed in the dielectric layer 70. The gate 51 is electrically connected to the gate polysilicon 31. The gate 51 is electrically connected to the conductive structure 33 through a via formed in the dielectric layer 70. In other embodiments, the conductive structure 33 can be electrically connected to the source.

[0099] In this step, the gate 51 and the source 52 can be formed in the same process step. The drain 53 can be formed after the source 52 or before the source 52.

[0100] The preparation method of the junction terminal structure provided in this application and the junction terminal structure belong to the same inventive concept. The beneficial effects and related details can be referred to each other, and will not be repeated here.

[0101] This application also provides a semiconductor device comprising the junction termination structure described in any of the above embodiments. The semiconductor device may also include other types of field-effect transistors.

[0102] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0103] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0104] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A junction terminal structure, characterized in that, The junction termination structure includes a cell region and a termination region located on the periphery of the cell region; the junction termination structure includes: Substrate having a first conductivity type; An epitaxial layer having a first conductivity type is located on the substrate; The epitaxial layer contains a plurality of annular grooves located in the termination region and surrounding the cell region. The plurality of annular grooves include a first type of annular groove and a second type of annular groove. Each annular groove contains a polysilicon structure and a first insulating layer covering the bottom and sidewalls of the annular groove. The first type of annular groove also contains a second insulating layer and a conductive structure. Two polysilicon structures are located within the first type of annular groove, positioned on opposite sides of the conductive structure. The second insulating layer is located between the polysilicon structure and the conductive structure. The conductive structure is located on the side of the bottom wall of the first type of annular groove covered by the first insulating layer, away from the substrate. At least one annular groove near the cell region is a first type of annular groove, and the conductive structure within at least one first type of annular groove is configured such that the junction termination structure is connected to zero potential during reverse breakdown. The junction termination structure also includes a gate and a source. The conductive structure is electrically connected to the gate or the source. During reverse breakdown, the gate and source of the junction termination structure are short-circuited and both are connected to zero potential.

2. The junction termination structure according to claim 1, characterized in that, The number of the first type of annular groove is one; or, When there are two or more of the first type of annular grooves, the distance between each of the first type of annular grooves and the cell region is less than the distance between the second type of annular groove and the cell region; the conductive structure in the first type of annular groove with the smallest distance from the cell region is configured such that the junction termination structure is connected to zero potential during reverse breakdown.

3. The junction termination structure according to claim 1, characterized in that, The junction terminal structure also includes a field-limiting ring with a second conductivity type located below the first type of annular groove.

4. The junction termination structure according to claim 1, characterized in that, The junction termination structure further includes a gate polysilicon located in the epitaxial layer; the polysilicon structure is made of the same material as the gate polysilicon.

5. The junction termination structure according to claim 1, characterized in that, The width of the first type of annular groove is greater than the width of the second type of annular groove.

6. A semiconductor device, characterized in that, The semiconductor device includes the junction termination structure according to any one of claims 1 to 5.

7. A method for preparing a junction terminal structure, characterized in that, The junction terminal structure includes a cellular region and a terminal region located on the periphery of the cellular region; the preparation method includes: Provide a substrate having a first conductivity type; An epitaxial layer having a first conductivity type is formed on the substrate; A plurality of annular grooves are formed in the epitaxial layer surrounding the cell region, the plurality of annular grooves being located in the terminal region; the plurality of annular grooves include a first type of annular groove and a second type of annular groove; at least one annular groove near the cell region is a first type of annular groove. Within the first type of annular groove, a first insulating layer, two polysilicon structures, a second insulating layer, and a conductive structure are sequentially formed, covering the sidewalls and bottom wall of the first type of annular groove. The two polysilicon structures are located on opposite sides of the conductive structure, and the second insulating layer is located between the polysilicon structures and the conductive structure. At least one of the conductive structures is configured such that the junction termination structure is connected to zero potential during reverse breakdown. Within the second type of annular groove, the first insulating layer and the polysilicon structure are sequentially formed, covering the sidewalls and bottom wall of the second type of annular groove. The conductive structure is located on the side of the first insulating layer covering the bottom wall of the first type of annular groove, away from the substrate. A gate and a source are formed; the conductive structure is electrically connected to the gate or the source; during reverse breakdown, the gate and the source of the junction termination structure are short-circuited and both are connected to zero potential.

8. The method for preparing the junction terminal structure according to claim 7, characterized in that, After forming the two polycrystalline silicon structures within the first type of annular groove, and before forming the conductive structure within the first type of annular groove, the method for preparing the junction termination structure further includes: A field-limiting ring with a second conductivity type is simultaneously formed below the first type of annular groove and between adjacent annular grooves.

9. The method for preparing the junction terminal structure according to claim 7, characterized in that, The preparation method includes: forming gate polysilicon in the epitaxial layer; The step of forming the gate polysilicon in the epitaxial layer is performed simultaneously with the step of forming the polysilicon structure.

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