A circuit and method for improving the resolution of PWM signals

Abstract

This invention provides a circuit and method for improving the resolution of a PWM signal, comprising at least a PWM signal generation module, a calibration module, and a resolution adjustment module. The PWM signal generation module generates a PWM signal based on a counting clock. The resolution adjustment module, connected to the PWM signal generation module, extends the period of the PWM signal based on a period adjustment value to generate a period-extended PWM signal, thereby improving the resolution of the PWM signal. The duty cycle of the PWM signal is controlled based on an edge delay value. The calibration module, connected to the resolution adjustment module, calibrates the edge delay of the PWM signal based on the clock signal. Without changing the counting clock, the resolution of the PWM signal is extended through algorithmic control. The operation is convenient, and the duty cycle and phase of the PWM signal are adjusted through edge adjustment. The structure is simple and easy to modularly implement.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a circuit and method for improving the resolution of PWM signals. Background Technology

[0002] In digital control switching power supplies, the generation of pulse width modulation (PWM) signals is a crucial step. With the development of high-speed power devices, the requirements for the period, duty cycle, and phase resolution of PWM signals have also increased. The resolution of PWM is directly related to the stability and accuracy of the output voltage. Therefore, improving the resolution of PWM is essential for enhancing the performance of digital control switching power supplies. For traditional counting-type PWM generators, the resolution of duty cycle, period, and phase adjustment is one counting clock cycle. To improve the resolution of this type of PWM generator, the frequency of its counting clock must be increased. For example, when the carrier frequency is 1MHz, to achieve 13-bit PWM accuracy, i.e., a resolution of 122ps, the counting clock of the digital PWM needs to reach a frequency of over 8GHz. This is difficult to achieve due to current integrated circuit technology limitations. Generally speaking, the resolution of the pulse width modulation (PWM) signal is determined by the counting clock of the PWM module. This clock is limited by the manufacturing process and cannot be arbitrarily increased, thus failing to meet the high-resolution requirements of PWM. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a circuit and method for improving the resolution of PWM signals, so as to solve the problem that in order to improve the resolution, the frequency of the counting clock must be increased.

[0004] To achieve the above and other related objectives, the present invention provides a circuit for improving the resolution of a PWM signal. This circuit includes at least: a PWM signal generation module, a calibration module, and a resolution adjustment module, wherein:

[0005] The PWM signal generation module generates a PWM signal based on a counting clock and performs statistics on the counting clock to determine the duty cycle of the PWM signal. When the statistical value exceeds the upper limit of the number of counting clocks, it is reset to zero and the statistics are repeated.

[0006] The resolution adjustment module is connected to the PWM signal generation module. It extends the period of the PWM signal based on the period adjustment value to generate a period-extended PWM signal, thereby improving the resolution of the PWM signal. It controls the duty cycle of the PWM signal based on the edge delay value, wherein the edge delay value includes rising edge delay value and falling edge delay value.

[0007] The calibration module is connected to the resolution adjustment module and calibrates the edge delay of the PWM signal based on the counting clock.

[0008] Optionally, when the period-extended PWM signal has the same duty cycle as the PWM signal, the period adjustment value is set to an even number less than or equal to the upper limit value, and both the rising edge delay value and the falling edge delay value are set to half the value of the period adjustment value.

[0009] Optionally, when the duty cycle of the period-extended PWM signal is not equal to that of the PWM signal, the period adjustment value is an odd number less than or equal to the upper limit value, and the rising edge delay value or the falling edge delay value is set to a value equal to the period adjustment value.

[0010] Optionally, the resolution adjustment module includes: an algorithm control unit, a rising edge delay structure, a falling edge delay structure, and an output unit, wherein:

[0011] The algorithm control unit outputs rising edge control signals and falling edge control signals based on the rising edge delay value, the falling edge delay value, and the period adjustment value, and determines the value of period extension based on the period adjustment value.

[0012] The rising edge delay structure is connected to the output terminal of the algorithm control unit, and performs a corresponding delay operation on the rising edge of the PWM signal based on the rising edge control signal.

[0013] The falling edge delay structure is connected to the output of the algorithm control unit, and performs a corresponding delay operation on the falling edge of the PWM signal based on the falling edge control signal;

[0014] The output unit is connected to the output terminals of the rising edge delay structure and the falling edge delay structure, and generates the period-extended PWM signal corresponding to the period adjustment value based on the delay operation results of the rising and falling edges of the PWM signal.

[0015] Optionally, the rising edge delay structure includes: a rising edge selection unit and N rising edge delay units, wherein the rising edge selection unit receives the rising edge control signal and generates a rising edge delay unit selection signal based on the rising edge control signal; the rising edge delay units are connected to the output terminal of the rising edge selection unit, and a corresponding number of the rising edge delay units are selected for delay operation based on the rising edge delay unit selection signal, where N is a natural number less than the upper limit value.

[0016] Optionally, the delay amount of each rising edge delay unit is equal to Where N is a natural number less than the upper limit value, T clkFor counting clock cycles.

[0017] Optionally, the falling edge delay structure includes: a falling edge selection unit and N falling edge delay units, wherein the falling edge selection unit receives the falling edge control signal and generates a falling edge delay unit selection signal based on the falling edge control signal; the falling edge delay units are connected to the output terminal of the falling edge selection unit, and a corresponding number of the falling edge delay units are selected for delay operation based on the falling edge delay unit selection signal, wherein N is a natural number less than the upper limit value.

[0018] Optionally, the delay amount of each falling edge delay unit is equal to Where N is a natural number less than the upper limit value, T clk For counting clock cycles.

[0019] This invention proposes a method for improving the resolution of PWM signals, implemented based on the aforementioned circuit for improving PWM signal resolution. The method for improving PWM signal resolution includes at least the following:

[0020] 11: Set the period adjustment value to X, where X is an even number less than or equal to the upper limit value, so that the period-extended PWM signal keeps the duty cycle of the PWM signal consistent;

[0021] 12: Set both the rising edge delay value and the falling edge delay value to...

[0022] 13: No period extension is performed during the first period of the PWM signal;

[0023] 14: Extend X*T in the second cycle of the PWM signal clk , among which, T clk For counting clock cycles;

[0024] 15: Extend the PWM signal by X*T in the next cycle. clk The next cycle is an extension of X*T based on the previous cycle. clk , among which, T clk For counting clock cycles;

[0025] 16: Repeat step 15. When the accumulated period extension value exceeds the upper limit value, the resolution adjustment module sends a control signal to the PWM signal generation module, setting the difference between the accumulated period extension value and the upper limit value to the next cycle, thereby ensuring that the period-extended PWM signal is X*T longer than the PWM signal period extension. clk , among which, T clk For counting clock cycles.

[0026] This invention proposes a method for improving the resolution of PWM signals, implemented based on the aforementioned circuit for improving PWM signal resolution. The method for improving PWM signal resolution includes at least the following:

[0027] 21: Set the period adjustment value to X, where X is an odd number less than or equal to the upper limit value, so that the period-extended PWM signal has a different duty cycle than the PWM signal;

[0028] 22: Set both the rising edge delay value and the falling edge delay value to X;

[0029] 23: No period extension is performed during the first period of the PWM signal;

[0030] 24: Extend X*T in the second cycle of the PWM signal clk , among which, T clk For counting clock cycles;

[0031] 25: Extend the PWM signal by X*T in the next cycle. clk The next cycle is an extension of X*T based on the previous cycle. clk , among which, T clk For counting clock cycles;

[0032] 26: Repeat step 25. When the accumulated period extension value exceeds the upper limit value, the resolution adjustment module sends a control signal to the PWM signal generation module, setting the difference between the accumulated period extension value and the upper limit value to the next cycle, thereby ensuring that the period-extended PWM signal is X*T longer than the PWM signal period extension. clk , among which, T clk For counting clock cycles.

[0033] As described above, the circuit and method for improving PWM signal resolution of the present invention have the following beneficial effects:

[0034] 1) Without changing the counting clock, the resolution of the PWM signal is expanded through algorithm control, which is convenient to operate.

[0035] 2) Without changing the counting clock, the duty cycle and phase of the PWM signal can be adjusted by edge adjustment. The structure is simple and easy to implement in a modular way. Attached Figure Description

[0036] Figure 1 The diagram shown is a schematic diagram of the circuit for improving PWM signal resolution provided in an embodiment of this application.

[0037] Figure 2The diagram shown is a structural schematic of the resolution adjustment module provided in an embodiment of this application.

[0038] Figure 3 The diagram shown is a schematic diagram of the rising edge delay structure provided in an embodiment of this application.

[0039] Figure 4 The diagram shown is a schematic diagram of the falling edge delay structure provided in an embodiment of this application.

[0040] Figure 5 The diagram shown is a timing schematic of a method for improving PWM signal resolution provided in an embodiment of this application.

[0041] Component designation explanation

[0042] 100 PWM signal generation module

[0043] 200 resolution adjustment module

[0044] 201 Algorithm Control Unit

[0045] 202 Rising Edge Delay Structure

[0046] 203 Falling Edge Delay Structure

[0047] 204 output units

[0048] 221 Rising Edge Selection Unit

[0049] 222 Rising Edge Delayed Unit

[0050] 231 Falling Edge Selection Unit

[0051] 232 Falling Edge Delayed Unit

[0052] 300 Calibration Module

[0053] Steps S11 to S16

[0054] Steps S21 to S26 Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please see Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Example 1

[0058] like Figure 1 As shown, this embodiment provides a circuit for improving the resolution of a PWM signal. The circuit for improving the resolution of a PWM signal includes at least: a PWM signal generation module 100, a calibration module 300, and a resolution adjustment module 200, wherein:

[0059] like Figure 1 As shown, the PWM signal generation module 100 generates a PWM signal based on a counting clock. The counting clock is statistically analyzed to determine the duty cycle of the PWM signal. When the statistical value exceeds the upper limit, it is reset to zero and the count is repeated.

[0060] Specifically, as an example, such as Figure 1 As shown, the PWM signal generation module 100 can be implemented using a counter and a comparator. The counter performs counting operations based on a counting clock. It should be noted that any scheme that can generate the PWM signal is applicable and is not limited to this embodiment.

[0061] like Figure 1 As shown, the resolution adjustment module 200 is connected to the PWM signal generation module 100. It extends the period of the PWM signal based on the period adjustment value to generate a period-extended PWM signal, thereby improving the resolution of the PWM signal. It controls the duty cycle of the PWM signal based on the edge delay value, wherein the edge delay value includes rising edge delay value and falling edge delay value.

[0062] Specifically, as an example, such as Figure 2 As shown, the resolution adjustment module 200 includes: an algorithm control unit 201, a rising edge delay structure 202, a falling edge delay structure 203, and an output unit 204, wherein:

[0063] More specifically, such as Figure 2 As shown, the algorithm control unit 201 outputs rising edge control signals and falling edge control signals based on the rising edge delay value, the falling edge delay value, and the period adjustment value, and determines the period extension value based on the period adjustment value. As an example, such as... Figure 2As shown, the algorithm control unit 201 can adopt an IP core (Intellectual Property core, a pre-designed circuit functional module used in application-specific integrated circuits or field-programmable gate arrays), and any scheme capable of algorithm control is applicable, not limited to this embodiment.

[0064] More specifically, such as Figure 2 As shown, the rising edge delay structure 202 is connected to the output terminal of the algorithm control unit 201, and performs a corresponding delay operation on the rising edge of the PWM signal based on the rising edge control signal. As an example, such as... Figure 3 As shown, the rising edge delay structure 202 includes: a rising edge selection unit 221 and N rising edge delay units 222. The rising edge selection unit 221 receives the rising edge control signal and generates a rising edge delay unit selection signal based on the rising edge control signal. The rising edge delay units 222 are connected to the output of the rising edge selection unit 221, and a corresponding number of rising edge delay units 222 are selected for delay operation based on the rising edge delay unit selection signal. Here, N is a natural number less than the upper limit of the number of counting clocks. It should be noted that, as an example, ... Figure 3 As shown, the upper limit of the number of counting clocks is 64, so the number of rising edge delay units 222 is 63, that is, N equals 63.

[0065] Furthermore, as an example, such as Figure 3 As shown, the delay amount of the delay unit 222 for each rising edge is equal to Where N is a natural number less than the upper limit of the number of counting clocks, and T clk This is for counting clock cycles. It should be noted that, as an example, such as... Figure 3 As shown, when N equals 63, the delay amount of the delay unit 222 on the rising edge is equal to... T clk For counting clock cycles.

[0066] More specifically, such as Figure 2 As shown, the falling edge delay structure 203 is connected to the output terminal of the algorithm control unit 201, and performs a corresponding delay operation on the falling edge of the PWM signal based on the falling edge control signal. As an example, such as... Figure 4As shown, the falling edge delay structure 203 includes: a falling edge selection unit 231 and N falling edge delay units 232, wherein the falling edge selection unit 231 receives the falling edge control signal and generates a falling edge delay unit selection signal based on the falling edge control signal; the falling edge delay units 232 are connected to the output terminal of the falling edge selection unit 231, and a corresponding number of the falling edge delay units 232 are selected for delay operation based on the falling edge delay unit selection signal, wherein N is a natural number less than the counting clock cycle.

[0067] Furthermore, as an example, such as Figure 4 As shown, the delay amount of each falling edge delay unit 232 is equal to Where N is a natural number less than the upper limit of the number of counting clocks, and T clk This is for counting clock cycles. It should be noted that, as an example, such as... Figure 3 As shown, when N equals 63, the delay of the falling edge delay unit 232 is equal to T clk For counting clock cycles.

[0068] More specifically, such as Figure 2 As shown, the output unit 204 is connected to the output terminals of the rising edge delay structure 202 and the falling edge delay structure 203, and generates the period-extended PWM signal corresponding to the period adjustment value based on the delay operation results of the rising and falling edges of the PWM signal.

[0069] Specifically, as an example, such as Figure 2 As shown, when the duty cycle of the period-extended PWM signal is equal to that of the PWM signal, the period adjustment value is set to an even number less than or equal to the upper limit of the number of counting clocks, and both the rising edge delay value and the falling edge delay value are set to half the value of the period adjustment value. It should be noted that any method that ensures the duty cycle of the period-extended PWM signal remains consistent with that of the PWM signal is applicable and should be set according to the actual application scenario, and is not limited to this embodiment.

[0070] Specifically, as an example, such as Figure 2 As shown, when the duty cycle of the period-extended PWM signal is not equal to that of the PWM signal, the period adjustment value is an odd number less than or equal to the upper limit of the number of counting clocks, and the rising edge delay value or the falling edge delay value is set to a value equal to the period adjustment value. It should be noted that any method that allows the duty cycle of the period-extended PWM signal to be different from that of the PWM signal is applicable and should be set according to the actual application scenario, and is not limited to this embodiment.

[0071] Specifically, as an example, such as Figure 1 As shown, the circuit for improving PWM signal resolution can be an IP core (Intellectual Property core, a pre-designed circuit function module used in application-specific integrated circuits or field-programmable gate arrays). Any scheme capable of improving PWM signal resolution is applicable and is not limited to this embodiment.

[0072] It needs to be explained, such as Figure 1 As shown, the PWM signal generation module 100 uses a first counter and a second counter to generate the PWM signal. Wherein:

[0073] The first counter counts synchronously with the counting clock (incrementing by 1 on the rising or falling edge of the counting clock). The counting range of the first counter is from 0 to the upper limit value. When the count value exceeds the upper limit value, the first counter is cleared and the count is restarted.

[0074] The second counter counts synchronously with the upper limit value of the first counter (when the first counter equals the upper limit value, the second counter increments by 1). The counting range of the second counter is from 0 to the upper limit value. When the count value exceeds the upper limit value, the second counter is cleared and the count is restarted.

[0075] The value of the first counter is compared with the value of the second counter to determine the duty cycle of the PWM signal.

[0076] It should be noted that the upper limit value is the value of the counting clock counting one cycle of the PWM signal output by the PWM signal generation module.

[0077] Example 2

[0078] like Figures 2 to 5 As shown, this embodiment provides a method for improving the resolution of a PWM signal, implemented based on the PWM signal resolution improvement circuit provided in Embodiment 1. The periodically extended PWM signal maintains the same duty cycle as the PWM signal. The method for improving the resolution of a PWM signal includes at least the following:

[0079] Specifically, as an example, the period adjustment value is set to 6, and the maximum number of counting clocks is 64.

[0080] S11: As Figure 2 As shown, for example, the cycle adjustment value is set to "6".

[0081] S12: As Figure 2 As shown, for example, both the rising edge delay value and the falling edge delay value are set to 3, that is, both the rising edge delay value and the falling edge delay value are equal to half of the period adjustment value. Specifically, as... Figure 3 As shown, the number of rising edge delay units 222 selected in the rising edge delay structure 202 is 3. Specifically, as... Figure 4 As shown, the number of falling edge delay units 232 selected in the falling edge delay structure 203 is 3.

[0082] S13: As Figure 5 As shown, as an example, no period extension is performed during the first cycle of the PWM signal.

[0083] S14: As Figure 5 As shown, as an example, the second cycle of the PWM signal is extended... T clk For counting clock cycles.

[0084] S15: As Figure 5 As shown, as an example, the PWM signal is extended in the next cycle. The next cycle is an extension of the previous cycle. T clk For counting clock cycles.

[0085] S16: Repeat step 15, as follows Figure 5 As shown in the example, when the accumulated period extension value exceeds the upper limit of the number of counting clocks, the resolution adjustment module sends a control signal to the PWM signal generation module to set the difference between the accumulated period extension value and the upper limit of the number of counting clocks to the next cycle, thereby ensuring that the period-extended PWM signal is longer than the PWM signal period extension. T clk For counting clock cycles.

[0086] Example 3

[0087] like Figures 2 to 5 As shown, this embodiment provides a method for improving the resolution of a PWM signal, implemented based on the PWM signal resolution improvement circuit provided in Embodiment 1. The periodically extended PWM signal does not have the same duty cycle as the PWM signal. The method for improving the resolution of a PWM signal includes at least the following:

[0088] Specifically, as an example, the period adjustment value is set to 3, and the maximum number of counting clocks is 64.

[0089] S21: As Figure 2 As shown, for example, the cycle adjustment value is set to 3.

[0090] S22: As Figure 2As shown, for example, both the rising edge delay value and the falling edge delay value are set to 3, that is, both the rising edge delay value and the falling edge delay value are equal to half of the period adjustment value. When setting the rising edge delay value, specifically, as shown... Figure 3 As shown, the number of rising edge delay units 222 selected in the rising edge delay structure 202 is 3. When setting the falling edge delay value, specifically, as... Figure 4 As shown, the number of falling edge delay units 232 selected in the falling edge delay structure 203 is 3;

[0091] S23: As Figure 5 As shown, as an example, no period extension is performed during the first cycle of the PWM signal.

[0092] S24: As Figure 5 As shown, as an example, the second cycle of the PWM signal is extended... T clk For counting clock cycles.

[0093] S25: As Figure 5 As shown, as an example, the PWM signal is extended in the next cycle. The next cycle is an extension of the previous cycle. T clk For counting clock cycles.

[0094] S26: Repeat step 25 in a loop, as follows Figure 5 As shown in the example, when the accumulated period extension value exceeds the upper limit of the number of counting clocks, the resolution adjustment module sends a control signal to the PWM signal generation module to set the difference between the accumulated period extension value and the upper limit of the number of counting clocks to the next cycle, thereby ensuring that the period-extended PWM signal is longer than the PWM signal period extension. T clkThe clock cycle is used for counting. In summary, the circuit and method for improving PWM signal resolution according to the present invention includes at least: a PWM signal generation module, a calibration module, and a resolution adjustment module, wherein: the PWM signal generation module generates a PWM signal based on a counting clock, wherein the counting clock is statistically analyzed to determine the duty cycle of the PWM signal, and when the statistical value exceeds an upper limit, it is reset to zero and the statistics are repeated; the resolution adjustment module is connected to the PWM signal generation module, and extends the period of the PWM signal based on a period adjustment value to generate a period-extended PWM signal, thereby improving the resolution of the PWM signal; the duty cycle of the PWM signal is controlled based on an edge delay value, wherein the edge delay value includes a rising edge delay value and a falling edge delay value; the calibration module is connected to the resolution adjustment module, and calibrates the edge delay of the PWM signal based on the counting clock. The circuit and method for improving PWM signal resolution according to the present invention achieves the extension of PWM signal resolution through algorithmic control without changing the counting clock, and is easy to operate. Without changing the counting clock, the duty cycle and phase of the PWM signal are adjusted through edge adjustment, resulting in a simple structure that is easy to modularly implement. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A circuit for increasing the resolution of a PWM signal, the circuit comprising: The resolution improvement circuit of the PWM signal comprises at least a PWM signal generation module, a calibration module and a resolution adjustment module, wherein: The PWM signal generation module generates the PWM signal based on a counting clock and counts the counting clock to determine the duty cycle of the PWM signal, and clears the counting value and then re-counts when the counting value exceeds an upper limit value of the counting clock; The resolution adjustment module is connected with the PWM signal generation module, expands the period of the PWM signal based on a period adjustment value to generate a period-expanded PWM signal, thereby improving the resolution of the PWM signal, and controls the duty cycle of the PWM signal based on an edge delay value, wherein the edge delay value comprises a rising edge delay value and a falling edge delay value; The calibration module is connected with the resolution adjustment module and calibrates the edge delay of the PWM signal based on the counting clock; When the duty cycle of the period-expanded PWM signal is equal to that of the PWM signal, the period adjustment value is set to an even number less than or equal to the upper limit value, and the rising edge delay value and the falling edge delay value are both set to half of the value of the period adjustment value; The resolution adjustment module comprises an algorithm control unit, a rising edge delay structure, a falling edge delay structure and an output unit, wherein: the algorithm control unit outputs a rising edge control signal and a falling edge control signal based on the rising edge delay value, the falling edge delay value and the period adjustment value, and determines the value of the period expansion based on the period adjustment value; the rising edge delay structure is connected to the output end of the algorithm control unit and performs corresponding delay operation on the rising edge of the PWM signal based on the rising edge control signal; the falling edge delay structure is connected to the output end of the algorithm control unit and performs corresponding delay operation on the falling edge of the PWM signal based on the falling edge control signal; and the output unit is connected to the output ends of the rising edge delay structure and the falling edge delay structure and generates the period-expanded PWM signal corresponding to the period adjustment value based on the delay operation results of the rising edge and the falling edge of the PWM signal; The rising edge delay structure comprises a rising edge selection unit and N rising edge delay units, wherein the rising edge selection unit receives the rising edge control signal and generates a rising edge delay unit selection signal based on the rising edge control signal; and the rising edge delay units are connected to the output end of the rising edge selection unit and select a corresponding number of the rising edge delay units for delay operation based on the rising edge delay unit selection signal, wherein N is a natural number less than the upper limit value. The falling edge delay structure comprises a falling edge selection unit and N falling edge delay units, wherein the falling edge selection unit receives the falling edge control signal, and generates a falling edge delay unit selection signal based on the falling edge control signal; the falling edge delay units are connected to the output end of the falling edge selection unit, and a corresponding number of the falling edge delay units are selected for delay operation based on the falling edge delay unit selection signal, wherein N is a natural number less than the upper limit value.

2. The boosted PWM signal resolution circuit of claim 1, wherein: When the period-expanded PWM signal is inconsistent with the duty cycle of the PWM signal, the period adjustment value is an odd number less than or equal to the upper limit value, and the rising edge delay value or the falling edge delay value is set to a value equal to the period adjustment value.

3. The boosted PWM signal resolution circuit of claim 1, wherein: The delay amount of each of the rising edge delay units is equal to wherein N is a natural number less than the upper limit value, T clk is the count clock period.

4. The boosted PWM signal resolution circuit of claim 1, wherein: The delay amount of each of the falling edge delay units is equal to wherein N is a natural number less than the upper limit value, T clk is a count clock period.

5. A method for increasing the resolution of a PWM signal, implemented based on the circuit for increasing the resolution of a PWM signal according to any one of claims 1-4, characterized in that, The method for improving the resolution of the PWM signal at least comprises: 11: setting the period adjustment value to X, wherein X is an even number less than or equal to the upper limit value, so that the period-expanded PWM signal is consistent with the duty cycle of the PWM signal; 12: set both the rising edge delay value and the falling edge delay value to 13: not performing period expansion in the first period of the PWM signal; 14: extend X*T in the second cycle of the PWM signal clk where T clk is the count clock period; 15: extend X*T in the next cycle of the PWM signal clk wherein the next cycle is extended X*T on the basis of the previous cycle clk wherein T clk is the count clock cycle; 16: repeating step 15, when the accumulated period extension value exceeds the upper limit value, the resolution adjustment module sends a control signal to the PWM signal generation module, sets the difference between the accumulated period extension value and the upper limit value to the next period, thereby ensuring that the period extended PWM signal is X*T longer than the PWM signal clk wherein T clk is the count clock period.

6. A method for increasing the resolution of a PWM signal, implemented based on the circuit for increasing the resolution of a PWM signal according to any one of claims 1-4, characterized in that, The method for improving the resolution of the PWM signal at least comprises: 21: setting the period adjustment value to X, wherein X is an odd number less than or equal to the upper limit value, so that the period-expanded PWM signal is inconsistent with the duty cycle of the PWM signal; 22: setting the rising edge delay value or the falling edge delay value to X; 23: not performing period expansion in the first period of the PWM signal; 24: extend X*T in the second cycle of the PWM signal clk where T clk is the count clock period; 25: extend X*T in the next cycle of the PWM signal clk wherein the next cycle is extended X*T on the basis of the previous cycle clk wherein T clk is the count clock cycle; 26: repeating step 25, when the accumulated period extension value exceeds the upper limit value, the resolution adjustment module sends a control signal to the PWM signal generation module, sets the difference between the accumulated period extension value and the upper limit value to the next period, thereby ensuring that the period extended PWM signal is X*T longer than the PWM signal clk wherein T clk is the count clock period.

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