High-speed encryption and decryption engine and encryption and decryption implementation method

Abstract

The application relates to a high-speed encryption and decryption engine and an encryption and decryption implementation method, wherein a plurality of physical channels are provided to provide a plurality of service processing modules with cryptographic services, the problem that a cryptographic card can only provide a single service channel is solved, secondary keys are imported into an FPGA chip for buffering, a session key is managed in a life cycle by the FPGA chip, the time cost of key updating required by cryptographic operation can be reduced, and the processing delay of the cryptographic service can be obviously reduced; the FPGA chip is used as a cryptographic operation processing core unit, multi-stage parallel pipeline processing is realized, and the processing performance is effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of cryptography, in particular to a high-speed encryption and decryption engine based on a new hardware architecture and an encryption and decryption implementation method. BACKGROUND

[0002] Cryptographic products are widely used in modern communication systems, common products including server cryptographic machines, cryptographic cards, CA systems, etc. As cryptographic products, they mainly include two functions, namely cryptographic operation and key management. In order to improve product reliability and facilitate maintenance, cryptographic operation and key management are generally implemented by independent modules, and the cryptographic card is such a product. In the existing product design, the functions of cryptographic operation and key management are generally implemented by integrating a cryptographic card, which usually has a PCI-E high-speed interface and can only provide cryptographic services for one business processing module. There are mainly two architectures for the implementation of cryptographic cards, one is the "DSP+FPGA" implementation architecture, and the other is the "DSP+cryptographic algorithm chip" architecture.

[0003] In the first architecture, DSP mainly implements key management function, and FPGA mainly implements cryptographic operation function, and the corresponding hardware architecture is as shown in Figure 1 The cryptographic card generally adopts a three-layer key structure, including master key, key encryption key and session key, all of which are managed by DSP. The cryptographic card receives service call instructions from the business processing module, extracts the corresponding key from DSP and passes it to FPGA, which calls the algorithm chip to implement cryptographic operation and returns the result to the business processing module.

[0004] In the second architecture, DSP mainly implements key management function, and the cryptographic algorithm chip implements cryptographic operation, and the corresponding hardware architecture is as shown in Figure 2

[0005] At present, cryptographic devices generally implement cryptographic operation, key management and other functions by integrating general PCI-E cryptographic cards. Through research, it is found that the existing technology at least has the following technical defects:

[0006] (1) The general cryptographic card can only provide one PCI-E interface and cannot provide cryptographic services for multiple business processing modules at the same time;

[0007] (2) The secondary and tertiary keys are stored in the security chip, and the time overhead of frequently switching keys for cryptographic operation is large, and the business processing delay is large;

[0008] (3) The cryptographic card does not implement parallel and multi-stage pipeline processing for cryptographic services, and the processing performance is low. SUMMARY

[0009] ​In view of the deficiencies in the prior art, the application provides multiple physical channels to provide password services for multiple service processing modules, solves the problem that a password card can only provide a single service channel, the secondary key is imported into the FPGA for caching, and the session key is managed in the life cycle by the FPGA, which can reduce the time cost of key update required by password operation and significantly reduce the password service processing delay, and the FPGA is used as the password operation processing core unit to realize multi-level parallel pipeline processing and effectively improve the processing performance.

[0010] The first aspect of the application relates to a high-speed encryption and decryption engine, which comprises an FPGA chip, a security chip and multiple password operation modules, wherein:

[0011] The FPGA chip is configured to allow receiving calling instructions from multiple service processing modules through multiple service interfaces and parsing the calling instructions to obtain instruction information;

[0012] The FPGA chip is further configured to allow performing password operation processing based on the instruction information in a classified manner in parallel according to the password service type in the instruction information, and sending password operation processing results to the password operation module corresponding to the password algorithm type according to the password algorithm type in the instruction information;

[0013] The password operation module is configured to perform password operation on service data in the instruction information under the password algorithm type and output the password operation result; and,

[0014] The high-speed encryption and decryption engine is provided with a key, and the key comprises a master key, a key encryption key and a session key;

[0015] The security chip is configured to implement the life cycle management of the master key and the key encryption key;

[0016] The FPGA chip is further configured to implement the life cycle management of the session key;

[0017] Before performing the password operation, the key encryption key is synchronized and cached into the FPGA chip.

[0018] Further, the calling instructions are encapsulated in the form of application interface functions; and / or, the password service type comprises symmetric encryption and decryption services, hash operation services, MAC operation services, asymmetric algorithm operation services, random number generation services, signature services and signature verification services; and / or, the instruction information comprises the password service type, the password algorithm type, the service data and service interface number information; and / or, the password algorithm type comprises SM2 algorithm, SM3 algorithm and SM4 algorithm.

[0019] Further, the FPGA chip is provided with an interface polling scheduling module and a calling instruction parsing / encapsulating module;

[0020] The interface polling scheduling module is configured to query the state of the service interface in a polling manner and read the calling instruction;

[0021] The calling instruction parsing / encapsulating module is configured to parse the calling instruction to obtain the instruction information.

[0022] Further, the FPGA chip is further provided with a password service classification scheduling module and a plurality of password operation processing modules;

[0023] The password service classification scheduling module is configured to classify according to the password service type and send the instruction information to the password operation processing module according to the classification result;

[0024] The password operation processing module is configured to obtain a password operation intermediate value, a key and the service data according to the instruction information, and generate a protocol frame based thereon.

[0025] Further, the FPGA chip is further provided with an arbitration module configured to poll the password operation processing module and send the protocol frame to the password operation module corresponding to the password algorithm type in sequence.

[0026] Further, the arbitration module is further configured to return the password operation result to the password operation processing module corresponding to the protocol frame;

[0027] The password operation processing module is further configured to regenerate a data frame based on the password operation result and send the data frame to the password service classification scheduling module;

[0028] The password service classification scheduling module is further configured to combine data in one or more data frames corresponding to the calling instruction into one and send it to the calling instruction parsing / encapsulating module;

[0029] The calling instruction parsing / encapsulating module is further configured to encapsulate the data returned by the password service classification scheduling module and return it to the interface polling scheduling module;

[0030] The interface polling scheduling module is further configured to return the encapsulated data to the service processing module corresponding to the calling instruction through the service interface.

[0031] Further, the high-speed encryption and decryption engine of the present application further comprises a non-volatile memory configured for caching at least one of the key, the cipher operation intermediate value, the service data and the random number; and / or, further comprises a random number generation module for generating a true random number for the generation of the key.

[0032] The second aspect of the present application relates to a high-speed encryption and decryption implementation method, comprising the following steps:

[0033] receiving a plurality of calling instructions in parallel through a plurality of service interfaces;

[0034] reading the calling instructions in a polling manner and parsing the calling instructions to obtain instruction information;

[0035] classifying according to the cipher service type and performing cipher operation processing based on the instruction information in a parallel manner to generate protocol frames;

[0036] classifying according to the cipher algorithm type and performing cipher operation based on the protocol frames in a parallel manner to generate cipher operation results.

[0037] Further, the high-speed encryption and decryption implementation method of the present application can further comprise the following steps:

[0038] classifying according to the cipher service type and generating data frames based on the cipher operation results in a parallel manner;

[0039] encapsulating the data frames according to the calling instructions;

[0040] and returning the encapsulated data via the service interface.

[0041] Preferably, the high-speed encryption and decryption implementation method of the present application is executed in the high-speed encryption and decryption engine described above. BRIEF DESCRIPTION OF DRAWINGS

[0042] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings required to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0044] Figure 1 An architecture of a cipher card in the prior art is shown;

[0045] Figure 2 Another architecture of the password card in the prior art is shown;

[0046] Figure 3 A hardware framework of the high-speed encryption and decryption engine according to the present application is shown;

[0047] Figure 4 A key cache mode of the three-level key system in the high-speed encryption and decryption engine and its implementation method according to the present application is shown;

[0048] Figure 5 A password service processing flow in the high-speed encryption and decryption engine and its implementation method according to the present application is shown;

[0049] Figure 6 A multi-stage pipeline scheduling process in the high-speed encryption and decryption engine and its implementation method according to the present application is shown. DETAILED DESCRIPTION

[0050] In the following, exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example in order to fully convey the spirit of the present application to those skilled in the art to which the present application pertains. Therefore, the present application is not limited to the embodiments disclosed herein.

[0051] Figure 3 A hardware framework of the high-speed encryption and decryption engine according to the present application is shown.

[0052] As shown, the high-speed encryption and decryption engine of the present application can simultaneously and at high speed process password services required by multiple service processing modules, which can include but are not limited to symmetric encryption and decryption services, hash operation services, MAC operation services, non-symmetric algorithm operation services, random number generation services, signature services, and signature verification services, etc.

[0053] The service processing modules can send call instructions to the FPGA chip via the service interfaces to convey their required password services to the FPGA chip. As shown, the encryption and decryption engine of the present application allows multiple service processing modules to exchange data with the FPGA chip in parallel through multiple service interfaces, thereby having the ability to simultaneously process multiple password services.

[0054] The call instructions can be encapsulated in the form of application interface functions. Among them, the application interface functions can be defined according to the specific types of the service interfaces.

[0055] In the present application, the calling instruction can include instruction information such as a cryptographic service type, service data, control information, a cryptographic algorithm type, and flow control information. Among them, the service data can include data for calling the encryption and decryption engine by the service processing module to implement the corresponding cryptographic algorithm operation. The cryptographic service type can include, for example, key management type, asymmetric cryptographic operation type, symmetric cryptographic operation type, and hash operation type. The cryptographic algorithm can include, for example, SM2 / 3 / 4 algorithm.

[0056] In addition, in order to facilitate the distinction of different service processing modules, the calling instruction here can also include service interface number information.

[0057] In a preferred embodiment, the service interface can adopt a high-speed serial interface, such as a SerDes (serializer / deserializer) interface.

[0058] When the FPGA chip receives the calling instruction from the service processing module via the service interface, the FPGA chip parses the calling instruction to obtain the corresponding instruction information, calls the corresponding key and cryptographic algorithm according to the instruction information to implement the corresponding cryptographic operation, and returns the operation result to the corresponding service processing module.

[0059] In the present application, in order to be able to handle multiple cryptographic services at the same time, multiple cryptographic operation modules can be provided in the high-speed encryption and decryption engine, which can be implemented by means of algorithm chips, such as SM4 algorithm chips, SM2 / 3 algorithm chips, and the like, as shown in Figure 3 .

[0060] Therefore, when the FPGA chip obtains the corresponding instruction information by parsing the calling instruction, the corresponding key and service data can be sent to the corresponding cryptographic operation module according to the cryptographic algorithm type in the instruction information, so as to implement the cryptographic operation on the service data based on the corresponding cryptographic algorithm and the key in the cryptographic operation module. For example, when the service processing module 1 sends a calling instruction to the FPGA chip through the service interface 1 to expect to perform encryption and decryption operation on the service data about the SM4 algorithm, the FPGA chip can send the corresponding key and service data to the SM4 algorithm chip based on the parsing result of the calling instruction, so as to perform encryption and decryption operation on the service data about the SM4 algorithm in the SM4 algorithm chip.

[0061] The present application will adopt a three-level key system, that is, the high-speed encryption and decryption engine of the present application will be provided with a master key, a key encryption key, and a session key, and the like.

[0062] In order to generate the key, the high-speed encryption and decryption engine of the present application can also be provided with a random number generation module, which generates a true random number for the generation of the key. As an example, the random number generation module can include a true random number chip.

[0063] In order to safely establish the three-level key system, a security chip is arranged in the high-speed encryption and decryption engine of the present application, which is used to implement the life cycle management of the master key and the key encryption key; meanwhile, the life cycle management of the session key is implemented by the FPGA chip. The life cycle of the key refers to the whole process from the generation to the final destruction of the key, for example, the life cycle management of the key can include the key generation, key installation, key storage, key use, key destruction and the like. In addition, the security chip can also be used to implement the user identity authentication and the like.

[0064] In order to improve the password operation processing performance and enable the high-speed simultaneous processing of multiple password services, in the encryption and decryption engine of the present application, before the password operation is performed, for example, when a legal user logs in, the key encryption key in the security chip can be synchronously stored into the cache inside the FPGA chip, for example, as shown in Figure 4 . Thus, when the password operation needs to be performed, both the secondary and the tertiary keys are cached in the FPGA chip, thereby the time overhead caused by the replacement of the key in the password operation process can be reduced, the delay of the password service can be effectively reduced, and the operation speed of the engine can be greatly improved, which is extremely beneficial to the implementation of the multi-task synchronous parallel processing.

[0065] The working flow of the FPGA chip in the high-speed encryption and decryption engine of the present application will be described below in combination with Figure 5 and Figure 6 .

[0066] As shown in Figure 5 , in the face of the calling instructions issued by multiple service processing modules, the states of the service interfaces are queried in the FPGA chip in a polling manner, the next calling instruction to be processed is read, and the calling instruction (application interface function) is parsed to obtain the corresponding instruction information.

[0067] In an embodiment, as shown in Figure 6 , an interface polling scheduling module and a calling instruction parsing / packaging module can be arranged in the FPGA chip. The interface polling scheduling module queries the states of the service interfaces in a polling manner and reads the calling instructions. The calling instruction parsing / packaging module parses the calling instruction (application interface function) to obtain the corresponding instruction information, for example, the password service type, the service data, the control information, the password algorithm type, the flow control information, the service interface number information and the like.

[0068] Continuing to refer to Figure 6The password service classification and scheduling module can also be arranged in the FPGA chip, and is configured to classify the password services according to the instruction information of the password service types, and forward the corresponding instruction information to the corresponding password operation processing modules according to the password service classification results. For example, one calling instruction can involve multiple password service types, and the password service classification and scheduling module can classify the password services in the calling instruction, and send the corresponding instruction information to different password operation processing modules (or password operation units) according to the password service types, so as to complete the password operations corresponding to the password service types in different password operation modules, and finally realize all the password services required in the calling instruction.

[0069] At this point, the first-level scheduling in the password service processing process is completed.

[0070] In the password operation processing module, the corresponding password operation intermediate value, the key, and the service data, the control information, the password algorithm, the flow control information and other data are obtained according to the instruction information. For example Figure 5 As shown in the figure, the key can be obtained from the corresponding key cache area according to the key address information. The password operation intermediate value can be, for example, data generated when the application interface function is called, such as the hash value generated in the digital signature process.

[0071] Continuing to refer to Figure 6 After obtaining the above data, the password operation processing module can generate a protocol frame based on (but not limited to) the key, the password operation intermediate value and the service data, and send the generated protocol frame to the arbitration module according to the type of the password algorithm.

[0072] The arbitration module can poll each password operation processing module, and transfer the protocol frames output by the password operation processing module to the corresponding password operation module (such as an algorithm chip) in order. At this point, the second-level scheduling in the password service processing process is completed.

[0073] In the password operation module, the service data is subjected to password operation based on the preset password algorithm using the key, and the operation result is output to the arbitration module.

[0074] The arbitration module returns the operation result output by the password operation module to the corresponding password operation processing module.

[0075] In the password operation processing module, the data frame is regenerated based on the returned operation result, and the data frame is sent to the password service classification and scheduling module.

[0076] In the password service classification and scheduling module, the data in the data frames belonging to the same calling instruction but possibly from one or more password operation processing modules are combined into one, and sent to the calling instruction analysis / packaging module.

[0077] At this point, the first level of scheduling in the password service processing result output process is completed.

[0078] In the calling instruction analysis / packaging module, the data returned by the password service classification and scheduling module is packaged, for example, an application interface function is formed, and the packaged application interface function is sent to the interface polling scheduling module.

[0079] In the interface polling scheduling module, the returned application interface function is returned to the corresponding service processing module through the corresponding service interface.

[0080] At this point, the second level of scheduling in the password service processing result output process is completed.

[0081] In the present application, data such as keys, cryptographic operation intermediate values, service data, random numbers, etc. can exist in the cache of the FPGA chip.

[0082] In a preferred embodiment, a non-volatile memory (such as a DDR memory) can also be provided in the encryption / decryption engine for caching data such as keys, cryptographic operation intermediate values, service data, random numbers, etc. to meet the demand for large data volume.

[0083] The working principle of the present application will be further explained below by describing the high-speed encryption / decryption implementation method according to the present application. For the sake of brevity, the same content as above will not be repeated.

[0084] In the high-speed encryption / decryption implementation method of the present application, the calling instructions can be sent in parallel by multiple service processing modules to the FPGA chip through multiple service interfaces (such as SerDes interfaces on the FPGA chip).

[0085] In the FPGA chip, the calling instructions at each service interface can be read by, for example, the interface polling scheduling module according to a predetermined rule (such as polling), and the calling instructions can be analyzed by, for example, the calling instruction analysis / packaging module to obtain instruction information.

[0086] Next, in the FPGA chip, the instruction information can be classified into password services by, for example, the password service classification and scheduling module; and cryptographic operation processing can be performed based on the corresponding instruction information in different cryptographic operation processing modules according to the password service type. In the present application, due to the existence of multiple cryptographic operation processing modules, multiple cryptographic operation processing can be performed in parallel. Therefore, it is possible to simultaneously process different password services from one or more calling instructions, greatly improving the operation efficiency. As an example, in the cryptographic operation processing, protocol frames can be generated based on (but not limited to) keys, cryptographic operation intermediate values, service data, etc.

[0087] Subsequently, in the FPGA chip, different password operation processing results (e.g. protocol frames) can be executed under corresponding password algorithms in parallel according to different password algorithm types to obtain operation results. For example, a plurality of password operation modules (algorithm chips) for executing the same or different password algorithm operations can be set to process a plurality of password operation processing results simultaneously.

[0088] When the password operation is completed, the operation results based on different password operation processing results are returned to the corresponding password operation processing modules, for example. Then, one or more operation results corresponding to the same calling instruction are packaged together (e.g. an application interface function is generated), and the packaged operation results are returned to the corresponding service processing module.

[0089] In the implementation method of the present application, a three-level key system will be adopted, in which the master key and the key encryption key can be stored in a secure chip, and the session key is stored in the FPGA chip. Moreover, when the password operation is executed, the key encryption key can be cached in the FPGA chip in advance.

[0090] Therefore, the present application combines the FPGA chip with the secure chip, and effectively improves the password operation processing performance and reduces the processing delay by means of multi-channel password service calling and multi-password operation module parallel operation.

[0091] In the high-speed encryption and decryption engine and the implementation method of the present application, a plurality of physical channels can be used to provide password services for different service processing modules by the same FPGA chip, which greatly improves the hardware resource use efficiency; the key cache and the password operation control are implemented in the same chip, which greatly reduces the time overhead of key update / switching and effectively reduces the password service processing delay; at the same time, the password operation execution process utilizes the parallel processing characteristics of the FPGA chip, and adopts a multi-stage parallel pipeline password operation running mechanism, which effectively improves the processing performance.

[0092] Although the present application has been described in detail with reference to the accompanying drawings and specific embodiments, those skilled in the art will readily recognize that the above-described embodiments are merely exemplary and are not intended to limit the scope of the present application, and various combinations, modifications and equivalent replacements of the above-described embodiments can be made without departing from the spirit and scope of the present application.

Claims

1. A high-speed encryption and decryption engine, comprising an FPGA chip, a security chip, and a plurality of cryptographic operation modules; the FPGA chip is configured to allow receiving calling instructions from a plurality of service processing modules through a plurality of service interfaces, and to parse the calling instructions to obtain instruction information; the FPGA chip is further configured to allow performing cryptographic operation processing based on the instruction information in a classified manner in parallel according to a cryptographic service type in the instruction information, and to send a cryptographic operation processing result to the cryptographic operation module corresponding to a cryptographic algorithm type according to the cryptographic algorithm type in the instruction information; the cryptographic operation module is configured to perform cryptographic operation on service data in the instruction information under the cryptographic algorithm type, and to output a cryptographic operation result; wherein, a key is arranged in the high-speed encryption and decryption engine, the key comprising a master key, a key encryption key, and a session key; the security chip is configured to implement life cycle management of the master key and the key encryption key; the FPGA chip is further configured to implement life cycle management of the session key; the key encryption key is synchronized and cached into the FPGA chip before the cryptographic operation is performed. 2.The high-speed encryption and decryption engine of claim 1, wherein: the calling instructions are encapsulated in the form of an application interface function; and / or, the cryptographic service type comprises symmetric encryption and decryption service, hash operation service, MAC operation service, asymmetric algorithm operation service, random number generation service, signature service, and signature verification service; and / or, the instruction information comprises the cryptographic service type, the cryptographic algorithm type, the service data, and service interface number information; and / or, the cryptographic algorithm type comprises SM2 algorithm, SM3 algorithm, and SM4 algorithm.

3. The high-speed encryption / decryption engine of claim 1, wherein, the FPGA chip is provided with an interface polling scheduling module and a calling instruction parsing / encapsulation module; the interface polling scheduling module is configured to query the state of the service interface in a polling manner, and to read the calling instructions; the calling instruction parsing / encapsulation module is configured to parse the calling instructions to obtain the instruction information. 4.The high-speed encryption and decryption engine of claim 3, wherein: the FPGA chip is further provided with a cryptographic service classification scheduling module and a plurality of cryptographic operation processing modules; the cryptographic service classification scheduling module is configured to classify according to the cryptographic service type, and to send the instruction information to the cryptographic operation processing module according to the classification result; the cryptographic operation processing module is configured to obtain a cryptographic operation intermediate value, a key, and the service data according to the instruction information, and to generate a protocol frame based thereon.

5. The high-speed encryption / decryption engine of claim 4, wherein, the FPGA chip is further provided with an arbitration module configured to poll the cryptographic operation processing module, and to send the protocol frame to the cryptographic operation module corresponding to the cryptographic algorithm type in sequence. 6.The high-speed encryption and decryption engine of claim 5, wherein, The arbitration module is further configured to return the cryptographic operation result to the cryptographic operation processing module corresponding to the protocol frame; The cryptographic operation processing module is further configured to regenerate data frames based on the cryptographic operation result and send the data frames to the cryptographic service classification and scheduling module; The cryptographic service classification and scheduling module is further configured to combine data in one or more data frames corresponding to the call instruction and send the data to the call instruction analysis and packaging module; The call instruction analysis and packaging module is further configured to package the data returned by the cryptographic service classification and scheduling module and return the data to the interface polling scheduling module; The interface polling scheduling module is further configured to return the packaged data to the service processing module corresponding to the call instruction via the service interface.

7. The high-speed encryption and decryption engine of claim 1, further comprising a non-volatile memory configured for caching at least one of the key, cryptographic operation intermediate value, service data, and random number; And / or, further comprising a random number generation module for generating a true random number for generation of the key.

8. A high-speed encryption and decryption implementation method, performed in the high-speed encryption and decryption engine of any one of claims 1-7, and comprising the steps of: receiving a plurality of call instructions in parallel through a plurality of service interfaces; reading the call instructions in a polling manner and analyzing the call instructions to obtain instruction information; classifying according to cryptographic service type and performing cryptographic operation processing based on the instruction information in a parallel manner to generate protocol frames; classifying according to cryptographic algorithm type and performing cryptographic operation based on the protocol frames in a parallel manner to generate cryptographic operation results.

9. The high-speed encryption and decryption implementation method of claim 8, further comprising the steps of: classifying according to the cryptographic service type and generating data frames based on the cryptographic operation results in a parallel manner; packaging the data frames according to the call instruction; and returning packaged data via the service interface.

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