Display panel, driving method thereof, and display device

Abstract

Embodiments of the present application provide a display panel, a driving method thereof and a display device, and relate to the technical field of display, and are used for improving flicker problem in low frequency mode. The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a driving transistor and a first light emitting control module; the working mode of the display panel comprises a first mode, in the first mode, the working period of the pixel driving circuit comprises a data writing stage and at least one data maintaining stage after the data writing stage; the data writing stage comprises at least one first light emitting period, and the data maintaining stage comprises at least one second light emitting period; the display panel further comprises a control module, and the control module is used for making the time length of the first first light emitting period in the data writing stage less than the time length of the at least one second light emitting period.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. [Background Technology]

[0002] With the development of display technology, display panels can use different refresh rates in different modes. For example, a higher refresh rate can be used to drive the display of dynamic images (such as sports events or game scenes) to ensure the smoothness of the display, while a lower refresh rate can be used to drive the display of static images to reduce the power consumption of the display panel.

[0003] However, currently, when driving display panels at a lower refresh rate, screen flickering issues are common. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and its driving method and display device to improve the flickering problem of the display panel in low-frequency mode.

[0005] On one hand, embodiments of the present invention provide a display panel, including an electrically connected light-emitting element and a pixel driving circuit. The pixel driving circuit includes a driving transistor and a first light-emitting control module. The gate of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node. The first light-emitting control module is electrically connected to a third node and the light-emitting element.

[0006] The display panel operates in a first mode, in which the working cycle of the pixel driving circuit includes a data writing phase and at least one data holding phase following the data writing phase; the data writing phase includes at least one first light emission period, and the data holding phase includes at least one second light emission period; during the first and second light emission periods, the first light emission control module is turned on.

[0007] The display panel also includes a control module, which is used to ensure that the duration of the first light-emitting period in the data writing phase is less than the duration of at least one second light-emitting period.

[0008] On the other hand, embodiments of the present invention provide a driving method for a display panel, the display panel including an electrically connected light-emitting element and a pixel driving circuit, the pixel driving circuit including a driving transistor and a first light-emitting control module; the gate of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node; the first light-emitting control module is electrically connected to a third node and the light-emitting element.

[0009] The display panel operates in a first mode, in which the working cycle of the pixel driving circuit includes a data writing phase and at least one data holding phase following the data writing phase; the data writing phase includes at least one first light emission period, and the data holding phase includes at least one second light emission period; during the first and second light emission periods, the first light emission control module is turned on.

[0010] The driving methods include:

[0011] The duration of the first emission period in the control data writing phase is less than the duration of at least one second emission period.

[0012] In another aspect, embodiments of the present invention provide a display device, including the display panel described above.

[0013] The display panel and its driving method and display device provided in the embodiments of the present invention, by including a first mode in the working mode of the display panel, can drive static images such as images in the first mode, which is beneficial to reduce the data refresh rate of the display panel and reduce the power consumption of the display panel when displaying static images or in the always-on display mode.

[0014] Furthermore, by providing a control module in the display panel, the present invention enables the duration of the first first light-emitting period in the data writing phase of the first mode to be less than the duration of at least one second light-emitting period. This helps to reduce the brightness of the light-emitting element in the data writing phase, thereby compensating for the reduction in brightness of the light-emitting element in the data holding phase caused by the change in the potential of the first node due to leakage current. This improves the brightness consistency of the light-emitting element in the data writing and data holding phases and reduces flickering problems. [Attached Image Description]

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 A circuit diagram of a sub-pixel provided in an embodiment of the present invention;

[0018] Figure 3 A timing diagram of a display panel in a first mode provided by an embodiment of the present invention;

[0019] Figure 4 A timing diagram of another display panel in a first mode provided in an embodiment of the present invention;

[0020] Figure 5 A schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 6 A timing diagram of another display panel in a first mode provided by an embodiment of the present invention;

[0022] Figure 7 A timing diagram of another display panel in a first mode provided by an embodiment of the present invention;

[0023] Figure 8 A timing diagram of another display panel in a first mode provided by an embodiment of the present invention;

[0024] Figure 9 A timing diagram of another display panel in a first mode provided by an embodiment of the present invention;

[0025] Figure 10 A circuit diagram of another sub-pixel provided in an embodiment of the present invention;

[0026] Figure 11 To and Figure 10 A corresponding timing diagram;

[0027] Figure 12 A circuit diagram of yet another sub-pixel provided in an embodiment of the present invention;

[0028] Figure 13 To and Figure 12 A corresponding timing diagram;

[0029] Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0030] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0032] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] It should be understood that although the terms first, second, third, etc., may be used to describe nodes in the embodiments of the present invention, these nodes should not be limited to these terms. These terms are only used to distinguish nodes from each other. For example, without departing from the scope of the embodiments of the present invention, a first node may also be referred to as a second node, and similarly, a second node may also be referred to as a first node.

[0035] In view of this, embodiments of the present invention provide a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel structure provided in an embodiment of the present invention. The display panel includes multiple sub-pixels, combined with... Figure 2 As shown, Figure 2 This is a circuit diagram of a sub-pixel provided in an embodiment of the present invention. The sub-pixel includes an electrically connected light-emitting element 11 and a pixel driving circuit 12. The light-emitting element 11 includes, but is not limited to, an organic light-emitting diode (OLED), a miniature light-emitting diode (Mini LED or Micro LED), or a quantum dot light-emitting diode (QLED).

[0036] The pixel driving circuit 12 includes a driving transistor M0, a storage capacitor Cst, a first reset module 21, a data writing module 22, a threshold compensation module 23, a first light emission control module 24, and a second light emission control module 25. The gate of the driving transistor M0 is electrically connected to the first node N1, the first terminal of the driving transistor M0 is electrically connected to the second node N2, and the second terminal of the driving transistor M0 is electrically connected to the third node N3. It should be noted that in this embodiment of the invention, the first node N1, the second node N2, and the third node N3 are defined only for the convenience of describing the structure of the pixel driving circuit 12, and the first node N1, the second node N2, and the third node N3 are not actual circuit units.

[0037] Combination Figure 2 As shown, the first reset module 21 is electrically connected to the first reset signal terminal Ref1 and the first node N1; the data writing module 22 is electrically connected to the data signal terminal Vdata and the second node N2; the threshold compensation module 23 is electrically connected to the third node N3 and the first node N1; the second light-emitting control module 25 is electrically connected to the first power supply voltage signal terminal PVDD and the second node N2; the first light-emitting control module 24 is electrically connected to the third node N3 and the first electrode of the light-emitting element 11; the second electrode of the light-emitting element 11 is electrically connected to the second power supply voltage signal terminal PVEE; and the storage capacitor Cst is electrically connected to the first node N1.

[0038] The display panel operates in two modes: a first mode and a second mode. The data refresh rate in the first mode is lower than that in the second mode. For example, the data refresh rate in the first mode can be less than 60Hz. For instance, the data refresh rate in the first mode could be 10Hz, 15Hz, or 30Hz. The data refresh rate in the second mode can be greater than or equal to 60Hz. For instance, the data refresh rate in the second mode could be 60Hz, 75Hz, or 120Hz.

[0039] During the display of one frame, the pixel driving circuit 12 of each row is activated sequentially to scan and write the data voltage corresponding to the current frame. In the first mode, combined with Figure 3 As shown, Figure 3 This is a timing diagram of a display panel in a first mode according to an embodiment of the present invention. The working cycle T of the pixel driving circuit 12 includes a data writing stage T1 and n data holding stages T2 located after the data writing stage T1; wherein n is an integer greater than or equal to 1. Figure 3 The working cycle T of the pixel driving circuit 12 is illustrated with n=3, that is, the working cycle T includes three data holding stages T2.

[0040] like Figure 3 As shown, the data writing phase T1 includes a first reset period a, a data writing period b, and m first light emission periods c1. The first reset period a precedes the data writing period b, and each first light emission period c1 follows the data writing period b. The data maintenance phase T2 includes m second light emission periods c2. m is an integer greater than or equal to 1. Figure 3 As shown in the diagram, m=1, that is, the data writing stage T1 includes a first light emission period c1, and the data maintenance stage T22 includes a second light emission period c2.

[0041] For example, such as Figure 4 As shown, Figure 4The following is a timing diagram of another display panel in a first mode provided by an embodiment of the present invention, wherein m=3, that is, the data writing stage T1 includes three first light emission periods c1, and the data maintenance stage T22 includes three second light emission periods c2 as an illustration.

[0042] When the display panel is working, in the first mode, combined with Figure 2 , Figure 3 and Figure 4 As shown, during the first reset period a, the first reset module 21 is turned on by the signal provided by the first scan control signal terminal S1N. The first reset signal provided by the first reset signal terminal Ref1 is written to the first node N1 through the first reset module 21 to reset the first node N1 and eliminate the influence of the signal written by the first node N1 during the previous frame display period, that is, during the previous working cycle T, on the potential of the first node N1 in the current working cycle T.

[0043] During data writing period b, the first reset module 21 is turned off, the data writing module 22 is turned on under the action of the signal provided by the second scan control signal terminal SP, and the threshold compensation module 23 is turned on under the action of the signal provided by the third scan control signal terminal S2N. The data signal terminal Vdata writes the data voltage corresponding to the current working cycle T to the first node N1 through the data writing module 22. At the same time, the threshold compensation module 23 detects the deviation from the threshold voltage Vth of the self-compensating driving transistor M0 during this stage. When the potential of the first node N1 reaches Vd-|Vth|, the driving transistor M0 is turned off, completing the capture of the threshold voltage Vth of the driving transistor M0. Vd is the data voltage provided by the data signal terminal Vdata corresponding to the current working cycle T.

[0044] During the first light-emitting period c1, the first reset module 21, data writing module 22, and threshold compensation module 23 are turned off, and the potential of the first node N1 is maintained by the storage capacitor Cst. The first light-emitting control module 24 is turned on by the signal provided by the light-emitting control signal terminal E, the second light-emitting control module 25 is turned on by the signal provided by the light-emitting control signal terminal E, the driving transistor M0 is turned on by the first node N1, and the light-emitting element 11 is lit by the driving current generated by the driving transistor M0.

[0045] For example, such as Figure 4As shown, when the data writing period T1 includes at least two first light-emitting periods c1, the pixel driving circuit 12 also includes a first non-light-emitting period d1 located between two adjacent first light-emitting periods c1. During the first non-light-emitting period d1, the first light-emitting control module 24 is turned off under the control of the light-emitting control signal terminal E, and the light-emitting element 11 is not lit. By setting multiple first light-emitting periods c1, with adjacent first light-emitting periods c1 separated by a first non-light-emitting period d1, the light-emitting element 11 can alternate between on and off during the driving process, thereby adjusting the brightness of the light-emitting element 11 during the data writing stage T1. For example, the light-emitting brightness of the light-emitting element 11 can be adjusted by adjusting the duration ratio of the first light-emitting period c1 and the first non-light-emitting period d1.

[0046] After the data writing phase T1, the pixel driving circuit 12 enters the data holding phase T2, combined with Figure 3 and Figure 4 As shown, the data maintenance phase T2 includes a second non-light-emitting period d2 and a second light-emitting period c2. During the second non-light-emitting period d2, the first light-emitting control module 24 is turned off under the control of the light-emitting control signal terminal E, and the light-emitting element 11 is not lit. During the second light-emitting period c2, the potential of the first node N1 is maintained under the action of the storage capacitor Cst, and the first light-emitting control module 24, the second light-emitting control module 22, and the driving transistor M0 are turned on; the third node N3 is electrically connected to the light-emitting element 11, and the driving transistor M0 generates a driving current under the control of the potential of the first node N1, causing the light-emitting element 11 to light up under the control of the driving current.

[0047] In this embodiment of the invention, the duration of the first first light emission period c1 in the data writing stage T1 is B01; the duration of the j-th second light emission period c2 in the i-th data maintenance stage T2 is Bij; i and j are both integers, and 1≤i≤n, 1≤j≤m.

[0048] like Figure 1 As shown, the display panel also includes a control module 2, combined with... Figure 3 and Figure 4 As shown, in this embodiment of the invention, the control module 2 is used to ensure that the duration B01 of the first first light-emitting period c1 in the data writing stage T1 is less than the duration Bij of at least one second light-emitting period c2 in the data maintenance stage T2. When the data writing stage T1 includes at least two first light-emitting periods c1, the first first light-emitting period c1 is the light-emitting period of the corresponding pixel driving circuit 12 that is closest to the data writing period b within one working cycle T. When the data writing stage T1 includes one first light-emitting period c1, that first light-emitting period c1 is simply the first first light-emitting period c1.

[0049] Optional, such as Figure 3 and Figure 4 As shown, in this embodiment of the invention, the duration of the data writing phase T1 and the single data maintenance phase T2 can be the same.

[0050] The embodiments of the present invention enable the display panel to operate in a first mode, which allows static images such as pictures to be driven in the first mode. This helps to reduce the data refresh rate of the display panel and reduce the power consumption of the display panel when displaying static images or in Always On Display (AOD) mode.

[0051] Combination Figure 2 As shown, in the first mode, the potential of the first node N1 in the pixel driving circuit 12 is not refreshed during the data maintenance phase T2, that is, the potential of the first node N1 needs to be maintained for a relatively long time under the action of the storage capacitor Cst. Due to the presence of leakage current, the potential of the first node N1 changes over time, causing the brightness of the light-emitting element 11 in the related art to decay. The embodiment of the present invention, by making the duration B01 of the first light-emitting period c1 in the data writing phase T1 shorter than the duration Bij of at least one second light-emitting period c2 in the data maintenance phase T2, helps to reduce the brightness of the light-emitting element 11 in the data writing phase T1, thereby compensating for the decrease in brightness of the light-emitting element 11 in the data maintenance phase T2 caused by the change in the potential of the first node N1 due to leakage current, improving the brightness consistency of the light-emitting element 11 in the data writing phase T1 and the data maintenance phase T2, and reducing the flicker problem.

[0052] like Figure 1 As shown, the display panel also includes a data line (Data), a first power supply voltage line (VDD), and a first scan control signal line (L). S1N Second scan control signal line L SP Third scan control signal line L S2N and the light control signal line L E The data line Data is connected to the data signal terminal of the pixel driving circuit 12. Figure 1 Electrically connected (not shown), the first power supply voltage line VDD is connected to the first power supply voltage signal terminal of the pixel driving circuit 12 (not shown). Figure 1 Electrical connection (not shown), first scan control signal line L S1N With the first scan control signal terminal of the pixel driving circuit 12 ( Figure 1 Electrical connection (not shown), second scan control signal line L SP With the second scan control signal terminal of the pixel driving circuit 12 ( Figure 1 Electrical connection (not shown), third scan control signal line L S2N The third scan control signal terminal of the pixel driving circuit 12 ( Figure 1Electrical connection (not shown), LED control signal line L E With the light emission control signal terminal of pixel driving circuit 12 ( Figure 1 Electrical connection (not shown).

[0053] For example, such as Figure 5 As shown, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel further includes a light-emitting control circuit 3, which includes cascaded light-emitting control units 30. The light-emitting control units 30 and the first light-emitting control module ( Figure 5 The control terminal (not shown) is electrically connected. Under the action of the light emission control signal output by the light emission control unit 30, the first light emission control module 24 can switch between on and off, so that the pixel driving circuit 12 switches between non-light emission periods and light emission periods. The first light emission period c1 and the second light emission period c2 are the periods when the light emission control signal is at an effective level (e.g., low level). The non-light emission period corresponds to the period when the light emission control signal is at an ineffective level (e.g., high level). Figure 3 and Figure 4 The illustration uses a low level for the effective level of the light emission control signal and a high level for the ineffective level. Of course, depending on the different design requirements of the pixel driving circuit 12, the effective level of the light emission control signal can be set to a high level, and the ineffective level of the light emission control signal can be set to a low level. This embodiment of the invention does not limit this.

[0054] In this embodiment of the invention, the control module ( Figure 5 (Not shown) is electrically connected to the light-emitting control circuit 3. The control module 2 is able to make the duty ratio of the first high-level pulse of the light-emitting control signal output by the light-emitting control circuit 3 in the data writing stage T1 greater than the duty ratio of at least one high-level pulse in the data holding stage T2, so that the duration B01 of the first light-emitting period c1 in the data writing stage T1 is less than the duration Bij of at least one second light-emitting period c2 in the data holding stage T2.

[0055] For example, in embodiments of the present invention, the duration B01 of the first first light emission period c1 within the data writing phase T1 can be made less than the duration of at least one second light emission period c2 within the data maintenance phase T2.

[0056] For example, compared to the reference light emission control signal, which refers to the light emission control signal in which the duty cycle of each high-level pulse in the data writing stage T1 is the same as the duty cycle of each high-level pulse in the data holding stage T2, the embodiments of the present invention can move the rising edge of the first high-level pulse in the data writing stage T1 of the reference light emission control signal forward, and / or move the falling edge of the first high-level pulse in the data writing stage T1 backward.

[0057] Alternatively, in embodiments of the present invention, the rising edge of at least one high-level pulse of the reference light emission control signal during the data holding phase T2 may be moved backward, and / or the falling edge of at least one high-level pulse during the data holding phase T2 may be moved forward.

[0058] For example, such as Figure 3 and Figure 4 As shown, in this embodiment of the invention, the number of second light-emitting periods c2 in the data maintenance phase T2 and the number of first light-emitting periods c1 in the data writing phase T1 can both be m. This setting is beneficial in two ways: firstly, it helps to improve the consistency of the bias state of the driving transistor M0 in the data maintenance phase T2 and the bias state in the data writing phase T1, which helps to improve the flickering problem; secondly, it also helps to design the working timing of the light-emitting control circuit 3.

[0059] Optional, such as Figure 2 As shown, in this embodiment of the invention, a second reset module 26 electrically connected to the second reset signal terminal Ref2 and the light-emitting element 11 can be provided in the pixel driving circuit 12, and a second reset period for resetting the light-emitting element 11 can be set before the first light-emitting period c1 of the data writing stage T2. During the second reset period, the second reset module 26 is turned on, and the second reset signal provided by the second reset signal terminal Ref2 resets the light-emitting element 11.

[0060] Optionally, the first reset period a or the data write period b mentioned above can be reused as the second reset period. Figure 2 The second reset module 26 is electrically connected to the second scan control signal terminal SP, that is, Figure 3 and Figure 4 The data write period b in the diagram is reused as the second reset period for illustration.

[0061] For example, such as Figure 2As shown, in this embodiment of the invention, the first reset module 21 can be configured to include a first transistor M1, the data writing module 22 can be configured to include a second transistor M2, the threshold compensation module 23 can be configured to include a third transistor M3, the first light emission control module 24 can be configured to include a fourth transistor M4, the second light emission control module 25 can be configured to include a fifth transistor M5, and the second reset module 26 can be configured to include a sixth transistor M6.

[0062] Optionally, in embodiments of the present invention, at least one of the first transistor M1 and the third transistor M3 may include an oxide transistor to reduce the off-state leakage current of the first transistor M1 or the third transistor M3, thereby reducing the influence of the leakage current on the potential of the first node N1, improving the potential stability of the first node N1, thereby improving the stability of the driving current flowing through the light-emitting element 11 during different light-emitting periods within a working cycle T, so as to further improve the uniformity of the light-emitting brightness of the light-emitting element 11 and reduce flicker.

[0063] For example, such as Figure 5 As shown, the display panel includes multiple pixel driving circuit row groups 4, each pixel driving circuit row group 4 includes N pixel driving circuit rows 40, each pixel driving circuit row 40 includes multiple pixel driving circuits 12 arranged along a first direction x, and the multiple pixel driving circuit rows 40 are arranged along a second direction y; multiple first light-emitting control modules ( Figure 5 (Not shown) is electrically connected to the same light-emitting control unit 30; where N is an integer greater than or equal to 1; that is, the light-emitting control unit 30 adopts a one-to-N driving method. In this embodiment of the invention, B01 = Bij - kNH, where i is any integer from 1 to n, j is any integer from 1 to m, k is an integer greater than or equal to 1, and H is the row scanning time of a pixel driving circuit row 40. This setting can reduce the timing design difficulty of the light-emitting control signal output by the light-emitting control unit 30, and is simple and easy to operate.

[0064] For example, in an embodiment of the present invention, m = 2 and k × N = 4. Optionally, in an embodiment of the present invention, k = 1 and N = 4. Or, k = 2 and N = 2.

[0065] By setting N≥2, the first-level light-emitting control unit 30 can drive more pixel driving circuits 40, which helps to reduce the number of light-emitting control units 30, thereby narrowing the bezel width of the display panel and increasing the screen ratio of the display panel. In addition, the one-drive-multiple-mode method can reduce the frequency of the light-emitting clock signal used to control the light-emitting control unit 30 compared to the one-drive-one-mode method, thereby reducing the power consumption of the light-emitting control unit 30.

[0066] For example, when the data sustaining phase T2 includes at least two second emission periods c2, when setting the duration of the at least two second emission periods c2 within the same data sustaining phase T2, optionally, in this embodiment of the invention, Bi1≤Bi2≤……≤Bim. Where i can be any integer from 1 to n. That is, the duty cycle of the multiple high-level pulses of the emission control signal within the same data sustaining phase T2 is gradually reduced. Combined with... Figure 2 As shown, in the first mode, the potential of the first node N1 in the pixel driving circuit 12 is not refreshed during the data maintenance phase T2, that is, the potential of the first node N1 needs to be maintained for a relatively long time under the action of the storage capacitor Cst. Due to the existence of leakage current, the potential of the first node N1 will change as time progresses, causing the brightness of the light-emitting element 11 in the related technology to continuously decay. The embodiment of the present invention, by letting Bi1≤Bi2≤……≤Bim, that is, by gradually increasing the duration of each second light-emitting period c2 within the same data maintenance phase T2, can compensate for the influence of leakage current on the brightness of the light-emitting element 11, which is beneficial to further improve the flickering problem in the first mode. Figure 6 As shown, Figure 6 This is a timing diagram of another display panel in a first mode provided by an embodiment of the present invention. Figure 6 Using m=3, n=3, and B11<B12<B13, B21<B22<B23, B31<B32<B33 as an example, that is, the duration of each second light emission period c2 in each data maintenance phase T2 satisfies the above relationship. With this setting, the brightness change caused by leakage current in each data maintenance phase T2 can be compensated, so as to improve the brightness consistency of the light emission element 11 in one working cycle T to a greater extent and reduce or avoid the flicker problem.

[0067] For example, when one operating cycle T of the pixel driving circuit 12 includes multiple data sustaining phases T2, the embodiments of the present invention can set B1j≤B2j≤……≤Bnj. Here, j can be any integer from 1 to m. That is, the duty cycle of the corresponding high-level pulse width of the light emission control signal transmitted by the light emission control signal terminal E is gradually reduced in different data sustaining phases T2 to compensate for the influence of leakage current on brightness, which is beneficial to further improve the flicker problem in the first mode.

[0068] For example, when the data maintenance phase T2 includes at least two second emission periods c2, that is, when m≥2, the embodiments of the present invention can ensure that each second emission period c2 in the data maintenance phase T2 satisfies the above relationship with the corresponding second emission period c2 in other data maintenance phases T2. Figure 6 The following diagram illustrates the relationships between B11, B21, B31, B12, B22, B32, and B13, B23, and B33.

[0069] Combination Figure 7 As shown, Figure 7 This is a timing diagram of another display panel in a first mode provided by an embodiment of the present invention. Figure 7 The following is an illustration, with m=3, n=3, and B11<B21<B31, B12<B22<B32, B13<B23<B33, and B11<B12<B13, B21<B22<B23, B31<B32<B33.

[0070] Optionally, when n≥2, the n data maintenance stages T2 include at least the (i-1)th data maintenance stage T2 and the ith data maintenance stage T2, which are set adjacently. The duration of the m-th second emission period c2 in the (i-1)th data maintenance stage T2 is less than or equal to the duration of the first second emission period c1 in the ith data maintenance stage T2. That is, in this embodiment of the invention, B(i-1)m < Bi1 can also be set. Here, B(i-1)m is the duration of the m-th second emission period c2 within the (i-1)th data maintenance stage T2, and Bi1 is the duration of the first second emission period c2 within the ith data maintenance stage T2. Combined with... Figure 8 As shown, Figure 8 This is a timing diagram of another display panel in a first mode provided by an embodiment of the present invention. Figure 8 The example uses m=3, n=3, and B11<B12<B13<B21<B22<B23<B31<B32<B33. This setting helps to further improve the flickering problem in the first mode.

[0071] For example, such as Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the working cycle of the pixel driving circuit 12 includes multiple data maintenance phases T2, and the data maintenance phase T2 includes multiple second light emission periods c2, the embodiment of the present invention can make any one of the durations of the second light emission periods c2 in each data maintenance phase T2 greater than the duration B01 of the first light emission period c1 in the data writing phase T1.

[0072] For example, in the m first light-emitting periods c1 included in the data writing phase T1, where m is an integer greater than or equal to 2, there are at least two adjacent first light-emitting periods c1, wherein the duration of the preceding first light-emitting period c1 is shorter than the duration of the following first light-emitting period c1. This embodiment of the invention, by making the duration of the preceding first light-emitting period c1 shorter than the duration of the following first light-emitting period c1, can compensate for the potential change of the first node N1 caused by leakage current during the data writing phase T1, thereby improving the flickering problem during the data writing phase T1. Combined with... Figure 9 As shown, Figure 9 This is a timing diagram of another display panel in a first mode provided by an embodiment of the present invention, wherein m = 3 is used as an illustration, wherein the duration of the first first light-emitting period c1 is B01, the duration of the second first light-emitting period c1 is B02, the duration of the third first light-emitting period c1 is B03, and B01 < B02 < B03.

[0073] For example, in combination Figure 10 and Figure 11 As shown, Figure 10 This is a circuit diagram of another sub-pixel provided in an embodiment of the present invention. Figure 11 To and Figure 10 In a corresponding timing diagram, the pixel driving circuit 12 also includes an adjustment module 27 electrically connected to the second node N2. The adjustment module 27 is electrically connected to the adjustment signal terminal Vpark and the second node N2, and the control terminal of the adjustment module 27 is electrically connected to the fourth scan control signal terminal S*. The data maintenance phase T12 also includes an adjustment phase e located before the second light emission phase c2. During the adjustment phase e, the adjustment module 27 is turned on, and the bias adjustment signal Vp provided by the adjustment signal terminal Vpark is written to the second node N2 through the adjustment module 27. The bias adjustment signal can adjust the bias state of the driving transistor M0. During the research process, the inventors discovered that in the data writing phase T1 located at the initial stage of each working cycle T, due to the existence of the hysteresis voltage of the driving transistor M0, the light-emitting element 11 has a light emission delay phenomenon, causing a brightness delay in the first light emission phase c1. In this embodiment of the invention, by setting the adjustment module 27 to adjust the bias of the driving transistor M0, the display brightness can also generate a brightness delay when entering the second light-emitting period c2, so as to reduce the brightness of the light-emitting element 11 in the data holding period T2, thereby reducing the brightness difference between the data holding period T1 and the data writing period T2, and improving the flickering problem in the first mode.

[0074] For example, such as Figure 11 As shown, the adjustment period e is located within the second non-luminescent period d2.

[0075] Specifically, when the display panel is used for low grayscale display, the light emission delay effect of the data writing phase T1 relative to the data holding phase T2 is significant. If the duration of the first light emission period c1 within the data writing phase T1 is made the same as the duration of the second light emission period c2 within the data holding phase T2, the brightness of the data writing phase T1 will be lower than the brightness of the data holding phase T2. This embodiment of the invention, by shortening the duration of the first light emission period c1 and adjusting the bias of the driving transistor M0 during the data holding phase T2, can reduce the brightness of the light-emitting element 11 during the data holding phase T2, thereby making the brightness of the light-emitting element 11 in the data writing phase T1 and the data holding phase T2 more consistent, improving the flicker problem of the display panel in the first mode.

[0076] When the display panel is used for high grayscale display, the bias voltage of the driving transistor M0 is relatively weak during the data writing phase T1. The light emission delay effect of the data writing phase T1 is relatively weak compared to the data holding phase T2. If the duration of the first light emission period c1 in the data writing phase T1 is the same as the duration of the second light emission period c2 in the data holding phase T2, the brightness of the data writing phase T1 will be higher than the brightness in the data holding phase T2. Based on the setting method provided in the embodiment of the present invention, by reducing the brightness of the light-emitting element 11 in the data writing phase T1 and the data holding phase T2, the difference in brightness between the light-emitting element 11 perceived by the human eye in the data writing phase T1 and the data holding phase T2 can be reduced, thus avoiding the worsening of the flicker problem.

[0077] As can be seen from Table 1, Table 1 shows the simulation data of flicker values ​​(in dB, the larger the absolute value of the flicker value, the weaker the flicker) of display panels with different timing designs at different gray levels. Among them, the highest gray level 255 corresponds to a brightness of 300 nits. The data refresh rate of Comparative Example 1, Comparative Example 2 and the embodiment are all 10Hz. Comparative Example 1 did not set the above-mentioned bias adjustment period e in the data maintenance phase T2. Moreover, the duration of the first first emission period c1 and the second emission period c2 in Comparative Example 1 are the same. Comparative Example 2, in the data maintenance phase... In segment T2, the aforementioned bias adjustment period e is provided. In Comparative Example 2, the duration of the first light emission period c1 is the same as the duration of the second light emission period c2. In the embodiment, the bias adjustment period e is provided in the data maintenance phase T2. In the embodiment, the duration of the first light emission period c1 is less than the duration of the second light emission period c2. It can be seen that, compared with Comparative Example 1 and Comparative Example 2, the flickering problem of the embodiment is significantly improved at low grayscale. Furthermore, at high grayscale, the flickering degree of the embodiment is also weak and does not deteriorate.

[0078] Table 1 Simulation data of flicker values ​​of display panels with different timing designs at different gray levels.

[0079]

[0080] For example, such as Figure 11 As shown in the embodiment of the present invention, the bias adjustment signal Vp provided by the bias adjustment signal terminal Vpark includes a constant signal.

[0081] Optional, such as Figure 12 and Figure 13 As shown, Figure 12 This is a circuit diagram of another sub-pixel provided in an embodiment of the present invention. Figure 13 To and Figure 12 In a corresponding timing diagram, the adjustment module 27 is also used to provide a data signal Vd to the second node N2 during the data writing period b. That is, the adjustment module 27 can be reused as the aforementioned data writing module 22, and the bias adjustment signal terminal Vpark can be reused as the aforementioned data signal terminal Vdata. This configuration simplifies the structure of the pixel driving circuit 12, reduces the area occupied by the pixel driving circuit 12, and improves the resolution of the display panel.

[0082] For example, in combination Figure 1 As shown, the display panel includes a data line Data, and the data line Data is connected to the data signal terminal of the pixel driving circuit 12. Figure 1 (Not shown) Electrical connection, adjustment module 27 is electrically connected to data line Data and second node N2; combined with Figure 13 As shown, the data line Data is used to transmit the data signal Vd required by the pixel driving circuit 12 in the current frame during the data writing period b, and to transmit the bias adjustment signal Vp during the adjustment period e. This configuration helps to reduce the number of wires in the display panel and further simplifies the panel structure.

[0083] For example, such as Figure 12 As shown, the gate of the second transistor M2 is electrically connected to the second scan control signal terminal SP. The first terminal of the second transistor M2 is electrically connected to the data line via the data signal terminal Vdata, and the second terminal is electrically connected to the second node N2. Combined with... Figure 13 As shown, the second scan control signal terminal SP transmits an effective level during both the data writing period b and the adjustment period e.

[0084] This invention also provides a driving method for a display panel, combined with... Figure 1As shown, the display panel includes multiple sub-pixels. Each sub-pixel includes an electrically connected light-emitting element 11 and a pixel driving circuit 12. The pixel driving circuit 12 includes a driving transistor M0 and a first light-emitting control module 24. The gate of the driving transistor M0 is electrically connected to a first node N1, the first electrode of the driving transistor M0 is electrically connected to a second node N2, and the second electrode of the driving transistor M0 is electrically connected to a third node N3. The first light-emitting control module 24 is electrically connected to the third node N3 and the light-emitting element 11.

[0085] The display panel's operating modes include a first mode, in which... Figure 3 As shown, the working cycle T of the pixel driving circuit 12 includes a data writing phase T1 and at least one data holding phase T2 following the data writing phase T1; the data writing phase T2 includes at least one first light emission period c1, and the data holding phase T2 includes at least one second light emission period c2; during the first light emission period c1 and the second light emission period c2, the first light emission control module 24 is turned on.

[0086] The driving method provided in this embodiment of the invention includes:

[0087] The duration of the first emission period c1 in the control data writing phase T1 is less than the duration of at least one second emission period c2 in the data maintenance phase T2.

[0088] This invention, by including a first mode in the operating mode of the display panel, allows static images, such as pictures, to be driven in the first mode, which helps reduce the data refresh rate of the display panel and the power consumption of the display panel when displaying static images or in Always On Display (AOD) mode. Furthermore, by making the duration B01 of the first light-emitting period c1 in the data writing phase T1 shorter than the duration of at least one second light-emitting period c2 in the data holding phase T2, this invention helps reduce the brightness of the light-emitting element 11 in the data writing phase T1. This compensates for the decrease in brightness of the light-emitting element 11 in the data holding phase T2 caused by the leakage current change in the potential of the first node N1, improving the brightness consistency of the light-emitting element 11 in the data writing phase T1 and the data holding phase T2, and reducing flicker problems.

[0089] For example, in the data writing stage T1 of the pixel driving circuit 12 provided in this embodiment of the invention, the duration of the first light emission period c1 is B01; the working cycle T of the pixel driving circuit 12 includes n data maintenance stages T2; the data maintenance stage T2 includes m second light emission periods c2; the duration of the j-th second light emission period c2 in the i-th data maintenance stage T2 is Bij; i and j are both integers, and 1≤i≤n, 1≤j≤m.

[0090] Combination Figure 5 As shown, the display panel includes multiple pixel driving circuit rows 4 and multiple cascaded light-emitting control units 30. The pixel driving circuit rows 4 include N pixel driving circuit rows 40, and each pixel driving circuit row 40 includes multiple pixel driving circuits 12 arranged along a first direction x; the first light-emitting control module in the same pixel driving circuit row 4 ( Figure 5 (Not shown) is electrically connected to the same light-emitting control unit 30; where N is an integer greater than or equal to 1; that is, the light-emitting control unit 30 adopts a one-to-N method.

[0091] For example, in an embodiment of the present invention, the method of making the duration of the first light-emitting period c1 in the control data writing stage T1 shorter than the duration of at least one second light-emitting period c2 in the data maintenance stage T2 includes: letting B01 = Bij - kNH, where k is an integer greater than or equal to 1, and H is the row scan time of a pixel driving circuit row 40. This setting reduces the timing design difficulty of the light-emitting control signal output by the light-emitting control unit 30, and is simple and easy to operate.

[0092] Optionally, the driving method for the display panel provided in this embodiment of the invention further includes: controlling Bi1≤Bi2≤……≤Bim. Where i can be any integer from 1 to n. That is, gradually decreasing the duty cycle of multiple high-level pulses of the light emission control signal within the same data maintenance phase T2. Combined with... Figure 2 As shown, in the first mode, the potential of the first node N1 in the pixel driving circuit 12 is not refreshed during the data maintenance phase T2, that is, the potential of the first node N1 needs to be maintained for a relatively long time under the action of the storage capacitor Cst. Due to the presence of leakage current, the potential of the first node N1 changes as time progresses, causing the brightness of the light-emitting element 11 in the related technology to continuously decay. In this embodiment of the invention, by setting Bi1≤Bi2≤……≤Bim, that is, by gradually increasing the duration of each second light-emitting period c2 within the same data maintenance phase T2, the influence of leakage current on the brightness of the light-emitting element 11 can be compensated, which is beneficial to further improve the flickering problem in the first mode. Figure 6 Using m=3, n=3, and B11<B12<B13, B21<B22<B23, B31<B32<B33 as an example, that is, the duration of each second light emission period c2 in each data maintenance phase T2 satisfies the above relationship, so as to compensate for the brightness changes caused by leakage current in each data maintenance phase T2, so as to improve the brightness consistency of the light emission element 11 within one working cycle T to a greater extent and reduce or avoid flickering problems.

[0093] Optionally, the driving method for the display panel provided in this embodiment of the invention further includes: controlling B1j≤B2j≤……≤Bnj. Here, j can be any integer from 1 to m. That is, the duty cycle of the corresponding high-level pulse width of the light-emitting control signal transmitted by the light-emitting control signal terminal E is gradually reduced during different data maintenance phases T2 to compensate for the influence of leakage current on brightness, which is beneficial to further improve the flicker problem in the first mode.

[0094] For example, when n≥2, the driving method provided in this embodiment of the invention further includes:

[0095] Let each of the n data maintenance stages T2 include at least the (i-1)th data maintenance stage T2 and the ith data maintenance stage T2, wherein the duration of the m-th second emission period c2 in the (i-1)th data maintenance stage T2 is less than or equal to the duration of the first second emission period c2 in the ith data maintenance stage T2. That is, in this embodiment of the invention, B(i-1)m < Bi1. Here, B(i-1)m is the duration of the m-th second emission period c2 within the (i-1)th data maintenance stage T2, and Bi1 is the duration of the first second emission period c2 within the ith data maintenance stage T2. Combined with... Figure 8 As shown, Figure 8 The example uses m=3, n=3, and B11<B12<B13<B21<B22<B23<B31<B32<B33. This setting helps to further improve the flickering problem in the first mode.

[0096] For example, such as Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown, when the working cycle of the pixel driving circuit 12 includes multiple data maintenance phases T2, and the data maintenance phase T2 includes multiple second light emission periods c2, the embodiment of the present invention can make any one of the durations of the second light emission periods c2 in each data maintenance phase T2 greater than the duration B01 of the first light emission period c1 in the data writing phase T1.

[0097] For example, in combination Figure 12 and Figure 13 As shown, the pixel driving circuit 12 also includes an adjustment module 27 electrically connected to the second node N2; the data writing stage T1 also includes a data writing stage b located before the first light emission stage c1; the data holding stage T2 also includes an adjustment stage e located before the second light emission stage c2.

[0098] The display panel driving method provided in this embodiment of the invention further includes:

[0099] During the data writing period b, the control adjustment module 27 provides a data signal Vd to the second node N2;

[0100] During adjustment period e, the control adjustment module 27 provides a bias adjustment signal Vp to the second node N2. The bias adjustment signal Vp can adjust the bias state of the driving transistor M0. During their research, the inventors discovered that in the data writing phase T1 at the beginning of each working cycle T, the presence of hysteresis voltage in the driving transistor M0 causes a light emission delay in the light-emitting element 11, resulting in a brightness delay in the first light emission period c1. This embodiment of the invention, by setting the adjustment module 27 to adjust the bias of the driving transistor M0, can also cause a brightness delay when entering the second light emission period c2, thereby reducing the brightness of the light-emitting element 11 in the data holding phase T2, thus reducing the brightness difference between the data holding phase T1 and the data writing phase T2, and improving the flickering problem in the first mode.

[0101] Furthermore, by having the adjustment module 27 conduct during the data writing period b to provide a data signal Vd to the second node N2, and also conduct during the adjustment period e to provide a bias adjustment signal Vp to the second node N2, this embodiment of the invention simplifies the structure of the pixel driving circuit 12, reduces the area occupied by the pixel driving circuit 12, and improves the resolution of the display panel.

[0102] This invention also provides a display device, such as... Figure 14 As shown, Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 14 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0103] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized by, The display panel comprises a light emitting element and a pixel driving circuit electrically connected, the pixel driving circuit comprises a driving transistor and a first light emitting control module; a gate of the driving transistor is electrically connected with a first node, a first pole of the driving transistor is electrically connected with a second node, and a second pole of the driving transistor is electrically connected with a third node; the first light emitting control module is electrically connected with the third node and the light emitting element; The working mode of the display panel comprises a first mode, in the first mode, a working period of the pixel driving circuit comprises a data writing stage and at least one data maintaining stage after the data writing stage; the data writing stage comprises at least one first light emitting period, and the data maintaining stage comprises at least one second light emitting period; In the first light emitting period and the second light emitting period, the first light emitting control module is turned on; The display panel further comprises a control module, and the control module is used for making a time length of a first first light emitting period in the data writing stage less than a time length of at least one second light emitting period; The time length of the first first light emitting period in the data writing stage is B01; The working period of the pixel driving circuit comprises n data maintaining stages; the data maintaining stage comprises m second light emitting periods, and a time length of a jth second light emitting period of an ith data maintaining stage is Bij; i and j are integers, and 1≤i≤n and 1≤j≤m; The display panel comprises a plurality of pixel driving circuit row groups and a plurality of light emitting control units which are cascaded with each other, the pixel driving circuit row group comprises N pixel driving circuit rows, the pixel driving circuit row comprises a plurality of pixel driving circuits, the first light emitting control modules in the same pixel driving circuit row group are electrically connected with the same light emitting control unit, and N is an integer greater than or equal to 1; B01=Bij-kNH, wherein k is an integer greater than or equal to 1, and H is a row scanning time of one pixel driving circuit row.

2. The display panel of claim 1, wherein m=2, and k×N=4.

3. The display panel of claim 1, wherein, Bi1≤Bi2≤……≤Bim.

4. The display panel of claim 1, wherein, B1j≤B2j≤……≤Bnj.

5. The display panel of claim 1, wherein, n≥2; at least an (i-1)th data maintaining stage and an ith data maintaining stage which are arranged adjacently are included in the n data maintaining stages, wherein a time length of an mth second light emitting period in the (i-1)th data maintaining stage is less than or equal to a time length of a first second light emitting period in the ith data maintaining stage.

6. The display panel of claim 1, wherein the data writing stage comprises m first light emitting periods, and m is an integer greater than or equal to 2; at least two first light emitting periods which are adjacent to each other exist, and a time length of a previous first light emitting period is less than a time length of a subsequent first light emitting period.

7. The display panel of claim 1, wherein the pixel driving circuit further comprises an adjusting module which is electrically connected with the second node. The data write stage further comprises a data write period before the first light emitting period; and the data maintaining stage further comprises an adjusting period before the second light emitting period. The adjusting module is configured to provide a data signal to the second node during the data write period, and provide a bias adjusting signal to the second node during the adjusting period.

8. The display panel of claim 7, wherein The display panel comprises a data line electrically connected to the adjusting module. The data line is configured to transmit the data signal during the data write period, and transmit the bias adjusting signal during the adjusting period.

9. The display panel of claim 7, wherein The bias adjusting signal comprises a constant signal.

10. A driving method for a display panel, characterized by, The display panel comprises a light emitting element and a pixel driving circuit electrically connected to each other, the pixel driving circuit comprises a driving transistor and a first light emitting control module, a gate of the driving transistor is electrically connected to a first node, a first electrode of the driving transistor is electrically connected to a second node, and a second electrode of the driving transistor is electrically connected to a third node, and the first light emitting control module is electrically connected to the third node and the light emitting element. The display panel comprises a first mode, in the first mode, a working period of the pixel driving circuit comprises a data write stage and at least one data maintaining stage after the data write stage, the data write stage comprises at least one first light emitting period, and the data maintaining stage comprises at least one second light emitting period. The first light emitting control module is turned on during the first light emitting period and the second light emitting period. The driving method comprises: controlling a time length of a first first light emitting period in the data write stage to be less than a time length of at least one second light emitting period; the time length of the first first light emitting period in the data write stage is B01; the working period of the pixel driving circuit comprises n data maintaining stages, the data maintaining stage comprises m second light emitting periods, a time length of a jth second light emitting period of an ith data maintaining stage is Bij, i and j are integers, and 1≤i≤n and 1≤j≤m; the display panel comprises a plurality of pixel driving circuit row groups and a plurality of cascaded light emitting control units, each pixel driving circuit row group comprises N pixel driving circuit rows, each pixel driving circuit row comprises a plurality of pixel driving circuits, the first light emitting control modules in the same pixel driving circuit row group are electrically connected to the same light emitting control unit, and N is an integer greater than or equal to 1; the method for controlling the time length of the first first light emitting period in the data write stage to be less than the time length of at least one second light emitting period comprises: B01=Bij-kNH, wherein k is an integer greater than or equal to 1, and H is a row scanning time of one pixel driving circuit row.

11. The driving method according to claim 10, wherein The driving method further comprises: controlling Bi1≤Bi2≤……≤Bim.

12. The driving method according to claim 10, wherein The driving method further comprises: controlling B1j≤B2j≤……≤Bnj.

13. The driving method of claim 10, wherein the driving method further comprises: n≥2； at least one of the n data maintaining stages comprises an (i-1)th data maintaining stage and an ith data maintaining stage which are arranged adjacently, wherein a length of an mth second light emitting period in the (i-1)th data maintaining stage is less than or equal to a length of a first second light emitting period in the ith data maintaining stage.

14. The driving method of claim 10, wherein the pixel driving circuit further comprises a regulating module electrically connected to the second node; the data writing stage further comprises a data writing period before the first light emitting period; the data maintaining stage further comprises a regulating period before the second light emitting period; the driving method comprises: in the data writing period, controlling the regulating module to provide a data signal to the second node; in the regulating period, controlling the regulating module to provide a bias regulating signal to the second node. A display panel comprising any one of claims 1-9. ​ 15. A display device comprising: ​

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