A power supply detection reset circuit, integrated circuit and electronic device

Abstract

The application provides a power supply detection reset circuit, which comprises a first detection module configured to detect a first power supply voltage and a second power supply voltage, and output a first reset control signal based on the first power supply voltage and the second power supply voltage; a second detection module configured to detect the first power supply voltage, and output a second reset control signal based on the first power supply voltage; and a processing module configured to operate the first reset control signal and the second reset control signal to obtain a target reset control signal, which is used to control circuit reset. In a multi-power domain system, the user can flexibly configure according to actual application requirements, and the multi-power domain system can support power-on in any sequence.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a power supply detection and reset circuit, integrated circuit, and electronic equipment. Background Technology

[0002] For integrated circuits, the power-on reset module is a crucial component. When the power supply voltage is too low, the internal analog modules of the chip may fail to operate stably, and the digital circuits may also malfunction, leading to system crashes. The power-on reset module sends a reset signal to each module when the power supply voltage drops below the voltage required for normal system operation. Once the power supply returns to the desired value, the module then de-resets. Simultaneously, when the power supply voltage drops to the system's minimum stable operating voltage, the power-on reset module also generates a reset signal to disable the enable bits of the relevant modules.

[0003] In many system applications, power domain systems are mostly divided into single-power-supply systems and multi-power-supply systems. In single-power-supply systems, the power-on reset module does not need to be designed to be very complex; most systems only require a self-test module to meet the system requirements. However, in multi-power-supply systems, a fixed power-on sequence is required, which restricts user operation and affects the user experience. Summary of the Invention

[0004] Based on this, the present invention provides a power detection and reset circuit, an integrated circuit, and an electronic device, which solves the problem that users are limited by the need to restrict the power-on sequence when multiple power supplies are powered on.

[0005] The technical solution of the present invention is as follows:

[0006] This invention provides a power detection and reset circuit, comprising:

[0007] The first detection module is configured to detect a first power supply voltage and a second power supply voltage, and output a first reset control signal based on the first power supply voltage and the second power supply voltage.

[0008] The second detection module is configured to detect the first power supply voltage and output a second reset control signal based on the first power supply voltage.

[0009] The processing module is configured to perform calculations on the first reset control signal and the second reset control signal to obtain a target reset control signal, which is used to control the circuit to reset.

[0010] In some embodiments, the first detection module is specifically configured as follows:

[0011] When the first power supply and the second power supply are powered on, if the voltage of the second power supply does not reach the preset threshold of the first detection module, the first reset control signal output by the first detection module follows the voltage of the first power supply and the first reset control signal is at a first level; if the voltage of the second power supply reaches the preset threshold of the first detection module, the first reset control signal output by the first detection module is at a second level.

[0012] In some embodiments, the second detection module is specifically configured as follows:

[0013] When the first power supply voltage does not reach the preset threshold of the second detection module, the second reset control signal follows the first power supply voltage and the second reset control signal is at the third level; when the first power supply voltage reaches the preset threshold of the second detection module, the second reset control signal is at the fourth level.

[0014] In some embodiments, the power detection and reset circuit further includes a first logic control unit, the input terminal of which is used to receive a first input signal and a second input signal, wherein the second input signal is the first reset control signal; the first logic control unit is configured to:

[0015] When the first input signal is set to a low level, the first logic control unit outputs a high level to control the second detection module to work, and the second detection module is normally open;

[0016] When the first input signal is set to a high level, the first logic control unit is controlled by the first reset signal to output a signal that can control the operation of the second detection module; when the second power supply voltage does not reach the preset threshold of the first detection module, the second detection module is turned on; when the second power supply voltage reaches the preset threshold of the first detection module, the second detection module is turned off.

[0017] In some embodiments, the power detection and reset circuit further includes:

[0018] The voltage monitoring unit is configured to monitor whether the first reset control signal and the second reset control signal follow the first power supply voltage before the first power supply and the second power supply are powered on; if the first reset control signal and the second reset control signal do not follow the first power supply voltage, the voltage monitoring unit generates the first power supply voltage following signal and transmits it to the processing module.

[0019] In some embodiments, the power detection and reset circuit further includes:

[0020] The second logic control unit is configured to perform level conversion on the target reset control signal and output a second target reset control signal, which is used to control the circuit reset.

[0021] In some embodiments, the power detection and reset circuit further includes:

[0022] The delay unit is configured to delay the transmission of the target reset control signal output by the processing module to the second logic control unit.

[0023] In some embodiments, the power detection and reset circuit further includes:

[0024] The battery power detection module is configured to detect a third power supply voltage, output a third reset control signal based on the third power supply voltage, and transmit the third reset control signal to the second logic control unit for level conversion.

[0025] In some embodiments, the battery power detection module is further configured to:

[0026] When the third power supply voltage does not reach the preset threshold of the battery power detection module, the third reset control signal of the fifth level is output.

[0027] When the third power supply voltage reaches the preset threshold of the battery power detection module, the third reset control signal of the sixth level is output.

[0028] The third reset control signal is used to control the circuit reset.

[0029] In some embodiments, the power detection and reset circuit further includes:

[0030] A programmable voltage detection module, wherein the programmable voltage detection module programs and controls the power-off threshold of the first detection module.

[0031] In some embodiments, the programmable voltage detection module is integrated with the first detection module.

[0032] In some embodiments, the first detection module includes a first power interface, a second power interface, a first resistor string, a first circuit connection control module, a first comparison module, and a first capacitor. The first power interface is used to connect to a first power source, the second power interface is used to connect to a second power source, the first resistor string is connected to the first power interface and the second power interface, the first circuit connection control module is connected to the first resistor string, the first comparison module is connected to the first circuit connection control module, and the first capacitor is connected between the first circuit connection control module and the first comparison module. The first comparison module outputs the first reset control signal.

[0033] In some embodiments, the second detection module includes a second resistor string, a second circuit connection control module, a second comparison module, and a second capacitor. The second resistor string is connected to the first comparison module, the second circuit connection control module is connected to the second resistor string, the second comparison module is connected to the second circuit connection control module, the second capacitor is connected between the second circuit connection control module and the second comparison module, and the second comparison module outputs the second reset control signal.

[0034] In some embodiments, the programmable voltage detection module includes a third resistor string, a threshold level selection module, a third comparison module, and a third capacitor. The third resistor string is connected to the first resistor string, the threshold level selection module is connected to the third resistor string, the third comparison module is connected to the threshold level selection module, and the third capacitor is connected between the threshold level selection module and the third comparison module. The third comparison module outputs a programmable control signal for the power-down threshold of the first detection module.

[0035] In some embodiments, the second logic control unit includes: a first logic NOT gate module, a level conversion module, a leakage protection module, and a second logic NOT gate module;

[0036] The first NOT gate module is connected to the delay unit, the level conversion module is connected to the first NOT gate module, the leakage protection module is connected to the level conversion module, the second NOT gate module is connected to the leakage protection module, and the second NOT gate module outputs a second target reset control signal and a third target reset control signal.

[0037] The present invention provides an integrated circuit including the power detection and reset circuit described above.

[0038] The present invention provides an electronic device, including a device body and an integrated circuit as described above disposed within the device body.

[0039] The power detection and reset circuit, integrated circuit, and electronic device provided by this invention enable users to flexibly configure the system according to actual application needs in a multi-power domain system, thereby supporting power-on in any sequence of power domains. Furthermore, based on actual application needs, the first logic control unit can control the second detection module to turn on or off, reducing system power consumption. Simultaneously, the programmable voltage detection module circuit supports programmable control of the power-down threshold of the first detection module. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A power detection and reset circuit block diagram provided in the first embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a power supply detection and reset circuit structure provided in the first embodiment of the present invention;

[0043] Figure 3 for Figure 1 A circuit diagram of the first detection module in the middle;

[0044] Figure 4 for Figure 1 A circuit diagram of the second detection module;

[0045] Figure 5 A power detection and reset circuit block diagram provided in the second embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a power detection and reset circuit structure provided in the second embodiment of the present invention;

[0047] Figure 7 for Figure 5 A schematic diagram of the logic function of the first logic control unit in the middle;

[0048] Figure 8 A power detection and reset circuit block diagram provided in an embodiment of the present invention;

[0049] Figure 9 This is a schematic diagram of a power detection and reset circuit structure provided in an embodiment of the present invention;

[0050] Figure 10 for Figure 8 A schematic diagram of the logic function of a medium voltage monitoring unit;

[0051] Figure 11 A power detection and reset circuit block diagram provided in an embodiment of the present invention;

[0052] Figure 12 This is a schematic diagram of a power detection and reset circuit structure provided in an embodiment of the present invention;

[0053] Figure 13 for Figure 11 A circuit diagram of the second logic control unit in the middle;

[0054] Figure 14 A power detection and reset circuit block diagram provided in an embodiment of the present invention;

[0055] Figure 15 This is a schematic diagram of a power detection and reset circuit structure provided in an embodiment of the present invention;

[0056] Figure 16 A power detection and reset circuit block diagram provided in an embodiment of the present invention;

[0057] Figure 17 This is a schematic diagram of a power detection and reset circuit structure provided in an embodiment of the present invention;

[0058] Figure 18 A power detection and reset circuit block diagram provided in an embodiment of the present invention;

[0059] Figure 19 This is a schematic diagram of a power detection and reset circuit structure provided in an embodiment of the present invention;

[0060] Figure 20 A circuit diagram showing the integration of the programmable voltage detection module PVD and the first detection module POR.

[0061] Figure 21 Schematic diagram of the power-on reset logic for the first power supply AVDD;

[0062] Figure 22 A schematic diagram of the power-on reset logic for DVDD using the second power supply voltage.

[0063] Figure 23 A schematic diagram of an integrated circuit provided in an embodiment of the present invention;

[0064] Figure 24 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0066] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention.

[0068] It should be noted that in the following description, the use of suffixes such as "module," "part," or "unit" to indicate elements is solely for the purpose of illustrative purposes and has no specific meaning in itself.

[0069] A power detection and reset circuit block diagram provided in the first embodiment of the present invention is shown below. Figure 1 As shown in the figure, a schematic diagram of a power detection and reset circuit structure provided in the first embodiment is shown below. Figure 2 As shown, the power detection and reset circuit includes:

[0070] The first detection module POR is configured to detect the first power supply voltage AVDD and the second power supply voltage DVDD, and output a first reset control signal por_rstf based on the first power supply voltage AVDD and the second power supply voltage DVDD.

[0071] As an example, a circuit diagram of the first detection module POR is shown below. Figure 3As shown, it includes a first power interface, a second power interface, a first resistor string, a first circuit connection control module, a first comparison module, and a first capacitor. The first power interface is used to receive a first power supply voltage AVDD, and the second power interface is used to receive a second power supply voltage DVDD. The first resistor string includes a first resistor R11, a second resistor R12, and a third resistor R13. The first circuit connection control module includes a switch S11 and a switch S12. One end of the first resistor R11 is used to receive the second power supply voltage DVDD, and the other end of the first resistor R11 is grounded through the second resistor R12 and the third resistor R13 connected in series. Switch S11 is connected at one end between the first resistor R11 and the second resistor R12, and at the other end to the first input terminal of the first comparator module. Switch S12 is connected at one end between the second resistor R12 and the third resistor R13, and at the other end to the first input terminal of the first comparator module. The second input terminal of the first comparator module is used to receive the first reference voltage VBG1. The first comparator module is used to detect the voltage at the connection node of the first resistor R11 and the second resistor R12 and compare it with the first reference voltage VBG1, or to detect the voltage at the connection node of the second resistor R12 and the third resistor R13 and compare it with the first reference voltage VBG1. During the second power supply power-on process, the voltage at the first input terminal of the first comparator module rises with the second power supply voltage DVDD. When the voltage at the first input terminal of the first comparator module is greater than or equal to the first reference voltage, the first reset control signal por_rstf output by the first comparator module can be flipped, for example, from the first level to the second level. One end of the first capacitor is connected between switches S11 and S12 and the first comparator module, and the other end of the first capacitor is grounded. The first comparator module is also connected to the first power supply to use the first power supply voltage AVDD as the supply voltage. Optionally, the number of resistors in the first resistor string can be increased or decreased, and correspondingly, the number of switches in the first circuit connection control module can also be increased or decreased. The connection nodes between each pair of adjacent resistors in the first resistor string can be connected to the first input terminal of the first comparator module via switches. It is understood that in this example, the connection relationships of the components can be direct or indirect. For example, one end of the first resistor string can be directly connected to the second power interface or indirectly connected to the second power interface through other components, and the other end of the first resistor string can be directly grounded or indirectly grounded through other components.

[0072] The second detection module PDR is configured to detect the first power supply voltage AVDD and output a second reset control signal pdr_rstf based on the first power supply voltage AVDD. As an example, a circuit diagram of the second detection module PDR is shown below. Figure 4As shown, it includes a second resistor string, a second circuit connection control module, a second comparison module, and a second capacitor. The second resistor string includes a fourth resistor R21, a fifth resistor R22, and a sixth resistor R23. The second circuit connection control module includes a switch S21 and a switch S22. One end of the fourth resistor R21 is used to receive the first power supply voltage AVDD. The fifth resistor R22 is connected to the fourth resistor R21. The sixth resistor R23 is connected to the fifth resistor R22 and is grounded. One end of the switch S21 is connected between the fourth resistor R21 and the fifth resistor R22, and the other end is connected to the first input terminal of the second comparison module. One end of the switch S22 is connected between the fifth resistor R22 and the sixth resistor R23, and the other end is connected to the first input terminal of the second comparison module. The second input terminal of the second comparison module is used to receive the second reference voltage VBG2. The second comparison module is used to detect the voltage at the connection node of the fourth resistor R21 and the fifth resistor R22 and compare it with the second reference voltage VBG2, or detect the voltage at the connection node of the fifth resistor R22 and the sixth resistor R23 and compare it with the second reference voltage VBG2. During the power-on process of the first power supply, the voltage at the first input terminal of the second comparator module rises with the first power supply voltage AVDD. When the voltage at the first input terminal of the second comparator module is greater than or equal to the second reference voltage, the second reset control signal por_rstf output by the second comparator module can be flipped, for example, from the third level to the fourth level. One end of the first capacitor is connected between switches S21 and S22 and the second comparator, and the other end of the second capacitor is grounded. Optionally, the number of resistors in the second resistor string can be increased or decreased, and correspondingly, the number of switches in the second circuit connection control module can also be increased or decreased. The connection nodes between each pair of adjacent resistors in the second resistor string can be connected to the first input terminal of the second comparator module via switches. It can be understood that in this example, the connection relationship of each component can be direct or indirect. For example, one end of the second resistor string can be directly connected to the first power interface or indirectly connected to the first power interface through other components, and the other end of the second resistor string can be directly grounded or indirectly grounded through other components.

[0073] The processing module is configured to perform calculations on the first reset control signal por_rstf and the second reset control signal pdr_rstf to obtain a target reset control signal power_rstf, which is used to control the circuit reset.

[0074] In one implementation, the first reset control signal por_rstf and the second reset control signal pdr_rstf are NAND-NOT processed, and then the NAND-processed signals are NOT-processed to obtain the target reset signal power_rstf of the control circuit.

[0075] In some embodiments, the first detection module POR is configured such that: when the first power supply and the second power supply are powered on, if the voltage of the second power supply does not reach a preset threshold of the first detection module, the first reset control signal output by the first detection module follows the voltage of the first power supply, and the first reset control signal is at a first level; when the voltage of the second power supply reaches the preset threshold of the first detection module, the first reset control signal output by the first detection module is at a second level. Specifically, taking a first level as low and a second level as high as an example, combined with... Figure 3 When the first and second power supplies are powered on, switch S11 is open and switch S12 is closed. When the voltage of the second power supply (DVDD) does not reach the preset threshold of the first detection module (POR), the voltage at the first input terminal of comparator COM0 in the first comparison module is less than the first reference voltage (VBG1). The first reset control signal por_rstf output by the first detection module (POR) follows the voltage of the first power supply (AVDD). At this time, the first reset control signal por_rstf is high, and the circuit is in a power-on reset state. When the voltage of the second power supply (DVDD) reaches the preset threshold of the first detection module (POR), that is, when the voltage at the first input terminal of comparator COM0 reaches the first reference voltage (VBG1), the first reset control signal por_rstf output by comparator COM0 flips to a low level, the power-on reset is released, and the circuit begins to enter the working state. Control switch S11 is closed and switch S12 is open, so that the voltage at the first input terminal of comparator COM0 remains greater than the first reference voltage (VBG1), thereby keeping the circuit in a normal working state.

[0076] In some embodiments, the second detection module PDR is configured such that: when the first power supply voltage does not reach a preset threshold of the second detection module, the second reset control signal follows the first power supply voltage and is at a third level; when the first power supply voltage reaches the preset threshold of the second detection module, the second reset control signal is at a fourth level. Specifically, taking a third level as high and a fourth level as low as an example, combined with... Figure 4When the first power supply is powered on, switch S21 is open and switch S22 is closed. When the first power supply voltage AVDD does not reach the preset threshold of the second detection module PDR, the voltage at the first input terminal of comparator COM1 in the second comparison module is less than the second reference voltage VBG2. The second reset control signal pdr_rstf follows the first power supply voltage AVDD and is at a high level, indicating that the circuit is in a power-on reset state. When the first power supply voltage AVDD reaches the preset threshold of the second detection module PDR, i.e., when the voltage at the first input terminal of comparator COM1 reaches the second reference voltage VBG2, the second reset control signal pdr_rstf output by comparator COM1 flips to a low level, the power-on reset is released, and the circuit begins to enter the working state. Control switch S21 is closed and switch S22 is open, ensuring that the voltage at the first input terminal of comparator COM1 remains greater than the second reference voltage VBG2, thereby maintaining the circuit in a normal working state.

[0077] If the first power supply AVDD is powered on first, followed by the second power supply DVDD, or if both AVDD and DVDD are powered on simultaneously, then until the first power supply AVDD powers on and before the second detection module PDR resets and releases a preset threshold, the second reset control signal pdr_rstf follows the first power supply AVDD, and outputs a low level after reaching the threshold. Similarly, when the second power supply DVDD powers on and before the first detection module POR resets and releases a threshold, the first reset control signal por_rstf follows the first power supply AVDD, and outputs a low level after reaching the threshold. The first reset control signal por_rstf and the second reset control signal pdr_rstf are processed by OR logic to generate a target reset control signal power_rstf for resetting the control circuit. The target reset control signal power_rstf is used to reset the circuits in the AVDD and DVDD power domains.

[0078] If the second power supply DVDD powers on first, followed by the first power supply AVDD, the first reset control signal por_rstf will remain low. Before the first power supply AVDD completes its power-on process, the second reset control signal pdr_rstf follows the first power supply AVDD. After the first power supply AVDD completes its power-on process, the second reset control signal pdr_rstf outputs a low level. The first reset control signal por_rstf and the second reset control signal pdr_rstf are processed by an OR logic to generate the target reset control signal power_rstf for resetting the circuit. The target reset control signal power_rstf is used to reset the circuit.

[0079] Therefore, embodiments of this application can support powering on the first power supply and the second power supply in any order.

[0080] In one alternative implementation, such as Figure 5 The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 6 The image shown is related to Figure 5 A schematic diagram of a corresponding power detection and reset circuit structure is provided. The power detection and reset circuit further includes a first logic control unit Logic1. The input terminal of the first logic control unit Logic1 is used to receive a first input signal pdr_enb and a second input signal, wherein the second input signal is the first reset control signal por_rstf; it is configured to control the second detection module PDR to turn on or off, including:

[0081] When the first input signal pdr_enb is set to low level, the first logic control unit Logic1 outputs a high level to control the second detection module PDR to work, and the second detection module is normally open;

[0082] When the first input signal pdr_enb is set to a high level, the first logic control unit Logic1 outputs a signal to control the operation of the second detection module PDR according to the first reset signal por_rstf; when the second power supply voltage DVDD does not reach the preset threshold of the first detection module POR, the second detection module PDR is turned on; when the second power supply voltage DVDD reaches the preset threshold of the first detection module POR, the second detection module PDR is turned off.

[0083] like Figure 7 The diagram shows the logic function of the first logic control unit Logic1. If the first power supply AVDD is powered on first and the second power supply DVDD is powered on later, or if the first power supply AVDD and the second power supply DVDD are powered on simultaneously, then the first input signal pdr_enb of the first logic control unit Logic1 is set to a high level, and the signal pdr_en of the second detection module PDR follows the first reset control signal por_rstf. When the second power supply voltage DVDD does not reach the preset threshold of the first detection module POR, the second detection module PDR is turned on. When the second power supply voltage DVDD reaches the preset threshold of the first detection module POR, the second detection module PDR is turned off to reduce power consumption.

[0084] If the second power supply DVDD is powered on first and the first power supply AVDD is powered on later, then the first input signal pdr_enb of the first logic control unit Logic1 is set to a low level, and the signal pdr_en of the second detection module PDR is set to a high level, so that the second detection module PDR is in a normally open state.

[0085] In one alternative implementation, such as Figure 8 The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 9 The diagram shows a power supply detection and reset circuit, which further includes:

[0086] The voltage monitoring unit Monitor is configured to monitor whether the first reset control signal por_rstf and the second reset control signal pdr_rstf follow the first power supply voltage AVDD before the first power supply AVDD and the second power supply DVDD are powered on; if the first reset control signal por_rstf and the second reset control signal pdr_rstf do not follow the first power supply voltage AVDD, the voltage monitoring unit Monitor generates a first power supply voltage following signal avdd_monitor and transmits it to the processing module.

[0087] The first reset control signal por_rstf and the second reset control signal pdr_rstf can be processed by NAND gate first, and then by NOT gate.

[0088] like Figure 10 The diagram shows the logic function of the voltage monitoring unit Monitor. The Monitor monitors whether the first reset control signal por_rstf and the second reset control signal pdr_rstf follow the first power supply voltage AVDD. Before the first power supply AVDD and the second power supply DVDD are powered on, and before the first detection module POR and the second detection module PDR are reset and released, i.e., before... Figure 10Before t1, the output signals of the first detection module POR and the second detection PDR should theoretically follow the first power supply voltage AVDD. However, in practice, the first power supply voltage AVDD and the second power supply voltage DVDD may reach the voltage required for normal system operation, but the output signals of the first detection module POR and the second detection PDR may remain at a low level. In this case, the system may experience three processes: reset release → reset → reset release. Before the first power supply AVDD and the second power supply DVDD are fully powered on, if the voltage monitoring unit Monitor detects that the first reset control signal por_rstf and the second reset control signal pdr_rstf do not follow the first power supply voltage AVDD, then the voltage monitoring unit Monitor will output a first power supply voltage AVDD following signal avdd_monitor that almost completely follows the first power supply voltage AVDD, thus avoiding the possible three processes of reset release → reset → reset release in the system.

[0089] In one alternative implementation, such as Figure 11 The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 12 The diagram shows a power supply detection and reset circuit, which further includes:

[0090] The second logic control unit Logic2 is configured to perform level conversion on the target reset control signal power_rstf and output a second target reset control signal dvdd_rstf. The second target reset control signal dvdd_rstf is used to reset the circuits in the AVDD power domain and the DVDD power domain.

[0091] Furthermore, such as Figure 13 As shown, the preferred second logic control unit Logic2 includes: a first logic NOT gate module, a level conversion module, a leakage protection module, and a second logic NOT gate module.

[0092] In some examples, the first NOT gate module includes a first NOT gate 1, a second NOT gate 2, a third NOT gate 3, and a fourth NOT gate 4; the leakage protection module includes NMOS transistors M1, M2, M4, M5, M8, M9, M13, M14, and M15; and PMOS transistors M3, M6, M7, M11, M12, and M16; the second NOT gate module includes a fifth NOT gate 5 and a sixth NOT gate 6.

[0093] The input of the first NOT gate 1 is the target reset signal power_rstf, and the output is connected to the second NOT gate 2, the gate of the NMOS transistor M1, the gate of the NMOS transistor M4, and the gate of the PMOS transistor M7.

[0094] The output of the second NOT gate 2 is connected to the first level conversion module 7;

[0095] The output terminal of the first level conversion module 7 is connected to the gate of the NMOS transistor M2 and the gate of the PMOS transistor M3;

[0096] The source of NMOS transistor M1 and the source of NMOS transistor M4 are grounded; the drain of PMOS transistor M7 is connected to the input of the fifth logic NOT gate 5.

[0097] The drain of the NMOS transistor M2 and the drain of the PMOS transistor M3 are connected to the gate of the PMOS transistor M6 and the gate of the NMOS transistor M5.

[0098] The source of the NMOS transistor M2 is connected to the drain of the NMOS transistor M1;

[0099] The drain of the NMOS transistor M5 and the drain of the PMOS transistor M6 are connected to the fifth logic NOT gate 5;

[0100] The source of the NMOS transistor M5 is connected to the drain of the NMOS transistor M4;

[0101] The source terminals of PMOS transistor M3, PMOS transistor M6, and PMOS transistor M7 are interconnected.

[0102] The output of the fifth NOT gate 5 is the second target reset control signal avdd_rstf;

[0103] The input of the third NOT gate 3 is the target reset signal power_rstf, and the output is connected to the fourth NOT gate 4, the gate of the NMOS transistor M8, the gate of the NMOS transistor M15, and the gate of the PMOS transistor M16.

[0104] The output of the fourth NOT gate 4 is connected to the second level conversion module 8;

[0105] The output terminal of the second level conversion module 8 is connected to the gate of the NMOS transistor M9 and the gate of the PMOS transistor M10;

[0106] The source of the NMOS transistor M8 and the source of the NMOS transistor M15 are grounded;

[0107] The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M8;

[0108] The drain of the NMOS transistor M9 is connected to the drain of the PMOS transistor M10;

[0109] The drain of the NMOS transistor M9 and the drain of the PMOS transistor M10 are connected to the gate of the PMOS transistor M11 and the gate of the NMOS transistor M14.

[0110] The drain of the PMOS transistor M11 is connected to the input terminal of the sixth logic NOT gate 6;

[0111] The source of the NMOS transistor M14 is connected to the drain of the NMOS transistor M15;

[0112] The drain of the PMOS transistor M16 is connected to the input of the sixth logic NOT gate 6;

[0113] The source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14;

[0114] The input terminals of both the PMOS transistor M12 and the NMOS transistor M13 are the third reset control signal;

[0115] The drain of the PMOS transistor M12 is connected to the drain of the NMOS transistor M13;

[0116] The source terminals of PMOS transistors M10, M11, M12, and M16 are interconnected.

[0117] The output of the sixth NOT gate 6 is the third target reset control signal.

[0118] If the first power supply AVDD is powered on first, followed by the second power supply DVDD, or if both AVDD and DVDD are powered on simultaneously, and the first input signal pdr_enb of the first logic control unit Logic1 is set to a high level, then before the target reset signal power_rstf is released, the signal S1 output by the first NOT gate 1 is low, and the signal S3 output by the third NOT gate 3 is low, controlling NMOS transistors M1, M4, M8, and M15 to turn off and weakly pulled-up PMOS transistors M7 and M16 to turn on, keeping the second target reset control signal dvdd_rstf low. Then, after the target reset signal power_rstf is released, the second target reset control signal dvdd_rstf follows the voltage of the second power supply DVDD.

[0119] If the second power supply DVDD is powered on first, followed by the first power supply AVDD, and the first input signal pdr_enb of the first logic control unit Logic1 is set to a low level, then before the first power supply AVDD is powered on, the signals S1, S2, S3, and S4 output by the first NOT gate 1, the second NOT gate 2, the third NOT gate 3, and the fourth NOT gate 4 are all at a low level. This controls NMOS transistors M1, M4, M8, and M15 to turn off and weakly pull-up PMOS transistors M7 and M16 to turn on, preventing excessive leakage current in the second logic control unit Logic2 due to the floating outputs of the first level conversion module 7 and the second level conversion module 8. The second target reset control signal dvdd_rstf remains at a low level. Then, when the target reset signal power_rstf is released, the signals S1 and S3 output by the first NOT gate 1 and the third NOT gate 3 are pulled up to a high level, controlling NMOS transistors M1, M4, M8, and M15 to turn on, and the second target reset control signal dvdd_rstf outputs a high level.

[0120] In an optional embodiment, such as Figure 14 The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 15 The diagram shows a power supply detection and reset circuit, which further includes:

[0121] The delay unit `Delay` is configured to delay the target reset control signal `power_rstf` from the processing module, and then transmit the delayed target reset control signal `power_rstf` to the second logic control unit `Logic2`. The delay unit `Delay` ensures that the power supply voltage has reached a relatively high level when the target reset control signal `power_rstf` is transmitted to each module of the system, allowing for normal operation. Optionally, the delay time of the delay unit can be several milliseconds. As an example, the delay time can be 3 milliseconds.

[0122] In one alternative implementation, such as Figure 16 The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 17 The diagram shows a power supply detection and reset circuit, which further includes:

[0123] The battery power detection module VBAT_POR is configured to detect the voltage of the third power supply VBAT and output a third reset control signal vbat_rstn based on the voltage of the third power supply VBAT. The third reset control signal vbat_rstn is then transmitted to the second logic control unit Logic2 for level conversion. The level-converted third reset control signal is vbat_rstf, which is used to control the circuit of the VBAT power domain.

[0124] The third reset control signal vbat_rstn, based on the voltage of the third power supply VBAT, includes:

[0125] When the voltage of the third power supply VBAT does not reach the preset threshold of the battery power detection module VBAT_POR, the third reset control signal vbat_rstn is high, and the power-on reset is released.

[0126] When the voltage of the third power supply VBAT reaches the preset threshold of the battery power detection module VBAT_POR, the third reset control signal vbat_rstn goes low, and a power-on reset occurs.

[0127] The third reset control signal vbat_rstn is input to the gates of the PMOS transistor M12 and the NMOS transistor M13, and the sixth logic NOT gate outputs the third target reset control signal vbat_rstf.

[0128] If the first power supply AVDD is powered on first and the second power supply DVDD is powered on later, or if the first power supply AVDD and the second power supply DVDD are powered on simultaneously, the first input signal pdr_enb of the first logic control unit Logic1 is set to a high level. When the third power supply VBAT is powered on before the second power supply DVDD, the PMOS transistor M12 is turned on before the target reset signal power_rstf is released. The signal L4 output by the PMOS transistors M11 and M16 follows the voltage of the third power supply VBAT, and the third target reset control signal vbat_rstf remains at a low level. When the first power supply AVDD and the power supply DVDD are both powered on and have completed their reset release, the NMOS transistors M8 and M15 are turned on, and the third target reset control signal vbat_rstf is pulled up to a high level. When the third power supply VBAT is powered on after the second power supply DVDD, the NMOS transistors M8 and M15 are already turned on before the third reset control signal vbat_rstn is released. The second level conversion module 8 outputs a low level, and the signal L3 output by the NMOS transistor M9 and the PMOS transistor M10 is pulled up to a high level. The NMOS transistor M14 is turned on, and the third reset control signal vbat_rstn output by the battery power detection module VBAT_POR can be directly transmitted.

[0129] If the second power supply DVDD is powered on first and the first power supply AVDD is powered on later, the first input signal pdr_enb of the first logic control unit Logic1 is set to a low level. When the third power supply VBAT is powered on before the second power supply DVDD, the PMOS transistor M12 is turned on before the target reset signal power_rstf is released. The signal L4 output by the PMOS transistors M11 and M16 follows the voltage of the third power supply VBAT, and the third target reset control signal vbat_rstf remains at a low level. When the first power supply AVDD and the power supply DVDD are both powered on and have completed their reset release, the NMOS transistors M8 and M15 are turned on, and the third target reset control signal vbat_rstf is pulled up to a high level. When the third power supply VBAT is powered on after the second power supply DVDD, the NMOS transistors M8 and M15 are already turned on before the third reset control signal vbat_rstn is released. The second level conversion module 8 outputs a low level, and the signal L3 output by the NMOS transistor M9 and the PMOS transistor M10 is pulled up to a high level. The NMOS transistor M14 is turned on, and the third reset control signal vbat_rstn output by the battery power detection module VBAT_POR can be directly transmitted.

[0130] In an optional embodiment, such as Figure 18The diagram shown is a block diagram of a power supply detection and reset circuit. Figure 19 The diagram shows a power supply detection and reset circuit, which further includes:

[0131] A programmable voltage detection module (PVD) is provided, which programs and controls the power-down threshold of the first detection module (POR).

[0132] Furthermore, the programmable voltage detection module PVD is integrated with the first detection module POR.

[0133] like Figure 20 The diagram shows a circuit diagram integrating the programmable voltage detection module (PVD) and the first detection module (POR). The programmable voltage detection module (PVD) includes a third resistor string, a threshold level selection module, a third comparison module, and a third capacitor. The third resistor string is connected to the first resistor string, the threshold level selection module is connected to the third resistor string, the third comparison module is connected to the threshold level selection module, and the third capacitor is connected between the threshold level selection module and the third comparison module. The third comparison module outputs a programmable control signal for the power-down threshold of the first detection module. The third resistor string includes multiple resistors connected in series, with each connection node between two adjacent resistors forming a voltage divider node; that is, the third resistor string includes one or more voltage divider nodes. In this embodiment, the threshold level selection module is selected as a selector. The selector is connected to different voltage divider nodes in the third resistor string to select the corresponding threshold. The user can select a threshold as the power-down threshold for the first detection module according to actual needs.

[0134] like Figure 21 The diagram shown illustrates the power-on reset logic of the first power supply AVDD. Figure 22 The diagram shown is a schematic of the second power supply voltage DVDD power-on reset logic.

[0135] like Figure 23 As shown in the figure, an embodiment of the present invention also provides a schematic diagram of an integrated circuit 200, which includes the power detection and reset circuit 100 described above.

[0136] The integrated circuit provided in this embodiment of the invention includes a first detection module POR, configured to detect a first power supply voltage AVDD and a second power supply voltage DVDD, and output a first reset control signal por_rstf based on the first power supply voltage AVDD and the second power supply voltage DVDD; a second detection module PDR, configured to detect the first power supply voltage, and output a second reset control signal pdr_rstf based on the first power supply voltage AVDD; and a processing module configured to perform calculations on the first reset control signal por_rstf and the second reset control signal pdr_rstf to obtain a target reset control signal power_rstf, which is used to control circuit reset. In a multi-power-domain system, users can flexibly configure the circuit according to actual application requirements, supporting arbitrary sequential power-on of the multi-power-domain system.

[0137] like Figure 24 As shown in the diagram, this application embodiment also provides a schematic diagram of an electronic device 300, which includes a device body 310 and the aforementioned integrated circuit 200. The integrated circuit 200 is disposed within the device body 310.

[0138] The electronic device provided in this embodiment of the invention includes a first detection module POR, configured to detect a first power supply voltage AVDD and a second power supply voltage DVDD, and output a first reset control signal por_rstf based on the first power supply voltage AVDD and the second power supply voltage DVDD; a second detection module PDR, configured to detect the first power supply voltage, and output a second reset control signal pdr_rstf based on the first power supply voltage AVDD; and a processing module configured to perform calculations on the first reset control signal por_rstf and the second reset control signal pdr_rstf to obtain a target reset control signal power_rstf, which is used to control circuit reset. In a multi-power domain system, users can flexibly configure the device according to actual application needs, supporting arbitrary sequential power-on of the multi-power domain system.

[0139] The above description is merely an embodiment of the present invention. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements all fall within the protection scope of the present invention.

Claims

1. A power supply detection and reset circuit, characterized in that, include The first detection module is configured to detect a first power supply voltage and a second power supply voltage, and output a first reset control signal based on the first power supply voltage and the second power supply voltage. The second detection module is configured to detect the first power supply voltage and output a second reset control signal based on the first power supply voltage. The processing module is configured to perform calculations on the first reset control signal and the second reset control signal to obtain a target reset control signal, which is used to control the circuit to reset. A first logic control unit, wherein the input terminal of the first logic control unit is used to receive a first input signal and a second input signal, wherein the second input signal is the first reset control signal; the first logic control unit is configured to: When the first input signal is set to a low level, the first logic control unit outputs a high level to control the second detection module to work, and the second detection module is normally open; When the first input signal is set to a high level, the first logic control unit outputs a signal to control the operation of the second detection module according to the first reset signal; when the second power supply voltage does not reach the preset threshold of the first detection module, the second detection module is turned on; when the second power supply voltage reaches the preset threshold of the first detection module, the second detection module is turned off.

2. The power supply detection and reset circuit according to claim 1, characterized in that, The first detection module is specifically configured as follows: When the first power supply and the second power supply are powered on, if the voltage of the second power supply does not reach the preset threshold of the first detection module, the first reset control signal output by the first detection module follows the voltage of the first power supply and the first reset control signal is at a first level; if the voltage of the second power supply reaches the preset threshold of the first detection module, the first reset control signal output by the first detection module is at a second level.

3. The power supply detection and reset circuit according to claim 1, characterized in that, The second detection module is specifically configured as follows: When the first power supply voltage does not reach the preset threshold of the second detection module, the second reset control signal follows the first power supply voltage and is at the third level; when the first power supply voltage reaches the preset threshold of the second detection module, the second reset control signal is at the fourth level.

4. The power supply detection and reset circuit according to claim 1, characterized in that, The power detection and reset circuit further includes: The voltage monitoring unit is configured to monitor whether the first reset control signal and the second reset control signal follow the first power supply voltage before the first power supply and the second power supply are powered on; if the first reset control signal and the second reset control signal do not follow the first power supply voltage, the voltage monitoring unit generates the first power supply voltage following signal and transmits it to the processing module.

5. A power supply detection and reset circuit according to claim 4, characterized in that, The power detection and reset circuit further includes: The second logic control unit is configured to perform level conversion on the target reset control signal and output a second target reset control signal, which is used to control the circuit reset.

6. A power supply detection and reset circuit according to claim 5, characterized in that, The power detection and reset circuit further includes: The delay unit is configured to delay the transmission of the target reset control signal output by the processing module to the second logic control unit.

7. A power supply detection and reset circuit according to claim 5, characterized in that, The power detection and reset circuit further includes: The battery power detection module is configured to detect a third power supply voltage, output a third reset control signal based on the third power supply voltage, and transmit the third reset control signal to the second logic control unit for level conversion.

8. A power supply detection and reset circuit according to claim 7, characterized in that, The battery power detection module is also configured to: When the third power supply voltage does not reach the preset threshold of the battery power detection module, the third reset control signal of the fifth level is output. When the third power supply voltage reaches the preset threshold of the battery power detection module, the third reset control signal of the sixth level is output. The third reset control signal is used to control the circuit reset.

9. A power supply detection and reset circuit according to claim 1, characterized in that, The power detection and reset circuit further includes: A programmable voltage detection module, wherein the programmable voltage detection module programs and controls the power-off threshold of the first detection module.

10. A power supply detection and reset circuit according to claim 9, characterized in that, The programmable voltage detection module is integrated with the first detection module.

11. A power supply detection and reset circuit according to claim 1, characterized in that, The power detection and reset circuit includes a first power interface and a second power interface. The first power interface is used to connect to a first power source, and the second power interface is used to connect to a second power source. The first detection module includes a first resistor string, a first circuit connection control module, a first comparison module, and a first capacitor. One end of the first resistor string is connected to the second power interface. The input terminal of the first comparison module is connected to the first resistor string through the first circuit connection control module. One end of the first capacitor is connected between the first circuit connection control module and the first comparison module, and the other end of the first capacitor is grounded. The first comparison module outputs the first reset control signal.

12. A power supply detection and reset circuit according to claim 1, characterized in that, The power detection and reset circuit includes a first power interface, which is used to connect to a first power source. The second detection module includes a second resistor string, a second circuit connection control module, a second comparison module, and a second capacitor. One end of the second resistor string is connected to the first power interface. The second circuit connection control module is connected to the second resistor string. The second comparison module is connected to the second resistor string through the second circuit connection control module. One end of the second capacitor is connected between the second circuit connection control module and the second comparison module, and the other end of the second capacitor is grounded. The second comparison module outputs the second reset control signal.

13. A power supply detection and reset circuit according to claim 9, characterized in that, The programmable voltage detection module includes a third resistor string, a threshold level selection module, a third comparison module, and a third capacitor. The third resistor string is connected to the first resistor string, the threshold level selection module is connected to the third resistor string, the third comparison module is connected to the threshold level selection module, and the third capacitor is connected between the threshold level selection module and the third comparison module. The third comparison module outputs a programming control signal for the threshold of the second detection module.

14. A power supply detection and reset circuit according to claim 8, characterized in that, The second logic control unit includes: a first logic NOT gate module, a level conversion module, a leakage protection module, and a second logic NOT gate module; The first NOT gate module is connected to the delay unit, the level conversion module is connected to the first NOT gate module, the leakage protection module is connected to the level conversion module, the second NOT gate module is connected to the leakage protection module, and the second NOT gate module outputs a second target reset control signal and a third target reset control signal.

15. An integrated circuit, characterized in that, Includes the power detection and reset circuit as described in any one of claims 1 to 14.

16. An electronic device, characterized in that, It includes a device body and an integrated circuit as described in claim 15 disposed within the device body.

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