An asymmetric parasitic calibration segmented capacitance array

Abstract

The application discloses an asymmetric parasitic calibration segmented capacitance array, which comprises a positive end capacitance array and a negative end capacitance array, and the capacitance array comprises sampling capacitance, conversion capacitance, calibration capacitance and compensation capacitance; the sampling capacitance adopts simple switch timing, and gain error caused by high segment parasitic capacitance can be eliminated; the conversion capacitance adopts a segmented capacitance array structure, and the number and area of capacitances are reduced; the calibration capacitance is used for calibrating nonlinearity caused by parasitic capacitance of bridging capacitance and parasitic of LSB array; and the compensation capacitance matches the positive end and negative end capacitance arrays. The calibration circuit and the calibration timing sequence thereof are simple in realization and low in power consumption.

Description

Technical Field

[0001] This invention belongs to the field of segmented capacitor technology, specifically relating to an asymmetric parasitic calibration segmented capacitor array. Background Technology

[0002] With the rapid development of integrated circuits and information digitization, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), serving as bridges between the real and digital worlds, have become important research directions in analog integrated circuits. Compared to other types of ADCs, traditional successive approximation analog-to-digital converters (SAR ADCs) require longer conversion times. However, SAR ADCs are characterized by simple structure, low power consumption, and ease of integration, making them well-suited to the development of microelectronics processes. For high-precision ADCs (resolution greater than 12 bits), the segmented capacitor array of a SAR ADC can significantly reduce the number of capacitors per unit compared to a typical binary capacitor array. However, it is more sensitive to parasitic capacitance, which can cause gain errors and linearity issues during conversion. As resolution increases, parasitic capacitance can severely degrade circuit performance, thus requiring calibration.

[0003] Existing solution: A calibration device and method for the gain error of a SAR-type ADC, publication number CN111181564A, such as... Figure 1 The gain error caused by the parasitic capacitance of the MSB array is calibrated by adding an additional calibration capacitor array, which compensates for the gain error. If the ADC exhibits a positive gain error, the calibration capacitor array should be connected to the positive terminal of the comparator; if the ADC exhibits a negative gain error, the calibration capacitor array should be connected to the negative terminal of the comparator.

[0004] A calibration circuit and calibration method for a bridging capacitor array, publication number CN115622561A, as shown. Figure 2 The linearity of the lowest capacitor in the low-segment capacitor array and the highest-segment capacitor array is calibrated by adjusting the bridging capacitor, parasitic capacitance, and the total capacitance of the low-segment capacitor array.

[0005] Existing technologies cannot fully calibrate the nonlinearity caused by parasitic capacitance in the bridging capacitor and low-side capacitor array, and require complex timing for calibration. The calibration circuit requires a large chip area and consumes a lot of power. Summary of the Invention

[0006] To overcome the problems existing in the prior art, the present invention aims to provide an asymmetric parasitic calibration segmented capacitor array. This capacitor array structure, using a simple timing sequence, can completely eliminate the dynamic range loss caused by gain error due to parasitic capacitance in the upper segment (MSB). For lower segment (LSB) array calibration, the difference between each capacitor weight value and the actual binary weight capacitor value is detected, a weight calibration code is generated, and the LSB array is calibrated, thereby reducing the nonlinearity caused by parasitic capacitance of the bridging capacitors and lower segment parasitic capacitance. The calibration circuit and its calibration timing are simple to implement and have low power consumption.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] An asymmetric parasitic calibration segmented capacitor array includes a positive terminal capacitor array and a negative terminal capacitor array. The positive terminal capacitor array includes a positive terminal sampling capacitor, a positive terminal conversion capacitor array, and a positive terminal compensation capacitor. The negative terminal capacitor array includes a negative terminal sampling capacitor, a negative terminal conversion capacitor array, a positive terminal calibration capacitor array, a negative terminal calibration capacitor array, and a negative terminal compensation capacitor. For an N-bit analog-to-digital converter:

[0009] The positive terminal conversion capacitor array consists of N-1 positive terminal conversion stubs. Each positive terminal conversion stub includes a positive terminal conversion capacitor and a selection switch. One end of each positive terminal conversion stub is connected to OUTN (negative differential output terminal), and the other end is set to 1 or 0 through the selection switch.

[0010] The negative terminal conversion capacitor array consists of N-1 negative terminal conversion stubs. Each negative terminal conversion stub includes a negative terminal conversion capacitor and a selection switch. One end of each negative terminal conversion stub is connected to OUTP (positive differential output terminal), and the other end is set to 1 or 0 through the selection switch.

[0011] The positive terminal calibration capacitor array is composed of several positive terminal calibration branches. Each positive terminal calibration branch includes a positive terminal calibration capacitor and a selection switch. One end of each positive terminal calibration branch is connected to the negative terminal capacitor LSB array, and the other end is set to 1 or 0 through the selection switch.

[0012] The negative terminal calibration capacitor array is composed of several negative terminal calibration branches. Each negative terminal calibration branch includes a negative terminal calibration capacitor and a selection switch. One end of each negative terminal calibration branch is connected to the negative terminal capacitor LSB array, and the other end is set to 1 or 0 through the selection switch.

[0013] One end of the positive sampling capacitor is connected to OUTN, and the other end is connected to the lower plate of Vinp or Cinn through a switch. One end of the negative sampling capacitor is connected to OUTP, and the other end is connected to the lower plate of Vinn or Cinn through a switch.

[0014] The positive terminal compensation capacitor Cp is connected to the OUTN (positive terminal capacitor MSB array) and the 0 terminal to compensate for the capacitance value of the positive terminal MSB array, so that the capacitance values ​​of the positive and negative terminal MSB arrays are equal.

[0015] The negative terminal compensation capacitor (Cn) is connected to the upper plate of the negative terminal capacitor LSB array, and the lower plate is connected to the 0 terminal. It is used to compensate for the capacitance value of the negative terminal LSB array so that the capacitance values ​​of the positive terminal and the negative terminal LSB array are equal.

[0016] The switching capacitor adopts a high M-bit (MSB) and low L-bit (LSB) structure (M+L=N-1);

[0017] The calibration capacitor is used to calibrate the parasitic capacitance caused by the bridging capacitor and the nonlinearity caused by the parasitic LSB array.

[0018] The compensation capacitor matches the capacitor arrays at the positive and negative ends.

[0019] The compensation capacitor includes a compensation capacitor Cp and a compensation capacitor Cn. The compensation capacitor Cp is used to compensate the capacitance value of the positive terminal MSB array, and the compensation capacitor Cn is used to compensate the capacitance value of the negative terminal LSB array. The sampling capacitor Cinp = Cinn.

[0020] In the calibration capacitor, the Kth bit of the calibration code controls the calibration capacitor Cnc. k CPC k Compared to the P-terminal MSB array, an additional unit capacitor Cn is introduced at the high-order bit of the N-terminal. M+1 Used to express the weight of the (M+1)th bit at the N-terminal; capacitor correction arrays P_CAL and N_CAL are added to the N-terminal LSB array.

[0021] In the aforementioned conversion capacitor, for ease of subsequent formula expression, C is a unit capacitance, which is considered as 1 in the following formulas. The sum of the high-segment capacitance at the P and N terminals and the sum of the low-segment capacitance are respectively...

[0022]

[0023]

[0024]

[0025]

[0026] Simultaneously satisfying Cmsb,p=Cmsb,n and Cmsb,p=Cmsb,n.

[0027] When there are high-segment parasitic capacitances Ccp1 and Ccn1, bridging capacitor parasitic capacitances Ccp3 and Ccn3, and low-segment parasitic capacitances Ccp2 and Ccn2, since the number of unit capacitances at the positive and negative terminals is equal, that is, the sum of the unit capacitances of MSB and LSB at the N terminal is equal to the sum of the unit capacitances of MSB and LSB at the P terminal, Ccp1 = Ccn1, Ccp2 = Ccn2, and Ccp3 = Ccn3.

[0028] Total capacitance of the LSB array as viewed from the output node (Cltot,p, Cltot,n)

[0029] Cltot,p=((Clsb,p+Ccp2)*(Csp+Ccp3)) / (Clsb,p+Csp+Ccp3+Ccp2)(5)

[0030] Cltot,n=((Clsb,n+Ccn2)*(Csn+Ccn3)) / (Clsb,n+Csn+Ccn3+Ccn2)(6)

[0031] Taking the weight of the highest bit in the positive LSB array, Weightp(M+1), as an example, the ideal weight of this bit is:

[0032] Weightp_i(M+1)=Cp M+1 *Csp / (Clsb,p+Csp)=1 / 2 (7)

[0033] When Ccp3 and Ccp2 exist, the weight of this bit deviates from the binary representation and changes as follows:

[0034] Weightp(M+1)=Cp M+1 *(Csp+Ccp3) / (Clsb,p+Csp+Ccp3+Ccp2)(8)

[0035] Therefore, weight correction is required.

[0036] The specific method for using the asymmetric parasitic calibration segmented capacitor array to eliminate gain errors caused by high-segment parasitic capacitance is as follows:

[0037] During the sampling phase, the differential inputs are Vinp and Vinn. The sampling switch T1 is closed, and the holding switch T2 is open. The lower plates of the sampling capacitors Cinp and Cinn are sampled, and the upper plate is connected to the common-mode voltage Vcm. The lower plates of the P_CAL capacitor array and the highest-order capacitors Cp1 and Cn1 of MSB are connected to the reference voltage Vrefp, and the remaining capacitors are all connected to the reference voltage Vrefn.

[0038] During the holding phase, sampling switch T1 is open and holding switch T2 is closed, connecting the lower plates of the sampling capacitor. Charge redistribution occurs between the upper and lower plates of the sampling capacitor. Due to the presence of high-segment parasitic capacitances Ccp1 and Ccn1, the parasitic capacitances of the bridging capacitor Ccp3 and Ccn3, and the low-segment parasitic capacitances Ccp2 and Ccn2, the actual total capacitance (Ctota,p, Ctota,n) at this time is:

[0039] Ctota,p=Cinp+Cmsb,p+Ccp1+Cltot,p (9)

[0040] Ctota,n=Cinn+Cmsb,n+Ccn1+Cltot,n (10)

[0041] Since Cinp=Cmsb,p+Ccp1+Cltot,p=Cinn=Cmsb,n+Ccn1+Cltot,n, Cmsb,p=Cmsb,n,Cltot,p=Cltot,n, therefore Ctota,n=Ctota,p.

[0042] According to the law of conservation of charge, the outputs OUTN and OUTP are:

[0043] OUTN=Vcm-β*(Vinp-Vinn) / 2 (11)

[0044] OUTP=Vcm-β*(Vinn-Vinp) / 2 (12)

[0045] OUTP-OUTN=β*(Vinp-Vinn) (13)

[0046] Where β=Cinp / Ctota,p=Cinn / Ctota,n;

[0047] If OUTP - OUTN < 0, the most significant bit is 0. Before the next comparison, the most significant bit capacitor Cp1 is switched to Vrefn. According to charge conservation, OUTN and OUTP are then:

[0048] OUTN=Vcm-β*((Vinp-Vinn) / 2+1.5*Cp1 / Cinp) (14)

[0049] OUTP=Vcm-β*((Vinn-Vinp) / 2+0.5*Cp1 / Cinp) (15)

[0050] OUTP-OUTN=β*(Vinp-Vinn+Cp1 / Cinp) (16)

[0051] In equations (14) and (15), the expressions for OUTN and OUTP both contain Cp1 / Cinp. This is because the lower plates of the two sampling capacitors Cinp and Cinn are connected during the conversion stage, causing the two output nodes OUTP and OUTN to no longer be independent of each other. Switching the highest-order capacitor Cp1 to Vrefn causes the three nodes of output nodes OUTP and OUTN and sampling capacitors Cinp and Cinn to undergo charge redistribution simultaneously. In equation (16), when the input Vinp-Vinn is compared with the conversion weight Cp1 / Cinp, it is not affected by the parasitic capacitors Ccp1 and Ccn1 in the high segment, thus eliminating the loss of dynamic range caused by the gain error brought by the parasitic capacitors Ccp1 and Ccn1 in the high segment.

[0052] The asymmetric parasitic calibration segmented capacitor array is used for the low-end capacitor calibration process:

[0053] During the calibration phase, the inputs at both the P and N terminals are connected to the common-mode voltage Vcm; during the sampling phase, switch T1 is closed and switch T2 is open. The P_CAL capacitor array, Cn, and the lower plates of the highest-order capacitors Cp1 and Cn1 of the MSB are connected to Vrefp, and the remaining capacitors (except for the sampling capacitor) are connected to Vrefn.

[0054] During the holding phase, switch T1 is open and switch T2 is closed. The lower plate of the sampling capacitor is connected to the positive and negative terminals. Therefore, charge redistribution occurs between the upper and lower plates of the sampling capacitor. At this time, OUTP-OUTN=0.

[0055] Switch Cn M+1 Cp M+1 Cp M+2 The capacitor is connected to Vrefp, Cn M+2 With the capacitor connected to Vrefn, the difference between OUTP and OUTN is 0 if there are no parasitic capacitors. Due to the presence of bridging parasitic capacitors Ccp3 and Ccn3, and lower-segment parasitic capacitors Ccp2 and Ccn2, the differential output voltage is:

[0056] OUTP-OUTN=β*(Ccp2-Clsb,p*Ccp3) / (Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2))

[0057] *Vrefp(17)

[0058] The voltage Vlsb_CAL that needs to be calibrated is the voltage represented by formula (17); Vlsb_CAL is reduced by switching the control switches in the P_CAL and N_CAL capacitor arrays in a successive approximation manner.

[0059] The successive approximation method is as follows:

[0060] If Vlsb_CAL > 0, then the highest bit of the calibration code is 1. Before the next comparison, the Cnc1 capacitor in the N_CAL capacitor array is switched to Vrefp. At this time, the differential output voltage becomes:

[0061] Vlsb_CAL=β*(((-Clsb,p*Ccp3+Ccp2)-0.25*Cp M+1 *(Csp+Ccp3)) / (

[0062] Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2)))*Vrefp(18)

[0063] If Vlsb_CAL < 0 at this time, the high-order bit of the calibration code is 0. Before the next comparison, the Cpc2 capacitor in the P_CAL capacitor array is switched to Vrefn. At this time, the differential output voltage becomes:

[0064] Vlsb_CAL=β*(((-Clsb,p*Ccp3+Ccp2)-0.125*Cp M+1 *(Csp+Ccp3) /

[0065] (Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2)))*Vrefp(19)

[0066] As can be seen from equations (17) to (19), Vlsb_CAL gradually decreases, and so on, to obtain the K-bit LSB calibration code D_CAL, at which point Vlsb_CAL is close to 0. The highest bit of D_CAL controls the weight of P_CAL and N_CAL, which is 1 / 4*Cp. M+1 Cpc1 and Cnc1; the second highest control weight is 1 / 8*Cp M+1 Cpc2 and Cnc2; the third control weight is 1 / 16*Cp M+1 Cpc3 and Cnc3; and so on, the Kth bit controls the weight bit 1 / 2^(K+1)*Cp M+1 Cpck and Cnck. The Cpc(k) and Cnc(k) switching control signals in the P_CAL and N_CAL capacitor arrays are complementary.

[0067] After calibration, the normal conversion phase begins. When converting to a lower bit, the obtained calibration code D_CAL is compensated bit by bit to the LSB array at ratios of 1 / 2, 1 / 4, 1 / 8, ..., 1 / 2^L. That is, when switching the effective weight of the LSB, the corresponding voltage value needs to be compensated. The digital code for switching the calibration content of the switching array is obtained by accumulating the comparison results, and is called the weight compensation code. Let b(i) (i = 1, 2, 3, ..., L) represent the comparison results of the (M+1)th to (M+L)th bits, and WN_CAL(i) and WP_CAL(i) represent the switching array control codes of N_CAL and P_CAL for calibrating the capacitor array when switching the lower segment capacitor array.

[0068]

[0069]

[0070] in

[0071] D_CAL(i)=D CAL / 2^i (22)

[0072] To switch the most significant bit Cp of the LSB M+1 Taking Vrefp as an example, if no voltage compensation is performed, the differential output will be:

[0073] OUTP-OUTN=-β*(Cp M+1 *(Csp+Ccp3)) / (Cinp*(Clsb,p+Csp+Ccp3+Ccp2))*Vrefp(23)

[0074] From the K-bit calibration code D_CAL, we can obtain the compensation code WP_CAL(1) = 1 / 2 * D_CAL(1). By switching the corresponding calibration capacitor of P_CAL, the differential output after compensating 1 / 2 * Vlsb_CAL is:

[0075] OUTP-OUTN=-β*(Cp M+1 *(Csp+Ccp3)+1 / 2*(Ccp2-Clsb,p*Ccp3) / (Cinp*(Clsb,p+Csp+Ccp3+Ccp2))*Vrefp (24)

[0076] The calibrated weights in the above formula are:

[0077] WeightWP_CAL(M+1)=(Cp M+1 +0.5Ccp3+0.5Ccp2) / (Clsb,p+Csp+Ccp3+Ccp2)=1 / 2(25)

[0078] Theoretically consistent with the ideal, which proves the calibration is effective.

[0079] Conversion process of the N-bit ADC (M+L segmented capacitor array):

[0080] During the sampling phase, switch T1 is closed and T2 is open. The lower plate of the sampling capacitor is connected to the input signal, and the upper plate is connected to Vcm.

[0081] According to the highest bit of the calibration code, determine whether the conversion capacitance weight of the LSB array increases or decreases due to the parasitic capacitance of the bridging capacitor and the parasitic capacitance of the LSB array; if the highest bit of the calibration code is 1, it means the conversion weight decreases, and the lower plates of the P_CAL capacitor array and the MSB highest bit capacitors Cp1 and Cn1 are connected to Vrefp; if the highest bit of the calibration code is 0, the conversion weight increases, and the lower plates of the N_CAL capacitor array and the MSB highest bit capacitors Cp1 and Cn1 are connected to Vrefp. The remaining capacitors are all connected to Vrefn;

[0082] During the conversion phase, switch T1 is open and T2 is closed. The upper plates of the positive and negative sampling capacitors are connected together, and charge redistribution occurs on the upper and lower plates of the sampling capacitors for the first comparison;

[0083] Switch the first-bit conversion capacitor according to the result of the first comparison; if the result of the first comparison is OUTN>OUTP, the highest bit is 0, and switch the Cp1 capacitor to connect to Vrefn before the next comparison; conversely, if OUTN<OUTP, the highest bit is 1, and switch the Cn1 capacitor to connect to Vrefn before the next comparison, and charge redistribution is performed for the second comparison;

[0084] Switch the second-bit conversion capacitor according to the result of the second comparison; if the result of the second comparison is OUTN>OUTP, the second highest bit is 0, and switch the Cn2 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN<OUTP, the second highest bit is 1, and switch the Cp2 capacitor to connect to Vrefp before the next comparison, and charge redistribution is performed for the third comparison; ......

[0086] Switch the M-bit conversion capacitor according to the result of the Mth comparison; if the result of the Mth comparison is OUTN>OUTP, the Mth bit is 0, and switch the Cn M capacitor to connect to Vrefp; conversely, if OUTN<OUTP, the Mth bit is 1, and switch the Cp M capacitor to connect to Vrefp, and charge redistribution is performed for the M+1th comparison;

[0087] So far, the conversion of the high-segment capacitor array is completed, and the high M+1-bit digital code is obtained.

[0088] Switch the (M + 1)-th conversion capacitor according to the result of the (M + 1)-th comparison; if the result of the (M + 1)-th comparison is OUTN > OUTP, the (M + 1)-th bit is 0, and switch Cn before the next comparison M+1 and Cp M+1 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(1); conversely, if OUTN < OUTP, the (M + 1)-th bit is 1, connect the Cp capacitor to Vrefp before the next comparison, and simultaneously switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(1), and perform the (M + 2)-th comparison after charge redistribution;

[0089] Switch the (M + 2)-th conversion capacitor according to the result of the (M + 2)-th comparison; if the result of the (M + 2)-th comparison is OUTN > OUTP, the (M + 2)-th bit is 0, and switch Cn before the next comparison M+2 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(2); conversely, if OUTN < OUTP, the (M + 2)-th bit is 1, and switch Cp before the next comparison M+2 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(2), and perform the (M + 3)-th comparison after charge redistribution; ......

[0091] Switch the (M + L - 1)-th conversion capacitor according to the result of the (M + L - 1)-th comparison; if the result of the (M + L - 1)-th comparison is OUTN > OUTP, the (M + L - 1)-th bit is 0, and switch Cn before the next comparison M+L-1 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(L - 1); conversely, if OUTN < OUTP, the (M + L - 1)-th bit is 1, and switch Cp before the next comparison M+L-1 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(L - 1), and perform the (M + L)-th comparison after charge redistribution;

[0092] Switch the (M + L)-th conversion capacitor according to the result of the (M + L)-th comparison; if the result of the (M + L)-th comparison is OUTN > OUTP, the (M + L)-th bit is 0, and switch Cn before the next comparison M+L Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(L); conversely, if OUTN < OUTP, the (M + L)-th bit is 1, and switch Cp before the next comparison M+LThe capacitor is connected to Vrefp, and the corresponding calibration capacitor of P_CAL is switched according to the LSB weight calibration code WP_CAL(L). After charge redistribution, the M+L+1th comparison is performed.

[0093] After the result of the M+L+1th comparison is obtained, the conversion of the M+L+1-bit digital code is completed.

[0094] The asymmetric parasitic calibration segmented capacitor array is applied to a high-precision successive approximation analog-to-digital converter.

[0095] The beneficial effects of this invention are:

[0096] This invention employs a sampling capacitor + binary bridge capacitor array structure, connecting the sampling capacitors after sampling. This ensures that the weight of each conversion capacitor in the MSB array is unaffected by parasitic capacitance, eliminating the gain error caused by high-order parasitics in CDAC with lower complexity. Furthermore, the design of the LSB low-order weight calibration unit reduces the nonlinearity caused by parasitic capacitance in the bridge capacitor and low-order capacitor array.

[0097] This invention employs a simple timing mechanism, which theoretically can completely eliminate the dynamic range loss caused by gain errors due to high-segment parasitic capacitance, and reduce the nonlinearity caused by low-segment parasitic capacitance. LSB array calibration is performed within the calibration period, detecting the difference between the LSB weight capacitor value and the actual binary weight capacitor value, generating a weight compensation code, and calibrating the LSB array to restore the binary weights of the CDAC conversion capacitors, thus reducing the impact of gain errors and nonlinearities caused by parasitic capacitance on conversion accuracy. Attached Figure Description

[0098] Figure 1 This is a schematic diagram of a calibration device for the gain error of a SAR-type ADC in the prior art.

[0099] Figure 2 This is a schematic diagram of a calibration circuit for a bridging capacitor array, as described in the prior art.

[0100] Figure 3 This is a schematic diagram of an asymmetric parasitic calibration segmented capacitor array according to the present invention.

[0101] Figure 4 This is a schematic diagram of an asymmetric parasitic calibration segmented capacitor array for a 12-bit ADC.

[0102] Figure 5 This is a schematic diagram of an asymmetric segmented capacitor array with parasitic capacitance for a 12-bit ADC. Detailed Implementation

[0103] The present invention will now be described in further detail with reference to the accompanying drawings.

[0104] The technical solution provided by this invention is as follows:

[0105] like Figure 3 As shown: This invention designs an asymmetric parasitic calibration segmented capacitor array for high-precision successive approximation analog-to-digital converters.

[0106] like Figure 4 As shown, taking a 12-bit ADC as an example, the capacitor array consists of positive terminal (P) and negative terminal (N) capacitor arrays, specifically including sampling capacitors (Cinp, Cinn), conversion capacitors (Cp1~11, Cn1~11), calibration capacitors (Cpc1~8, Cnc1~8) and compensation capacitors (Cp, Cn), where Cinp = Cinn.

[0107] The switching capacitor adopts a high 6-bit (MSB) and low 5-bit (LSB) structure;

[0108] The calibration capacitors include a positive terminal calibration capacitor array (P_CAL) and a negative terminal calibration capacitor array (N_CAL) to calibrate the nonlinearity caused by the parasitic capacitance of the bridging capacitors and the parasitic nonlinearity of the LSB array.

[0109] The highest bit of the calibration code controls calibration capacitors Cnc1 and Cic1; the lowest bit of the calibration code controls calibration capacitors Cnc8 and Cic8; Cnc4 and Cic4 are bridging capacitors in the calibration capacitor array.

[0110] The compensation capacitor Cp is used to compensate for the capacitance value of the MSB array at the positive terminal, and the compensation capacitor Cn is used to compensate for the capacitance value of the LSB array at the negative terminal, so that the capacitor arrays at both ends are matched.

[0111] Compared with the P-terminal MSB array, an additional unit capacitor Cn7 is introduced in the high-order bits of the N-terminal to express the weight of the 7th bit of the N-terminal;

[0112] Capacitor correction arrays P_CAL and N_CAL were added to the N-terminal LSB array.

[0113] For ease of expression in subsequent formulas, C is the unit capacitance, which is considered as 1 in the following formulas. The sum of the high-segment capacitance (Cmsb,p,Cmsb,n) and the sum of the low-segment capacitance (Clsb,p,Clsb,n) at the P and N terminals are:

[0114] Cmsb,p=Cp1+Cp2+Cp3+Cp4+Cp5+Cp6+Cp=64 (1)

[0115] Cmsb,n=Cn1+Cn2+Cn3+Cn4+Cn5+Cn6+Cn7=64 (2)

[0116] Clsb,p=Cp7+Cp8+Cp9+Cp10+Cp11=31 (3)

[0117] Clsb,n=Cn8+Cn9+Cn10+Cn11+Cn+CP_CAL+CN_CAL=31 (4)

[0118] in

[0119] CP_CAL=Cpc1+Cpc2+Cpc3+(Cpc5+Cpc6+Cpc7+Cpc8)*Cpc4 /

[0120] (Cpc5+Cpc6+Cpc7+Cpc8+Cpc4)(5)CN_CAL=Cnc1+Cnc2+Cnc3+(Cnc5+Cnc6+Cnc7+Cnc8)*Cnc4 /

[0121] (Cnc5+Cnc6+Cnc7+Cnc8+Cnc4)(6)

[0122] When there are high-segment parasitic capacitances Ccp1 and Ccn1, parasitic capacitances of bridging capacitors Ccp3 and Ccn3, and low-segment parasitic capacitances Ccp2 and Ccn2 (e.g.) Figure 5 As shown in the figure, since the number of unit capacitances on the positive and negative terminals is equal, that is, the sum of the unit capacitances of MSB and LSB on the N terminal is equal to the sum of the unit capacitances of MSB and LSB on the P terminal respectively, without considering device mismatch, the corresponding parasitic capacitances to ground are also equal, that is, Ccp1=Ccn1, Ccp2=Ccn2, Ccp3=Ccn3.

[0123] Total capacitance of the LSB array as viewed from the output node (Cltot,p, Cltot,n)

[0124] Cltot,p=((31+Ccp2)*(1+Ccp3)) / (32+Ccp3+Ccp2) (7)

[0125] Cltot,n=((31+Ccn2)*(1+Ccn3)) / (32+Ccn3+Ccn2) (8)

[0126] Taking the weight of the highest bit in the positive LSB array, Weightp(7), as an example, the ideal weight of this bit is:

[0127] Weightp_i(7)=16*Csp / (31+Csp)=1 / 2 (9)

[0128] When Ccp3 and Ccp2 exist, if the parasitics are not calibrated, the weight of this bit will deviate from the binary representation as follows:

[0129] Weightp(7)=16*(1+Ccp3) / (32+Ccp3+Ccp2) (10)

[0130] Therefore, weight correction is required.

[0131] The following explains why this structure can eliminate gain errors caused by parasitic capacitance in the high-segment area.

[0132] During the sampling phase, the differential inputs are Vinp and Vinn. Switch T1 is closed and T2 is open. The lower plates of sampling capacitors Cinp and Cinn are sampled, and the upper plate is connected to the common-mode voltage Vcm. The lower plates of the P_CAL capacitor array and the highest-order capacitors Cp1 and Cn1 of MSB are connected to the reference voltage Vrefp, and the remaining capacitors are all connected to the reference voltage Vrefn.

[0133] During the holding phase, switch T1 is open and switch T2 is closed, connecting the lower plate of the sampling capacitor. Therefore, charge redistribution occurs between the upper and lower plates of the sampling capacitor. Due to the presence of high-segment parasitic capacitances Ccp1 and Ccn1, the parasitic capacitances of the bridging capacitor Ccp3 and Ccn3, and the low-segment parasitic capacitances Ccp2 and Ccn2, the actual total capacitance (Ctota,p, Ctota,n) at this time is:

[0134] Ctota,p=Cinp+Cmsb,p+Ccp1+Cltot,p (11)

[0135] Ctota,n=Cinn+Cmsb,n+Ccn1+Cltot,n (12)

[0136] Since Cinp = Cinn, Cmsb,p = Cmsb,n, and Cltot,p = Cltot,n, then Ctota,n = Ctota,p.

[0137] According to the law of conservation of charge, the outputs OUTN and OUTP are:

[0138] OUTN=Vcm-β*(Vinp-Vinn) / 2 (13)

[0139] OUTP=Vcm-β*(Vinn-Vinp) / 2 (14)

[0140] OUTP-OUTN=β*(Vinp-Vinn) (15)

[0141] Where β=Cinp / Ctota,p=Cinn / Ctota,n.

[0142] If OUTP - OUTN < 0, the most significant bit is 0. Before the next comparison, the most significant bit capacitor Cp1 is switched to Vrefn. According to charge conservation, OUTN and OUTP are then:

[0143] OUTN=Vcm-β*((Vinp-Vinn) / 2+1.5*Cp1 / Cinp) (16)

[0144] OUTP=Vcm-β*((Vinn-Vinp) / 2+0.5*Cp1 / Cinp) (17)

[0145] OUTP-OUTN=β*(Vinp-Vinn+Cp1 / Cinp) (18)

[0146] In equations (16) and (17), the expressions for OUTN and OUTP both contain Cp1 / Cinp. This is because the lower plates of the two sampling capacitors Cinp and Cinn are connected during the conversion stage, causing the two output nodes OUTP and OUTN to no longer be independent of each other. Switching the highest-order capacitor Cp1 to Vrefn causes the three nodes—output nodes OUTP and OUTN and the lower plates of sampling capacitors Cinp and Cinn—to undergo charge redistribution simultaneously. In equation (18), when the input Vinp-Vinn is compared with the conversion weight Cp1 / Cinp, it is not affected by the parasitic capacitors Ccp1 and Ccn1 in the higher segment, thus eliminating the loss of dynamic range caused by the gain error brought by the parasitic capacitors Ccp1 and Ccn1 in the higher segment.

[0147] The following is a detailed calibration process for low-end capacitors:

[0148] During the calibration phase, both the P and N terminals are connected to the common-mode voltage Vcm. During the sampling phase, switch T1 is closed and T2 is open. The P_CAL capacitor array, Cn8, and the lower plates of the highest-order capacitors Cp1 and Cn1 of the MSB are connected to Vrefp, and all other capacitors (except the sampling capacitor) are connected to Vrefn.

[0149] During the holding phase, switch T1 is open and switch T2 is closed, and the lower plate of the sampling capacitor is connected to the positive and negative terminals. Therefore, charge redistribution occurs between the upper and lower plates of the sampling capacitor, and at this time OUTP-OUTN=0.

[0150] Switch capacitors Cn7, Cp7, and Cp8 to Vrefp, and capacitor Cn8 to Vrefn. If there are no parasitic capacitors, the difference between OUTP and OUTN is 0. Due to the presence of bridging parasitic capacitors Ccp3 and Ccn3, and low-segment parasitic capacitors Ccp2 and Ccn2, the differential output voltage is:

[0151] OUTP-OUTN=β*(Ccp2-31*Ccp3) / (Ctota,p*(32+Ccp3+Ccp2))*Vrefp(19)

[0152] The voltage Vlsb_CAL that needs to be calibrated is the voltage represented by formula (19). Vlsb_CAL is reduced by switching the control switches in the P_CAL and N_CAL capacitor arrays using a successive approximation method. The successive approximation method is as follows:

[0153] If Vlsb_CAL > 0, then the highest bit of the calibration code is 1. Before the next comparison, the Cnc1 capacitor in the N_CAL capacitor array is switched to Vrefp. At this time, the differential output voltage becomes:

[0154] Vlsb_CAL=β*(((-31Ccp3+Ccp2)-4*(1+Ccp3)) / (Ctota,p*(

[0155] 32+Ccp3+Ccp2)))*Vrefp(20)

[0156] If Vlsb_CAL < 0 at this time, the high-order bit of the calibration code is 0. Before the next comparison, the Cpc2 capacitor in the P_CAL capacitor array is switched to Vrefn. At this time, the differential output voltage becomes:

[0157] Vlsb_CAL=β*(((-31Ccp3+Ccp2)-2*(1+Ccp3) / (Ctota,p*(

[0158] 32+Ccp3+Ccp2)))*Vrefp(21)

[0159] As can be seen from equations (19) to (21), Vlsb_CAL gradually decreases. This process is repeated to obtain the 7-bit LSB calibration code D_CAL, at which point Vlsb_CAL approaches 0. The highest bit of D_CAL controls Cpc1 and Cnc1 in P_CAL and N_CAL with a weight of 4; the second highest bit controls Cpc2 and Cnc2 with a weight of 2; the third bit controls Cpc3 and Cnc3 with a weight of 1; the fourth bit controls Cpc5 and Cnc5 with a weight of 1 / 2; the fifth bit controls Cpc6 and Cnc6 with a weight of 1 / 4; the sixth bit controls Cpc7 and Cnc7 with a weight of 1 / 8; and the seventh bit controls Cpc8 and Cnc8 with a weight of 1 / 16. The switching control signals of Cpc(i) and Cnc(i) in the P_CAL and N_CAL capacitor arrays are complementary.

[0160] After calibration, the normal conversion phase begins. When converting to a lower bit, the obtained calibration code D_CAL is compensated bit by bit to the LSB array at ratios of 1 / 2, 1 / 4, 1 / 8, 1 / 16, and 1 / 32. That is, when switching the effective weight of the LSB, the corresponding voltage value needs to be compensated. The digital code for switching the calibration band content switch array is obtained by accumulating the comparison results and is called the weight compensation code. Let b(i) (i = 1, 2, 3, 4, 5) represent the comparison results of bits 7 to 11, and WN_CAL(i) and WP_CAL(i) represent the switch array control codes of N_CAL and P_CAL for calibrating the capacitor array when switching the lower segment capacitor array.

[0161]

[0162]

[0163] Taking switching the most significant bit Cp7 of the LSB to Vrefp as an example, if no voltage compensation is performed, the differential output will be:

[0164] OUTP-OUTN=-β*(16*(1+Ccp3)) / (Cinp*(32+Ccp3+Ccp2))*Vrefp (twenty four)

[0166] If the calibration code D_CAL is 1010100, then according to the 7th bit compensation code WP_CAL(1)

[0167] =0101010, switch the corresponding calibration capacitor for P_CAL. Here, switch the capacitors Cpc2, Cpc5, and Cpc7 connected to Vrefn. The differential output after compensating 1 / 2*Vlsb_CAL is:

[0168] OUTP-OUTN=-β*(16*(1+Ccp3)+1 / 2*(Ccp2-31*Ccp3) / (Cinp*

[0169] (32+Ccp3+Ccp2))*Vrefp(25) The calibrated weights in the above formula are:

[0170] WeightWP_CAL(7)=(16+0.5Ccp3+0.5Ccp2) / (32+Ccp3+Ccp2)=1 / 2

[0171] (26) Theoretically consistent with ideal, that is, the calibration is proven to be effective.

[0172] The following describes the ADC 12-bit conversion process in detail:

[0173] During the sampling phase, switch T1 is closed and switch T2 is open. The lower plate of the sampling capacitor is connected to the input signal, and the upper plate is connected to Vcm.

[0174] Judge whether the conversion capacitance weight of the LSB array increases or decreases due to the parasitic capacitance of the bridging capacitor and the parasitic capacitance of the LSB array according to the highest bit of the calibration code. If the calibration code is 1010100 and the highest bit of the calibration code is 1, it means that the conversion weight decreases, and the lower plates of the P_CAL capacitor array and the MSB highest bit capacitors Cp1 and Cn1 are connected to Vrefp; if the highest bit of the calibration code is 0, the conversion weight increases, and the lower plates of the N_CAL capacitor array and the MSB highest bit capacitors Cp1 and Cn1 are connected to Vrefp. The remaining capacitors are all connected to Vrefn.

[0175] In the conversion stage, switch T1 is disconnected and T2 is closed. The upper plates of the positive and negative sampling capacitors are connected together, and charge redistribution occurs on the upper and lower plates of the sampling capacitors for the first comparison.

[0176] Switch the first conversion capacitor according to the result of the first comparison. If the result of the first comparison is OUTN > OUTP, the highest bit is 0, and switch the Cp1 capacitor to connect to Vrefn before the next comparison; conversely, if OUTN < OUTP, the highest bit is 1, and switch the Cn1 capacitor to connect to Vrefn before the next comparison. After charge redistribution, the second comparison is performed.

[0177] Switch the second conversion capacitor according to the result of the second comparison. If the result of the second comparison is OUTN > OUTP, the second highest bit is 0, and switch the Cn2 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN < OUTP, the second highest bit is 1, and switch the Cp2 capacitor to connect to Vrefp before the next comparison. After charge redistribution, the third comparison is performed.

[0178] Switch the third conversion capacitor according to the result of the third comparison. If the result of the third comparison is OUTN > OUTP, the third bit is 0, and switch the Cn3 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN < OUTP, the third bit is 1, and switch the Cp3 capacitor to connect to Vrefp before the next comparison. After charge redistribution, the fourth comparison is performed.

[0179] Switch the fourth conversion capacitor according to the result of the fourth comparison. If the result of the fourth comparison is OUTN > OUTP, the fourth bit is 0, and switch the Cn4 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN < OUTP, the fourth bit is 1, and switch the Cp4 capacitor to connect to Vrefp before the next comparison. After charge redistribution, the fifth comparison is performed.

[0180] Switch the 5th conversion capacitor according to the 5th comparison result. If the 5th comparison result is OUTN > OUTP, the 5th bit is 0, and switch the Cn5 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN < OUTP, the 5th bit is 1, and switch the Cp5 capacitor to connect to Vrefp before the next comparison. After charge redistribution, perform the 6th comparison.

[0181] Switch the 6th conversion capacitor according to the 6th comparison result. If the 6th comparison result is OUTN > OUTP, the 6th bit is 0, and switch the Cn6 capacitor to connect to Vrefp before the next comparison; conversely, if OUTN < OUTP, the 6th bit is 1, and switch the Cp6 capacitor to connect to Vrefp before the next comparison. After charge redistribution, perform the 7th comparison.

[0182] 至此高段电容阵列转换结束,得到高7位数字码。 At this point, the conversion of the high - segment capacitor array ends, and the high 7 - bit digital code is obtained.

[0183] Switch the 7th conversion capacitor according to the 7th comparison result. If the 7th comparison result is OUTN > OUTP, the 7th bit is 0. Before the next comparison, switch the Cn7 and Cp7 capacitors to connect to Vrefp, and at the same time, switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(1)=0101010. Here, switch the Cpc2, Cpc5, and Cpc7 capacitors to connect to Vrefn; conversely, if OUTN < OUTP, the 7th bit is 1. Before the next comparison, switch the Cp7 capacitor to connect to Vrefp, and at the same time, switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(1)=0101010. Here, switch the Cpc2, Cpc5, and Cpc7 capacitors to connect to Vrefn. After charge redistribution, perform the 8th comparison.

[0184] Switch the 8th conversion capacitor according to the 8th comparison result. If the 8th comparison result is OUTN > OUTP, the 8th bit is 0. Before the next comparison, switch the Cn8 capacitor to connect to Vrefp, and at the same time, switch the corresponding calibration capacitors of N_CAL according to the LSB weight calibration code WN_CAL(2)=0010101. Here, switch the Cnc3, Cnc6, and Cnc8 capacitors to connect to Vrefp; conversely, if OUTN < OUTP, the 8th bit is 1. Before the next comparison, switch the Cp8 capacitor to connect to Vrefp, and at the same time, switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(2)=0111111. Here, switch the Cpcr3, Cpc6, and Cpc8 capacitors to connect to Vrefn. After charge redistribution, perform the 9th comparison.

[0185] Switch the 9th conversion capacitor according to the result of the 9th comparison. If the result of the 9th comparison is OUTN>OUTP, the 9th bit is 0. Before the next comparison, switch the Cn9 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of N_CAL according to the LSB weight calibration code WN_CAL(3)=0011111. Here, switch the Cpc5 and Cnc7 capacitors to Vrefp; conversely, if OUTN<OUTP, the 9th bit is 1. Before the next comparison, switch the Cp9 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(3). If the 8th bit is 0, then WP_CAL(3)=0110100. Here, switch the Cpc3 and Cpc6 capacitors to Vrefn, and the Cpc5 and Cpc7 capacitors to Vrefp; if the 8th bit is 1, then WP_CAL(3)=1001001. Here, switch the Cpc1 capacitor to Vrefn, and the Cpc2, Cpc3, Cpc6 and Cpc7 capacitors to Vrefp. After charge redistribution, perform the 10th comparison.

[0186] Switch the 10th conversion capacitor according to the result of the 10th comparison. If the result of the 10th comparison is OUTN>OUTP, the 10th bit is 0. Before the next comparison, switch the Cn10 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of N_CAL according to the LSB weight calibration code WN_CAL(4); conversely, if OUTN<OUTP, the 10th bit is 1. Before the next comparison, switch the Cp10 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(4). After charge redistribution, perform the 11th comparison.

[0187] Switch the 11th conversion capacitor according to the result of the 11th comparison. If the result of the 11th comparison is OUTN>OUTP, the 11th bit is 0. Before the next comparison, switch the Cn11 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of N_CAL according to the LSB weight calibration code WN_CAL(5); conversely, if OUTN<OUTP, the 11th bit is 1. Before the next comparison, switch the Cp11 capacitor to Vrefp, and at the same time switch the corresponding calibration capacitors of P_CAL according to the LSB weight calibration code WP_CAL(5). After charge redistribution, perform the 12th comparison.

[0188] After the result of the 12th comparison is obtained, the conversion of the 12-bit digital code is completed.

Claims

1. An asymmetric parasitic calibration segmented capacitor array, characterized in that, This includes a positive terminal capacitor array and a negative terminal capacitor array. The positive terminal capacitor array includes a positive terminal sampling capacitor Cinp, a positive terminal conversion capacitor array, and a positive terminal compensation capacitor Cp. The negative terminal capacitor array includes a negative terminal sampling capacitor Cinn, a negative terminal conversion capacitor array, a positive terminal calibration capacitor array Cpc, a negative terminal calibration capacitor array Cnc, and a negative terminal compensation capacitor Cn. For an N-bit analog-to-digital converter: The positive terminal conversion capacitor array consists of N-1 positive terminal conversion stubs. Each positive terminal conversion stub includes a positive terminal conversion capacitor and a selection switch. One end of each positive terminal conversion stub is connected to OUTN, and the other end is set to 1 or 0 through the selection switch TP. The negative terminal conversion capacitor array consists of N-1 negative terminal conversion stubs. Each negative terminal conversion stub includes a negative terminal conversion capacitor and a selection switch. One end of each negative terminal conversion stub is connected to OUTP, and the other end is set to 1 or 0 through the selection switch TN. The positive terminal calibration capacitor array is composed of several positive terminal calibration branches. Each positive terminal calibration branch includes a positive terminal calibration capacitor and a selection switch. One end of each positive terminal calibration branch is connected to the negative terminal LSB array, and the other end is set to 1 or 0 through the selection switch. The positive terminal conversion capacitor array includes an M-bit positive terminal MSB array and an L-bit positive terminal LSB array connected by bridging capacitors. The negative terminal conversion capacitor array includes an M-bit negative terminal MSB array and an L-bit negative terminal LSB array connected by bridging capacitors. The negative terminal calibration capacitor array is composed of several negative terminal calibration branches. Each negative terminal calibration branch includes a negative terminal calibration capacitor and a selection switch. One end of each negative terminal calibration branch is connected to the negative terminal LSB array, and the other end is set to 1 or 0 through the selection switch. One end of the positive sampling capacitor is connected to OUTN, and the other end is connected to Vinp through switch T1 and to the lower plate of Cinn through switch T2. One end of the negative sampling capacitor is connected to OUTP, and the other end is connected to Vinn through switch T1 and to the lower plate of Cinn through switch T2. The positive terminal compensation capacitor Cp is connected to the OUTN and 0 terminals to compensate for the positive terminal MSB array capacitance value, so that the positive and negative terminal MSB array capacitance values ​​are equal. The negative terminal compensation capacitor Cn is connected to the upper plate of the negative terminal LSB array and the lower plate is connected to the 0 terminal. It is used to compensate the capacitance value of the negative terminal LSB array so that the capacitance values ​​of the positive terminal and negative terminal LSB array are equal. The calibration capacitor is used to calibrate the parasitic capacitance caused by the bridging capacitor and the nonlinearity caused by the parasitic LSB array. The sampling capacitor Cinp = Cinn; In the calibration capacitor, the Kth bit of the calibration code controls the calibration capacitor Cnc. k CPC k ; Compared to the positive-end MSB array, an additional unit capacitor Cn is introduced in the higher-order bits of the negative end. M+1 Used to express the weight of the (M+1)th bit of the negative end; add a positive end calibration capacitor array Cpc and a negative end calibration capacitor array Cnc to the negative end LSB array.

2. The asymmetric parasitic calibration segmented capacitor array according to claim 1, characterized in that, In the aforementioned conversion capacitor, for ease of subsequent formula expression, C is a unit capacitance, which is considered as 1 in the following formulas. The sum of the high-segment capacitance at the positive and negative terminals and the sum of the low-segment capacitance are respectively... Cmsb,p= (1) Cmsb,n= (2) Clsb,p= (3) Clsb,n= (4) Simultaneously satisfying Cmsb,p=Cmsb,n and Cmsb,p=Cmsb,n; When there are high-segment parasitic capacitances Ccp1 and Ccn1, bridging capacitor parasitic capacitances Ccp3 and Ccn3, and low-segment parasitic capacitances Ccp2 and Ccn2, since the number of unit capacitances on the positive and negative terminals is equal, that is, the sum of the unit capacitances of MSB and LSB on the negative terminal is equal to the sum of the unit capacitances of MSB and LSB on the positive terminal, Ccp1=Ccn1, Ccp2=Ccn2, and Ccp3=Ccn3; Total capacitance of the LSB array (Cltot,p,Cltot,n) as seen from the output node Cltot,p=((Clsb,p+Ccp2)*(Csp+Ccp3)) / (Clsb,p+Csp+Ccp3+Ccp2)(5) Cltot,n=((Clsb,n+Ccn2)*(Csn+Ccn3)) / (Clsb,n+Csn+Ccn3+Ccn2)(6) Taking the weight of the highest bit in the positive LSB array, Weightp(M+1), as an example, the ideal weight of this bit is: Weightp_i(M+1)=Cp M+1 *Csp / (Clsb,p+Csp)=1 / 2(7) When Ccp3 and Ccp2 exist, the weight of this bit deviates from the binary representation and changes as follows: Weightp(M+1)=Cp M+1 *(Csp+Ccp3) / (Clsb,p+Csp+Ccp3+Ccp2)(8)。 3. The asymmetric parasitic calibration segmented capacitor array according to claim 2, characterized in that, The specific method for using the asymmetric parasitic calibration segmented capacitor array to eliminate gain errors caused by high-segment parasitic capacitance is as follows: During the sampling phase, the differential inputs are Vinp and Vinn. The sampling switch T1 is closed, and the holding switch T2 is open. The lower plates of the sampling capacitors Cinp and Cinn are sampled, and the upper plate is connected to the common-mode voltage Vcm. The lower plates of the P_CAL capacitor array and the highest-order capacitors Cp1 and Cn1 of MSB are connected to the reference voltage Vrefp, and the remaining capacitors are all connected to the reference voltage Vrefn. During the holding phase, sampling switch T1 is open and holding switch T2 is closed, connecting the lower plates of the sampling capacitor. Charge redistribution occurs between the upper and lower plates of the sampling capacitor. Due to the presence of high-segment parasitic capacitances Ccp1 and Ccn1, the parasitic capacitances of the bridging capacitor Ccp3 and Ccn3, and the low-segment parasitic capacitances Ccp2 and Ccn2, the actual total capacitance (Ctota,p, Ctota,n) at this time is: Ctota,p=Cinp+Cmsb,p+Ccp1+Cltot,p(9) Ctota,n=Cinn+Cmsb,n+Ccn1+Cltot,n(10) Since Cinp=Cmsb,p+Ccp1+Cltot,p=Cinn=Cmsb,n+Ccn1+Cltot,n,Cmsb,p=Cmsb,n,Cltot,p=Cltot,n,thereforeCtota,n=Ctota,p. According to the law of conservation of charge, the outputs OUTN and OUTP are: OUTN=Vcm-β*(Vinp-Vinn) / 2(11) OUTP=Vcm-β*(Vinn-Vinp) / 2(12) OUTP-OUTN=β*(Vinp-Vinn)(13) Where β=Cinp / Ctota,p= Cinn / Ctota,n; If OUTP - OUTN < 0, the most significant bit is 0. Before the next comparison, the most significant bit capacitor Cp1 is switched to Vrefn. According to charge conservation, OUTN and OUTP are then: OUTN=Vcm-β*((Vinp-Vinn) / 2+1.5*Cp1 / Cinp)(14) OUTP=Vcm-β*((Vinn-Vinp) / 2+0.5*Cp1 / Cinp)(15) OUTP-OUTN=β*(Vinp-Vinn+Cp1 / Cinp)(16) In equations (14) and (15), the expressions for OUTN and OUTP both contain Cp1 / Cinp. This is because the lower plates of the two sampling capacitors Cinp and Cinn are connected during the conversion stage, causing the two output nodes OUTP and OUTN to no longer be independent of each other. Switching the highest-order capacitor Cp1 to Vrefn causes the three nodes of output nodes OUTP and OUTN and sampling capacitors Cinp and Cinn to undergo charge redistribution simultaneously. In equation (16), when the input Vinp-Vinn is compared with the conversion weight Cp1 / Cinp, it is not affected by the parasitic capacitors Ccp1 and Ccn1 in the high segment, thereby eliminating the loss of dynamic range caused by the gain error brought by the parasitic capacitors Ccp1 and Ccn1 in the high segment.

4. An asymmetric parasitic calibration segmented capacitor array according to claim 3, characterized in that, The asymmetric parasitic calibration segmented capacitor array is used for the low-end capacitor calibration process: During the calibration phase, both the positive and negative inputs are connected to the common-mode voltage Vcm; during the sampling phase, switch T1 is closed and T2 is open, the P_CAL capacitor array, Cn, and the lower plates of the highest-order capacitors Cp1 and Cn1 of MSB are connected to Vrefp, and the remaining capacitors (except for the sampling capacitor) are connected to Vrefn. During the holding phase, switch T1 is open and switch T2 is closed. The lower plate of the sampling capacitor is connected to the positive and negative terminals. Therefore, charge redistribution occurs between the upper and lower plates of the sampling capacitor. At this time, OUTP-OUTN=0. Switch Cn M+1 Cp M+1 Cp M+2 The capacitor is connected to Vrefp, Cn M+2 With the capacitor connected to Vrefn, the difference between OUTP and OUTN is 0 if there are no parasitic capacitors. Due to the presence of bridging parasitic capacitors Ccp3 and Ccn3, and lower-segment parasitic capacitors Ccp2 and Ccn2, the differential output voltage is: OUTP-OUTN=β*(Ccp2-Clsb,p*Ccp3) / (Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2))*Vrefp(17) The voltage Vlsb_CAL that needs to be calibrated is the voltage represented by formula (17); Vlsb_CAL is reduced by switching the control switches in the P_CAL and N_CAL capacitor arrays in a successive approximation manner.

5. An asymmetric parasitic calibration segmented capacitor array according to claim 4, characterized in that, in, The successive approximation method is as follows: If Vlsb_CAL > 0, the highest bit of the calibration code is 1. Before the next comparison, the Cnc1 capacitor in the N_CAL capacitor array is switched to Vrefp. At this time, the differential output voltage becomes: Vlsb_CAL= β*(((-Clsb,p*Ccp3+Ccp2)-0.25*Cp M+1 *(Csp+Ccp3)) / (Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2)))*Vrefp(18) If Vlsb_CAL < 0 at this time, the high-order bit of the calibration code is 0. Before the next comparison, the Cpc2 capacitor in the P_CAL capacitor array is switched to Vrefn. At this time, the differential output voltage becomes: Vlsb_CAL= β*(((-Clsb,p*Ccp3+Ccp2)-0.125*Cp M+1 *(Csp+Ccp3) / (Ctota,p*(Clsb,p+Csp+Ccp3+Ccp2)))*Vrefp(19) As can be seen from equations (17) to (19), Vlsb_CAL gradually decreases, and the K-bit LSB calibration code D_CAL is obtained by analogy. At this time, Vlsb_CAL is close to 0. The highest bit of D_CAL controls the weight of P_CAL and N_CAL, which is 1 / 4*Cp. M+1 Cpc1 and Cnc1; the second highest control weight is 1 / 8*Cp M+1 Cpc2 and Cnc2; the third control weight is 1 / 16*Cp M+1 Cpc3 and Cnc3; and so on, the Kth bit controls the weight bit 1 / 2^(K+1)*Cp M+1 Cpck and Cnck; Cpc in P_CAL and N_CAL capacitor arrays k With Cnc k The switch control signals are complementary.

6. An asymmetric parasitic calibration segmented capacitor array according to claim 5, characterized in that, After calibration, enter the normal conversion stage. When converting to the lower bits, the above-mentioned calibrated code D_CAL is compensated to the LSB array bit by bit at ratios of 1 / 2, 1 / 4, 1 / 8,......, 1 / 2^L. That is, when switching the effective weight of the LSB, the corresponding voltage value needs to be compensated. The digital code of the switching calibration tape content switch array is obtained by accumulating according to the comparison result, which is called the weight compensation code. Let b(i), i = 1, 2, 3,......, L, represent the comparison results of the (M + 1)-th bit to the (M + L)-th bit, and WN_CAL(i), WP_CAL(i) represent the switch array control codes of the N_CAL and P_CAL calibration capacitor arrays when switching the lower-segment capacitor array. Then WN_CAL(i)= (20) WP_CAL(i)= (21) Where D_CAL(i)= (22) To switch the most significant bit Cp of the LSB M+1 Taking Vrefp as an example, if no voltage compensation is performed, the differential output will be: OUTP-OUTN= -β*(Cp M+1 *(Csp+Ccp3)) / (Cinp*(Clsb,p+Csp+Ccp3+Ccp2))*Vrefp(23) From the K-bit calibration code D_CAL, the compensation code of the (M + 1)-th bit is obtained as WP_CAL(1) = 1 / 2 * D_CAL(1). After switching the corresponding calibration capacitor of P_CAL and compensating 1 / 2 * Vlsb_CAL, the differential output is OUTP-OUTN= -β*(Cp M+1 *(Csp+Ccp3)+1 / 2*(Ccp2-Clsb,p*Ccp3) / (Cinp*(Clsb,p+Csp+Ccp3+Ccp2))*Vrefp(24) The calibrated weight in the above formula is WeightWP_CAL(M+1)=(Cp M+1 +0.5Ccp3+0.5Ccp2) / (Clsb,p+Csp+Ccp3+Ccp2)=1 / 2(25) Theoretically, it is consistent with the ideal situation, which proves that the calibration is effective.

7. An asymmetric parasitic calibration segmented capacitor array according to claim 6, characterized in that, The conversion process of the N-bit ADC (M + L segmented capacitor array): In the sampling stage, switch T1 is closed and T2 is open. The lower plate of the sampling capacitor is connected to the input signal, and the upper plate is connected to Vcm. According to the highest bit of the calibration code, judge whether the conversion capacitance weight of the LSB array increases or decreases due to the parasitic capacitance of the bridging capacitor and the parasitic capacitance of the LSB array. If the highest bit of the calibration code is 1, it means that the conversion weight decreases, and the lower plates of the P_CAL capacitor array and the highest-bit capacitor Cp1 and Cn1 of the MSB are connected to Vrefp. If the highest bit of the calibration code is 0, the conversion weight increases, and the lower plates of the N_CAL capacitor array and the highest-bit capacitor Cp1 and Cn1 of the MSB are connected to Vrefp. The remaining capacitors are all connected to Vrefn. In the conversion stage, switch T1 is open and T2 is closed. The upper plates of the positive and negative sampling capacitors are connected together, and charge redistribution occurs on the upper and lower plates of the sampling capacitors for the first comparison. According to the result of the first comparison, switch the first conversion capacitor. If the result of the first comparison is OUTN > OUTP, the highest bit is 0, and switch the Cp1 capacitor to connect to Vrefn before the next comparison. Conversely, if OUTN < OUTP, the highest bit is 1, and switch the Cn1 capacitor to connect to Vrefn before the next comparison. After charge redistribution, the second comparison is carried out. ...... Switch the Mth conversion capacitor according to the result of the Mth comparison; if the result of the Mth comparison is OUTN > OUTP, the Mth bit is 0, and switch Cn before the next comparison M Connect the capacitor to Vrefp; conversely, if OUTN < OUTP, the Mth bit is 1, and switch Cp before the next comparison M Connect the capacitor to Vth M + 1 comparison after charge redistribution According to the result of the second comparison, switch the second conversion capacitor. If the result of the second comparison is OUTN > OUTP, the second-highest bit is 0, and switch the Cn2 capacitor to connect to Vrefp before the next comparison. Conversely, if OUTN < OUTP, the second-highest bit is 1, and switch the Cp2 capacitor to connect to Vrefp before the next comparison. After charge redistribution, the third comparison is carried out. Switch the (M + 1)-th conversion capacitor according to the result of the (M + 1)-th comparison; if the result of the (M + 1)-th comparison is OUTN > OUTP, the (M + 1)-th bit is 0, and switch Cn before the next comparison M+1 , Cp M+1 Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(1); conversely, if OUTN < OUTP, the (M + 1)-th bit is 1, and switch Cp before the next comparison M+1 Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(1), and perform the (M + 2)-th comparison after charge redistribution; Switch the (M + 2)-th conversion capacitor according to the result of the (M + 2)-th comparison; if the result of the (M + 2)-th comparison is OUTN > OUTP, the (M + 2)-th bit is 0, and switch Cn before the next comparison M+2 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(2); conversely, if OUTN < OUTP, the (M + 2)-th bit is 1, and switch Cp before the next comparison M+2 Connect the capacitor to Vrefp, and simultaneously switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(2), and perform the (M + 3)-th comparison after charge redistribution; ...... Switch the (M + L - 1)-th conversion capacitor according to the result of the (M + L - 1)-th comparison; if the result of the (M + L - 1)-th comparison is OUTN > OUTP, the (M + L - 1)-th bit is 0, and switch Cn before the next comparison M+L-1 Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(L - 1); conversely, if OUTN < OUTP, the (M + L - 1)-th bit is 1, and switch Cp before the next comparison M+L-1 Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(L - 1), and perform the (M + L)-th comparison after charge redistribution; Switch the (M + L)-th conversion capacitor according to the result of the (M + L)-th comparison; if the result of the (M + L)-th comparison is OUTN > OUTP, the (M + L)-th bit is 0, and switch Cn before the next comparison M+L Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of N_CAL according to the LSB weight calibration code WN_CAL(L); conversely, if OUTN < OUTP, the (M + L)-th bit is 1, and switch Cp before the next comparison M+L Connect the capacitor to Vrefp, and at the same time switch the corresponding calibration capacitor of P_CAL according to the LSB weight calibration code WP_CAL(L), and perform the (M + L + 1)-th comparison after charge redistribution; So far, the conversion of the high-segment capacitor array is completed, and the high (M + 1)-bit digital code is obtained.

8. An application of an asymmetric parasitic calibration segmented capacitance array according to claims 1-7, characterized in that, After the result of the (M + L + 1)-th comparison is obtained, the conversion of the (M + L + 1)-bit digital code is completed. The asymmetric parasitic calibration segmented capacitor array is applied to a high-precision successive approximation analog-to-digital converter.

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