Analog-to-digital converter and method of increasing bandwidth of an analog-to-digital converter

Abstract

The application provides an analog-digital converter, a method for improving bandwidth of the analog-digital converter and an electronic device, and relates to the technical field of signal processing. A dynamic amplifier and a time-to-digital converter are added in the SAR ADC. The first input end of the dynamic amplifier is coupled with a capacitor array, the second input end of the dynamic amplifier is coupled with a comparator, and the output end of the dynamic amplifier is coupled with the time-to-digital converter. When the comparator enters a metastable state, the dynamic amplifier receives a control signal sent by the comparator, converts an input analog electric signal into a time sequence signal with time, and then converts the time sequence signal into a digital signal through the time-to-digital converter, so that higher resolution is obtained at the same time, that is, the conversion speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more particularly to an analog-to-digital converter, a method for increasing the bandwidth of an analog-to-digital converter, and an electronic device. Background Technology

[0002] An analog-to-digital converter (ADC) is a converter that transforms analog signals into digital signals. Successive approximation register (SAR) ADCs are used for medium to high-resolution applications with sampling rates below 5 Msps (millions of samples per second). In each conversion process, all quantized values ​​are iterated and converted to analog values, and the input signal is compared with each of these analog values ​​to obtain the final digital output signal. Due to their low power consumption and small size, SAR ADCs are widely used in various electronic devices. However, the single-channel bandwidth of existing SAR ADCs, which is half the Nyquist sampling rate, is insufficient to meet the high bandwidth / multi-mode direct sampling requirements of current wireless and optical communications. Therefore, improving the single-channel bandwidth of SAR ADCs is a pressing issue that needs to be addressed. Summary of the Invention

[0003] To address the aforementioned issues, embodiments of this application provide an analog-to-digital converter, a method for increasing the bandwidth of an analog-to-digital converter, and an electronic device. In this analog-to-digital converter, after the comparator enters a metastable state, the SAR logic circuit stops working. The dynamic amplifier acquires the residual voltage and converts the input residual voltage into a timing signal. Then, a time-to-digital converter converts the timing information into a digital signal to obtain LSB information, achieving higher resolution within the same time frame, i.e., increasing the conversion speed of the SAR ADC, thereby increasing the single-channel bandwidth of the SAR ADC.

[0004] Therefore, the following technical solutions are adopted in the embodiments of this application:

[0005] In a first aspect, embodiments of this application provide an analog-to-digital converter, comprising: an analog signal input terminal, a capacitor array, a comparator circuit, a dynamic amplifier, and a time-to-digital converter; the capacitor array is coupled between the analog signal input terminal and a first output terminal of the comparator circuit; the input terminal of the comparator circuit is coupled to the analog signal input terminal, the first output terminal of the comparator circuit is coupled to a control terminal of the capacitor array, and the second output terminal of the comparator circuit is coupled to a control terminal of the dynamic amplifier; the comparator circuit is configured to generate a comparison signal based on the analog signal received at the analog signal input terminal and output it to the capacitor array through the first output terminal, and to generate a first control signal based on the analog signal and output it to the dynamic amplifier through the second output terminal; the first control signal is configured to enable the dynamic amplifier to operate, and the comparison signal is configured to generate a first portion of a digital signal; the input terminal of the dynamic amplifier is coupled to the analog signal input terminal, and the output terminal of the dynamic amplifier is coupled to the input terminal of the time-to-digital converter; the output terminal of the time-to-digital converter is configured to output a second portion of a digital signal.

[0006] In this embodiment, a dynamic amplifier and a time-to-digital converter are added to the SAR ADC. The first input terminal of the dynamic amplifier is coupled to a capacitor array, the second input terminal is coupled to a comparator, and the output terminal is coupled to the time-to-digital converter. When the comparator enters a metastable state, the dynamic amplifier receives the control signal sent by the comparator, converts the input analog electrical signal into a time-series signal, and then converts the time-series signal into a digital signal through the time-to-digital converter. This achieves higher resolution in the same amount of time, thus increasing the conversion speed of the SAR ADC and thereby increasing the single-channel bandwidth of the SAR ADC.

[0007] In one embodiment, the system further includes a successive approximation register-type SAR logic circuit, wherein the input terminal of the SAR logic circuit is coupled to the first output terminal of the comparator circuit, the first output terminal of the SAR logic circuit is coupled to the control terminal of the capacitor array, the second output terminal of the SAR logic circuit is used to output a second control signal, the second output terminal of the SAR logic circuit is used to output the first part of the digital signal, and the second control signal is used to enable the capacitor array to operate.

[0008] In one embodiment, the comparator circuit is configured to generate the first control signal based on whether the difference between the analog signals received at the analog signal input terminal is less than a set threshold, and when the difference between the analog signals is less than the set threshold.

[0009] In one embodiment, the comparator circuit includes a clock signal input terminal, a comparator, a delay circuit, and a flip-flop; the first input terminal of the comparator is coupled to the analog signal input terminal, the second input terminal of the comparator is coupled to the clock signal input terminal, and the output terminal of the comparator is coupled to the output terminal of the SAR logic circuit and the first input terminal of the flip-flop, respectively. The comparator is used to generate the comparison signal based on the clock signal input terminal and the analog signal received at the analog signal input terminal; the delay circuit is coupled between the clock signal input terminal and the second input terminal of the flip-flop; the input terminal of the flip-flop is coupled to the control terminal of the dynamic amplifier, and the input terminal of the flip-flop is used to output the first control signal.

[0010] In one embodiment, the comparator includes a first MOSFET M1, a second MOSFET M2, a first inverter, a second inverter, and a logic device. The sources of the first MOSFET M1 and the second MOSFET M2 are coupled to a first power input terminal, the drains of the first MOSFET M1 and the second MOSFET M2 are grounded, and the gates of the first MOSFET M1 and the second MOSFET M2 are coupled to the analog signal input terminal. The input terminal of the first inverter is coupled between the first power input terminal and the source of the first MOSFET M1, the input terminal of the second inverter is coupled between the first power input terminal and the source of the second MOSFET M2, the output terminals of the first inverter and the second inverter are coupled to the input terminal of the logic device, and the output terminal of the logic device is used to output the comparison signal.

[0011] In one embodiment, the comparator further includes a third MOSFET M7, a fourth MOSFET M8, a fifth MOSFET M9, and a sixth MOSFET M10; the source of the third MOSFET M7 is coupled between the first power input terminal and the first inverter, and the source of the fourth MOSFET M8 is coupled between the first power input terminal and the second inverter; the source of the fifth MOSFET M9 is coupled to the drain of the first MOSFET M1 and the drain of the second MOSFET M2, and the drain of the fifth MOSFET M9 is grounded; the sixth MOSFET M10 is coupled between the source of the first MOSFET M1 and the source of the second MOSFET M2; the gates of the third MOSFET M7, the fourth MOSFET M8, the fifth MOSFET M9, and the sixth MOSFET M10 are respectively coupled to the clock signal input terminal.

[0012] In one embodiment, the delay circuit is used to generate a second clock signal based on the clock signal received at the clock signal input terminal, wherein the second clock signal is a clock signal that is delayed by a set time from the clock signal received at the clock signal input terminal.

[0013] In one embodiment, the trigger is used to generate the first control signal based on the comparison signal and the second clock signal.

[0014] In one embodiment, the dynamic amplifier includes a first switching circuit, a second switching circuit, a first MOSFET, a second MOSFET, and a current source; one end of the first switching circuit is coupled to a second power input terminal, the other end of the first switching circuit is coupled to the source of the first MOSFET, and the other end of the second switching circuit is coupled to the source of the second MOSFET; the drains of the first MOSFET and the second MOSFET are coupled to one end of the current source, and the other end of the current source is grounded; the gates of the first MOSFET and the second MOSFET are coupled to the analog signal input terminal.

[0015] In one embodiment, the dynamic amplifier further includes a first capacitor and a second capacitor; one end of the first capacitor is coupled between the first switching circuit and the first MOSFET, and the other end of the first capacitor is grounded; one end of the second capacitor is coupled between the second switching circuit and the second MOSFET, and the other end of the second capacitor is grounded.

[0016] In one embodiment, the dynamic amplifier is used to disconnect the first switching circuit and the second switching circuit according to the first control signal sent by the comparator circuit.

[0017] Secondly, embodiments of this application provide a method for converting an analog signal to a digital signal, comprising: a comparator circuit generating a first control signal based on a first analog signal and outputting it to a dynamic amplifier; the dynamic amplifier receiving the first control signal converting the first analog signal into a second analog signal, the second analog signal carrying time information; and a time-to-digital converter receiving the second analog signal and converting the second analog signal into a digital signal.

[0018] In one embodiment, the method further includes: the comparator circuit receiving a clock signal; the comparator circuit generating a first control signal based on a first analog signal and outputting it to a dynamic amplifier, specifically including: the comparator circuit generating the first control signal based on the clock signal and the first analog signal.

[0019] In one embodiment, the method further includes: the comparator circuit generating a comparison signal based on the first analog signal and the clock signal, and outputting it to a successive approximation register-type SAR logic circuit; the SAR logic circuit receiving the comparison signal and generating a digital signal based on the comparison signal.

[0020] Thirdly, embodiments of this application provide an electronic device, comprising: an analog circuit for generating an analog signal; a clock circuit for generating a clock signal; at least one analog-to-digital converter as may be implemented in the first aspect, for receiving the analog signal and the clock signal and converting the analog signal into a digital signal; and a digital circuit for receiving the digital signal and processing it. Attached Figure Description

[0021] The accompanying drawings used in the description of the embodiments or prior art are briefly introduced below.

[0022] Figure 1 This is a schematic diagram of the structure of an existing SAR ADC;

[0023] Figure 2 This is a schematic diagram of the structure of a SAR ADC provided in the embodiments of this application;

[0024] Figure 3 This is a schematic diagram of the specific structure of a SAR ADC provided in the embodiments of this application;

[0025] Figure 4 This is a schematic diagram of a comparator circuit provided in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of a comparator provided in an embodiment of this application;

[0027] Figure 6 The simulation graph shows the relationship between the discharge time of capacitor C and the voltage difference before and after discharge.

[0028] Figure 7 A schematic diagram comparing the performance of two existing SAR ADCs with that of the SAR ADC protected in this application;

[0029] Figure 8 This is a flowchart illustrating a method for improving the bandwidth of a SAR ADC provided in an embodiment of this application;

[0030] Figure 9 This is a schematic diagram of the frame of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0032] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0033] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0034] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0035] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0036] Figure 1 This is a schematic diagram of the structure of an existing SAR ADC. Figure 1 As shown, the SAR ADC mainly includes a capacitor array, a comparator, and SAR logic circuitry.

[0037] In practical applications, the capacitor array reacts to the input analog signal V. IN Sampling is performed, and the analog input voltage V is output after sampling is complete. IN and analog output voltage V OUT Analog input voltage V OUTN and analog output voltage V OUTP The inputs are respectively fed to the positive and negative input terminals of the comparator. The comparator accepts the analog input voltage V. OUTN and analog output voltage V OUTP The comparison is performed, and a comparison signal V is generated. comp If the analog input voltage V OUTN Greater than the analog output voltage V OUTP The comparator outputs a comparison signal V. compIt is either a logic high level or "1"; if the analog input voltage V OUTN Less than the analog output voltage V OUTP The comparator outputs a comparison signal V. comp It is a logic low level or "0".

[0038] The clock signal clk serves as the enable signal, controlling the output update of the comparator and SAR logic circuit. When the clock signal clk is in the most significant bit (MSB) stage, the comparator updates the analog input voltage V. OUTN and analog output voltage V OUTP Compare and output comparison signal V comp The SAR logic circuit uses the comparison signal V comp After setting the bit once, the bit is shifted to the second most significant bit, preparing for the next comparison. This process continues until the clock signal clk reaches the least significant bit (LSB), completing the conversion. After the entire successive comparison process is complete, the SAR ADC completes one analog-to-digital conversion and outputs the corresponding digital code.

[0039] To improve the single-channel bandwidth of SAR ADCs, the following solutions have been proposed in the existing technology:

[0040] 1. Multi-bit synchronous comparison technology. In SAR ADC, setting 2... N Multiple comparators are used simultaneously during the comparison process in the SAR ADC. In this scheme, the SAR ADC sampling rate reaches N bit / cycle, which reduces the number of SAR conversions and improves the single-channel bandwidth of the SAR ADC. However, setting 2 in the SAR ADC... N Two comparators were added, increasing the number of comparators by 2. N The -1 comparator makes the SAR ADC consume a relatively large amount of power.

[0041] 2. Loop-unroll technique. In a SAR ADC, N comparators are configured. During comparison, each bit uses one comparator. After a comparator completes a comparison, it is not reset; the next comparator is started immediately. This process saves time waiting for comparator resets, thus increasing the single-channel bandwidth of the SAR ADC. However, with technological advancements and improved manufacturing processes, comparator reset times have become increasingly shorter, so this approach is no longer effective in improving the single-channel bandwidth of the SAR ADC.

[0042] 3. Phase-Switch Techniques. Traditional SAR ADCs require N phase transitions to achieve N-bit accuracy. To improve the comparison time of a SAR ADC, multiple phases can be skipped by judging other conditions, directly obtaining the final quantization result. This technique is collectively known as phase-switch techniques. Taking metastability detection as an example, in a comparison, if the comparator enters a metastable state, it can be assumed that the residual input voltage has converged to a very small range, and the quantization result has been obtained, allowing the remaining phases to be skipped. However, if metastability does not occur or the metastability detection is incorrect, the comparison time of the SAR ADC cannot be improved, thus failing to increase the single-channel bandwidth of the SAR ADC. Metastability refers to a state where the voltages at the two input terminals of the comparator are very close, causing the comparator to require a long time to output the comparison signal.

[0043] To address the problems existing in current SAR ADCs, embodiments of this application provide a novel SAR ADC. For example... Figure 2 As shown, the SAR ADC includes a capacitor array 210, a comparator circuit 220, a SAR logic circuit 230, a dynamic amplifier 240, and a time-to-digital converter 250. The newly added dynamic amplifier 240 is connected to both input terminals of the comparator circuit 220 and is connected in parallel with the comparator circuit 220. The comparator circuit 220 determines whether the clock signal clk is in the MSB phase, that is, whether the SAR ADC is in the MSB phase. When the SAR ADC is in the MSB phase, the comparator circuit 220 compares the residual voltages received at the two input terminals and outputs a comparison signal V. comp The SAR logic circuit 230 compares the signal V... comp After completing one set operation, the bit is shifted to the second-highest bit, generating a control signal and sending it to capacitor array 210, preparing for the next comparison. SAR logic circuit 230 will also compare the signal V... comp The analog signal is converted to a digital signal, and the corresponding digital code is output. When the comparator circuit 220 detects that the difference between the residual voltages at the two input terminals is small, it determines that the system has entered a metastable state. The comparator circuit 220 then controls the SAR logic circuit 230 to stop operating. The comparator circuit 220 sends a control signal to the dynamic amplifier 240, causing the dynamic amplifier 240 to operate.

[0044] The dynamic amplifier 240 converts the input residual voltage into a timing signal, which is then input to the time-to-digital converter 250. Upon receiving two timing signals, the time-to-digital converter 250 measures the time interval between them and converts the time information corresponding to the time interval into a digital signal to obtain the LSB information. It then outputs the digital code corresponding to the analog quantity. In the SAR ADC designed in this application, after the comparator enters a metastable state, the SAR logic circuit stops working. The dynamic amplifier acquires the residual voltage and converts it into a timing signal. The time-to-digital converter then converts this timing signal into a digital signal to obtain the LSB information. This achieves higher resolution within the same time frame, thus increasing the conversion speed of the SAR ADC and consequently improving the single-channel bandwidth of the SAR ADC.

[0045] Figure 3 This is a schematic diagram of the specific structure of a SAR ADC provided in an embodiment of this application. Figure 3 As shown, the SARADC includes a capacitor array 210, a comparator circuit 220, a SAR logic circuit 230, a dynamic amplifier 240, and a time-to-digital converter 250.

[0046] The capacitor array 210 samples and holds the analog signal to obtain two voltage signals, namely the first voltage signal V1 and the second voltage signal V2. Then, the first voltage signal V1 and the second voltage signal V2 are respectively input to the two input terminals of the comparator circuit 220.

[0047] like Figure 3 As shown, the capacitor array 210 provided in this application includes two input paths. The input circuit inputs a voltage signal to the input terminal of the comparator circuit 220. The input path is connected to the negative reference voltage V. refn Circuit or positive reference voltage V refp Four capacitors C are connected in parallel across the circuit. Each capacitor C is connected to a negative reference voltage V. refn Circuit or positive reference voltage V refp A switching circuit S is electrically connected between the circuits. The SAR logic circuit 230 uses the comparison signal V output by the comparator circuit 220. comp The system generates control signals and sends them to the capacitor array 210 to control each switching circuit and select the input circuit and the negative reference voltage V. refn Electrical connection of the circuit, or the input circuit and the positive reference voltage V refp Electrical circuit connection.

[0048] The operation of the capacitor array 210 can be divided into three stages: sampling stage, holding stage, and charge redistribution stage. The specific implementation process is as follows:

[0049] 1. Sampling stage. The capacitor array 210 can control the switching circuit S. 11 and switching circuit S 21 When closed, the first voltage signal V1 and the second voltage signal V2 are directly input to the two input terminals of the comparator circuit 220. In input circuit 1, the SAR logic circuit 230 can control the switching circuit S. 12 -S 15 Closed, input circuit 1 and negative reference voltage V refn Electrical circuit connection. Capacitor C. 11 -C 14 After the circuit is connected, the stored charge is Q1 = C. 1总 ×(V1-V refn ),C 1总 =C 11 +C 12 +C 13 +C 14 In input circuit 2, SAR logic circuit 230 can control switching circuit S. 22 -S 25 Closed, input circuit 2 is connected to the positive reference voltage V refp Circuit electrical connection, capacitor C 21 -C 24 After the circuit is connected, the stored charge is Q2 = C. 2总 ×(V2-V refp ),C 2总 =C 21 +C 22 +C 23 +C 24 .

[0050] 2. Holding phase. The capacitor array 210 can control the switching circuit S. 11 and switching circuit S 21 When closed, the first voltage signal V1 and the second voltage signal V2 are directly input to the two input terminals of the comparator circuit 220. In input circuit 1, the SAR logic circuit 230 can control the switching circuit S. 12 -S 15 Disconnect, capacitor C 11 -C 14 The stored charge is Q1 = C 1总 ×V1,C 1总 =C 11 +C 12 +C 13 +C 14 In input circuit 2, SAR logic circuit 230 can control switching circuit S. 22 -S 25 Disconnect, capacitor C 21 -C 24The stored charge is Q2 = C 1总 ×V2,C 2总 =C 21 +C 22 +C 23 +C 24 .

[0051] 3. Charge redistribution stage. After completing the "sampling stage" and "holding stage", the capacitor array 210 can redistribute the charge based on the comparison signal V from the comparator circuit 220. cmp =V1-V2, quantizing the comparison signal. Specifically: during the first comparison, if the comparison signal V... cmp1 A value greater than 0 indicates that the first voltage signal V1 is greater than the second voltage signal V2. Therefore, the SAR logic circuit 230 sends a high level or a "1" to each switching circuit. At this time, the SAR logic circuit 230 can control the switching circuit S. 12 -S 15 Disconnect, input circuit 1 and reference voltage V ref The circuit is open, that is, the capacitor C on input circuit 1 is disconnected. 11 -C 14 Grounding (GND); SAR logic circuit 230 can control the switching circuit S. 22 -S 25 Closed, input circuit 2 and negative reference voltage V refn The circuit is electrically connected, that is, the capacitor C on the input circuit 2. 21 -C 24 The other end is connected to the negative reference voltage V refn The circuit is electrically connected. If the comparison signal V... cmp1 A value less than 0 indicates that the first voltage signal V1 is less than the second voltage signal V2. Therefore, the SAR logic circuit 230 sends a low level or "0" to each switching circuit. At this time, the SAR logic circuit 230 can control the switching circuit S. 12 -S 15 Closed, input circuit 1 is connected to the positive reference voltage V refp The circuit is electrically connected, that is, the capacitor C on input circuit 1. 11 -C 14 The other end is connected to the positive reference voltage V refp Electrical circuit connections; SAR logic circuit 230 can control the switching circuit S 22 -S 25 Disconnect the input circuit 2 from the reference voltage V. ref The circuit is open, that is, the capacitor C on input circuit 1 is disconnected. 21 -C 24 Ground (GND).

[0052] After the first comparison is completed, the charge is redistributed again, and the comparator circuit 220 outputs a comparison signal V. cmp2The comparison signal V in the first comparison cmp1 Increase or decrease by 1 / 2 of the reference voltage V ref That is, increasing or increasing the reference voltage V ref Multiply by the proportion of the capacitance value participating in this quantization to the total capacitance.

[0053] During the second comparison, if the comparison signal V cmp2 A value greater than 0 indicates that the first voltage signal V1 is greater than the second voltage signal V2. Therefore, the SAR logic circuit 230 sends a high level or a "1" to each switching circuit. At this time, the SAR logic circuit 230 can control the switching circuit S. 13 -S 15 Disconnect, input circuit 1 and reference voltage V ref The circuit is open, that is, the capacitor C on input circuit 1 is disconnected. 12 -C 14 Grounding (GND); SAR logic circuit 230 can control the switching circuit S. 23 -S 25 Closed, input circuit 2 and negative reference voltage V refn The circuit is electrically connected, that is, the capacitor C on the input circuit 2. 22 -C 24 The other end is connected to the negative reference voltage V refn The circuit is electrically connected. If the comparison signal V... cmp2 A value less than 0 indicates that the first voltage signal V1 is less than the second voltage signal V2. Therefore, the SAR logic circuit 230 sends a low level or "0" to each switching circuit. At this time, the SAR logic circuit 230 can control the switching circuit S. 13 -S 15 Closed, input circuit 1 is connected to the positive reference voltage V refp The circuit is electrically connected, that is, the capacitor C on input circuit 1. 12 -C 14 The other end is connected to the positive reference voltage V refp Electrical circuit connections; SAR logic circuit 230 can control the switching circuit S 23 -S 25 Disconnect the input circuit 2 from the reference voltage V. ref The circuit is open, that is, the capacitor C on input circuit 1 is disconnected. 22 -C 24 Ground (GND).

[0054] After the second comparison is completed, the charge is redistributed again, and the comparator circuit 220 outputs a comparison signal V. cmp3 The comparison signal V in the second comparison cmp2 Increase or decrease by 1 / 4 of the reference voltage V ref This process is repeated until the quantization of the signal at that level is complete.

[0055] After receiving the clock signal clk, comparator circuit 220 can determine whether it is in the MSB (Maximum Segment Bus) phase by checking the timing of its own signals. When comparator circuit 220 determines that the clock signal clk is in the MSB phase, it compares the received first voltage signal V1 and second voltage signal V2, and outputs a comparison signal V. comp .

[0056] like Figure 4 As shown, this application provides a comparator circuit 220, which includes a comparator 221, a delay module 222, and a flip-flop 223. Input terminals 1 and 2 of the comparator 221 are electrically connected to the two output terminals of the capacitor array 210, respectively. One input terminal 3 of the comparator 221 is electrically connected to an external clock circuit, and the output terminal 4 of the comparator 221 is electrically connected to the SAR logic circuit 230 and one input terminal 7 of the flip-flop 223. When the clock signal input from the external clock circuit is in the MSB phase, the comparator 221 compares the received first voltage signal V1 with the second voltage signal V2 and outputs a comparison signal V. comp .

[0057] Normally, when the relationship between the first voltage signal V1 and the second voltage signal V2 is V1-V2>0, the comparator 221 outputs a comparison signal V. comp It is either a logic high level or "1". When the relationship between the first voltage signal V1 and the second voltage signal V2 is V1-V2<0, the comparator 221 outputs a comparison signal V. comp The logic level is low or "0". When the first voltage signal V1 and the second voltage signal V2 are very close, that is, the relationship between the first voltage signal V1 and the second voltage signal V2 is V1-V2≈0, the time required for comparator 221 to compare the first voltage signal V1 and the second voltage signal V2 will be longer than in other cases. If comparator 221 cannot give a judgment result within a specified time, comparator 221 enters a "metastable" state. In addition, after entering the metastable state, comparator circuit 220 locks the first voltage signal V1 and the second voltage signal V2 to fix the high bit information, so as to provide a stable electrical signal for dynamic amplifier 240.

[0058] For example, such as Figure 5As shown, in the comparator 221, the sources of MOSFETs M1 and M2 are connected to the power supply, and the drains of MOSFETs M1 and M2 are connected to the source of MOSFET M9, with the drain of MOSFET M9 grounded. The gates of transistors M1 and M2 are electrically connected to the two output terminals of capacitor array 210, respectively, to receive the first voltage signal V1 and the second voltage signal V2. The input terminal of the first inverter is coupled between the power supply and the source of MOSFET M1, and the input terminal of the second inverter is coupled between the power supply and the source of MOSFET M2. The output terminals of the first and second inverters are coupled to the input terminals of an OR logic device, and the output terminal of the OR logic device is used to output the comparison signal. The source of MOSFET M7 is coupled between the power supply and the first inverter, and the source of MOSFET M8 is coupled between the power supply and the second inverter. MOSFET M10 is coupled between the sources of MOSFETs M1 and M2. The gates of MOSFETs M7, M8, M9, and M10 are connected to an external clock circuit. When the difference between the first voltage signal V1 and the second voltage signal V2 received by comparator 221 is greater than a set threshold, one of the electrical signals Von and Vop input to the OR logic device is high or "1", or the comparison signal output by the logic device is high or "1". When the difference between the first voltage signal V1 and the second voltage signal V2 received by comparator 221 is not greater than the set threshold, that is, when the two voltage signals are close, both the electrical signals Von and Vop input to the OR logic device are low or "0", or the comparison signal output by the logic device is low or "0".

[0059] The delay module 222 is generally composed of one or more inverters. Its input terminal 5 is electrically connected to an external clock circuit, and its output terminal 6 is electrically connected to the input terminal 8 of the flip-flop 223. It is used to delay the clock signal clk by a set time and then input it into the flip-flop 223.

[0060] A flip-flop 223 is an electronic component that can store circuit states. The circuit structure of a flip-flop 223 is generally composed of logic gates, used to handle the interaction between input signals, output signals, and clock frequency. In this application, input terminals 7 and 8 of the flip-flop 223 receive a comparison signal V. comp After the clock signal clk with the set delay time, the comparison signal V will be... comp The comparison signal V output by comparator 221 is compared with the rising edge of the clock signal clk, which has a set delay time. compThe trigger signal is valid at the trigger moment. When the output signal is valid at the trigger moment, it indicates that comparator 221 has not entered a metastable state, and trigger 223 outputs a high level; when the output signal is invalid at the trigger moment, it indicates that comparator 221 has entered a metastable state, and trigger 223 outputs a low level. The signal output from terminal 9 of trigger 223, which is also the control signal, is input to dynamic amplifier 240.

[0061] When comparator 221 is in a metastable state, the comparison signal V input to the SAR logic circuit 230 is... comp This can stop the SAR logic circuit 230 from operating. The SAR logic circuit 230 stops operating after the comparator 221 enters a metastable state, which reduces the number of transition phases and effectively increases the transition speed of the SAR logic circuit 230. The trigger 223 sending a control signal to the dynamic amplifier 240 can reset the dynamic amplifier 240.

[0062] During the period when comparator circuit 220 enters metastable state, SAR ADC 200 has no digital signal output. To improve the digital signal output of SAR ADC 200, SAR ADC 200 quantizes the input voltage of comparator circuit 220 during the metastable state period in the time domain to obtain LSB information, thereby increasing the sampling rate of SAR ADC 200 and improving the single-channel bandwidth of SAR ADC 200.

[0063] SAR logic circuit 230 is used to receive the clock signal clk from the external clock circuit and the comparison signal V from the comparator 220. comp The system generates a control signal and inputs it to the capacitor array 210, controlling the switching circuits in the capacitor array 210 to turn on or off, thereby controlling the capacitor array 210 to enter the sampling phase, holding phase, and charge redistribution phase. In this application, the SAR logic circuit 230 receives the comparison signal V input from the comparator 220. comp After that, the comparison signal V can also be used. comp The signal is converted into a digital signal, and the corresponding digital code is output, thus converting the analog signal into a digital signal. Since the SAR logic circuit 230 used in this application is a conventional SAR logic circuit, it will not be described in detail here.

[0064] After receiving the control signal, the dynamic amplifier 240 receives the first voltage signal V1 and the second voltage signal V2 output by the capacitor array 210, converts the first voltage signal V1 and the second voltage signal V2 into timing signals with time, and then inputs them into the time-to-digital converter 250.

[0065] like Figure 3As shown, this application provides a dynamic amplifier 240, which includes two metal-oxide-semiconductor field-effect transistors (MOSFETs) (Mos1, Mos2) and two capacitors (C). sp C sm ) and two switching circuits (S sp S sm Switching circuit S sp With switching circuit S sm They are connected in series. Switching circuit S sp The other end is connected to capacitor C sp After electrical connection, ground (GND). Switching circuit S sm The other end is connected to capacitor C sm After electrical connection, ground (GND) is established. The gate of transistor Mos1 is connected to input circuit 1, and the source of transistor Mos1 is electrically connected to switching circuit S. sp With capacitor C sp Between them, the drain of transistor Mos1 is grounded to GND. The gate of transistor Mos2 is connected to input circuit 2, and the source of transistor Mos2 is electrically connected to switching circuit S. sm With capacitor C sm Between them, the drain of transistor Mos2 is grounded to GND.

[0066] After receiving the control signal, the dynamic amplifier 240 controls the switching circuit S. sp With switching circuit S sm Opening or closing, and allowing the first voltage signal V1 and the second voltage signal V2 to be respectively passed into capacitor C. sp and capacitor C sm The gate allows the dynamic amplifier 240 to sequentially perform the reset phase, amplification phase, and sampling phase. Specifically:

[0067] During the reset phase, the switching circuit S sp With switching circuit S sm When closed, transistor Mos1 is not supplied with the first voltage signal V1, and the gate of transistor Mos2 is not supplied with the second voltage signal V2. Capacitor C sp and capacitor C sm Both ends are reset to the set voltage level, denoted as the set voltage V. sp and set voltage V sm .

[0068] During the amplification stage, the dynamic amplifier 240 can enable the switching circuit S sp With switching circuit S smWhen the transistor is disconnected, transistor Mos1 is supplied with the first voltage signal V1, and the gate of transistor Mos2 is supplied with the second voltage signal V2. Current source Is provides current for the amplification stage. The current source can be coupled to capacitor C through transistor Mos1. sp The current source can be coupled to capacitor C through transistor Mos2. sm Capacitor C sp and capacitor C sm Discharge, set voltage V sp and set voltage V sm The voltage level drops. When the set voltage V sp and set voltage V sm The amplification phase ends when the common-mode voltage reaches the set common-mode voltage difference.

[0069] After the amplification stage, the sampling stage begins. The dynamic amplifier 240 acquires the capacitance C. sp and capacitor C sm The voltage after discharge is denoted as the sampling voltage ΔV. sp and sampling voltage ΔV sm The dynamic amplifier 240 is based on the capacitor C. sp and capacitor C sm Voltage difference and capacitance C before and after discharge sp and capacitor C sm The discharge time determines the capacitance C. sp Discharge time and capacitance C sp The change in voltage difference before and after discharge, also known as the timing signal S. p and capacitor C sm Discharge time and capacitance C sm The change in voltage difference before and after discharge, also known as the timing signal S. m Subsequently, the dynamic amplifier 240 will output the timing signal S p and timing signal S m Send time-to-time converter 250.

[0070] Figure 6 This is a simulation graph showing the relationship between the discharge time of capacitor C and the voltage difference before and after discharge. (Example:) Figure 6 As shown, when the dynamic amplifier 240 sends a signal to the switching circuit S sp and switching circuit S sm When sending the RST signal, the switching circuit S sp and switching circuit S sm When closed, dynamic amplifier 240 is in the reset phase. When dynamic amplifier 240 sends a signal to switching circuit S... sp and switching circuit S sm When the conv signal is sent, the switching circuit S sp and switching circuit S smWhen disconnected, dynamic amplifier 240 is in the amplification phase. At this time, the discharge time of capacitor C is linearly related to the voltage difference before and after capacitor C discharges.

[0071] The time-to-digital converter 250 receives the timing signal S sent by the dynamic amplifier 240. p and timing signal S m After that, the timing signal S can be measured. p With timing signal S m The time interval between them is then converted into a digital signal to obtain LSB information.

[0072] In the SAR ADC protected in this application, a dynamic amplifier and a time-to-digital converter are added. When the comparator enters the metastable state, the dynamic amplifier converts the input residual voltage into a timing signal with time. Then, the time-to-digital converter converts the timing signal into a digital signal to obtain LSB information, thereby achieving higher resolution in the same amount of time, that is, improving the sampling speed of the SAR ADC and increasing the single-channel bandwidth of the SAR ADC.

[0073] It should be noted that the structures of the capacitor array 210, comparator circuit 220, and dynamic amplifier 240 in the SAR ADC protected in this application are not limited to... Figure 3 The example shown can be of other structures; this application is merely an example. The number of capacitor array 210, comparator circuit 220, dynamic amplifier 240, and time-to-digital converter 250 in this application is not limited. Figure 3 One of them, or any number, is not limited hereby.

[0074] In one example, the number of capacitor array 210, comparator circuit 220, dynamic amplifier 240, and time-to-digital converter 250 are all N, where N is a positive integer greater than 2. Each capacitor array 210, comparator circuit 220, dynamic amplifier 240, and time-to-digital converter 250 can be configured as follows: Figure 3 The connections shown are made according to the given relationship. The output of each comparator circuit 220 is connected to the SAR logic circuit 230, which can be electrically connected to each capacitor array 210 to control each capacitor array 210.

[0075] In one example, there is one capacitor array 210, and N comparator circuits 220, dynamic amplifiers 240, and time-to-digital converters 250, where N is a positive integer greater than 2. The two inputs of each comparator circuit 220 are connected in parallel to the two outputs of the capacitor array 210, and the output of each comparator circuit 220 is connected to the SAR logic circuit 230. Each comparator circuit 220, dynamic amplifier 240, and time-to-digital converter 250 can be configured as follows: Figure 3 Connect according to the relationships shown.

[0076] Figure 7 This is a schematic diagram comparing the performance of two existing SAR ADCs with that of the SAR ADC protected in this application. Figure 7 The figure shows the resolution number and number of conversions for three SAR ADCs under the same accuracy conditions. Among them, Figure 7 (a) is an existing SAR ADC in which the comparator does not detect metastability during operation; Figure 7 (b) is an existing SAR ADC in which the comparator detects metastable states during operation; Figure 7 (b) is the SAR ADC protected in this application, in which a comparator detects metastability and a dynamic amplifier and a time-to-digital converter quantize the time domain during operation.

[0077] The SAR ADC protected in this application, compared to Figure 7 The SAR ADC shown in (a) reduces the number of phase transitions in the SAR logic circuit 230, thus improving the conversion speed; compared to Figure 7 (b) shows a SAR ADC that achieves higher resolution in the same amount of time, which can improve the conversion speed.

[0078] Table 1 shows the simulation results of various performance parameters of the three SAR ADCs. As can be seen from the results presented in Table 1, under the same effective bit count, the maximum sampling rate of the SAR ADC protected in this application is nearly doubled.

[0079] Table 1. Simulation results of various performance parameters of the three SAR ADCs

[0080]

[0081] Figure 8 This is a flowchart illustrating a method for improving the bandwidth of a SAR ADC provided in an embodiment of this application. Figure 8 As shown, the specific implementation process of this method is as follows:

[0082] In step S801, the comparator circuit generates a control signal based on the first analog signal and outputs it to the dynamic amplifier.

[0083] Prior to this, the capacitor array in the SAR ADC samples and holds the analog signal, resulting in two voltage signals: a first output signal and a second output signal. These two output signals are then input to the two input terminals of the comparator circuit, respectively. For detailed implementation details, please refer to [reference needed]. Figure 3 and Figure 3 The corresponding descriptions will not be elaborated upon here.

[0084] The comparator circuit in a SAR ADC determines whether it is in the MSB (Maximum Segment Bus) phase based on the timing of its internal clock signal clk. When the comparator circuit determines that it is in the MSB phase, it compares the received first and second output signals and outputs a comparison signal.

[0085] When the first output signal is greater than the second output signal, the comparator circuit outputs a logic high level or "1". When the first output signal is less than the second output signal, the comparator circuit outputs a logic low level or "0". When the first output signal is equal to or approximately equal to the second output signal, the comparator circuit takes a relatively long time to compare the first and second output signals. If the comparator circuit cannot provide a result within the specified time, the comparator enters a metastable state.

[0086] After entering a metastable state, the comparator circuit locks the first and second output signals to provide a stable signal for the dynamic amplifier. The comparator circuit then sends a comparison signal to the SAR logic circuit, stopping its operation and reducing the number of phase transitions. Subsequently, the comparator circuit sends a reset signal to the dynamic amplifier to de-reset it. For detailed implementation details, please refer to [reference needed]. Figures 4-5 and Figures 4-5 The corresponding descriptions will not be elaborated upon here.

[0087] In step S802, after receiving the control signal, the dynamic amplifier converts the first analog signal into a second analog signal.

[0088] This step is performed by the dynamic amplifier in the SAR ADC. Upon receiving the reset signal, the dynamic amplifier receives the first and second input electrical signals output from the capacitor array, converts them into timing signals, and then inputs them into the time-to-digital converter. For a detailed implementation process, please refer to [reference needed]. Figure 3 and Figure 3 The corresponding descriptions will not be elaborated upon here.

[0089] In step S803, after receiving the second analog signal, the time-to-digital converter converts the second analog signal into a digital signal.

[0090] This step is performed by the time-to-digital converter in the SAR ADC. After receiving the timing signal sent by the dynamic amplifier, the time-to-digital converter can measure the time interval between the timing signals, and then convert the time information corresponding to the time interval into a digital signal to obtain the LSB information.

[0091] In the method protected by this application, after the comparator enters the metastable state, the dynamic amplifier converts the first input electrical signal and the second input electrical signal into a timing signal with time. Then, the time information is converted into a digital signal by the time-to-digital converter to obtain LSB information, thereby achieving higher resolution in the same time, that is, improving the sampling speed of the SAR ADC and improving the single-channel bandwidth of the SAR ADC.

[0092] Figure 9 This is a schematic diagram of the framework of an electronic device provided in an embodiment of this application. Figure 9 As shown, the electronic device 900 includes an analog circuit 910, a clock circuit 920, a digital circuit 930, and at least one... Figures 2-8 And the SAR ADC 200 described in the corresponding protection scheme above.

[0093] Analog circuit 910 is used to generate analog signals to provide input electrical signals to capacitor array 210 in SAR ADC 200. Analog circuit 910 can be an analog sensor, or a component or device that includes an analog sensor.

[0094] Clock circuit 920 is used to generate a clock signal, providing clock signal clk to comparator circuit 220 and SAR logic circuit in SAR ADC 200. Clock circuit 920 can be an oscillator or a component including an oscillator.

[0095] Digital circuit 930 is used to process the digital signal output by SAR ADC 200. Digital circuit 930 can be various processors, transceivers, memories, etc.

[0096] Because electronic equipment 900 includes, for example Figures 2-8As described in the corresponding protection scheme above, the electronic device 900 possesses all or at least some of the advantages of the SAR ADC 200. The electrical device can be a set-top box, entertainment unit, navigation device, communication device, fixed location data unit, mobile location data unit, global positioning system (GPS) device, mobile phone, cellular phone, smartphone, session initialization protocol (SIP) phone, tablet computer, tablet phone, server, computer, portable computer, mobile computing device, wearable computing device (e.g., smartwatch, health or fitness tracker, glasses, etc.), desktop computer, personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio, satellite broadcasting, music player, digital music player, portable music player, digital video player, video player, digital video disc (DVD) player, portable digital video player, automobile, vehicle component, avionics system, drone, and multi-rotor aircraft.

[0097] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions in the embodiments of this application.

Claims

1. An analog-to-digital converter, characterized in that, include: Analog signal input terminal, capacitor array, comparator circuit, dynamic amplifier and time-to-digital converter; The capacitor array is coupled between the analog signal input terminal and the first output terminal of the comparator circuit; The input terminal of the comparator circuit is coupled to the analog signal input terminal, the first output terminal of the comparator circuit is coupled to the control terminal of the capacitor array, and the second output terminal of the comparator circuit is coupled to the control terminal of the dynamic amplifier. The comparator circuit is used to generate a comparison signal based on the analog signal received at the analog signal input terminal and output it to the capacitor array through the first output terminal. It is also used to output a first control signal generated by the analog signal to the dynamic amplifier through the second output terminal when the comparator circuit is detected to enter a metastable state. The first control signal is used to enable the dynamic amplifier to work, and the comparison signal is used to generate a first part of the digital signal. The input terminal of the dynamic amplifier is coupled to the analog signal input terminal and connected in parallel with the comparator circuit. The output terminal of the dynamic amplifier is coupled to the input terminal of the time-to-digital converter. It is used to convert the analog signal into an analog signal carrying time information upon receiving the first control signal output by the comparator circuit. The output of the time-to-digital converter is used to output the second part of the digital signal.

2. The analog-to-digital converter according to claim 1, characterized in that, Also includes: A successive approximation register-type SAR logic circuit is provided, wherein the input terminal of the SAR logic circuit is coupled to the first output terminal of the comparator circuit, the first output terminal of the SAR logic circuit is coupled to the control terminal of the capacitor array, the second output terminal of the SAR logic circuit is used to output a second control signal, the second output terminal of the SAR logic circuit is used to output the first part of the digital signal, and the second control signal is used to enable the capacitor array to work.

3. The analog-to-digital converter according to claim 1, characterized in that, The comparator circuit is used to generate the first control signal based on whether the difference between the analog signals received at the analog signal input terminal is less than a set threshold, and when the difference between the analog signals is less than the set threshold.

4. The analog-to-digital converter according to claim 2, characterized in that, The comparator circuit includes a clock signal input terminal, a comparator, a delay circuit, and a flip-flop; The first input terminal of the comparator is coupled to the analog signal input terminal, the second input terminal of the comparator is coupled to the clock signal input terminal, and the output terminal of the comparator is coupled to the output terminal of the SAR logic circuit and the first input terminal of the flip-flop, respectively. The comparator is used to generate the comparison signal based on the clock signal input to the clock signal input terminal and the analog signal received by the analog signal input terminal. The delay circuit is coupled between the clock signal input terminal and the second input terminal of the flip-flop; The output terminal of the trigger is coupled to the control terminal of the dynamic amplifier, and the output terminal of the trigger is used to output the first control signal.

5. The analog-to-digital converter according to claim 4, characterized in that, The comparator includes a first MOSFET M1, a second MOSFET M2, a first inverter, a second inverter, and / or logic devices. The source of the first MOSFET M1 and the source of the second MOSFET M2 are respectively coupled to the first power input terminal, the drain of the first MOSFET M1 and the drain of the second MOSFET M2 are respectively grounded, and the gate of the first MOSFET M1 and the gate of the second MOSFET M2 are respectively coupled to the analog signal input terminal. The input terminal of the first inverter is coupled between the first power input terminal and the source of the first MOS transistor M1, the input terminal of the second inverter is coupled between the first power input terminal and the source of the second MOS transistor M2, the output terminals of the first inverter and the second inverter are coupled to the input terminal of the OR logic device, and the output terminal of the OR logic device is used to output the comparison signal.

6. The analog-to-digital converter according to claim 5, characterized in that, The comparator also includes a third MOSFET M7, a fourth MOSFET M8, a fifth MOSFET M9, and a sixth MOSFET M10; The source of the third MOS transistor M7 is coupled between the first power input terminal and the first inverter, and the source of the fourth MOS transistor M8 is coupled between the first power input terminal and the second inverter. The source of the fifth MOS transistor M9 is coupled to the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2, and the drain of the fifth MOS transistor M9 is grounded; the sixth MOS transistor M10 is coupled between the source of the first MOS transistor M1 and the source of the second MOS transistor M2. The gates of the third MOS transistor M7, the fourth MOS transistor M8, the fifth MOS transistor M9, and the sixth MOS transistor M10 are respectively coupled to the clock signal input terminal.

7. The analog-to-digital converter according to any one of claims 4-6, characterized in that, The delay circuit is used to generate a second clock signal based on the clock signal received at the clock signal input terminal. The second clock signal is a clock signal that is delayed by a set time from the clock signal received at the clock signal input terminal.

8. The analog-to-digital converter according to claim 7, characterized in that, The trigger is used to generate the first control signal based on the comparison signal and the second clock signal.

9. The analog-to-digital converter according to any one of claims 1-6, characterized in that, The dynamic amplifier includes a first switching circuit, a second switching circuit, a first MOSFET Mos1, a second MOSFET Mos2, and a current source; One end of the first switching circuit and the other end of the first switching circuit are respectively coupled to the second power input terminal. The other end of the first switching circuit is coupled to the source of the first MOSFET Mos1, and the other end of the second switching circuit is coupled to the source of the second MOSFET Mos2. The drains of the first MOSFET Mos1 and the second MOSFET Mos2 are respectively coupled to one end of the current source, and the other end of the current source is grounded; the gates of the first MOSFET Mos1 and the second MOSFET Mos2 are respectively coupled to the analog signal input terminal.

10. The analog-to-digital converter according to claim 9, characterized in that, The dynamic amplifier also includes a first capacitor and a second capacitor; One end of the first capacitor is coupled between the first switching circuit and the first MOSFET Mos1, and the other end of the first capacitor is grounded; one end of the second capacitor is coupled between the second switching circuit and the second MOSFET Mos2, and the other end of the second capacitor is grounded.

11. The analog-to-digital converter according to claim 9, characterized in that, The dynamic amplifier is used to disconnect the first switching circuit and the second switching circuit according to the first control signal sent by the comparator circuit.

12. A method for converting analog signals to digital signals, characterized in that, include: When the comparator circuit enters a metastable state, it generates a first control signal based on the first analog signal and outputs it to the dynamic amplifier. After receiving the first control signal, the dynamic amplifier converts the first analog signal into a second analog signal, the second analog signal carrying time information. After receiving the second analog signal, the time-to-digital converter converts the second analog signal into a digital signal.

13. The method according to claim 12, characterized in that, The method further includes: The comparator circuit receives a clock signal; The comparator circuit generates a first control signal based on the first analog signal and outputs it to the dynamic amplifier, specifically including: The comparator circuit generates the first control signal based on the clock signal and the first analog signal.

14. The method according to claim 13, characterized in that, The method further includes: The comparator circuit generates a comparison signal based on the first analog signal and the clock signal, and outputs it to the successive approximation register-type SAR logic circuit. After receiving the comparison signal, the SAR logic circuit generates a digital signal based on the comparison signal.

15. An electronic device, characterized in that, include: Analog circuits are used to generate analog signals; Clock circuit, used to generate clock signals; At least one analog-to-digital converter as described in any one of claims 1-11, configured to receive the analog signal and the clock signal, and convert the analog signal into a digital signal; Digital circuitry is used to receive and process the digital signals.

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