Rerouting layer structure, semiconductor package structure and manufacturing method thereof

Abstract

The application provides a redistribution layer structure, a semiconductor packaging structure and a manufacturing method thereof. The redistribution layer structure comprises a first connection pad, a first dielectric layer, a first conductive plug, a first metal wiring layer, a second dielectric layer, a second conductive plug and a second metal wiring layer. The first metal wiring layer is electrically connected with the first conductive plug, and the second metal wiring layer is electrically connected with the second conductive plug. The orthographic projection area of the first metal wiring layer on the first connection pad is a first projection area, and the first projection area is not less than 80% of the surface area of the first connection pad. The orthographic projection area of the second metal wiring layer on the first connection pad is a second projection area, and the second projection area is not less than 50% of the surface area of the first connection pad. The application can make the redistribution layer structure stable and robust, and improve the product reliability and production yield.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a redistribution layer structure, a semiconductor packaging structure, and a method for manufacturing the same. Background Technology

[0002] With the continuous evolution of advanced packaging technologies, chiplet packaging is becoming increasingly widely used. In existing packaging structures, redistribution layers (RDLs) can be used to interconnect heterogeneous or homogeneous chips, ultimately achieving microsystem integration. A redistribution layer structure includes at least one metal wiring layer and at least two dielectric layers. Each metal wiring layer covers one dielectric layer, and another dielectric layer covers the same metal wiring layer, thus forming a stacked structure. In practice, the overall layout of the stacked structure needs to be considered to form a stable and robust redistribution layer structure. Poor design of the overall layout can lead to distortion of the redistribution layer structure, affecting flip-chip yield, causing broken or short-circuited wiring within the redistribution layer structure, and impacting product reliability. Summary of the Invention

[0003] The purpose of this invention is to provide a redistribution layer structure, a semiconductor packaging structure, and a method for manufacturing the same, so as to overcome the problems in the prior art, such as the redistribution layer structure being unstable and not robust enough, easily causing structural distortion, and affecting the yield of semiconductor packaging products.

[0004] To address the aforementioned problems, the present invention provides a redistribution layer structure, comprising: a first connection pad, a first dielectric layer located on the surface of the first connection pad, a first conductive plug penetrating the first dielectric layer and electrically connected to the first connection pad, a first metal wiring layer located on the surface of the first dielectric layer, a second dielectric layer located on the surface of the first metal wiring layer, a second conductive plug penetrating the second dielectric layer and electrically connected to the first metal wiring layer, and a second metal wiring layer located on the surface of the second dielectric layer; the first metal wiring layer is electrically connected to the first conductive plug, and the second metal wiring layer is electrically connected to the second conductive plug; wherein, the orthographic projection area of ​​the first metal wiring layer on the first connection pad is a first projection area, and the first projection area is not less than 80% of the surface area of ​​the first connection pad, and the orthographic projection area of ​​the second metal wiring layer on the first connection pad is a second projection area, and the second projection area is not less than 50% of the surface area of ​​the first connection pad.

[0005] As an optional technical solution, the redistribution layer structure further includes: a third dielectric layer located on the surface of the second metal wiring layer; a third conductive plug penetrating the third dielectric layer and electrically connected to the second metal wiring layer; a third metal wiring layer located on the surface of the third dielectric layer, and the third metal wiring layer being electrically connected to the third conductive plug; the orthographic projection area of ​​the third metal wiring layer on the first connection pad is the third projection area, wherein the third projection area is not less than 20% of the surface area of ​​the first connection pad.

[0006] As an optional technical solution, the redistribution layer structure further includes: a fourth dielectric layer located on the surface of the third metal wiring layer; a fourth conductive plug penetrating the fourth dielectric layer and electrically connected to the third metal wiring layer; a fourth metal wiring layer located on the surface of the fourth dielectric layer, and the fourth metal wiring layer being electrically connected to the fourth conductive plug; the orthographic projection area of ​​the fourth metal wiring layer on the first connection pad is the fourth projection area, wherein the fourth projection area is not less than 5% of the surface area of ​​the first connection pad.

[0007] As an optional technical solution, the first projection area, the second projection area, and the third projection area gradually decrease.

[0008] As an optional technical solution, the redistribution layer structure further includes: a fourth dielectric layer located on the surface of the third metal wiring layer; a fourth conductive plug penetrating the fourth dielectric layer and electrically connected to the third metal wiring layer; and a second connecting pad located on the surface of the fourth dielectric layer, wherein the second connecting pad is electrically connected to the fourth conductive plug.

[0009] As an optional technical solution, the redistribution layer structure further includes solder balls, which are electrically connected to the second connection pad.

[0010] As an optional technical solution, the first metal wiring layer and the second metal wiring layer are made of titanium, titanium tungsten, aluminum or copper; the first dielectric layer and the second dielectric layer are made of phenylcyclobutene, epoxy resin or polyimide.

[0011] To address the aforementioned problems, the present invention also provides a semiconductor packaging structure, which includes the aforementioned redistribution layer structure and a semiconductor device, wherein the semiconductor device has electrodes, and the first connection pad is correspondingly disposed with and electrically connected to the electrodes.

[0012] As an optional technical solution, the semiconductor device includes at least one chip, and the semiconductor packaging structure is a fan-out packaging structure or a fan-in packaging structure.

[0013] Furthermore, to address the aforementioned problems, the present invention also provides a method for fabricating a semiconductor packaging structure, comprising,

[0014] A carrier plate and semiconductor devices located on the carrier plate are provided;

[0015] A molding compound is formed, the molding compound covering the semiconductor device; and

[0016] The carrier plate is removed and a redistribution layer structure is connected to the side of the semiconductor device opposite to the molding compound. The redistribution layer structure includes a first connection pad, a first dielectric layer on the surface of the first connection pad, a first conductive plug penetrating the first dielectric layer and electrically connected to the first connection pad, a first metal wiring layer on the surface of the first dielectric layer, a second dielectric layer on the surface of the first metal wiring layer, a second conductive plug penetrating the second dielectric layer and electrically connected to the first metal wiring layer, and a second metal wiring layer on the surface of the second dielectric layer. The first metal wiring layer is electrically connected to the first conductive plug, and the second metal wiring layer is electrically connected to the second conductive plug. The projected area of ​​the first metal wiring layer on the first connection pad is a first projected area, which is not less than 80% of the surface area of ​​the first connection pad. The projected area of ​​the second metal wiring layer on the first connection pad is a second projected area, which is not less than 50% of the surface area of ​​the first connection pad.

[0017] Compared with the prior art, this invention specifically limits the projected area of ​​each metal wiring layer on the first connection pad, that is, limits the overlap area between each metal wiring layer and the first connection pad in the stacking direction. This makes the redistribution layer structure within the vertical projection of the first connection pad more stable, and the entire redistribution layer structure is more robust and stable, avoiding the problem of twisting and deformation, and improving the reliability of the redistribution layer structure. In turn, it can ensure the electrical connection effect between the redistribution structure and the semiconductor device. At the same time, it can avoid the problem of short circuits or broken wires due to the twisting of the redistribution layer structure, which greatly improves the first-pass yield and increases the product yield. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a first embodiment of the semiconductor packaging structure of the present invention;

[0019] Figure 2 for Figure 1 A magnified view of a portion of the image;

[0020] Figure 3 for Figure 1 A partial projection diagram of the middle redundancy layer structure;

[0021] Figure 4 This is a partially enlarged schematic diagram of a second embodiment of the semiconductor packaging structure of the present invention;

[0022] Figure 5 for Figure 4 A partial projection diagram of the rewiring layer structure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] Please refer to Figures 1 to 3 , Figure 1 This is a schematic diagram of a first embodiment of the semiconductor packaging structure of the present invention. Figure 2 for Figure 1 A partially enlarged schematic diagram, Figure 3 for Figure 1 A partial projection diagram of the rewiring layer structure. (See attached diagram.) Figure 1 As shown, the semiconductor package structure 10 of the present invention includes a redistribution layer structure 100 and a semiconductor device 200 that are electrically connected to each other.

[0025] like Figure 1 As shown, the redistribution layer structure 100 includes a first metal wiring layer 111, a second metal wiring layer 112, a first dielectric layer 121, a second dielectric layer 122, a first conductive plug a1, a second conductive plug a2, and a first connecting pad 130.

[0026] like Figure 1 and 2 As shown, the first dielectric layer 121 is located on the surface of the first connecting pad 130, and the first conductive plug a1 penetrates the first dielectric layer 121 and is electrically connected to the first connecting pad 130. The first metal wiring layer 111 is located on the surface of the first dielectric layer 121 opposite to the first connecting pad 130, and the first metal wiring layer 111 is electrically connected to the first conductive plug a1. That is, the first connecting pad 130 and the first metal wiring layer 111 are located on opposite surfaces of the first dielectric layer 121, one end of the first conductive plug a1 penetrating the first dielectric layer 121 is electrically connected to the first connecting pad 130, and the other end is electrically connected to the first metal wiring layer 111, so that the first connecting pad 130 and the first metal wiring layer 111 are electrically connected.

[0027] The second dielectric layer 122 is located on the surface of the first metal wiring layer 111 opposite to the first dielectric layer 121. The second conductive plug a2 penetrates the second dielectric layer 122 and is electrically connected to the first metal wiring layer 111. The second metal wiring layer 112 is located on the surface of the second dielectric layer 122 opposite to the first metal wiring layer 112, and the second metal wiring layer 112 is electrically connected to the second conductive plug a2. That is, the first metal wiring layer 111 and the second metal wiring layer 112 are located on opposite surfaces of the second dielectric layer. One end of the second conductive plug a2, which penetrates the second dielectric layer 121, is electrically connected to the first metal wiring layer 111, and the other end is electrically connected to the second metal wiring layer 112, so that the first metal wiring layer 111 and the second metal wiring layer 112 are electrically connected.

[0028] like Figure 1 and Figure 2 As shown, a first connecting pad 130, a first dielectric layer 121, a first metal wiring layer 111, a second dielectric layer 122, and a second metal wiring layer 112 are stacked sequentially. The first dielectric layer 121 is located between the first connecting pad 130 and the first metal wiring layer 111, and the second dielectric layer 122 is located between the first metal wiring layer 111 and the second metal wiring layer 112. The first connecting pad 130 and the first metal wiring layer 111 are electrically connected through a first conductive plug a1 penetrating the first dielectric layer 121, and the first metal wiring layer 111 and the second metal wiring layer 112 are electrically connected through a second conductive plug a2 penetrating the second dielectric layer 122. In one embodiment, the first connecting pad 130 is used to connect a semiconductor device 200.

[0029] Combination Figure 1 , Figure 2 and Figure 3 As shown, the first connecting pad 130 has a connecting surface S facing the first dielectric layer 121 and contacting the first conductive plug a1 to be electrically connected to the first metal wiring layer 111. The connecting surface has a surface area. The orthographic projection area of ​​the first metal wiring layer 111 on the first connecting pad 130 is the first projected area, which is not less than 80% of the surface area of ​​the first connecting pad. The orthographic projection area of ​​the second metal wiring layer 112 on the first connecting pad 130 is the second projected area, which is not less than 50% of the surface area of ​​the first connecting pad 130.

[0030] In one embodiment, a first connecting pad 130, a first dielectric layer 121, a first metal wiring layer 111, a second dielectric layer 122, and a second metal wiring layer 112 are stacked sequentially with a defined stacking direction. The area of ​​the vertical projection of the first metal wiring layer 111 onto the first connecting pad 130 along the stacking direction is the first projected area, and the area of ​​the vertical projection of the second metal wiring layer 112 onto the first connecting pad 130 along the stacking direction is the second projected area. The surface area of ​​the first connecting pad 130 is the surface area of ​​the connecting surface S.

[0031] In one embodiment, a first through-hole b1 is formed in the first dielectric layer 121, and a conductive material is used to fill the first through-hole b1 to form the aforementioned first conductive plug a1. The second dielectric layer 122 may also have a second through-hole b2, and a conductive material is used to fill the second through-hole b2 to form the aforementioned second conductive plug a2.

[0032] In one embodiment, the first dielectric layer 121 and the second dielectric layer 122 may be made of phenylcyclobutene (BCB), epoxy resin, or polyimide (PI), or other polymer dielectric materials and filler-containing polymer dielectric materials. The first metal wiring layer 111 and the second metal wiring layer 112 may be made of titanium, titanium-tungsten, aluminum, or copper. The first metal wiring layer 111 and the second metal wiring layer 112 may be made of the same material. In another embodiment, their materials may also be different. The first conductive plug a1 and the second conductive plug a2 may be made of the same or different material than the first metal wiring layer 111 and / or the second metal wiring layer 112.

[0033] like Figure 1 As shown, the semiconductor device 200 may include at least one chiplet 210. In this embodiment, the semiconductor device 200 includes two chips 210. When the semiconductor device 200 includes two or more chips 210, each chip 210 may be the same or different. Each chip 210 may have multiple electrodes 220, and the redistribution layer structure 100 may have multiple first connection pads 130. The multiple electrodes 220 correspond to the multiple first connection pads 130 and are electrically connected to each other. In one embodiment, each electrode 220 and each first connection pad 130 may be electrically connected through multiple microbumps 300.

[0034] In one embodiment, the first dielectric layer 121 has a plurality of first through holes, each of which is filled with conductive material to form a plurality of first conductive plugs. Each first connecting pad 130 has a connecting surface S that contacts the corresponding first conductive plug for electrical connection with the first metal wiring layer 111. The first projected area of ​​the first metal wiring layer 111 along the stacking direction on each connecting surface is not less than 80% of the surface area of ​​the first connecting pad 130, that is, the ratio of the first projected area to the area of ​​the first connecting surface is not less than 80%, or the proportion of the first projected area to the surface area of ​​the first connecting pad 130 facing the first metal wiring layer is not less than 80%. In one embodiment, the first projected area is set to completely cover the first connecting surface, that is, the aforementioned area proportion is 100%. The second projected area of ​​the second metal wiring layer 112 along the stacking direction on each connecting surface is not less than 50% of the surface area of ​​the first connecting pad 130.

[0035] In one embodiment, the redistribution layer structure 100 is a stacked structure. If the projected area of ​​each metal wiring layer is not limited as mentioned above and is arbitrarily designed, as mentioned in the background art, the structure of the redistribution layer structure 100 will not be stable or robust enough and will be prone to deformation. This will cause at least two problems. First, the first connection pad 130 will become misaligned due to the deformation of the redistribution layer structure 100. Since the first connection pad 130 is used to connect with the semiconductor device (e.g., chip) 200, the yield of the semiconductor device (e.g., chip) 200 will be damaged. Second, due to the deformation of the redistribution layer structure 100, in reliability tests such as temperature cycling, the uneven stress can easily lead to delamination or cracking.

[0036] The redistribution layer structure 100 and semiconductor package structure 10 of this invention have a first connecting pad 130 with a connecting surface S that contacts the first conductive plug a1 for electrical connection with the first metal wiring layer 111. Along the stacking direction of the first connecting pad 130, the first dielectric layer 121, the first metal wiring layer 111, the second dielectric layer 122, and the second metal wiring layer 112, the projected area formed by each metal wiring layer is specifically limited, that is, the overlap area between each metal wiring layer and the first connecting pad in the stacking direction is limited. This makes the redistribution layer structure within the vertical projection of the first connecting pad more stable, and the entire redistribution layer structure 100 is more robust and stable, avoiding the problem of twisting and deformation, and improving the reliability of the redistribution layer structure 100. Furthermore, it can ensure the electrical connection effect between the redistribution structure 100 and the semiconductor device 200; at the same time, it can avoid the problem of short circuits or broken wires in each metal wiring layer due to the twisting of the redistribution layer structure 100, greatly improving the first-pass yield and increasing the product yield.

[0037] In this embodiment, the first projected area of ​​the first metal wiring layer 111 along the stacking direction on each connection surface is not less than 80% of the surface area of ​​the first connection pad 130, and the second projected area of ​​the second metal wiring layer 112 along the stacking direction on the first connection pad 130 is not less than 50% of the surface area of ​​the first connection pad. In one embodiment, the ratio range of the projected areas of the first metal wiring layer 111 and the second metal wiring layer 112 to the surface area of ​​the first connection pad can be used as a design range value for reference when designing the redistribution layer structure 100.

[0038] Specifically, in the design process of the redistribution layer structure 100, the first projected area has a minimum design value of 80% of the surface area of ​​the first connection pad 130, and a maximum design value of 100% of the surface area of ​​the first connection pad 130; the second projected area has a minimum design value of 50% of the surface area of ​​the first connection pad 130, and a maximum design value of 100% of the surface area of ​​the first connection pad 130. That is, during the design process, the first and second projected areas can be selected within a certain range. The redistribution layer structure 100 formed after this selection and design can have a stable and robust structure while meeting electrical connection requirements.

[0039] like Figure 1 and Figure 2 As shown, in the semiconductor package structure 20 of this embodiment, the redistribution layer structure 100 further includes a third dielectric layer 123, a third conductive plug a3, and a third metal wiring layer 113. The third dielectric layer 123 is located on the surface of the second metal wiring layer 112 facing away from the second dielectric layer 122. The third conductive plug a3 penetrates the third dielectric layer 123 and is electrically connected to the second metal wiring layer 112. The third metal wiring layer 113 is located on the surface of the third dielectric layer 123 facing away from the second metal wiring layer 112, and the third metal wiring layer 113 is electrically connected to the third conductive plug a3. That is, the second metal wiring layer 112 and the third metal wiring layer 113 are located on opposite surfaces of the third dielectric layer 123. One end of the third conductive plug a3 penetrating the third dielectric layer 123 is electrically connected to the second metal wiring layer 112, and the other end is electrically connected to the third metal wiring layer 113. The second metal wiring layer 112 and the third metal wiring layer 113 are electrically connected through the third conductive plug a3. The projected area of ​​the third metal wiring layer 113 on the first connecting pad 130 is the third projected area, and the third projected area is not less than 20% of the surface area of ​​the first connecting pad 130.

[0040] In one embodiment, a first connecting pad 130, a first dielectric layer 121, a first metal wiring layer 111, a second dielectric layer 122, a second metal wiring layer 112, a third dielectric layer 123, and a third metal wiring layer 113 are stacked sequentially with a defined stacking direction, and the first connecting pad 130, the first metal wiring layer 111, the second metal wiring layer 112, and the third metal wiring layer 113 are electrically connected. In one embodiment, the area of ​​the third metal wiring layer 113 projected vertically onto the first connecting pad 130 along the aforementioned stacking direction is the aforementioned third projected area.

[0041] In one embodiment, the third dielectric layer 123 has a third through-hole b3, and a conductive material is filled into the third through-hole b3 to form the aforementioned third conductive plug a3. The material of the third metal wiring layer 113 can be titanium, titanium-tungsten, aluminum, or copper. The material of the third conductive plug a3 can be the same as or different from the material of the third metal wiring layer 113.

[0042] In one embodiment, the third dielectric layer 123 has a plurality of third through holes, each of which is filled with conductive material to form a plurality of third conductive plugs. The second metal wiring layer 112 and the third metal wiring layer 113 located on opposite surfaces of the third dielectric layer 123 are electrically connected through the plurality of third through holes.

[0043] In this embodiment, the third projected area of ​​the third metal wiring layer 113 on the first connecting pad 130 along the aforementioned stacking direction is not less than 20% of the surface area of ​​the first connecting pad 130. In actual operation, when designing the redistribution layer structure 100, the area ratio of the aforementioned third projected area on the first connecting pad 130 can be adjusted for reference within a design range of not less than 20%. Specifically, in the design process of the redistribution layer structure 100, the third projected area has a minimum design value of 20% of the surface area of ​​the first connecting pad 130, and a maximum design value of 100% of the surface area of ​​the first connecting pad 130. That is, the third projected area can be selected within this range during the design process. The redistribution layer structure 100 formed after this selection can have a stable and robust structure while meeting the electrical connection requirements, avoiding the problem of twisting and deformation, and improving the reliability of the redistribution layer structure 100.

[0044] like Figure 1 and Figure 2As shown, in this invention, the redistribution layer structure 100 further includes a fourth dielectric layer 124, a fourth conductive plug a4, and a second connecting pad 140. The fourth dielectric layer 124 is located on the surface of the third metal wiring layer 113 facing away from the third dielectric layer 123. The fourth conductive plug a4 penetrates the fourth dielectric layer 124 and is electrically connected to the third metal wiring layer 113. The second connecting pad 140 is located on the surface of the fourth dielectric layer 124 facing away from the third metal wiring layer 113, and the second connecting pad 140 is electrically connected to the fourth conductive plug a4. That is, the third metal wiring layer 113 and the second connecting pad 140 are located on opposite surfaces of the third dielectric layer 123. One end of the fourth conductive plug a4, which penetrates the fourth dielectric layer 124, is electrically connected to the third metal wiring layer 113, and the other end is electrically connected to the second connecting pad 140. The third metal wiring layer 113 and the second connecting pad 140 are electrically connected through the fourth conductive plug a4.

[0045] In this embodiment, the redistribution layer structure 100 also includes solder balls 150 electrically connected to the second connection pads 140. That is, the fourth conductive plug a3 and the solder balls 150 are located on opposite surfaces of the second connection pads 140, with one end of the second connection pad 140 electrically connected to the fourth conductive plug a4 and the other end electrically connected to the solder balls 150. Each second connection pad 140 can be electrically connected to other external circuits (not shown), such as a circuit board (PCB), through its corresponding solder balls 150. In other words, one end of the second connection pad 140 is electrically connected to the internal metal wiring layer of the redistribution layer structure 100 through the conductive plug, and the other end of the second connection pad 140 is electrically connected to other external circuits of the redistribution layer structure 100 through the solder balls. This allows for electrical connection between the semiconductor package structure 10 and other external circuits. The solder balls 150 can be solder balls or copper pillars with solder caps, etc.

[0046] like Figure 1 As shown, in this embodiment, the semiconductor package structure 10 further includes a molding compound 400, which encapsulates the semiconductor device 200 to protect it. Furthermore, the semiconductor package structure 10 also includes an underfill 500, which is disposed between adjacent chips 210 and between each chip 210 and the redistribution layer structure 100, thereby further enhancing the connection strength between each chip 210 and the redistribution layer structure 100. In addition, the redistribution layer structure 100 of the present invention can be applied to both fan-out and fan-in package structures. In some embodiments, the semiconductor package structure 10 can be either a fan-out or fan-in package structure.

[0047] In the first embodiment, a redistribution layer structure 100 comprising three metal wiring layers is used as an example. Those skilled in the art should understand that the redistribution layer structure may include four, five, or more metal wiring layers. The number of metal wiring layers and dielectric layers in the redistribution layer structure 100 can be set according to actual needs. Please refer to... Figures 4 to 5 , Figure 4 This is a partially enlarged schematic diagram of a second embodiment of the semiconductor packaging structure of the present invention. Figure 5 for Figure 4 A partial projection diagram of the rewiring layer structure.

[0048] like Figure 4 and Figure 5 As shown, in the semiconductor package structure 20 of this embodiment, the redistribution layer structure 100 includes a fourth dielectric layer 124, a fourth conductive plug a4, and a fourth metal wiring layer 114. The fourth dielectric layer 124 is located on the surface of the third metal wiring layer 113 facing away from the third dielectric layer 123. The fourth conductive plug a4 penetrates the fourth dielectric layer 124 and is electrically connected to the third metal wiring layer 113. The fourth metal wiring layer 114 is located on the surface of the fourth dielectric layer 124 facing away from the third metal wiring layer 113, and the fourth metal wiring layer 114 is electrically connected to the fourth conductive plug a4. That is, the third metal wiring layer 113 and the fourth metal wiring layer 114 are located on opposite surfaces of the fourth dielectric layer 124. One end of the fourth conductive plug a4 penetrating the fourth dielectric layer 124 is electrically connected to the third metal wiring layer 113, and the other end is electrically connected to the fourth metal wiring layer 114, so as to realize the electrical connection between the third metal wiring layer 113 and the fourth metal wiring layer 114.

[0049] The first connecting pad 130, the first dielectric layer 121, the first metal wiring layer 111, the second dielectric layer 122, the second metal wiring layer 112, the third dielectric layer 123, the third metal wiring layer 113, the third dielectric layer 124, and the fourth metal wiring layer 114 are stacked sequentially with a defined stacking direction, and the first connecting pad 130, the first metal wiring layer 111, the second metal wiring layer 112, the third metal wiring layer 113, and the fourth metal wiring layer 114 are electrically connected. Figure 5 As shown, the projected area of ​​the fourth metal wiring layer 114 on the first connection pad 130 is the fourth projected area, which is not less than 5% of the surface area of ​​the first connection pad 130. In one embodiment, the fourth metal wiring layer 114 is located on the first connection pad 130 along the aforementioned stacking direction (marked on...). Figure 5 The area of ​​the vertical projection of ) is the aforementioned fourth projection area.

[0050] In this embodiment, the fourth projected area of ​​the fourth metal wiring layer 114 on the first connecting pad 130 along the aforementioned stacking direction is not less than 5% of the surface area of ​​the first connecting pad 130. In actual operation, when designing the redistribution layer structure 100, the area ratio of the aforementioned fourth projected area on the first connecting pad 130 can be adjusted for reference within a design range of not less than 5%. Specifically, in the design process of the redistribution layer structure 100, the fourth projected area has a minimum design value of 5% of the surface area of ​​the first connecting pad 130, and a maximum design value of 100% of the surface area of ​​the first connecting pad 130. That is, in the design process, the fourth projected area can be selected within the range of 5% to 100% of the surface area of ​​the first connecting pad 130. The redistribution layer structure 100 formed after this selection can have a stable and robust structure while meeting the electrical connection requirements, avoiding the problem of twisting and deformation, and improving the reliability of the redistribution layer structure 100.

[0051] In one embodiment, the vertical projected area formed by each metal wiring layer in the redistribution layer structure 100 on the first connecting pad 130 along the stacking direction can gradually decrease in the direction away from the first connecting pad 130. For example, the first projected area of ​​the first metal wiring layer 111, the second projected area of ​​the second metal wiring layer 112, and the third projected area of ​​the third metal wiring layer 113 can gradually decrease. In other words, the metal layer farther away from the first connecting pad 130 has a smaller projected area formed on the first connecting pad 130 along the stacking direction; the metal layer closer to the first connecting pad 130 has a larger projected area formed on the first connecting pad 130 along the stacking direction. In actual operation, this is not a limitation.

[0052] like Figure 4 As shown, the redistribution layer structure 100 further includes a second connecting pad 140, a fifth dielectric layer 125, and a fifth conductive plug a5. The fifth conductive plug a5 penetrates the fifth dielectric layer 124 and is electrically connected to the fourth metal layer 124. The second connecting pad 140 is located on the surface of the fifth dielectric layer 124 facing away from the fourth metal wiring layer 114, and the second connecting pad 140 is electrically connected to the fifth conductive plug a5. That is, the fourth metal wiring layer 114 and the second connecting pad 140 are respectively located on opposite surfaces of the fifth dielectric layer 125. One end of the fifth conductive plug a5, which penetrates the opposite surfaces of the fifth dielectric layer 125, is electrically connected to the fourth metal wiring layer 114, and the other end is electrically connected to the second connecting pad 140, so that the fourth metal wiring layer 114 and the second connecting pad 140 are electrically connected.

[0053] Similar to the first embodiment, the redistribution layer structure 100 also includes solder balls 150 electrically connected to the second connection pad 140. That is, the fifth conductive plug a5 and the solder balls 150 are located on opposite surfaces of the second connection pad 140, with one end of the second connection pad 140 electrically connected to the fifth conductive plug a5 and the other end electrically connected to the solder balls 150. The second connection pad 140 can be electrically connected to other external circuits (not shown), such as a circuit board (PCB), through the corresponding solder balls 150. The solder balls 150 can be solder balls or copper pillars with solder caps, etc.

[0054] In one embodiment, the redistribution layer structure 100 may further include a fifth dielectric layer (not shown), a fifth conductive plug (not shown), and a fifth metal wiring layer (not shown). The fifth conductive plug penetrates the fifth dielectric layer and is electrically connected to the fourth metal wiring layer. The fifth metal wiring layer is located on the surface of the fifth dielectric layer away from the fourth metal wiring layer, and the fifth metal wiring layer is electrically connected to the fifth conductive plug. That is, the fourth metal wiring layer and the fifth metal wiring layer are located on opposite surfaces of the fifth dielectric layer, one end of the fifth conductive plug penetrating the fifth dielectric layer is electrically connected to the fourth metal wiring layer, and the other end is electrically connected to the fifth metal wiring layer, so that the fourth metal wiring layer and the fifth metal wiring layer are electrically connected.

[0055] A first connecting pad 130, a first dielectric layer 121, a first metal wiring layer 111, a second dielectric layer 122, a second metal wiring layer 112, a third dielectric layer 123, a third metal wiring layer 114, a fourth dielectric layer 124, a fourth metal wiring layer 114, a fifth dielectric layer, and the fifth metal wiring layer are stacked sequentially, and the first connecting pad 130, the first metal wiring layer 111, the second metal wiring layer 112, the third metal wiring layer 113, the fourth metal wiring layer 114, and the fifth metal wiring layer are electrically connected. The orthogonal projection area of ​​the fifth metal wiring layer on the first connecting pad 130 along the stacking direction is the fifth vertical projection area, which is not limited by the aforementioned ratio. In one embodiment, the area of ​​the fifth metal wiring layer's vertical projection onto the aforementioned reference plane along the stacking direction is the aforementioned fifth projection area.

[0056] This invention also proposes a method for fabricating a semiconductor packaging structure, which includes,

[0057] A carrier plate and semiconductor devices located on the carrier plate are provided;

[0058] A molding compound is formed, the molding compound covering the semiconductor device; and

[0059] The carrier plate is removed and a redistribution layer structure is connected to the side of the semiconductor device opposite to the molding compound. The redistribution layer structure includes a first connection pad, a first dielectric layer on the surface of the first connection pad, a first metal wiring layer on the surface of the first dielectric layer, a second dielectric layer on the surface of the first metal wiring layer, and a second metal wiring layer on the surface of the second dielectric layer. A portion of the first metal wiring layer passes through the first dielectric layer and is electrically connected to the first connection pad, and a portion of the second metal wiring layer passes through the second dielectric layer and is electrically connected to the first metal wiring layer. The projected area of ​​the first metal wiring layer on the first connection pad is a first projected area, which is not less than 80% of the surface area of ​​the first connection pad. The projected area of ​​the second metal wiring layer on the first connection pad is a second projected area, which is not less than 50% of the surface area of ​​the first connection pad.

[0060] In one embodiment, when setting the redistribution layer structure, the aforementioned first connection pad 130, first dielectric layer 121, first metal wiring layer 111, second dielectric layer 122, and second metal wiring layer 112 can be deposited on the surface of the semiconductor device 200 to form the redistribution layer structure 100. There are two methods for manufacturing the redistribution layer structure 100: one method is to fabricate the metal wiring layer using a dry etching method, followed by dielectric layer filling; the other method is to first etch the pattern for the metal wiring layer onto the dielectric layer, and then form the metal wiring layer using, for example, an electroplating process.

[0061] In one embodiment, the method of forming the redistribution layer structure 100 includes:

[0062] Form the first connecting pad 130;

[0063] A first dielectric layer 121 is formed on the surface of the first connecting pad 130;

[0064] A first through hole b1 is formed in the first dielectric layer 121, and conductive material is filled in the first through hole b1 to form a first conductive plug a1, and the first conductive plug a1 is electrically connected to the first connecting pad 130.

[0065] A first metal wiring layer 111 is formed on the surface of the first dielectric layer 121 opposite to the first connecting pad 130, and the first metal wiring layer 111 is electrically connected to the first conductive plug a1; wherein, the first projected area of ​​the first metal wiring layer 111 on the first connecting pad 130 is not less than 80% of the surface area of ​​the first connecting pad 130.

[0066] A second dielectric layer 122 is formed on the surface of the first metal wiring layer 111 that is opposite to the first dielectric layer 121;

[0067] A second through-hole b2 is formed in the second dielectric layer 122, and conductive material is filled into the second through-hole b2 to form a second conductive plug a2, and the second conductive plug a2 is electrically connected to the first metal wiring layer 111; and

[0068] A second metal wiring layer 112 is formed on the surface of the second dielectric layer 122 opposite to the first metal wiring layer 111, and the second metal wiring layer 112 is electrically connected to the second conductive plug a2. The second projected area of ​​the second metal wiring layer 112 on the first connecting pad 130 is not less than 50% of the surface area of ​​the first connecting pad 130.

[0069] In one embodiment, the method of forming the redistribution layer structure 100 further includes:

[0070] A third dielectric layer 123 is formed on the surface of the second metal wiring layer 112 that is opposite to the second dielectric layer 122;

[0071] A third through-hole b3 is formed in the third dielectric layer 123, and conductive material is filled into the third through-hole b3 to form a third conductive plug a3, and the third conductive plug a3 is electrically connected to the second metal wiring layer 112; and

[0072] A third metal wiring layer 113 is formed on the surface of the third dielectric layer 123 opposite to the second metal wiring layer 112, and the third metal wiring layer 113 is electrically connected to the third conductive plug a3. The third projected area of ​​the third metal wiring layer 113 on the first connection pad 130 along the stacking direction is not less than 20% of the surface area of ​​the first connection pad 130.

[0073] In one embodiment, the method for forming the redistribution layer structure further includes:

[0074] A fourth dielectric layer 124 is formed on the surface of the third metal wiring layer 113 that is opposite to the third dielectric layer 123;

[0075] A fourth through hole b4 is formed in the fourth dielectric layer 124, and conductive material is filled in the fourth through hole b4 to form a fourth conductive plug a4, and the fourth conductive plug a4 is electrically connected to the third metal wiring layer 113.

[0076] A second connection pad 140 is formed on the surface of the fourth dielectric layer 124 opposite to the third metal wiring layer 113, and the second connection pad 140 is electrically connected to the fourth conductive plug a4; and

[0077] Solder balls 150 are formed on the surface of the second connection pad 140 away from the fourth dielectric layer 124, and the solder balls 150 are electrically connected to the second connection pad 140.

[0078] In practice, the semiconductor device 200 includes at least one chip. After the solder balls 150 are installed, the method for fabricating the semiconductor package structure also includes cutting the semiconductor package structure into individual packages.

[0079] In the redistribution layer, semiconductor packaging structure, and semiconductor packaging structure fabrication method of the present invention, the projected area formed by each metal wiring layer on the first connecting pad is specifically limited, that is, the overlap area between each metal wiring layer and the first connecting pad in the stacking direction is limited. This makes the redistribution structure within the vertical projection of the first connecting pad more stable, and the entire redistribution layer structure 100 is more robust and stable, avoiding the problem of twisting and deformation, and improving the reliability of the redistribution layer structure 100. This ensures the connection effect between the redistribution structure and the semiconductor device 200. At the same time, it avoids the problem of short circuits or broken wires caused by the twisting of the redistribution layer structure 100, greatly improving the first-pass yield and increasing the product yield.

[0080] The present invention has been described by the above-described embodiments; however, these embodiments are merely examples for implementing the present invention. Furthermore, the technical features involved in the different embodiments of the present invention described above can be combined with each other as long as they do not conflict with each other. It must be noted that the present invention may have other various embodiments, and those skilled in the art can make various corresponding changes and modifications based on the present invention without departing from its spirit and essence; however, all such corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims

1. A redistribution layer structure, characterized in that, include: First connecting pad; The first dielectric layer is located on the surface of the first connection pad; A first conductive plug that penetrates the first dielectric layer and is electrically connected to the first connecting pad; A first metal wiring layer is located on the surface of the first dielectric layer, and the first metal wiring layer is electrically connected to the first conductive plug; A second dielectric layer located on the surface of the first metal wiring layer; A second conductive plug that penetrates the second dielectric layer and is electrically connected to the first metal wiring layer; A second metal wiring layer is located on the surface of the second dielectric layer, and the second metal wiring layer is electrically connected to the second conductive plug; Wherein, the orthographic projection area of ​​the first metal wiring layer on the first connection pad is the first projection area, and the first projection area is not less than 80% of the surface area of ​​the first connection pad; the orthographic projection area of ​​the second metal wiring layer on the first connection pad is the second projection area, and the second projection area is not less than 50% of the surface area of ​​the first connection pad.

2. The redistribution layer structure according to claim 1, characterized in that, The redistribution layer structure further includes: a third dielectric layer located on the surface of the second metal wiring layer; a third conductive plug penetrating the third dielectric layer and electrically connected to the second metal wiring layer; a third metal wiring layer located on the surface of the third dielectric layer, and the third metal wiring layer being electrically connected to the third conductive plug; the orthographic projection area of ​​the third metal wiring layer on the first connection pad is the third projection area, wherein the third projection area is not less than 20% of the surface area of ​​the first connection pad.

3. The redistribution layer structure according to claim 2, characterized in that, The redistribution layer structure further includes: a fourth dielectric layer located on the surface of the third metal wiring layer; a fourth conductive plug penetrating the fourth dielectric layer and electrically connected to the third metal wiring layer; a fourth metal wiring layer located on the surface of the fourth dielectric layer, and the fourth metal wiring layer being electrically connected to the fourth conductive plug; the orthographic projection area of ​​the fourth metal wiring layer on the first connection pad is the fourth projection area, wherein the fourth projection area is not less than 5% of the surface area of ​​the first connection pad.

4. The redistribution layer structure according to claim 2, characterized in that, The first projected area, the second projected area, and the third projected area gradually decrease.

5. The redistribution layer structure according to claim 2, characterized in that, The redistribution layer structure further includes: a fourth dielectric layer located on the surface of the third metal wiring layer; a fourth conductive plug penetrating the fourth dielectric layer and electrically connected to the third metal wiring layer; and a second connecting pad located on the surface of the fourth dielectric layer, wherein the second connecting pad is electrically connected to the fourth conductive plug.

6. The redistribution layer structure according to claim 5, characterized in that, The redistribution layer structure also includes solder balls electrically connected to the second connection pad.

7. The redistribution layer structure according to claim 1, characterized in that, The first metal wiring layer and the second metal wiring layer are made of titanium, titanium tungsten, aluminum or copper; the first dielectric layer and the second dielectric layer are made of phenylcyclobutene, epoxy resin or polyimide.

8. A semiconductor packaging structure, characterized in that, include, The redistribution layer structure as described in any one of claims 1 to 7; as well as A semiconductor device having electrodes, wherein a first connection pad is disposed corresponding to and electrically connected to the electrodes.

9. The semiconductor packaging structure according to claim 8, characterized in that, The semiconductor device includes at least one chip, and the semiconductor packaging structure is a fan-out packaging structure or a fan-in packaging structure.

10. A method for fabricating a semiconductor packaging structure as described in claim 8, characterized in that, include, A carrier plate and semiconductor devices located on the carrier plate are provided; A molding compound is formed, the molding compound covering the semiconductor device; as well as The carrier plate is removed and a redistribution layer structure is connected to the side of the semiconductor device opposite to the molding compound. The redistribution layer structure includes a first connection pad, a first dielectric layer on the surface of the first connection pad, a first conductive plug penetrating the first dielectric layer and electrically connected to the first connection pad, a first metal wiring layer on the surface of the first dielectric layer, a second dielectric layer on the surface of the first metal wiring layer, a second conductive plug penetrating the second dielectric layer and electrically connected to the first metal wiring layer, and a second metal wiring layer on the surface of the second dielectric layer. The first metal wiring layer is electrically connected to the first conductive plug, and the second metal wiring layer is electrically connected to the second conductive plug. The projected area of ​​the first metal wiring layer on the first connection pad is a first projected area, which is not less than 80% of the surface area of ​​the first connection pad. The projected area of ​​the second metal wiring layer on the first connection pad is a second projected area, which is not less than 50% of the surface area of ​​the first connection pad.

Images