Voltage regulation method and system for on-chip charge recycling interconnects

Abstract

The present application relates to the technical field of on-chip interconnection, and particularly relates to a voltage adjusting method and system applied to on-chip charge recovery interconnection lines, which comprises the following steps: calculating a first data activity difference caused by data in a current period when the data is transmitted on upper and lower channels of the interconnection line based on charge recovery; accumulating a second data activity difference caused by data in past several periods when the data is transmitted on the upper and lower channels of the interconnection line on the basis of the first data activity difference to obtain a total data activity difference; when the total data activity difference exceeds a first threshold, performing voltage compensation on an intermediate voltage of the upper and lower channels to stabilize the intermediate voltage, and the voltage compensation is performed simultaneously with charging and discharging of the intermediate voltage. By predicting the intermediate voltage fluctuation of the upper and lower channels of the interconnection line, and then performing early intervention and compensation before the intermediate voltage appears large deviation, the problem of voltage compensation lag in the traditional charge recovery interconnection line design is solved.

Description

Technical Field

[0001] This invention relates to the field of on-chip interconnect technology, and in particular to a voltage regulation method and system for on-chip charge recovery interconnects. Background Technology

[0002] Repeater-based interconnect circuits are a common interconnect design. Specifically, the interconnect line is divided into multiple segments, which are connected by repeaters based on inverters or buffers. This allows the signal quality to be restored after each transmission distance, resulting in less propagation delay. Repeater-based interconnects have a full voltage swing, which simplifies the design of the transmitting and receiving circuits, but also leads to higher power consumption.

[0003] Another interconnect technology commonly used for high-bandwidth transmission is low-swing interconnect technology. Low-swing interconnect technology achieves a low signal swing through special signal propagation mechanisms and specialized transceiver circuit designs, thereby effectively reducing signal transmission power consumption on the interconnect. Because it involves voltage conversion between full-swing and low-swing signals, low-swing interconnect technology often requires relatively complex transmitting and receiving circuits. Common low-swing interconnect transmission methods include low-swing differential signal transmission, current-mode transmission, and capacitive coupling transmission.

[0004] Another actively explored low-power interconnect design is based on charge recovery. Its basic principle is to stack two repeater-based data channels between power and ground, allowing the lower channel to reuse the current generated by the upper channel. Ideally, the intermediate voltage between the upper and lower channels is VDD / 2, resulting in a signal swing of VDD / 2 for both channels. This reduces the dynamic power consumption of the interconnect to 25% of that based on a full-swing repeater design. However, to ensure the stability of the intermediate voltage, the current in the lower and upper channels needs to be balanced, requiring both channels to have the same data activity. However, in actual data transmission, the data activity of different channels often differs significantly, causing a shift in the intermediate voltage. This, in turn, leads to a decrease in the operating voltage of the upper or lower channel, affecting the data transmission speed.

[0005] Solutions to address intermediate voltage offset include periodically switching the upper and lower channels to balance data activity, and using a regulator to provide additional current to compensate for the current difference between the two channels.

[0006] Channel-switched designs insert switching circuits at intervals along interconnects. These circuits transmit data from the channel (lower channel) on the previous interconnect to the lower channel (upper channel) on the next interconnect, thus balancing data activity between the upper and lower channels. However, channel switching involves half-swing-full-swing-half-swing voltage conversion between the two channel signals, which consumes additional power. Furthermore, channel switching only guarantees a long-term average intermediate voltage of VDD / 2; under specific data transmission modes, its instantaneous value can still deviate significantly, leading to a decrease in data transmission speed. To ensure circuit functionality, designers must allow for timing margins, impacting circuit performance.

[0007] The regulator-based design connects the intermediate voltage of the interconnect to the regulator. The regulator compares the intermediate voltage with the standard VDD / 2 voltage using a sensitive amplifier. When the intermediate voltage is too low, the regulator provides additional current to charge it and raise the voltage; when the intermediate voltage is too high, the regulator provides discharge current to lower the intermediate voltage. The problem is that the regulator has limited energy efficiency, and the greater the current difference between the upper and lower channels, the lower the regulator efficiency. In extreme cases, when only one channel is active, the regulator efficiency can degrade to 50%, causing the energy gain of the charge recovery method to drop from 75% to 50%. Furthermore, the regulator's compensation for the intermediate voltage is lagging, meaning that the intermediate voltage has already shifted to some extent before the regulator functions properly, leading to circuit performance degradation. Summary of the Invention

[0008] The purpose of this invention is to provide a voltage regulation method and system for on-chip charge recovery interconnects, which solves the problem of intermediate voltage fluctuation caused by the mismatch of data activity between the upper and lower channels in charge recovery interconnects, and overcomes the disadvantage of voltage compensation lag in traditional charge recovery interconnect designs.

[0009] To achieve the above objectives, the present invention provides a voltage regulation method for on-chip charge recovery interconnects, comprising the following steps:

[0010] Calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during this period;

[0011] The total data activity difference is obtained by adding the second data activity difference caused by the transmission of data from the previous several cycles in the upper and lower channels of the interconnect to the first data activity difference.

[0012] When the total data activity difference exceeds a first threshold, voltage compensation is performed on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage, and the voltage compensation is performed simultaneously with the charging and discharging of the intermediate voltage.

[0013] Optionally, the step of calculating the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during the current cycle specifically includes:

[0014] The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel.

[0015] The first data activity difference is obtained by subtracting the second data activity from the first data activity difference.

[0016] Optionally, the intermediate voltage may be compensated with different intensities based on the magnitude of the difference in the total activity of the data.

[0017] Optionally, when the total data activity difference exceeds a second threshold, the operating voltage of the interconnect is increased, wherein the second threshold is greater than the first threshold.

[0018] Optionally, when performing voltage compensation on the intermediate voltage of the upper and lower channels, the upper and lower channels of the interconnect simultaneously transmit data.

[0019] Based on the same inventive concept, this invention also provides a voltage regulation system for on-chip charge recovery interconnects, comprising a charge recovery-based interconnect and a voltage regulation circuit. The data to be transmitted per cycle is divided into two parts and transmitted separately through the upper and lower channels of the interconnect in a charge recovery manner. The voltage regulation circuit includes an activity calculation unit and an intermediate voltage regulator; wherein...

[0020] The activity calculation unit is configured to calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the interconnect based on charge recovery in the current period, and to accumulate the second data activity difference caused by the transmission of data in the upper and lower channels of the interconnect in the past several periods on the basis of the first data activity difference, so as to obtain the total data activity difference.

[0021] The intermediate voltage regulator is configured to perform voltage compensation on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage when the total data activity difference exceeds a first threshold, and the voltage compensation is performed simultaneously with the charging and discharging of the intermediate voltage.

[0022] Optionally, the activity calculation unit is specifically configured as follows:

[0023] The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel.

[0024] The first data activity difference is obtained by subtracting the second data activity from the first data activity difference.

[0025] Optionally, the intermediate voltage regulator is provided with different settings to compensate the intermediate voltage with different intensities according to the magnitude of the difference in the total activity of the data.

[0026] Optionally, the voltage regulation circuit further includes an operating voltage regulator configured to raise the operating voltage of the interconnect when the total data activity difference exceeds a second threshold, wherein the second threshold is greater than the first threshold.

[0027] Based on the same inventive concept, the present invention also provides a readable storage medium having a computer program stored thereon, which, when executed, enables the voltage regulation method applied to on-chip charge recovery interconnects as described above.

[0028] The voltage regulation method and system for on-chip charge recovery interconnects provided by this invention have at least one of the following beneficial effects:

[0029] 1) By adding the second data activity difference caused by the transmission of data on the interconnect in the past several cycles to the first data activity difference caused by the transmission of data on the interconnect in the current cycle, the intermediate voltage fluctuation of the upper and lower channels in the interconnect can be predicted. This allows for early intervention and compensation before the intermediate voltage deviates significantly, solving the problem of voltage compensation lag in traditional charge recovery interconnect design. This further reduces the timing margin on the data channel and achieves a higher data transmission rate.

[0030] 2) The intermediate voltage can be compensated with different strengths according to the magnitude of the difference in total data activity, thereby reducing the energy consumption of voltage regulation and improving the energy efficiency of data transmission while ensuring the transmission rate.

[0031] 3) When the total data activity difference exceeds the second threshold, it indicates that the data activity difference is extremely large, and the shift in intermediate voltage is unavoidable. At this time, the voltage swing of the upper or lower channel repeater will decrease, resulting in a decrease in data transmission speed. To cope with this worst-case scenario, the operating voltage of the interconnect can be increased for a short period of time to improve the driving capability of the repeater, thereby offsetting the speed loss caused by intermediate voltage fluctuations and improving circuit performance.

[0032] 4) Different voltage regulation strategies can be dynamically selected based on the magnitude of the total data activity difference, so as to reduce the energy consumption of voltage regulation while ensuring the transmission rate. Attached Figure Description

[0033] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0034] Figure 1 A flowchart of a voltage regulation method for on-chip charge recovery interconnects provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram illustrating the adjustment principle of a voltage regulation method applied to an on-chip charge recovery interconnect according to an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of an active computing unit provided in an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of an intermediate voltage regulation circuit based on transistor charging and discharging provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of an intermediate voltage regulation circuit based on ACTIVE DECAP provided in an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram of a working voltage regulation circuit based on a switched capacitor charge pump according to an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of a working voltage regulation circuit based on a Dickson charge pump provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of this invention, and are not intended to limit the conditions for implementing this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0042] It should also be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., in the specification are used only to distinguish the various components, elements, steps, etc., in the specification, and not to indicate the logical or sequential relationships between the various components, elements, steps, etc. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0043] Please refer to Figure 1 This embodiment provides a voltage regulation method for on-chip charge recovery interconnects, including the following steps:

[0044] S1. Calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during this period;

[0045] S2. Based on the first data activity difference, add the second data activity difference caused by the transmission of data in the upper and lower channels of the interconnect over the past several cycles to obtain the total data activity difference;

[0046] S3. When the total data activity difference exceeds the first threshold, voltage compensation is performed on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage, and the voltage compensation and the charging and discharging of the intermediate voltage are performed simultaneously.

[0047] By adding the second data activity difference caused by the transmission of data on the interconnect over several past cycles to the first data activity difference caused by the transmission of data on the interconnect in the current cycle, the intermediate voltage fluctuations of the upper and lower channels in the interconnect can be predicted. This allows for early intervention and compensation before a significant shift in the intermediate voltage occurs, solving the problem of voltage compensation lag in traditional charge recovery interconnect designs. This further reduces the timing margin on the data channel and enables higher data transmission rates.

[0048] First, step S1 is executed to calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during this cycle. For example... Figure 2 As shown, the total bit width of the data transmitted on the charge-recovery interconnect is denoted as N. Each cycle of N bits of data is transmitted in two channels, upper and lower, using charge recovery. The transmission process requires passing through an M-stage pipeline.

[0049] Specifically, the interconnect section employs charge recovery technology, stacking two repeater channels between power and ground. The upper channel's repeater is powered by VDD and releases current to the intermediate voltage VMID. The lower channel then utilizes this current to complete data transmission, thus saving energy. In practical applications, multi-channel data synchronous parallel transmission is often required; however, the data transmission rates of different channels are difficult to perfectly match. The longer the transmission distance, the greater the phase difference between different channels. If the phase difference is too large when the data arrives at the receiving end, timing disorders will occur, preventing the simultaneous sampling of multiple channels that should be synchronized. Therefore, the interconnect needs to be piped, forming an M-stage pipeline architecture by inserting triggers into the interconnect, ensuring that data is synchronized after each transmission distance, thereby preventing sampling errors at the receiving end.

[0050] Furthermore, the steps for calculating the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during this period specifically include:

[0051] The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel.

[0052] The difference in first data activity is obtained by subtracting second data activity from first data activity.

[0053] After obtaining the first data activity difference of the current period, step S2 is executed to accumulate the second data activity difference caused by the transmission of data in the upper and lower channels of the interconnect over the past several periods on the basis of the first data activity difference, so as to obtain the total data activity difference.

[0054] In this embodiment, since there are M-stage pipelines on the interconnect, this means that data activity over M cycles will affect VMID. Therefore, it is necessary to calculate and save the activity difference values ​​for the previous M-1 cycles, add the activity difference value of the current cycle to the activity difference values ​​for the previous M-1 cycles, and calculate the sum of the activity differences over M cycles to measure the voltage fluctuations on VMID.

[0055] Finally, step S3 is executed. When the total data activity difference exceeds the first threshold, voltage compensation is performed on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage. Voltage compensation and intermediate voltage charging / discharging occur simultaneously. When the calculated total data activity difference is small, it indicates that the intermediate voltage fluctuation is minimal and will not affect normal data transmission; in this case, voltage compensation is not required. When the total data activity difference exceeds the set first threshold, it indicates that the intermediate voltage fluctuation is significant, requiring voltage compensation. The size of the first threshold can be determined based on factors such as the bit width and RC parameters of the interconnect in the actual application. Since voltage compensation and intermediate voltage charging / discharging occur simultaneously, compensation can be performed before intermediate voltage fluctuations occur, thus avoiding the lag in compensation seen in traditional charge recovery interconnect designs.

[0056] Preferably, the intermediate voltage can be compensated with different intensities according to the magnitude of the difference in total data activity, thereby reducing the energy consumption of voltage regulation and improving the energy efficiency of data transmission while ensuring the transmission rate.

[0057] Preferably, when the total data activity difference exceeds a second threshold, the operating voltage of the interconnect is increased, where the second threshold is greater than the first threshold. When the total data activity difference exceeds the second threshold, it indicates a significant data activity difference, making intermediate voltage fluctuations unavoidable. In this case, the voltage swing of the upper or lower channel repeater will decrease, leading to a drop in data transmission speed. To address this worst-case scenario, the operating voltage of the interconnect is increased for a short period to enhance the repeater's driving capability, thereby offsetting the speed loss caused by intermediate voltage fluctuations and improving circuit performance. The magnitude of the second threshold also depends on the bit width of the actual application, the RC parameters of the interconnect, etc.

[0058] Based on the same inventive concept, this invention also provides a voltage regulation system for on-chip charge recovery interconnects, including a charge recovery-based interconnect and a voltage regulation circuit. The data to be transmitted per cycle is divided into two parts and transmitted separately through the upper and lower channels of the interconnect using a charge recovery method. The voltage regulation circuit includes an activity calculation unit and an intermediate voltage regulator.

[0059] The activity calculation unit is configured to calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the interconnect based on charge recovery in the current cycle, and to accumulate the second data activity difference caused by the transmission of data in the upper and lower channels of the interconnect in the past several cycles on the basis of the first data activity difference to obtain the total data activity difference.

[0060] The intermediate voltage regulator is configured to perform voltage compensation on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage when the total data activity difference exceeds a first threshold, and the voltage compensation is performed simultaneously with the charging and discharging of the intermediate voltage.

[0061] By adding the second data activity difference caused by the transmission of data on the interconnect over several past cycles to the first data activity difference caused by the transmission of data on the interconnect in the current cycle, the intermediate voltage fluctuation of the upper and lower channels in the interconnect is predicted by the activity calculation unit. Then, the intermediate voltage regulator is used to compensate for the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage. Early intervention and compensation before the intermediate voltage deviates significantly solves the problem of voltage compensation lag in traditional charge recovery interconnect design. This can further reduce the timing margin on the data channel and achieve a higher data transmission rate.

[0062] Preferably, the active computing unit is specifically configured as follows:

[0063] The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel.

[0064] The difference in first data activity is obtained by subtracting second data activity from first data activity.

[0065] Preferably, the intermediate voltage regulator has different settings to compensate the intermediate voltage with different strengths according to the magnitude of the difference in total data activity.

[0066] Preferably, the voltage regulation circuit further includes an operating voltage regulator configured to raise the operating voltage of the interconnect when the total data activity difference exceeds a second threshold, wherein the second threshold is greater than the first threshold.

[0067] In this embodiment, the intermediate voltage regulator is connected to VMID and is responsible for providing compensation voltage to stabilize the intermediate voltage; the working voltage regulator is connected to VDD and is used to raise the working voltage of the interconnect. The switching of the intermediate voltage regulator and the working voltage regulator is determined by the results of the activity calculation unit. When the calculated total data activity difference is very small, it indicates that the intermediate voltage fluctuation is small and will not affect the normal data transmission. At this time, the intermediate voltage regulator is turned off to save energy. When the data activity difference exceeds a first threshold, it indicates that the intermediate voltage fluctuation is significant and needs to be compensated. At this time, the intermediate voltage regulator is turned on to stabilize the intermediate voltage. When the total data activity difference is extremely large, making the intermediate voltage offset unavoidable, the voltage swing of the upper or lower channel repeater will decrease, resulting in a decrease in data transmission speed. To cope with this worst-case scenario, the intermediate voltage regulator and the working voltage regulator will be turned on simultaneously. By raising the working voltage of the interconnect for a short time, the driving capability of the repeater is improved, thereby offsetting the speed loss caused by the intermediate voltage fluctuation and improving circuit performance. When the data activity difference is less than a second threshold, the working voltage regulator will be turned off to save energy.

[0068] Therefore, two voltage regulation strategies can be dynamically enabled based on the magnitude of the difference in total data activity, thereby reducing the energy consumption of voltage regulation and improving data transmission efficiency while ensuring the transmission rate.

[0069] The technical concept of the present invention is further illustrated below through a specific example. It is assumed that the input bit width of the interconnect is N = 16, the number of pipeline stages is M = 5, the first threshold is N1 = 5, and the second threshold is N2 = 10.

[0070] Please refer to Figure 3 , Figure 3This diagram illustrates one circuit implementation of the activity calculation unit. The activity calculation unit uses two 8-bit register groups to store the data S[15:8] and S[7:0] of the upper and lower channels from the previous cycle, respectively. Performing a bitwise XOR operation with the input data D[15:0] of the current cycle yields the result indicating whether each bit of the data in the current cycle has changed. Counters at the outputs of the two XOR gates count the XOR counts of the upper and lower channel data, and the subtraction result is the first data activity difference for the current cycle. The activity calculation unit stores the data activity difference values ​​of the past four cycles through a shift register group. Including the current cycle, the activity difference values ​​for five cycles are accumulated using an adder to obtain the total data activity difference SUM on the entire interconnect line. This calculation result is sent to the intermediate voltage regulator and the operating voltage regulator, controlling the two voltage regulators to adjust the intermediate voltage and the operating voltage respectively. In this example, assume D[15:0] = 01010000 11000111 and S[15:0] = 1110111011000110. D[15:8] and S[15:8] differ by 6 bits, and D[7:0] and S[7:0] differ by 1 bit. Therefore, the first data activity difference value for this period is 5. Assuming the activity differences for the past four periods are -2, 6, 7, and 6, then the total data activity difference SUM on the interconnect is 21.

[0071] The function of the intermediate voltage regulator is to stabilize the intermediate voltage. This example introduces two specific implementation methods: the implementation method based on transistor charging and discharging, and the implementation method based on ACTIVE DECAP (active decoupling capacitor).

[0072] The implementation method based on transistor charging and discharging is as follows: Figure 4As shown, the circuit comprises two parts: a leading regulator and a lagging regulator. The leading regulator generates a compensation current based on the calculation results of the activity calculation unit, thereby balancing the charging and discharging of the intermediate voltage by the upper and lower channels in real time and preventing the intermediate voltage from shifting. When the activity difference is small, the shift in the intermediate voltage is negligible, and the leading regulator will turn off to save energy. When the activity difference exceeds the first threshold N1, the leading regulator turns on to prevent significant shifts in the intermediate voltage. Different levels can be set internally within the leading regulator to compensate for intermediate voltage shifts caused by different degrees of total data activity difference. Specifically, when the total data activity difference is greater than 5, MN1 will turn on to balance the excess current in the upper channel; when the total data activity difference is less than -5, MP1 will turn on to balance the excess current in the lower channel. In addition, when the total data activity difference is greater than 10 or less than -10, the leading regulator will additionally turn on MN2 or MP2 to provide a stronger compensation current. In this example, the active calculation unit outputs SUM = 21, therefore MN1 and MN2 in the lead regulator are turned on, discharging the intermediate voltage. The lag regulator is implemented using a dual-loop regulator circuit, its function being to eliminate the intermediate voltage deviation that the lead regulator could not completely prevent. The dual-loop regulator has a fast feedback loop and a slow feedback loop. The fast feedback loop directly charges and discharges the intermediate voltage based on the comparison result between the intermediate voltage and the reference voltage, achieving rapid adjustment of the intermediate voltage. The slow feedback loop first low-pass filters the comparison result, causing it to drive the transistor to provide a more stable compensation current. By distributing the compensation current across the fast and slow feedback loops, the dual-loop regulator can reduce voltage ripple caused by excessive instantaneous compensation.

[0073] The implementation based on ACTIVE DECAP is as follows: Figure 5As shown, an ACTIVE DECAP is deployed in the upper and lower channels respectively, and its capacitance size is configurable. During circuit operation, the VMID can be charged and discharged by configuring its capacitance, thereby stabilizing the intermediate voltage. Specifically, each ACTIVE DECAP has 4 capacitors of size C. By changing the connection relationship of the 4 capacitors, 3 different sizes of ACTIVE DECAP capacitors can be obtained: (1) The 4 capacitors are divided into two groups, connected in series within the group and in parallel between the groups, and the total capacitance of the ACTIVE DECAP is C; (2) The 4 capacitors are connected in series, and the total capacitance is C / 4; (3) The 4 capacitors are connected in parallel, and the total capacitance is 4C. When the data activity of the upper and lower channels is relatively balanced, that is, -5≤SUM≤5, the capacitance of the ACTIVE DECAP of the upper and lower channels is configured as C, which does not affect the intermediate voltage. When the circuit detects that the data activity of the bottom channel is strong, that is, SUM<-5, the ACTIVE DECAP of the lower channel will be reduced to C / 4, resulting in an excess of positive charge on its upper plate. The excess positive charge is transferred to the VMID, thereby raising the intermediate voltage. Meanwhile, the upper channel's ACTIVE DECAP is configured at 4C, and its lower plate has insufficient negative charge. Therefore, the negative charge on VMID will transfer to the ACTIVE DECAP, which also causes the intermediate voltage to rise. When the data activity of the top channel is strong, i.e., SUM>5, the lower channel's ACTIVE DECAP is configured at 4C, and the upper channel's ACTIVE DECAP is configured at C / 4, which can provide discharge current to reduce the intermediate voltage.

[0074] The function of the operating voltage regulator is to momentarily raise the interconnect operating voltage when the difference in data activity between the upper and lower channels is too large (exceeding the second threshold N2), thereby preventing the reduction in transmission rate caused by intermediate voltage offset and improving circuit performance. This example provides two implementations of the operating voltage regulator based on charge pumps: an implementation based on a switched capacitor charge pump and an implementation based on a Dickson charge pump. Figure 6This diagram illustrates the working principle of a switched capacitor charge pump. When the clock is low (clk = 0, clkb = 1), transistor M3 turns on, grounding the lower plate of capacitor C2; transistors M1 and M2 turn on, charging nodes a and c of the upper plates of capacitors C1 and C2 to VDDL; the transmission gate connecting C1 and C2 closes to prevent charge transfer between a and b; M4 turns off to prevent VDDH and VDDL from connecting. When the clock goes high (clk = 1, clkb = 0), M1, M2, and M3 disconnect, the transmission gate between a and b opens, capacitors C1 and C2 become connected in series, and the voltage difference between the two capacitors stacks, thus raising the voltage at point c above VDDL; M4 turns on, thus transferring the high voltage at point c to VDDH. VDDH is connected to the operating voltage VDD of the interconnect via M5. When the active computing unit outputs SUM > 20 or SUM < -20, M5 turns on, thereby raising the operating voltage of the interconnect. It should be noted that in order for M5 to switch normally, the swing of the driving voltage of M5 needs to be between 0 and VDDH. Therefore, a voltage converter is used in the circuit to convert the output swing of U1.

[0075] Figure 7 This diagram illustrates an implementation based on a Dickson charge pump. The three nodes a, b, and c in the circuit are connected to the upper plates of capacitors C1, C2, and C3, respectively. The lower plates of these three capacitors are connected to clk, clkb, and clk, respectively. Due to the coupling effect of the capacitors, when clk = 1 and clkb = 0, nodes a and c are in a high-voltage state, while node b is in a low-voltage state. This makes the voltage at point a higher than that at point b, allowing point b to be charged through M2. Simultaneously, M1, M3, and M4 are closed to prevent charge at point a from flowing back to VDDL, and charge at point c and VDDH from flowing back to point b. When clk = 0 and clkb = 1, the voltages at points a and c decrease, and the voltage at point b increases. VDDL charges point a through M1, and point b charges VDDH and point c through M3 and M4. M2 is closed to prevent charge at point b from flowing back to point a. By continuously switching between these two clock states, charge can be continuously accumulated from the left end of the circuit to the right end, thereby increasing the voltage of VDDH. Similar to implementations based on switched-capacitor charge pumps, VDDH is connected to the operating voltage VDD of the interconnect only when the activity difference is sufficiently large (SUM>20 or SUM<-20). In this example, SUM=21, so VDDH is connected to VDD, boosting the operating voltage.

[0076] The graded voltage regulation scheme, which combines intermediate voltage regulators and operating voltage regulators, can effectively reduce the fluctuation of intermediate voltage on charge recovery interconnects through advanced voltage regulation, and reduce the impact of intermediate voltage fluctuations on data transmission speed by instantaneously boosting the operating voltage, thereby improving circuit performance.

[0077] Based on the same inventive concept, this embodiment also provides a readable storage medium storing a computer program thereon, which, when executed, can implement the voltage regulation method applied to on-chip charge recovery interconnects as described above.

[0078] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives and forwards a computer program from the network for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0079] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0080] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0081] In summary, this invention provides a voltage regulation method and system for on-chip charge recovery interconnects. By adding a second data activity difference caused by the transmission of data in the past several cycles to the first data activity difference caused by the transmission of data in the current cycle on the interconnect, the intermediate voltage fluctuation of the upper and lower channels in the interconnect can be predicted. This allows for early intervention and compensation before a significant shift in the intermediate voltage occurs, solving the problem of voltage compensation lag in traditional charge recovery interconnect designs. Consequently, the timing margin on the data channel can be further reduced, achieving a higher data transmission rate.

[0082] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A voltage regulation method applied to on-chip charge recovery interconnects, characterized in that, Includes the following steps: The first data activity difference caused by the transmission of data in the upper and lower channels of the charge-recovery interconnect during this cycle is calculated. The total bit width of the data transmitted on the charge-recovery interconnect is denoted as N. Each cycle of N bits of data is transmitted in two channels using charge recovery. The transmission process requires M stages of pipeline. The interconnect uses charge recovery technology, stacking two repeater channels between power and ground. The repeater of the upper channel is powered by VDD and releases current to the intermediate voltage VMID. The lower channel uses the current to complete data transmission. The total data activity difference is obtained by adding the second data activity difference caused by the transmission of data from the previous several cycles in the upper and lower channels of the interconnect to the first data activity difference. The intermediate voltage of the upper and lower channels is compensated with different intensities based on the magnitude of the total difference in data activity. When the total data activity difference exceeds a first threshold, voltage compensation is performed on the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage, and the voltage compensation is performed simultaneously with the charging and discharging of the intermediate voltage. When the total data activity difference exceeds a second threshold, the operating voltage of the interconnect is increased, wherein the second threshold is greater than the first threshold; The specific steps for calculating the first data activity difference caused by the transmission of data in the upper and lower channels of the charge recovery-based interconnect during this period include: The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel. The first data activity difference is obtained by subtracting the second data activity from the first data activity.

2. A voltage regulation system for on-chip charge recovery interconnects, characterized in that, It includes charge-recovery-based interconnects and voltage regulation circuits. The total bit width of the data transmitted on the charge-recovery-based interconnects is denoted as N. The data to be transmitted in each cycle is divided into two parts and transmitted through the upper and lower channels of the interconnects respectively in a charge-recovery manner. The transmission process requires passing through an M-stage pipeline. The interconnect section employs charge recovery technology, stacking two repeater channels between power and ground. The upper channel's repeater is powered by VDD and releases current to the intermediate voltage VMID, while the lower channel utilizes this current to complete data transmission. The voltage regulation circuit includes an activity calculation unit and an intermediate voltage regulator. The activity calculation unit is configured to calculate the first data activity difference caused by the transmission of data in the upper and lower channels of the interconnect based on charge recovery in the current period, and to accumulate the second data activity difference caused by the transmission of data in the upper and lower channels of the interconnect in the past several periods on the basis of the first data activity difference, so as to obtain the total data activity difference. The intermediate voltage regulator has different settings to compensate the intermediate voltage with different intensities based on the magnitude of the total data activity difference. The intermediate voltage regulator is configured to compensate the intermediate voltage of the upper and lower channels to stabilize the intermediate voltage when the total data activity difference exceeds a first threshold, and the voltage compensation is performed simultaneously with the charging and discharging of the intermediate voltage. The voltage regulation circuit also includes a working voltage regulator, which is configured to increase the working voltage of the interconnect when the total data activity difference exceeds a second threshold, wherein the second threshold is greater than the first threshold. Specifically, the activity calculation unit is configured as follows: The data of this cycle is XORed bit by bit with the data transmitted in the upper and lower channels of the interconnect in the previous cycle to calculate the first data activity of the data in the upper channel and the second data activity in the lower channel. The first data activity difference is obtained by subtracting the second data activity from the first data activity.

3. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it can implement the voltage regulation method for on-chip charge recovery interconnects as described in claim 1.

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