A soft switching method for three-phase NPC three-level inverter

Abstract

The application discloses a soft switching method of a three-phase NPC three-level inverter. The application can realize zero-voltage turn-on of a power switching device of the three-phase NPC inverter through a frequency conversion control strategy, is high in reliability and easy to realize. The application does not need an auxiliary network, a sensor and a high-speed zero-crossing detection circuit, and no additional loss is generated except for a main circuit. In the application, a final critical switching frequency curve of the last synthesis is symmetrical, and the clamping state is symmetrical and the clamping angle is the same in each large sector, so that the midpoint capacitor voltage offset of the inverter is small, and the midpoint potential can be well balanced.

Description

Technical Field

[0001] This invention belongs to the field of high-frequency power electronic conversion, specifically a soft-switching method for a three-phase NPC (diode neutral point clamped) type three-level inverter. Background Technology

[0002] In recent years, with the rapid development of new energy grid connection, changes in power system structure, and the continuous improvement of requirements for voltage level, capacity, and output quality of converters, traditional two-level converters are struggling to meet the needs of different applications. Compared with traditional two-level inverters, three-level NPC inverters are widely used in power, transportation, and energy industries due to their advantages such as high withstand voltage, low output harmonic content, and low output common-mode voltage.

[0003] Existing three-phase NPC-type three-level inverters mostly use silicon IGBT (Insulated Gate Bipolar Transistor) devices. Limited by the high switching losses and on-state voltage drop of silicon-based IGBTs, the switching frequency of the converter is generally less than 20kHz, resulting in problems such as large size of passive filter components and heat sinks, and low efficiency. With the development of power semiconductor devices, new semiconductor materials such as SiC (Silicon Carbide) and GaN (Gallium Nitride) possess characteristics such as wide bandgap and high breakdown field strength. Power devices fabricated with these materials have advantages such as fast switching speed and low on-resistance, and are expected to significantly improve the power density of converters. However, higher switching frequencies lead to higher switching losses and electromagnetic interference (EMI) problems. Introducing soft-switching technology can effectively reduce the switching losses of switching devices and improve the conversion efficiency of the device. At the same time, it can improve the electromagnetic interference (EMI) of the converter to a certain extent and reduce the design difficulty of EMI filters.

[0004] Traditional soft-switching technology uses auxiliary circuits to achieve soft switching of the main switching devices. Based on the location of the added auxiliary circuits, it is divided into two categories: AC-side resonant circuits and DC-side resonant circuits. AC-side resonant circuits achieve ZVS (Zero Voltage Switching) by changing the direction of the current on the bridge arm through the auxiliary circuit, clamping the voltage of the main circuit power devices to zero via diode freewheeling. This mainly includes load-side resonant circuits and auxiliary resonant commutator circuits. DC-side resonant circuits achieve ZVS of the main circuit power devices by resonating the voltage of the DC-side bus to zero before the power device switches through the auxiliary circuit. This mainly includes resonant DC loops, quasi-resonant DC loops, and composite active clamping. While auxiliary network soft-switching technology can achieve soft switching of the main switching devices, using auxiliary networks increases the complexity of the main circuit, drive circuit, and control circuit, reduces reliability, and increases the cost and losses of the auxiliary switching devices.

[0005] In recent years, some scholars have proposed a method for soft-switching technology without auxiliary networks. This method achieves zero-voltage switching (ZVS) by increasing the inductor current ripple to change the direction of the inductor current and causing resonance between the inductor and the output capacitor of the switching device. It has advantages such as low cost, simple control, and ease of implementation. However, the method of soft-switching without auxiliary networks is mainly applicable to single-phase NPC three-level inverters and is difficult to directly extend to three-phase inverters. The main reason is that three-phase NPC inverters have major problems such as mutual coupling of three-phase inductor currents, mutual coupling of three-phase bridge arm switching states, and neutral point voltage deviation. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the technical problem this invention aims to solve is to provide a soft-switching method for a three-phase NPC type three-level inverter.

[0007] The technical solution of the present invention to solve the aforementioned technical problem is to provide a soft-switching method for a three-phase NPC type three-level inverter, characterized in that the method includes the following steps:

[0008] Step 1: Determine the voltage synthesis vector U at this time based on the spatial vector diagram of the three-level SVPWM. ref The large sector N and small sector n are traversed; then, based on the converter's inductance value L and the minimum reverse bias current I required to achieve ZVS... ZVS Sample three-phase voltage v a v b v c and three-phase current i a i b i c The critical switching frequencies fs for achieving ZVS in phases A, B, and C were obtained respectively. sx (θ), where N = 1, 2, 3, 4, 5, 6; n = 1, 2, 3, 4, 5, 6; θ is the phase-locked angle obtained by phase-locking the grid voltage; x = a, b, c;

[0009] Step 2: The seven-segment SVPWM switching sequence operates in the following order: it begins with a negative small vector, ends with a negative small vector, and has a positive small vector in between. Then, the negative small vectors at the beginning and end are discarded, clamping one of the three phases, resulting in a five-segment space vector CPWM1. At this point, the allocation factor k = -1, and the critical switching frequency for the unclamped phase is f. sy1 (θ), where y1 = a,b or a,c or b,c;

[0010] Similarly, discarding the middle positive small vector clamps another phase of the three-phase system, resulting in a five-segment space vector CPWM2. At this point, the allocation factor k = 1, and the critical switching frequency for the unclamped phase is f. sy2 (θ), where y2 = a,b or a,c or b,c;

[0011] Step 3: The angle corresponding to the Nth largest sector is (N-1)60°≤θ<N60°. Analyze it to obtain the final critical switching frequency f when N is odd and N is even. s ;

[0012] Step 4: Based on the final critical switching frequency f obtained in Step 3 s The carrier period is 1 / f. s Then, based on the allocation factor k obtained in step 3 and its corresponding carrier period 1 / f s The modulation waveform of SVPWM is modified into a five-segment waveform based on the k value to obtain the modulation waveform of DPWM. Then, in-phase stacked carrier modulation is selected, and the modulated switching sequence is the equivalent DPWM switching sequence. Based on the switching sequence, the on and off states of each switching device are determined.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] (1) The present invention can realize the zero-voltage turn-on of the power switching devices of the three-phase NPC inverter through the frequency conversion control strategy, which has high reliability and is easy to implement.

[0015] (2) This invention does not require an auxiliary network, sensor and high-speed zero-crossing detection circuit, and will not generate additional losses except for the main circuit.

[0016] (3) The present invention can realize wide-range soft switching of switching devices, and one phase of the three-phase bridge arm will always be non-operating within half of the power frequency cycle. Therefore, it can greatly reduce the switching loss of the inverter, improve the conversion efficiency, and further increase the switching frequency.

[0017] (4) The filter inductance value used in this invention is relatively small, resulting in a large overall inverter volume and high power density. At the same time, the smaller inductance value can improve the cutoff frequency of the inverter, and the dynamic response of the system is better.

[0018] (5) The final critical switching frequency curve of the final synthesis in this invention is symmetrical, and the clamping state is symmetrical and the clamping angle is the same in each large sector. Therefore, the voltage deviation of the inverter midpoint capacitor is small, and the midpoint potential can achieve adaptive balance well. Attached Figure Description

[0019] Figure 1 This is a diagram of the main circuit topology of the diode-clamped three-level inverter according to Embodiment 1 of the present invention.

[0020] Figure 2 This is the spatial vector diagram of SVPWM in Embodiment 1 of the present invention;

[0021] Figure 3This is a graph showing the critical switching frequency curves of the non-clamped phases of CPWM1 and CPWM2 in the first large sector of Embodiment 1 of the present invention.

[0022] Figure 4 This is a graph showing the critical switching frequency curves of the non-clamped phases of CPWM1 and CPWM2 in the second large sector of Embodiment 1 of the present invention.

[0023] Figure 5 This is a graph showing the final critical switching frequency synthesized in Embodiment 1 of the present invention;

[0024] Figure 6 This is a control block diagram of Embodiment 1 of the present invention;

[0025] Figure 7 This is a typical waveform diagram within the power frequency cycle of Embodiment 1 of the present invention;

[0026] Figure 8 This is a diagram illustrating the soft-switching implementation process of Embodiment 1 of the present invention;

[0027] Figure 9 This is a diagram showing the midpoint voltage offset in Embodiment 1 of the present invention. Detailed Implementation

[0028] Specific embodiments of the present invention are given below. These specific embodiments are only used to further illustrate the present invention in detail and do not limit the scope of protection of the claims of the present invention.

[0029] This invention provides a soft-switching method (hereinafter referred to as the method) for a three-phase NPC type three-level inverter, characterized in that the method includes the following steps:

[0030] Step 1: Determine the voltage synthesis vector U at this time based on the space vector diagram of the three-level SVPWM (Space Vector Pulse Width Modulation). ref The large sector N and small sector n are traversed; then, based on the converter's inductance value L and the minimum reverse bias current I required to achieve ZVS... ZVS Sample three-phase voltage v a v b v c and three-phase current i a i b i c The critical switching frequencies fs for achieving ZVS in phases A, B, and C were obtained respectively. sx (θ), where N = 1, 2, 3, 4, 5, 6; n = 1, 2, 3, 4, 5, 6; θ is the phase-locked angle obtained by phase-locking the grid voltage; x = a, b, c;

[0031] Step 2: The seven-segment SVPWM switching sequence operates in the following order: it begins with a negative small vector, ends with a negative small vector, and has a positive small vector in between. Then, the negative small vectors at the beginning and end are discarded, clamping one of the three phases, resulting in a five-segment space vector CPWM1. At this point, the allocation factor k = -1, and the critical switching frequency for the unclamped phase is f. sy1 (θ), where y1 = a,b or a,c or b,c;

[0032] Similarly, discarding the middle positive small vector clamps another phase of the three-phase system, resulting in a five-segment space vector CPWM2. At this point, the allocation factor k = 1, and the critical switching frequency for the unclamped phase is f. sy2 (θ), where y2 = a,b or a,c or b,c;

[0033] Step 3: The angle corresponding to the Nth largest sector is (N-1)60°≤θ<N60°. Analyze it to obtain the final critical switching frequency f when N is odd and N is even. s ;

[0034] Preferably, in step 3, when N is an odd number, i.e., the voltage synthesis vector U ref When passing through sectors 1, 3, and 5, the final critical switching frequency f is reached. s The solution steps are as follows:

[0035] Step A1: Within the first 30°, find the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k=1 and (N-1)60°, where 0°<θ1<60°; since the first 30° and the last 30° are symmetrical, the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k=-1 and N60° is θ1.

[0036] Step A2, when the voltage synthesis vector U ref When the phase-locked angle θ satisfies (N-1)60°≤θ<(N-1)60°+θ1, f s =f sy1min f sy1min The minimum critical switching frequency for the non-clamped phase is k = -1; when θ satisfies (N-1)60° + θ1 ≤ θ < (N-0.5)60°, f s =f sy2min f sy2min This is the minimum critical switching frequency for the non-clamped phase when k = 1; when θ satisfies (N-0.5)60°≤θ<N60°-θ1, f s =f sy1min At this time, k = -1; when θ satisfies N60° - θ1 ≤ θ < N60°, f s =f sy2minAt this point, k = -1.

[0037] Preferably, in step 3, when N is an even number, i.e., the voltage synthesis vector U... ref When passing through sectors 2, 4, and 6, the final critical switching frequency f is reached. s The solution steps are as follows:

[0038] Step B1: Within the first 30°, find the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k = -1 and (N-1)60°, where 0° < θ1 < 60°. Since the first 30° and the last 30° are symmetrical, the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k = 1 and N60° is θ1.

[0039] Step B2, when the voltage synthesis vector U ref When the phase-locked angle θ satisfies (N-1)60°≤θ<(N-1)60°+θ1, f s =f sy2min At this time, k = 1; when θ satisfies (N-1)60° + θ1 ≤ θ < (N-0.5)60°, f s =f sy1min At this time, k = -1; when θ satisfies (N-0.5)60°≤θ<N60°-θ1, f s =f sy2min At this time, k = 1; when θ satisfies N60° - θ1 ≤ θ < N60°, f s =f sy1min At this point, k = -1.

[0040] Step 4: Based on the final critical switching frequency f obtained in Step 3 s The carrier period is 1 / f. s Then, based on the allocation factor k obtained in step 3 and its corresponding carrier period 1 / f s The modulation waveform of SVPWM is modified by transforming it into a five-segment waveform based on the k value to obtain the modulation waveform of DPWM (Discontinuous Space Vector). Then, in-phase stacked carrier modulation is selected, and the modulated switching sequence is the equivalent DPWM switching sequence. Based on the switching sequence, the on and off states of each switching device are determined.

[0041] Example 1

[0042] The main circuit topology of an NPC inverter is as follows: Figure 1 As shown, Figure 1 S i1 S i3 The switching signals of (i = a, b, c) are complementary, S i2 S i4The switching signals are complementary. The DC side voltage is 800V, the effective value of the three-phase line voltage on the AC side is 380V, the rated power is 6.6kW, and it can achieve grid-connected charging and discharging with unity power factor.

[0043] In step 1, the space vector diagram of the three-level SVPWM is as follows: Figure 2 As shown, based on the DC side voltage and the AC side line voltage, the voltage synthesis vector U can be determined at this time. ref The process proceeds sequentially through sectors 5, 3, 4, and 6. Three-phase voltage and current are sampled, and after filtering out the instantaneous values ​​of the switching frequency component, phase-locked loop (PLL) is applied to the grid voltage to obtain the PLL angle θ. Simultaneously, the critical switching frequency expressions for achieving ZVS (Zero-Voltage Switching) for each of the A, B, and C phase arms in different sector sizes can be obtained.

[0044] In step 2, based on the critical switching frequency expression obtained in step 1, let the allocation factors k = 1 and -1 to obtain the critical switching frequency curve for the non-clamped phase, as shown below. Figure 3 and Figure 4 As shown. Among them. Figure 3 The critical switching frequency curve is for the first major sector when it is in the non-clamped phase. Figure 4 This is the critical switching frequency curve for the non-clamped phase of the second largest sector. Figure 3 In the diagram, the non-critical switching frequency curve corresponding to k=1 is shown as the solid line, and the non-critical switching frequency curve corresponding to k=-1 is shown as the dashed line. The steps, result shapes, and principles of the third and fifth major sectors are the same as those of the first major sector, and the steps, result shapes, and principles of the fourth and sixth major sectors are the same as those of the second major sector. Therefore, the first and second major sectors will be used as examples for explanation.

[0045] In step 3, the angle corresponding to the first large sector is 0°≤θ<60°, according to Figure 3 For the curve shown, when 0°≤θ<30°, f can be obtained. sa1 and f sb1 The absolute value of the difference θ1 between the intersection point and 0° is 5.4°. Since the first 30° and the last 30° are symmetrical, then f sb2 and f sc2 The intersection point is 54.6°. When the voltage composite vector U ref When the phase-locked angle θ satisfies 0°≤θ<5.4°, f s =f sb2 At this time, k = -1; when θ satisfies 5.4° ≤ θ < 30°, f s =f sa1 At this time, k = 1; when θ satisfies 30° ≤ θ < 54.6°, f s =f sc2 At this time, k = -1; when θ satisfies 54.6° ≤ θ < 60°, f s =f sb1At this point, k = 1.

[0046] The angle corresponding to the second largest sector is 60°≤θ<120°, according to Figure 4 For the curve shown, when 60°≤θ<90°, f can be obtained. sa2 and f sc2 The absolute value of the difference between the intersection point θ1 and 60° is 5.4°. Since the first 30° and the last 30° are symmetrical, then f sa1 and f sb1 The intersection point is 54.6°. When the voltage composite vector U ref When the phase-locked angle θ satisfies 0°≤θ<5.4°, f s =f sb2 At this time, k = 1; when θ satisfies 5.4° ≤ θ < 30°, f s =f sa1 At this time, k = -1; when θ satisfies 30° ≤ θ < 54.6°, f s =f sc2 At this time, k = 1; when θ satisfies 54.6° ≤ θ < 60°, f s =f sb1 At this point, k = -1.

[0047] By analogy, the critical switching frequency curves f within the six major sectors (i.e., the power frequency cycle) are obtained. s like Figure 5 As shown.

[0048] In step 4, based on the final critical switching frequency f obtained in step 3... s The carrier period is 1 / f. s Then, based on the allocation factor k obtained in step 3 and its corresponding carrier period 1 / f s The modulation waveform of DPWM can be obtained by modifying the modulation waveform of SVPWM, such as... Figure 6 As shown; then, the upcarrier and downcarrier are selected for modulation, and finally the switching signal S is obtained. i1 S i2 S i3 S i4 The switching devices are controlled to turn on and off via a drive circuit.

[0049] Figure 7 It is an inverter operating waveform within a power frequency cycle. The inductor current on the inverter side has high current ripple, but the grid current has almost no ripple. Figure 8 To achieve ZVS waveform for the inverter's external transistors, the voltage across the switching transistors drops to 0 before the drive signal arrives, thus enabling ZVS. Figure 9 The midpoint voltage deviation is shown. The peak value of the capacitor voltage difference is ±15V, the DC voltage is 800V, and the midpoint voltage deviation is small. Figure 8and Figure 9 The effectiveness and feasibility of the proposed method were verified.

[0050] Any aspects not covered in this invention are applicable to existing technologies.

Claims

1. A soft-switching method for a three-phase NPC type three-level inverter, characterized in that, The method includes the following steps: Step 1: Determine the voltage synthesis vector U at this time based on the spatial vector diagram of the three-level SVPWM. ref The large sector N and small sector n are traversed; then, based on the converter's inductance value L and the minimum reverse bias current I required to achieve ZVS... ZVS Sample three-phase voltage v a v b v c and three-phase current i a i b i c The critical switching frequencies fs for achieving ZVS in phases A, B, and C were obtained respectively. sx (θ), where N=1,2,3,4,5,6; n=1,2,3,4,5,6; θ is the phase-locked angle obtained by phase-locking the grid voltage; x=a,b,c; Step 2: The seven-segment SVPWM switching sequence operates in the following order: it begins with a negative small vector, ends with a negative small vector, and has a positive small vector in between. Then, the negative small vectors at the beginning and end are discarded, clamping one of the three phases, resulting in a five-segment space vector CPWM1. At this point, the allocation factor k = -1, and the critical switching frequency for the unclamped phase is f. sy1 (θ), where y1 = a,b or a,c or b,c; Similarly, discarding the middle positive small vector clamps another phase of the three-phase system, resulting in a five-segment space vector CPWM2. At this point, the allocation factor k = 1, and the critical switching frequency for the unclamped phase is f. sy2 (θ), where y2 = a,b or a,c or b,c; Step 3: The angle corresponding to the Nth largest sector is (N-1)60°≤θ<N60°. Analyze it to obtain the final critical switching frequency f when N is odd and N is even. s ; Step 4: Based on the final critical switching frequency f obtained in Step 3 s The carrier period is 1 / f. s Then, based on the allocation factor k obtained in step 3 and its corresponding carrier period 1 / f s The modulation waveform of SVPWM is modified into a five-segment waveform based on the k value to obtain the modulation waveform of DPWM. Then, in-phase stacked carrier modulation is selected, and the modulated switching sequence is the equivalent DPWM switching sequence. Based on the switching sequence, the on and off states of each switching device are determined.

2. The soft-switching method for a three-phase NPC type three-level inverter according to claim 1, characterized in that, In step 3, when N is an odd number, i.e., the voltage synthesis vector U ref When passing through sectors 1, 3, and 5, the final critical switching frequency f is reached. s The solution steps are as follows: Step A1: Within the first 30°, find the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k=1 and (N-1)60°, where 0°<θ1<60°; since the first 30° and the last 30° are symmetrical, the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k=-1 and N60° is θ1. Step A2, when the voltage synthesis vector U ref When the phase-locked angle θ satisfies (N-1)60°≤θ<(N-1)60°+θ1, f s =f sy1min f sy1min The minimum critical switching frequency for the non-clamped phase is k = -1; when θ satisfies (N-1)60° + θ1 ≤ θ < (N-0.5)60°, f s =f sy2min f sy2min This is the minimum critical switching frequency for the non-clamped phase when k = 1; when θ satisfies (N-0.5)60°≤θ<N60°-θ1, f s =f sy1min At this time, k = -1; when θ satisfies N60° - θ1 ≤ θ < N60°, f s =f sy2min At this point, k = -1.

3. The soft-switching method for a three-phase NPC type three-level inverter according to claim 1, characterized in that, In step 3, when N is an even number, i.e., the voltage synthesis vector U... ref When passing through sectors 2, 4, and 6, the final critical switching frequency f is reached. s The solution steps are as follows: Step B1: Within the first 30°, find the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k = -1 and (N-1)60°, where 0° < θ1 < 60°. Since the first 30° and the last 30° are symmetrical, the absolute value of the angle difference between the intersection of the critical switching frequencies of the other two phases of the non-clamped phase when k = 1 and N60° is θ1. Step B2, when the voltage synthesis vector U ref When the phase-locked angle θ satisfies (N-1)60°≤θ<(N-1)60°+θ1, f s =f sy2min At this time, k = 1; when θ satisfies (N-1)60° + θ1 ≤ θ < (N-0.5)60°, f s =f sy1min At this time, k = -1; when θ satisfies (N-0.5)60°≤θ<N60°-θ1, f s =f sy2min At this time, k = 1; when θ satisfies N60° - θ1 ≤ θ < N60°, f s =f sy1min At this point, k = -1.

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