Memory device and zq calibration method

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a plurality of cascaded first slave chips, a second master chip and a plurality of cascaded second slave chips connected with the ZQ calibration resistance, and a first transmission end and a second transmission end used for transmitting a ZQ flag signal; a recognition module used for recognizing a priority calibration chip, a delay calibration chip, a master-slave chip cascaded with the priority calibration chip, and a secondary slave chip cascaded with the delay calibration chip; in a command mode, the priority calibration chip starts calibration based on a ZQ calibration command, the delay calibration chip starts calibration based on a delayed ZQ calibration command, and after calibration is completed, the ZQ flag signal is sent through the second transmission end; and the master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal, so as to realize theoretically unlimited number of multi-chip sharing the ZQ calibration resistance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a memory device and a ZQ calibration method. Background Technology

[0002] ZQ calibration is a very important function in Dynamic Random Access Memory (DRAM). Specifically, it relates to whether the output impedance of the output port is accurate and whether the termination resistor of the input port is accurate. Deviations in these parameters can cause severe distortion of the signal during transmission due to impedance mismatch. Moreover, the higher the signal frequency, the greater the impact of distortion on the signal.

[0003] JEDEC's packaging definition specifies the number of ZQ calibration resistors required for LPDDR5. For example, DIS315 chips have one ZQ calibration resistor, while POP496 chips have two ZQ calibration resistors. It is evident that the number of ZQ calibration resistors in LPDDR5 is significantly less than that in LPDDR4.

[0004] As the demand for LPDDR capacity increases, more and more chips are being placed in a single LPDDR package. Each chip requires individual ZQ calibration due to its unique characteristics. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to LPDDR4, requiring more chips to share a single ZQ. How to achieve ZQ calibration by sharing ZQ calibration resistors among multiple chips is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a memory device and a ZQ calibration method, which, through the design of a novel control circuit, enables theoretically unlimited number of chips to share a ZQ calibration resistor.

[0006] One embodiment of this disclosure provides a memory device, including: two calibration resistor interfaces connected to the same ZQ calibration resistor; a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips, all connected to the ZQ calibration resistor; the first master chip, the first slave chip, the second master chip, and the second slave chip are provided with a first transmission terminal and a second transmission terminal, which are used to transmit a ZQ flag signal; wherein, the second transmission terminal of the first master chip is connected to the first transmission terminal of a first-level first slave chip, the second transmission terminal of each first-level first slave chip is connected to the first transmission terminal of the next-level first slave chip, the second transmission terminal of the second master chip is connected to the first transmission terminal of a first-level second slave chip, and the second transmission terminal of each second-level second slave chip is connected to the first terminal of the next-level second slave chip; a first signal receiver is provided in the first master chip and the second master chip, and a second signal receiver is provided in the first slave chip and the second slave chip; an identification module is used to identify the first master chip and the second master chip. One chip serves as the priority calibration chip, and the other as the delay calibration chip. The first or second slave chip cascaded with the priority calibration chip is the master / slave chip, and the first or second slave chip cascaded with the delay calibration chip is the secondary slave chip. In command mode, the first signal receiver receives the ZQ calibration command provided by the memory through the ZQ signal terminal, or receives the ZQ calibration command through the ZQ signal terminal and then delays the ZQ calibration command. The priority calibration chip starts calibration based on the ZQ calibration command, and the delay calibration chip starts calibration based on the delayed ZQ calibration command. After the first and second master chips complete calibration, they send a ZQ flag signal through the second transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The second signal receiver receives the ZQ flag signal through the first transmission terminal. The master / slave chip and the secondary slave chip start calibration based on the ZQ flag signal. After the current master / slave chip and the secondary slave chip complete calibration, they send a ZQ flag signal through the second transmission terminal until all first or second slave chips have completed calibration.

[0007] In the memory device provided in this embodiment, multiple chips calibrated through a first calibration interface are configured as a first master chip and multiple first slave chips; multiple chips calibrated through a second calibration interface are configured as a second master chip and multiple second slave chips; a recognition module identifies the priority calibration chip and the delayed calibration chip in the first master chip and the second master chip, and the first slave chip or the second slave chip cascaded with the priority calibration chip is the master slave chip, and the first slave chip or the second slave chip cascaded with the delayed calibration chip is the secondary slave chip; the priority calibration chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory, and the delayed calibration chip performs ZQ calibration using a calibration resistor after a certain delay based on the ZQ calibration command provided by the memory. After the priority calibration chip and the delayed calibration chip have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the master slave chip and the secondary slave chip. The master slave chip and the secondary slave chip then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby realizing theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0008] Additionally, the second transmission terminal of the last-stage first slave chip is connected to the first transmission terminal of the first master chip; the second transmission terminal of the last-stage second slave chip is connected to the first transmission terminal of the second master chip. When the first master chip receives the ZQ flag signal, it proves that all first slave chips have completed ZQ calibration; when the second master chip receives the ZQ flag signal, it proves that all second slave chips have completed ZQ calibration, and the memory can proceed to the next operation.

[0009] In addition, the delay calibration chip also includes a third transmission terminal, which is enabled in background mode to receive the ZQ flag signal. The third transmission terminal is connected to the second transmission terminal of the last master-slave chip. The identification module is configured to identify the priority calibration chip and the delay calibration chip before entering background mode. In background mode, the first signal receiver is used to receive the clock signal or power-on signal provided by the memory through the ZQ signal terminal. The priority calibration chip starts calibration based on the clock signal or power-on signal. After the priority calibration chip completes calibration, it sends the ZQ flag signal through the second transmission terminal. The master-slave chip, the delay calibration chip, and the secondary slave chip start calibration based on the ZQ flag signal.

[0010] In addition, the priority calibration chip also includes a fourth transmission terminal, which is enabled in background mode to receive the ZQ flag signal. This fourth transmission terminal is connected to the second transmission terminal of the last-level slave chip. When the priority calibration chip receives the ZQ flag signal, it indicates that all slave chips have completed ZQ calibration in background mode, and the memory can proceed to the next step.

[0011] Additionally, the first signal receiver includes: a first selector, one input for receiving a ZQ calibration command, another input for delaying the ZQ calibration command after receiving it, and a selection terminal for receiving a priority calibration flag signal or a delayed calibration flag signal; the first selector is configured to output a ZQ calibration command based on the priority calibration flag signal, or output a delayed ZQ calibration command based on the delayed calibration flag signal; a first AND gate, one input connected to the output of the first selector, and another input for receiving a command indication signal, the command indication signal being used to characterize that the memory is operating in command mode; a second selector, one input for receiving a clock signal or a power-on signal, and another input for receiving a ZQ flag signal transmitted through a third transmission terminal, and a selection terminal for receiving the priority calibration flag signal and the delayed calibration flag signal; the second selector is configured to output a clock signal or a power-on signal based on the priority calibration flag signal, or output a ZQ flag signal based on the delayed calibration flag signal; a second AND gate, one input connected to... The output of the second selector has another input terminal for receiving a background indication signal, which indicates that the memory is operating in background mode. The first input selector has a first input terminal connected to the output of a first AND gate, and a second input terminal connected to the output of a second AND gate. The first selection terminal is used to receive a command indication signal or a background indication signal, and the first output terminal is used to output a first internal calibration signal, which instructs either the priority calibration chip or the delayed calibration chip to perform calibration. The first input selector is configured to connect its first input terminal to the first output terminal based on the command indication signal, or to connect its second input terminal to the first output terminal based on the background indication signal. The second signal receiver includes a third AND gate, with one input terminal for receiving a ZQ flag signal, and another input terminal for receiving a first indication signal, which indicates that the current chip is either a first slave chip or a second slave chip. Its output terminal is used to output a second internal calibration signal, which instructs both the first and second slave chips to perform calibration.

[0012] In addition, the first master chip and the second master chip also include a second signal receiver, and the slave chip also includes a first signal receiver; the first master chip, the first slave chip, the second master chip and the second slave chip also include: a second input selector, a third input terminal for receiving a first internal calibration signal, a fourth input terminal for receiving a second internal calibration signal, a second selection terminal for receiving a first indication signal or a second indication signal, the second indication signal being used to characterize whether the current chip is a priority calibration chip or a delayed calibration chip, and a second output terminal for outputting the first internal calibration signal and the second internal calibration signal; wherein, the third input selector is configured to connect the fourth input terminal to the second output terminal based on the first indication signal, or to connect the third input terminal to the second output terminal based on the second indication signal.

[0013] In addition, the identification module is integrated into the first main chip or the second main chip; the identification module is configured to detect whether the other main chip is in ZQ calibration state in the first clock cycle; if the other main chip is in ZQ calibration state, the identification module sets the current main chip as the delay calibration chip and the other main chip as the priority calibration chip; if the other main chip is not in ZQ calibration state, the identification module sets the current main chip as the priority calibration chip and the other main chip as the delay calibration chip.

[0014] In addition, before setting the current main chip as the priority calibration chip, the identification module is also configured to detect whether the level at the calibration resistor interface is higher than a first preset value in the second clock cycle; if the level at the calibration resistor interface is lower than the first preset value, the identification module sets the current main chip as the delay calibration chip and sets the other main chip as the priority calibration chip; if the level at the calibration resistor interface is higher than the first preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

[0015] In addition, before setting the current main chip as the priority calibration chip, the identification module is also configured to, in the third clock cycle, enable the pull-down transistor in the ZQ calibration module of the current main chip and detect whether the level at the calibration resistor interface is lower than the second preset value; if the level at the calibration resistor interface is lower than the second preset value, the identification module sets the current main chip as the delay calibration chip and sets the other main chip as the priority calibration chip; if the level at the calibration resistor interface is higher than the second preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

[0016] In addition, before setting the current main chip as the priority calibration chip, the identification module is also configured to, in the fourth clock cycle, disable the pull-down transistor in the ZQ calibration module of the current main chip and detect whether the level at the calibration resistor interface is higher than a first preset value; if the level at the calibration resistor interface is lower than the first preset value, the identification module sets the current main chip as the delay calibration chip and sets the other main chip as the priority calibration chip; if the level at the calibration resistor interface is higher than the first preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

[0017] Another embodiment of this disclosure provides a ZQ calibration method applied to the memory device provided in the above embodiments, comprising: identifying a priority calibration chip and a delay calibration chip in a first master chip and a second master chip, and designating a first slave chip or a second slave chip cascaded with the priority calibration chip as a master-slave chip, and a first slave chip or a second slave chip cascaded with the delay calibration chip as a secondary slave chip; in command mode, acquiring a ZQ calibration command applied externally to the memory device; in response to the ZQ calibration command, performing a first calibration operation on the priority calibration chip; after the first calibration operation is completed, transmitting a ZQ flag signal to the first-level master-slave chip, and simultaneously performing a second calibration operation on the priority calibration chip; in response to the ZQ flag signal, performing a first calibration operation on the first-level master-slave chip; and after the first calibration operation on the first-level master-slave chip is completed... The process involves transmitting the ZQ flag signal to the next-level master / slave chip, simultaneously performing a second calibration operation on the first-level master / slave chip, until the last-level master / slave chip completes the first calibration operation; performing the second calibration operation on the last-level master / slave chip; responding to the delayed ZQ calibration command, performing a first calibration operation on the delayed calibration chip; after the first calibration operation is completed, transmitting the ZQ flag signal to the first-level secondary slave chip, simultaneously performing a second calibration operation on the delayed calibration chip; responding to the ZQ flag signal, performing a first calibration operation on the first-level secondary slave chip; after the first calibration operation of the first-level secondary slave chip is completed, transmitting the ZQ flag signal to the next-level secondary slave chip, simultaneously performing a second calibration operation on the first-level secondary slave chip, until the last-level secondary slave chip completes the first calibration operation; and performing the second calibration operation on the last-level secondary slave chip.

[0018] Additionally, the system identifies the priority calibration chip and the delayed calibration chip in the first and second master chips, designating the first or second slave chip cascaded with the priority calibration chip as the master-slave chip, and the first or second slave chip cascaded with the delayed calibration chip as the secondary slave chip. In background mode, in response to the ZQ calibration command, a first calibration operation is performed on the priority calibration chip. After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level master-slave chip, while a second calibration operation is performed on the priority calibration chip. In response to the ZQ flag signal, a first calibration operation is performed on the first-level master-slave chip. After the first calibration operation on the first-level master-slave chip is completed, the ZQ flag signal is transmitted to the next-level master-slave chip, while a second calibration operation is performed on the first-level master-slave chip. The calibration process continues until the last-level master-slave chip completes the first calibration operation; the ZQ flag signal is transmitted to the delayed calibration chip, while a second calibration operation is performed on the last-level master-slave chip; in response to the ZQ flag signal, a first calibration operation is performed on the delayed calibration chip; after the first calibration operation is completed, the ZQ flag signal is transmitted to the next-level slave chip, while a second calibration operation is performed on the delayed calibration chip; in response to the ZQ flag signal, a first calibration operation is performed on the first-level slave chip; after the first calibration operation of the first-level slave chip is completed, the ZQ flag signal is transmitted to the next-level slave chip, while a second calibration operation is performed on the first-level slave chip, until the last-level slave chip completes the first calibration operation; the second calibration operation is performed on the last-level slave chip.

[0019] In addition, before entering background mode, the priority calibration chip and the delay calibration chip are identified, including: in the first clock cycle, detecting whether the other main chip is in ZQ calibration state; if the other main chip is in ZQ calibration state, the current main chip is set as the delay calibration chip and the other main chip is set as the priority calibration chip; if the other main chip is not in ZQ calibration state, the current main chip is set as the priority calibration chip and the other main chip is set as the delay calibration chip.

[0020] In addition, before setting the current main chip as the priority calibration chip, the method further includes: in the second clock cycle, detecting whether the level at the calibration resistor interface is higher than a first preset value; if the level at the calibration resistor interface is higher than the first preset value, then setting the current main chip as the delay calibration chip and setting the other main chip as the priority calibration chip; if the level at the calibration resistor interface is lower than the first preset value, then setting the current main chip as the priority calibration chip and setting the other main chip as the delay calibration chip.

[0021] In addition, before setting the current main chip as the priority calibration chip, the process includes: in the third clock cycle, turning on the pull-down transistor in the ZQ calibration module of the current main chip and detecting whether the level at the calibration resistor interface is lower than the second preset value; if the level at the calibration resistor interface is lower than the second preset value, then setting the current main chip as the delay calibration chip and setting the other main chip as the priority calibration chip; if the level at the calibration resistor interface is higher than the second preset value, then setting the current main chip as the priority calibration chip and setting the other main chip as the delay calibration chip.

[0022] In addition, before setting the current master chip as the priority calibration chip, the process includes: in the fourth clock cycle, disabling the pull-down transistor in the ZQ calibration module of the current master chip, and detecting whether the level at the calibration resistor interface is higher than a first preset value; if the level at the calibration resistor interface is higher than the first preset value, then the current master chip is set as the delay calibration chip, and the other master chip is set as the priority calibration chip; if the level at the calibration resistor interface is lower than the first preset value, then the current master chip is set as the priority calibration chip, and the other master chip is set as the delay calibration chip. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram showing two calibration resistor interfaces connected to the same ZQ calibration resistor according to an embodiment of the present disclosure;

[0025] Figures 2-5 This is a schematic diagram of the structure of a memory device with different connection methods according to an embodiment of the present disclosure;

[0026] Figure 6 This is a schematic diagram of the structure of a first signal receiver provided in an embodiment of the present disclosure;

[0027] Figure 7 This is a schematic diagram of the structure of a second signal receiver provided in an embodiment of the present disclosure;

[0028] Figure 8 This is a schematic diagram of the integrated structure of a first signal receiver and a second signal receiver provided in an embodiment of the present disclosure;

[0029] Figure 9 A schematic diagram of the identification process of an identification module provided in an embodiment of this disclosure;

[0030] Figure 10 Timing and schematic diagram of a ZQ calibration method for a memory device in command mode, provided in another embodiment of this disclosure;

[0031] Figure 11 The timing diagram and schematic diagram are provided for a ZQ calibration method for a memory device in background mode, according to another embodiment of this disclosure. Detailed Implementation

[0032] As the background technology shows, with the increasing demand for LPDDR capacity, more and more chips are put into one LPDDR package. Each chip needs to be individually calibrated due to individual differences. In particular, the number of ZQ calibration resistors in LPDDR5 packages is significantly reduced compared to the number of ZQ calibration resistors in LPDDR4, requiring more chips to share a single ZQ.

[0033] One embodiment of this disclosure provides a memory device that, through the design of a novel control circuit, enables theoretically unlimited numbers of chips to share a ZQ calibration resistor.

[0034] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0035] Figure 1 This is a schematic diagram showing the two calibration resistor interfaces connected to the same ZQ calibration resistor in this embodiment. Figures 2-5 This is a schematic diagram of the structure of the memory device under different connection methods provided in this embodiment. Figure 6 This is a schematic diagram of the structure of the first signal receiver provided in this embodiment. Figure 7 This is a schematic diagram of the structure of the second signal receiver provided in this embodiment. Figure 8 This is a schematic diagram of the integrated structure of the first and second signal receivers provided in this embodiment. Figure 9 This is a schematic diagram of the identification process of the identification module provided in this embodiment. The structure of the memory device provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0036] Memory devices, including:

[0037] There are two calibration resistor interfaces, and both calibration resistor interfaces are connected to the same ZQ calibration resistor.

[0038] refer to Figure 1 The memory device is an LPDDR5 memory device 10, which includes: a first calibration resistor interface, a second calibration resistor interface, a first calibration command interface, and a second calibration command interface. The calibration command received by the first calibration command interface is calibrated through the calibration resistor connected to the first calibration resistor interface, and the calibration command received by the second calibration command interface is calibrated through the calibration resistor connected to the second calibration resistor interface. In this embodiment, the first and second calibration resistor interfaces are both connected to the same ZQ calibration resistor Rzq. Accordingly, the first and second calibration command interfaces perform calibration based on the ZQ calibration command through the ZQ calibration resistor Rzq.

[0039] refer to Figures 2-5 The memory device also includes: a first master chip commonly connected to the ZQ calibration resistor, multiple cascaded first slave chips, a second master chip, and multiple cascaded second slave chips.

[0040] The first master chip, the first slave chip, the second master chip, and the second slave chip are provided with a first transmission terminal A and a second transmission terminal B, wherein the first transmission terminal A and the second transmission terminal B are used to transmit the ZQ flag signal.

[0041] It should be noted that the "cascading" mentioned above refers to: multiple first slave chips respectively serving as first-level first slave chips, second-level first slave chips, ..., M-1-level first slave chips and M-level first slave chips connected end-to-end; and multiple second slave chips respectively serving as first-level second slave chips, second-level second slave chips, ..., K-1-level second slave chips and K-level second slave chips connected end-to-end. Specifically, the second transmission terminal B of the first master chip is connected to the first transmission terminal A of the first-level first slave chip, and the second transmission terminal B of each first slave chip is connected to the first transmission terminal A of the next-level first slave chip; similarly, the second transmission terminal B of the second master chip is connected to the first transmission terminal A of the first-level second slave chip, and the second transmission terminal B of each second slave chip is connected to the first transmission terminal A of the next-level second slave chip.

[0042] The first master chip and the second master chip are equipped with a first signal receiver, and the first slave chip and the second slave chip are equipped with a second signal receiver.

[0043] The identification module is used to identify the first master chip and the second master chip, one of which is the priority calibration chip and the other is the delay calibration chip. The first slave chip or the second slave chip cascaded with the priority calibration chip is the master slave chip, and the first slave chip or the second slave chip cascaded with the delay calibration chip is the secondary slave chip.

[0044] Specifically, in command mode, the first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal, or to receive the ZQ calibration command through the ZQ signal terminal and then delay the ZQ calibration command. The priority calibration chip starts calibration based on the ZQ calibration command, and the delay calibration chip starts calibration based on the delayed ZQ calibration command. After the first master chip and the second master chip complete calibration, they send a ZQ flag signal through the second transmission terminal B. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The second signal receiver is used to receive the ZQ flag signal through the first transmission terminal A. The master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal. After the current master-slave chip and the secondary slave chip complete calibration, they send a ZQ flag signal through the second transmission terminal B until all first slave chips or second slave chips have completed calibration.

[0045] In the memory device provided in this embodiment, multiple chips calibrated through a first calibration interface are configured as a first master chip and multiple first slave chips; multiple chips calibrated through a second calibration interface are configured as a second master chip and multiple second slave chips; a recognition module identifies the priority calibration chip and the delayed calibration chip in the first master chip and the second master chip, and the first slave chip or the second slave chip cascaded with the priority calibration chip is the master slave chip, and the first slave chip or the second slave chip cascaded with the delayed calibration chip is the secondary slave chip; the priority calibration chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory, and the delayed calibration chip performs ZQ calibration using a calibration resistor after a certain delay based on the ZQ calibration command provided by the memory. After the priority calibration chip and the delayed calibration chip have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the master slave chip and the secondary slave chip. The master slave chip and the secondary slave chip then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby realizing theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0046] It should be noted that, regarding the "delay" mentioned above, in some embodiments, the delay is half a calibration cycle. That is, in the first half of the calibration cycle, the priority calibration chip and the master-slave chip are calibrated based on the ZQ calibration resistor, and in the second half of the calibration cycle, the delay calibration signal and the secondary slave chip are calibrated based on the ZQ calibration resistor. The specific "delay" can be limited according to the number of chips, where the number of chips includes the number of chipsets and the total number of master chips and slave chips in the same chipset. This embodiment does not constitute a limitation on the specific delay time.

[0047] for Figures 2-5The first master chip, first slave chip, second master chip, and second slave chip shown are used to reset the chip according to the reset signal, to select the target chip for enable according to the strobe signal, and to complete data writing or reading according to the clock signal and data signal; it should be noted that... Figures 2-5 The reset signal, data signal, clock signal, and strobe signal shown are used to illustrate the operation of the first master chip, the first slave chip, the second master chip, and the second slave chip, and do not constitute a limitation on the structure of the memory device.

[0048] refer to Figures 2-5 In some embodiments, the second transmission terminal B of the last-stage first slave chip is connected to the first transmission terminal A of the first master chip; the second transmission terminal B of the last-stage second slave chip is connected to the first transmission terminal A of the second master chip. When the first master chip receives the ZQ flag signal, it proves that all first slave chips have completed ZQ calibration; when the second master chip receives the ZQ flag signal, it proves that all second slave chips have completed ZQ calibration, and the memory can proceed to the next operation.

[0049] refer to Figure 4 and Figure 5 In some embodiments, the delay calibration chip further includes a third transmission terminal C, which is enabled in background mode and is used to receive the ZQ flag signal. Specifically, the third transmission terminal C is used to receive the ZQ flag signal sent by the last master-slave chip. In background mode, the delay calibration chip starts calibration based on the ZQ flag signal.

[0050] The identification module is configured to identify priority calibration chips and delayed calibration chips before entering background mode.

[0051] In background mode, the first signal receiver receives the clock signal or power-on signal provided by the memory through the ZQ signal terminal. The priority calibration chip starts calibration based on the clock signal or power-on signal. After completing calibration, the priority calibration chip sends the ZQ flag signal through the second transmission terminal. The master-slave chip, the delay calibration chip, and the secondary slave chip start calibration sequentially based on the ZQ flag signal. Specifically, after the priority calibration chip completes ZQ calibration, it sends the ZQ flag signal to the first-level master-slave chip through the second transmission terminal B. The ZQ flag signal sent by the last-level master-slave chip after completing ZQ calibration is received by the delay calibration chip through the third transmission terminal C. The delay calibration chip performs calibration based on the ZQ flag signal. After completing ZQ calibration, the delay calibration chip sends the ZQ flag signal to the first-level secondary slave chip through the second transmission terminal B, until the last-level secondary slave chip completes ZQ calibration.

[0052] In some embodiments, the priority calibration chip further includes a fourth transmission terminal D, which is enabled in background mode and used to transmit the ZQ flag signal. The fourth transmission terminal is connected to the second transmission terminal B of the last-level slave chip. When the priority calibration chip receives the ZQ flag signal, it proves that all slave chips have completed ZQ calibration in background mode, and the memory can proceed to the next operation. It should be noted that in command mode, the priority calibration chip receives the ZQ flag signal sent by the last-level master-slave chip through the first transmission terminal; in background mode, the priority calibration chip receives the ZQ flag signal sent by the last-level slave chip through the fourth transmission terminal.

[0053] It should be noted that, Figures 2-5 This diagram illustrates a first master chip as the priority calibration chip, a first slave chip as the master-slave chip, a second master chip as the delay calibration chip, and a second slave chip as the secondary slave chip. It is only intended for those skilled in the art to understand the implementation of the calibration process disclosed herein and does not constitute a limitation on this embodiment. In other embodiments, the second master chip can also be the priority calibration chip, the second slave chip as the master-slave chip, the first master chip as the delay calibration chip, and the first slave chip as the secondary slave chip.

[0054] In some embodiments, reference Figure 6The first signal receiver 100 includes: a first selector 401, one input for receiving a ZQ calibration command, another input for delaying the ZQ calibration command after receiving it, and a selection terminal for receiving a priority calibration flag signal or a delayed calibration flag signal, wherein the priority calibration flag signal indicates that the current main chip is a priority calibration chip, and the delayed calibration flag signal indicates that the current main chip is a delayed calibration chip; the first selector 401 is configured to output a ZQ calibration command based on the priority calibration flag signal, or output a delayed ZQ calibration command based on the delayed calibration flag signal; a first AND gate 101, one input connected to the output of the first selector 401, and another input for receiving a command indication signal, which indicates that the memory is operating in command mode; a second selector 402, one input for receiving a clock signal or a power-on signal, and another input for receiving a ZQ flag signal transmitted by a third transmission terminal, and a selection terminal for receiving... The system receives either a priority calibration flag signal or a delayed calibration flag signal; the second selector 402 is configured to output a clock signal or a power-on signal based on the priority calibration flag signal, or to output a ZQ flag signal based on the delayed calibration flag signal; the second AND gate 102 has one input connected to the output of the second selector 402, and the other input used to receive a background indication signal, which indicates that the memory is operating in background mode; the first input selector 103 has a first input connected to the output of the first AND gate 101, and a second input connected to the output of the second AND gate 102. The first input is used to receive a command indication signal or a background indication signal, and the first output is used to output a first internal calibration signal, which instructs the priority calibration chip and the delayed calibration chip to perform calibration; wherein, the first input selector 103 is configured to connect the first input to the first output based on the command indication signal, or to connect the second input to the first output based on the background indication signal.

[0055] In some embodiments, the memory device further includes a delay unit 201 for delaying the ZQ calibration signal received by the first signal receiver 100. The delay unit 201 delays the ZQ calibration command. The delay unit 201 may be composed of an even number of inverters. This disclosure does not limit the structure of the delay unit 201.

[0056] It should be noted that, regarding the command mode and background mode mentioned in this embodiment, the memory is started based on a preset command in command mode, and the memory is started based on its internal signals in background mode. The internal signals include the power-on signal and the clock signal.

[0057] Specifically, if the first signal receiver 100 receives a priority calibration flag signal, after being selected and turned on by the first selector 401 and the second selector 402, the first signal receiver 100 is used to instruct the priority calibration chip to work. Specifically: when the memory is in command mode, it provides a command indication signal to the first signal receiver 100. The first input selector 103 connects the first input terminal to the first output terminal based on the command indication signal. At this time, the first signal receiver 100 provides a first internal calibration signal based on the output of the first AND gate 101. That is, when the first signal receiver 100 receives a ZQ calibration command, it generates the first internal calibration signal, thereby controlling the priority calibration chip to perform ZQ calibration. When the memory is in background mode, it provides a background indication signal to the first signal receiver 100. The first input selector 103 connects the second input terminal to the first output terminal based on the background indication signal. At this time, the first signal receiver 100 provides a first internal calibration signal based on the output of the second AND gate 102. That is, when the first signal receiver 100 receives a clock signal or a power-on signal, it generates the first internal calibration signal, thereby controlling the priority calibration chip to perform ZQ calibration.

[0058] If the first signal receiver 100 receives a delayed calibration flag signal, and after being selected and turned on by the first selector 401 and the second selector 402, the first signal receiver 100 is used to instruct the delayed calibration chip to work. Specifically: when the memory is in command mode, it provides a command indication signal to the first signal receiver 100. The first input selector 103 connects the first input terminal to the first output terminal based on the command indication signal. At this time, the first signal receiver 100 provides a first internal calibration signal based on the output of the first AND gate 101. That is, when the first signal receiver 100 receives a delayed ZQ calibration command, it generates the first internal calibration signal, thereby controlling the delayed calibration chip to perform ZQ calibration. When the memory is in background mode, it provides a background indication signal to the first signal receiver 100. The first input selector 103 connects the second input terminal to the first output terminal based on the background indication signal. At this time, the first signal receiver 100 provides the first internal calibration signal based on the output of the second AND gate 102. That is, when the first signal receiver 100 receives a ZQ flag signal, it generates the first internal calibration signal, thereby controlling the delayed calibration chip to perform ZQ calibration.

[0059] In some embodiments, reference Figure 7 The second signal receiver 200 includes: a third AND gate 305, one input terminal for receiving the ZQ flag signal, another input terminal for receiving the first indication signal, the first indication signal for characterizing whether the current chip is a first slave chip or a second slave chip, and an output terminal for outputting a second internal calibration signal, the second internal calibration signal for instructing the first slave chip and the second slave chip to perform calibration.

[0060] Specifically, the second signal receiver 200 is disposed in the first slave chip and the second slave chip. The second signal receiver 200 continuously receives the first indication signal so that when the third signal receiver 300 receives the ZQ flag signal, it can generate a second internal calibration signal, thereby controlling the first slave chip and the second slave chip to perform ZQ calibration.

[0061] Figure 2 and Figure 4 In the memory device structure shown, only the first master chip and the second master chip receive the ZQ calibration command, and the structures of the first master chip, the first slave chip, the second master chip, and the second slave chip differ; Reference Figure 3 and Figure 5 In some embodiments, the first master chip, the first slave chip, the second master chip, and the second slave chip have the same structure. In this case, the first slave chip and the second slave chip also need to receive ZQ calibration commands. The first master chip and the second master chip also include a second signal receiver 200, and the first slave chip and the second slave chip also include a first signal receiver 100.

[0062] refer to Figure 8 The first master chip, the first slave chip, the second master chip, and the second slave chip further include: a second input selector 403, a third input terminal for receiving a first internal calibration signal, a fourth input terminal for receiving a second internal calibration signal, a second selection terminal for receiving a first indication signal or a second indication signal, the second indication signal being used to characterize whether the current chip is a priority calibration chip or a delayed calibration chip, and a second output terminal for outputting the first internal calibration signal or the second internal calibration signal; wherein, the second input selector 403 is configured to connect the fourth input terminal to the second output terminal based on the first indication signal, or to connect the third input terminal to the second output terminal based on the second indication signal.

[0063] Specifically, the second input selector 403 selects the output based on the first indication signal and the second indication signal. If the second indication signal is received, it indicates that the current chip is a priority calibration chip or a delay calibration chip, that is, the first master chip or the second master chip, and the second input selector 403 selects the output signal of the first signal receiver 100 for output. If the first indication signal is received, it indicates that the current chip is a first slave chip or a second slave chip, and the second input selector 403 selects the output signal of the second signal receiver 200 for output.

[0064] refer to Figures 2-5In this embodiment, the number of first slave chips equals the number of second slave chips. The first master chip and the first slave chips are arranged in a first array with 1 column and N rows, and the first master chip is located at row N. The second master chip and the second slave chip are arranged in a second array with 1 column and N rows, and the second master chip is located at row N / 2. N-1 represents the number of first slave chips and the number of second slave chips. In other embodiments, the chips can be arranged in an array with i columns and j rows according to the number of chips and the layout area to be set. In this case, the first master chip is located at the array position in the first column and j-th row, and the second master chip is located at the array position in the array position in the i / 2+1 column and j / 2 row.

[0065] It is understood that the number of chips in the loop varies depending on the mode of the memory. In the embodiment shown in this disclosure, in command mode, the memory includes two calibration loops, and each calibration loop contains one master chip and N-1 slave chips. In background mode, the memory includes only one calibration loop, and the calibration loop contains two master chips and 2N-2 slave chips.

[0066] Regarding the identification module mentioned in the embodiments, the identification module is integrated into the first main chip or the second main chip, or integrated within the first main chip and the second main chip, but only one identification module is enabled at any given time. (See reference...) Figure 9 The identification module is configured to detect whether another main chip is in ZQ calibration state during the first clock cycle. Specifically, if the other main chip is in ZQ calibration state, then there is already a main chip that takes priority over the current main chip for calibration, and the identification module sets the current main chip as the delayed calibration chip and the other main chip as the priority calibration chip; if the other main chip is not in ZQ calibration state, then there is no main chip for calibration in the current state, and the identification module sets the current main chip as the priority calibration chip and the other main chip as the delayed calibration chip.

[0067] It should be noted that the identification module detects whether another main chip is in ZQ calibration state by detecting the main chip's flag bit. The flag bit is used to characterize whether the loop containing the main chip is in ZQ calibration state. Specifically, when the main chip receives a ZQ calibration command or receives a ZQ flag signal for the first time, the aforementioned flag bit is in a first state; correspondingly, after the main chip with the flag bit in the first state receives the ZQ flag signal, the aforementioned flag bit is in a second state.

[0068] To ensure the accuracy of the recognition module, please continue to refer to... Figure 9 Before setting the current main chip as the priority calibration chip, the identification module is also configured to detect whether the level at the calibration resistor interface is higher than a first preset value during the second clock cycle. (See details...) Figure 1 In one example, the first preset value is set to V.DDQ / 2; When the main chip is using the calibration resistor Rzq for calibration, the voltage level at the calibration resistor interface will decrease; when the main chip is not using the calibration resistor Rzq for calibration, the voltage level at the calibration resistor interface will be close to V. DDQ Therefore, if the voltage level at the calibration resistor interface is lower than the first preset value, the identification module sets the current main chip as the delayed calibration chip and the other main chip as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the first preset value, the identification module sets the current chip as the priority calibration chip and the other main chip as the delayed calibration resistor.

[0069] To further ensure the accuracy of the recognition module, continue to refer to... Figure 9 Before setting the current main chip as the priority calibration chip, the identification module is also configured to, within the third clock cycle, enable the pull-down transistor in the ZQ calibration module of the current main chip and detect whether the level at the calibration resistor interface is lower than the second preset value; see details. Figure 1 In one example, the first preset value is set to V. DDQ / 4; When multiple main chips are calibrated using the calibration resistor Rzq, the voltage level at the calibration resistor interface will further decrease. Therefore, if the voltage level at the calibration resistor interface is lower than the second preset value, the identification module will set the current main chip as the delayed calibration chip and the other main chip as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the second preset value, the identification module will set the current main chip as the priority calibration chip and the other main chip as the delayed calibration chip.

[0070] To further ensure the accuracy of the recognition module, continue to refer to... Figure 9 Before setting the current master chip as the priority calibration chip, the identification module is also configured to, during the fourth clock cycle, disable the pull-down transistor in the ZQ calibration module of the current master chip and detect whether the level at the calibration resistor interface is higher than a first preset value; when a master chip is using the calibration resistor Rzq for calibration, the level at the calibration resistor interface will decrease; when no master chip is using the calibration resistor Rzq for calibration, the level at the calibration resistor interface will approach V. DDQ Therefore, if the voltage level at the calibration resistor interface is lower than the first preset value, the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the first preset value, the current chip is set as the priority calibration chip, and the other main chip is set as the delayed calibration resistor.

[0071] It should be noted that the above example sets the first preset value to V. DDQ / 2 does not constitute a limitation on the first preset value. The first preset value can be set to any threshold, which is the level value at the calibration resistor interface and is used to distinguish whether a chip is being calibrated using the calibration resistor. Additionally, the example above sets the second preset value to V. DDQ / 4 does not constitute a limitation on the second preset value. The second preset value can be set to any threshold value, which is the level value at the calibration resistor interface and is used to distinguish whether multiple chips are calibrated using the calibration resistor.

[0072] In the memory device provided in this embodiment, multiple chips calibrated through a first calibration interface are configured as a first master chip and multiple first slave chips; multiple chips calibrated through a second calibration interface are configured as a second master chip and multiple second slave chips; a recognition module identifies the priority calibration chip and the delayed calibration chip in the first master chip and the second master chip, and the first slave chip or the second slave chip cascaded with the priority calibration chip is the master slave chip, and the first slave chip or the second slave chip cascaded with the delayed calibration chip is the secondary slave chip; the priority calibration chip performs ZQ calibration using a calibration resistor based on the ZQ calibration command provided by the memory, and the delayed calibration chip performs ZQ calibration using a calibration resistor after a certain delay based on the ZQ calibration command provided by the memory. After the priority calibration chip and the delayed calibration chip have finished performing ZQ calibration using the calibration resistor, they send a ZQ flag signal to the master slave chip and the secondary slave chip. The master slave chip and the secondary slave chip then sequentially perform ZQ calibration using the ZQ calibration resistor based on the ZQ flag signal, thereby realizing theoretically unlimited number of chips sharing the ZQ calibration resistor for ZQ calibration.

[0073] It should be noted that, given the limitation on ZQ calibration time, the number of chips sharing the ZQ calibration resistor is also limited. The longer the time required for each chip to perform ZQ calibration, the fewer chips are needed to share the ZQ calibration resistor. Furthermore, the features disclosed in the memory devices provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory device embodiments.

[0074] Another embodiment of this disclosure provides a ZQ calibration method applied to the memory device provided in the above embodiments, thereby enabling theoretically unlimited number of chips to share a ZQ calibration resistor for ZQ calibration.

[0075] Figure 10 This embodiment provides the timing diagram and schematic diagram corresponding to the ZQ calibration method for memory devices in command mode. Figure 11 The following is a timing diagram and schematic diagram of the ZQ calibration method provided in this embodiment for a memory device in background mode. The ZQ calibration method provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0076] refer to Figure 10 The ZQ calibration method includes: identifying a priority calibration chip and a delayed calibration chip in a first master chip and a second master chip, and designating a first slave chip or a second slave chip cascaded with the priority calibration chip as a master-slave chip, and a first slave chip or a second slave chip cascaded with the delayed calibration chip as a secondary slave chip; in command mode, acquiring a ZQ calibration command applied externally to the memory device, and in response to the ZQ calibration command, performing a first calibration operation on the priority calibration chip; after the first calibration operation is completed, transmitting a ZQ flag signal to the first-level master-slave chip, and simultaneously performing a second calibration operation on the priority calibration chip; in response to the ZQ flag signal, performing a first calibration operation on the first-level master-slave chip, and after the first calibration operation on the first-level master-slave chip is completed, transmitting the ZQ flag signal to the next-level master chip. Simultaneously, the first-level master-slave chip performs a second calibration operation until the last-level master-slave chip completes the first calibration operation and then performs the second calibration operation. In response to a delayed ZQ calibration command, the first calibration operation is performed on the delayed calibration chip. After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level secondary slave chip, and the second calibration operation is performed on the delayed calibration chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level secondary slave chip. After the first calibration operation of the first-level secondary slave chip is completed, the ZQ flag signal is transmitted to the next-level secondary slave chip, and the second calibration operation is performed on the first-level secondary slave chip, until the last-level secondary slave chip completes the first calibration operation and then performs the second calibration operation.

[0077] In some embodiments, while performing the second calibration operation on the last-stage master-slave chip, the method further includes: transmitting a ZQ flag signal to the priority calibration chip; while performing the second calibration operation on the last-stage secondary slave chip, the method further includes: transmitting a ZQ flag signal to the delay calibration chip. When the priority calibration chip receives the ZQ flag signal, it proves that all master-slave chips have completed ZQ calibration; when the delay calibration chip receives the ZQ flag signal, it proves that all secondary slave chips have completed ZQ calibration, and the memory can proceed to the next operation.

[0078] It should be noted that, Figure 10 The ZQ calibration timing diagram shown uses a three-level slave chip as an example for illustration. It is only for those skilled in the art to understand the implementation of ZQ calibration in this embodiment and does not constitute a limitation of this embodiment. Figure 10 The illustration and the ZQ calibration method mentioned above can be used to... Figure 10 The timing is further derived to apply to the case of K first slave chips and second slave chips.

[0079] refer to Figure 11The ZQ calibration method further includes: identifying a priority calibration chip and a delayed calibration chip in the first master chip and the second master chip, and designating a first slave chip or a second slave chip cascaded with the priority calibration chip as a master-slave chip, and a first slave chip or a second slave chip cascaded with the delayed calibration chip as a secondary slave chip; in background mode, in response to a ZQ calibration command, performing a first calibration operation on the priority calibration chip; after the first calibration operation is completed, transmitting a ZQ flag signal to the first-level master-slave chip, and simultaneously performing a second calibration operation on the priority calibration chip; in response to the ZQ flag signal, performing a first calibration operation on the first-level master-slave chip; after the first calibration operation on the first-level master-slave chip is completed, transmitting the ZQ flag signal to the next-level master-slave chip, and simultaneously performing a second calibration operation on the first-level master-slave chip. The second calibration operation continues until the last-level master-slave chip completes the first calibration operation; the ZQ flag signal is transmitted to the delayed calibration chip, and the second calibration operation is performed on the last-level master-slave chip simultaneously; in response to the ZQ flag signal, the first calibration operation is performed on the delayed calibration chip; after the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level secondary slave chip, and the second calibration operation is performed on the delayed calibration chip simultaneously; in response to the ZQ flag signal, the first calibration operation is performed on the first-level secondary slave chip; after the first calibration operation of the first-level secondary slave chip is completed, the ZQ flag signal is transmitted to the next-level secondary slave chip, and the second calibration operation is performed on the first-level secondary slave chip simultaneously, until the last-level secondary slave chip completes the first calibration operation; the second calibration operation is completed on the last-level secondary slave chip.

[0080] In some embodiments, in background mode, while performing the second calibration operation on the last-stage slave chip, the process also includes transmitting a ZQ flag signal to the priority calibration chip. When the priority calibration chip receives the ZQ flag signal, it indicates that all chips have completed ZQ calibration, and the memory can proceed to the next step.

[0081] It should be noted that, Figure 11 The ZQ calibration timing diagram shown uses a three-level slave chip as an example for illustration. It is only for those skilled in the art to understand the implementation of ZQ calibration in this embodiment and does not constitute a limitation of this embodiment. Figure 11 The illustration and the ZQ calibration method mentioned above can be used to... Figure 11 The timing is further derived to apply to the case of K first slave chips and second slave chips.

[0082] In some embodiments, prior to entering background mode, a priority calibration chip and a delayed calibration chip are identified among the first master chip, the second master chip, the first slave chip, and the second slave chip; wherein, the first slave chip or the second slave chip cascaded with the priority calibration chip is a master slave chip, and the first slave chip or the second slave chip cascaded with the delayed calibration chip is a secondary slave chip.

[0083] Specifically, refer to Figure 9 In the first clock cycle, it checks whether the other main chip is in ZQ calibration state. Specifically, if the other main chip is in ZQ calibration state, then there is already a main chip that has been calibrated before the current main chip, so the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; if the other main chip is not in ZQ calibration state, then there is no main chip to be calibrated in the current state, so the current main chip is set as the priority calibration chip, and the other main chip is set as the delayed calibration chip.

[0084] To ensure the accuracy of the identification, please continue to refer to... Figure 9 Before setting the current main chip as the priority calibration chip, it is also configured to detect whether the level at the calibration resistor interface is higher than a first preset value during the second clock cycle. (See details...) Figure 1 In one example, the first preset value is set to V. DDQ / 2; When the main chip is using the calibration resistor Rzq for calibration, the voltage level at the calibration resistor interface will decrease; when the main chip is not using the calibration resistor Rzq for calibration, the voltage level at the calibration resistor interface will be close to V. DDQ Therefore, if the voltage level at the calibration resistor interface is lower than the first preset value, the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the first preset value, the current chip is set as the priority calibration chip, and the other main chip is set as the delayed calibration resistor.

[0085] To further ensure the accuracy of the identification, please continue to refer to... Figure 9 Before setting the current main chip as the priority calibration chip, it is also configured to, during the third clock cycle, enable the pull-down transistor in the ZQ calibration module of the current main chip and check whether the level at the calibration resistor interface is lower than the second preset value; see details. Figure 1 In one example, the first preset value is set to V. DDQ / 4; When multiple main chips are calibrated using the calibration resistor Rzq, the voltage level at the calibration resistor interface will further decrease. Therefore, if the voltage level at the calibration resistor interface is lower than the second preset value, the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the second preset value, the current main chip is set as the priority calibration chip, and the other main chip is set as the delayed calibration chip.

[0086] To further ensure the accuracy of the identification, please continue to refer to... Figure 9Before setting the current master chip as the priority calibration chip, it is also configured to, during the fourth clock cycle, disable the pull-down transistor in the ZQ calibration module of the current master chip and check whether the level at the calibration resistor interface is higher than a first preset value; when a master chip is using the calibration resistor Rzq for calibration, the level at the calibration resistor interface will decrease; when no master chip is using the calibration resistor Rzq for calibration, the level at the calibration resistor interface will approach V. DDQ Therefore, if the voltage level at the calibration resistor interface is lower than the first preset value, the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; if the voltage level at the calibration resistor interface is higher than the first preset value, the current chip is set as the priority calibration chip, and the other main chip is set as the delayed calibration resistor.

[0087] It should be noted that the above example sets the first preset value to V. DDQ / 2 does not constitute a limitation on the first preset value. The first preset value can be set to any threshold, which is the level value at the calibration resistor interface and is used to distinguish whether a chip is being calibrated using the calibration resistor. Additionally, the example above sets the second preset value to V. DDQ / 4 does not constitute a limitation on the second preset value. The second preset value can be set to any threshold value, which is the level value at the calibration resistor interface and is used to distinguish whether multiple chips are calibrated using the calibration resistor.

[0088] It should be noted that, in this embodiment, the first calibration operation is one of the pull-up calibration operation that generates the pull-up calibration code and the pull-down calibration operation that generates the pull-down calibration code, and the second calibration operation is the other of the pull-up and pull-down calibration operations. The first calibration operation requires calibration using a calibration resistor, while the second calibration operation is based on the result of the first calibration operation and does not require a calibration resistor. Furthermore, the features disclosed in the ZQ calibration method provided in the above embodiments can be arbitrarily combined without conflict to obtain new ZQ calibration method embodiments.

[0089] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, include: Two calibration resistor interfaces, and both calibration resistor interfaces are connected to the same ZQ calibration resistor; A first master chip, multiple cascaded first slave chips, a second master chip, and multiple cascaded second slave chips are all connected to the ZQ calibration resistor. The first master chip, the first slave chip, the second master chip, and the second slave chip are provided with a first transmission terminal and a second transmission terminal, which are used to transmit the ZQ flag signal. Wherein, the second transmission terminal of the first master chip is connected to the first transmission terminal of the first slave chip of the first level, the second transmission terminal of each first slave chip of the first level is connected to the first transmission terminal of the next first slave chip, the second transmission terminal of the second master chip is connected to the first transmission terminal of the second slave chip of the first level, and the second transmission terminal of each second slave chip of the second level is connected to the first transmission terminal of the next second slave chip. The first master chip and the second master chip are provided with a first signal receiver, and the first slave chip and the second slave chip are provided with a second signal receiver; An identification module is used to identify one of the first main chip and the second main chip as a priority calibration chip and the other as a delay calibration chip. The first slave chip or the second slave chip cascaded with the priority calibration chip is a master slave chip, and the first slave chip or the second slave chip cascaded with the delay calibration chip is a secondary slave chip. In command mode, the first signal receiver is used to receive the ZQ calibration command provided by the memory through the ZQ signal terminal, or to receive the ZQ calibration command through the ZQ signal terminal and then delay the ZQ calibration command. The priority calibration chip starts calibration based on the ZQ calibration command, and the delayed calibration chip starts calibration based on the delayed ZQ calibration command. After the first main chip and the second main chip complete the calibration, they send the ZQ flag signal through the second transmission terminal. The ZQ flag signal indicates that the current chip has been calibrated using the calibration resistor. The second signal receiver is used to receive the ZQ flag signal through the first transmission terminal. The master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal. After the master-slave chip and the secondary slave chip complete calibration, they send the ZQ flag signal through the second transmission terminal until all the first slave chips or the second slave chips complete calibration.

2. The memory device according to claim 1, characterized in that, include: The second transmission terminal of the first slave chip in the last stage is connected to the first transmission terminal of the first master chip; The second transmission terminal of the second slave chip in the final stage is connected to the first transmission terminal of the second master chip.

3. The memory device according to claim 2, characterized in that, include: The delay calibration chip also includes a third transmission terminal, which is enabled in background mode to receive the ZQ flag signal. The third transmission terminal is connected to the second transmission terminal of the last-stage master-slave chip. The identification module is configured to identify the priority calibration chip and the delayed calibration chip before entering the background mode. In the background mode, the first signal receiver is used to receive a clock signal or power-on signal provided by the memory through the ZQ signal terminal. The priority calibration chip starts calibration based on the clock signal or the power-on signal. After the priority calibration chip completes calibration, it sends the ZQ flag signal through the second transmission terminal. The master-slave chip, the delay calibration chip, and the secondary slave chip start calibration based on the ZQ flag signal.

4. The memory device according to claim 3, characterized in that, The priority calibration chip further includes a fourth transmission terminal, which is enabled in background mode to receive the ZQ flag signal. The fourth transmission terminal is connected to the second transmission terminal of the last-stage slave chip.

5. The memory device according to claim 3, characterized in that, include: The first signal receiver includes: The first selector has one input terminal for receiving the ZQ calibration command, and another input terminal for delaying the ZQ calibration command after receiving it. The selection terminal is used to receive a priority calibration flag signal or a delayed calibration flag signal. The first selector is configured to output the ZQ calibration command based on the priority calibration flag signal, or output the delayed ZQ calibration command based on the delayed calibration flag signal. The first AND gate has one input connected to the output of the first selector and the other input used to receive a command indication signal, which indicates that the memory is working in command mode. The second selector has one input terminal for receiving a clock signal or a power-on signal, another input terminal for receiving the ZQ flag signal transmitted through the third transmission terminal, and a selection terminal for receiving the priority calibration flag signal and the delay calibration flag signal; the second selector is configured to output the clock signal or the power-on signal based on the priority calibration flag signal, or output the ZQ flag signal based on the delay calibration flag signal. The second AND gate has one input connected to the output of the second selector and the other input used to receive a background indication signal, which indicates that the memory is working in background mode. A first input selector has a first input terminal connected to the output terminal of a first AND gate, and a second input terminal connected to the output terminal of a second AND gate. The first selector terminal is used to receive the command indication signal or the background indication signal, and the first output terminal is used to output a first internal calibration signal, which is used to instruct the priority calibration chip or the delayed calibration chip to perform calibration. The first input selector is configured to connect the first input terminal to the first output terminal based on the command indication signal, or to connect the second input terminal to the first output terminal based on the background indication signal. The second signal receiver includes: The third AND gate has one input terminal for receiving the ZQ flag signal and another input terminal for receiving a first indication signal, which indicates that the current chip is the first slave chip or the second slave chip. The output terminal is used to output a second internal calibration signal, which instructs the first slave chip and the second slave chip to perform calibration.

6. The memory device according to claim 5, characterized in that, include: The first master chip and the second master chip also include the second signal receiver, and the slave chip also includes the first signal receiver; The first master chip, the first slave chip, the second master chip, and the second slave chip further include: The second input selector has a third input terminal for receiving the first internal calibration signal, a fourth input terminal for receiving the second internal calibration signal, a second selection terminal for receiving either the first indication signal or the second indication signal, the second indication signal being used to characterize the current chip as the priority calibration chip or the delay calibration chip, and a second output terminal for outputting the first internal calibration signal and the second internal calibration signal; wherein, the second input selector is configured to connect the fourth input terminal to the second output terminal based on the first indication signal, or to connect the third input terminal to the second output terminal based on the second indication signal.

7. The memory device according to claim 3, characterized in that, include: The identification module is integrated into the first main chip or the second main chip; The identification module is configured to detect whether the other main chip is in ZQ calibration state during the first clock cycle. If the other main chip is in ZQ calibration state, the identification module sets the current main chip as the delayed calibration chip and sets the other main chip as the priority calibration chip. If the other main chip is not in ZQ calibration state, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

8. The memory device according to claim 7, characterized in that, Before setting the current main chip as the priority calibration chip, the identification module is also configured to detect whether the level at the calibration resistor interface is higher than a first preset value during the second clock cycle. If the voltage level at the calibration resistor interface is lower than the first preset value, the identification module sets the current main chip as the delayed calibration chip and sets the other main chip as the priority calibration chip. If the voltage level at the calibration resistor interface is higher than the first preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

9. The memory device according to claim 8, characterized in that, Before setting the current main chip as the priority calibration chip, the identification module is also configured to, in the third clock cycle, turn on the pull-down transistor in the ZQ calibration module of the current main chip and detect whether the level at the calibration resistor interface is lower than the second preset value. If the voltage level at the calibration resistor interface is lower than the second preset value, the identification module sets the current main chip as the delayed calibration chip and sets the other main chip as the priority calibration chip. If the voltage level at the calibration resistor interface is higher than the second preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

10. The memory device according to claim 9, characterized in that, Before setting the current main chip as the priority calibration chip, the identification module is also configured to, in the fourth clock cycle, turn off the pull-down transistor in the ZQ calibration module of the current main chip and detect whether the level at the calibration resistor interface is higher than the first preset value. If the voltage level at the calibration resistor interface is lower than the first preset value, the identification module sets the current main chip as the delayed calibration chip and sets the other main chip as the priority calibration chip. If the voltage level at the calibration resistor interface is higher than the first preset value, the identification module sets the current main chip as the priority calibration chip and sets the other main chip as the delay calibration chip.

11. A ZQ calibration method, applied to the memory device according to any one of claims 1 to 10, characterized in that, include: Identify the priority calibration chip and the delay calibration chip in the first master chip and the second master chip, and designate the first slave chip or the second slave chip cascaded with the priority calibration chip as the master-slave chip, and designate the first slave chip or the second slave chip cascaded with the delay calibration chip as the secondary slave chip; In command mode, acquire the ZQ calibration command applied externally to the memory device; In response to the ZQ calibration command, a first calibration operation is performed on the priority calibration chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level master-slave chip, and at the same time, the second calibration operation is performed on the priority calibration chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level master-slave chip; After the first calibration operation of the first-level master-slave chip is completed, the ZQ flag signal is transmitted to the next-level master-slave chip, and the second calibration operation is performed on the first-level master-slave chip until the last-level master-slave chip completes the first calibration operation. The second calibration operation is performed on the last-stage master-slave chip; In response to the delayed ZQ calibration command, a first calibration operation is performed on the delayed calibration chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level slave chip, and the second calibration operation is performed on the delayed calibration chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level slave chip; After the first calibration operation of the first-level slave chip is completed, the ZQ flag signal is transmitted to the next-level slave chip, and the second calibration operation is performed on the first-level slave chip until the last-level slave chip completes the first calibration operation. The second calibration operation is performed on the last stage chip.

12. The ZQ calibration method according to claim 11, characterized in that, include: Identify the priority calibration chip and the delay calibration chip in the first master chip and the second master chip, and designate the first slave chip or the second slave chip cascaded with the priority calibration chip as the master-slave chip, and designate the first slave chip or the second slave chip cascaded with the delay calibration chip as the secondary slave chip; In background mode, in response to the ZQ calibration command, a first calibration operation is performed on the priority calibration chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level master-slave chip, and at the same time, the second calibration operation is performed on the priority calibration chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level master-slave chip; After the first calibration operation of the first-level master-slave chip is completed, the ZQ flag signal is transmitted to the next-level master-slave chip, and the second calibration operation is performed on the first-level master-slave chip until the last-level master-slave chip completes the first calibration operation. The ZQ flag signal is transmitted to the delay calibration chip, and a second calibration operation is performed on the last master-slave chip. In response to the ZQ flag signal, the first calibration operation is performed on the delay calibration chip; After the first calibration operation is completed, the ZQ flag signal is transmitted to the first-level slave chip, and the second calibration operation is performed on the delayed calibration chip. In response to the ZQ flag signal, the first calibration operation is performed on the first-level slave chip; After the first calibration operation of the first-level slave chip is completed, the ZQ flag signal is transmitted to the next-level slave chip, and the second calibration operation is performed on the first-level slave chip until the last-level slave chip completes the first calibration operation. The second calibration operation is performed on the last stage chip.

13. The ZQ calibration method according to claim 11 or 12, characterized in that, Before entering the background mode, the priority calibration chip and the delay calibration chip are identified, including: during the first clock cycle, detecting whether the other main chip is in ZQ calibration state; If the other main chip is in ZQ calibration state, then the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip; If the other main chip is not in ZQ calibration state, then the current main chip is set as the priority calibration chip, and the other main chip is set as the delay calibration chip.

14. The ZQ calibration method according to claim 13, characterized in that, Before setting the current main chip as the priority calibration chip, the method further includes: during the second clock cycle, detecting whether the level at the calibration resistor interface is higher than a first preset value; If the voltage level at the calibration resistor interface is higher than the first preset value, then the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip. If the voltage level at the calibration resistor interface is lower than the first preset value, then the current main chip is set as the priority calibration chip, and the other main chip is set as the delay calibration chip.

15. The ZQ calibration method according to claim 14, characterized in that, Before setting the current main chip as the priority calibration chip, the method further includes: in the third clock cycle, turning on the pull-down transistor in the ZQ calibration module of the current main chip, and detecting whether the level at the calibration resistor interface is lower than the second preset value. If the voltage level at the calibration resistor interface is lower than the second preset value, then the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip. If the voltage level at the calibration resistor interface is higher than the second preset value, then the current main chip is set as the priority calibration chip, and the other main chip is set as the delay calibration chip.

16. The ZQ calibration method according to claim 15, characterized in that, Before setting the current main chip as the priority calibration chip, the method further includes: in the fourth clock cycle, turning off the pull-down transistor in the ZQ calibration module of the current main chip, and detecting whether the level at the calibration resistor interface is higher than the first preset value. If the voltage level at the calibration resistor interface is higher than the first preset value, then the current main chip is set as the delayed calibration chip, and the other main chip is set as the priority calibration chip. If the voltage level at the calibration resistor interface is lower than the first preset value, then the current main chip is set as the priority calibration chip, and the other main chip is set as the delay calibration chip.

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