Analog-to-digital conversion circuit, control method, chip and electronic device

Abstract

The application provides an analog-to-digital conversion circuit, a control method, a chip and an electronic device, and belongs to the technical field of electronics. The analog-to-digital conversion circuit comprises a first analog-to-digital conversion module, a second sigma-delta analog-to-digital conversion module and a control module. The first analog-to-digital conversion module is configured to periodically convert an input signal according to a first conversion period and output a first conversion result. The second sigma-delta analog-to-digital conversion module is configured to convert the input signal in a first number of second conversion periods and output a second conversion result, wherein the first number is an integer greater than 1. The control module is configured to determine a target conversion result of the input signal according to the second conversion result and at least two first conversion results. The application can improve the conversion accuracy of the analog-to-digital conversion circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to an analog-to-digital conversion circuit, a control method, a chip, and an electronic device. Background Technology

[0002] Σ-Δ analog-to-digital converters (Σ-ΔADCs) are often the first choice for low-speed, high-precision measurements and are widely used for measuring low-frequency signals and even DC signals.

[0003] Σ-Δ analog-to-digital converters (ADCs) use the same input for multiple DC signal measurements. When the circuit noise is much smaller than the quantization error, the quantization error remains essentially unchanged for the same input in each conversion cycle. For some applications with DC input signals, higher precision may be required, such as during system calibration. Therefore, there is a pressing need for an ADC to improve the accuracy of DC signal conversion. Summary of the Invention

[0004] To address the problems of existing technologies, embodiments of this application provide an analog-to-digital conversion circuit, a control method, a chip, and an electronic device, which can improve conversion accuracy. The technical solution is as follows:

[0005] According to one aspect of this application, an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit including a first analog-to-digital conversion module, a second Σ-Δ analog-to-digital conversion module, and a control module;

[0006] The first analog-to-digital converter module is configured to periodically convert the input signal according to a first conversion period and output a first conversion result;

[0007] The second Σ-Δ analog-to-digital converter module is configured to convert the input signal within a first number of second conversion cycles and output a second conversion result, wherein the first number is an integer greater than 1;

[0008] The control module is configured to determine the target conversion result of the input signal based on the second conversion result and at least two of the first conversion results.

[0009] Optionally, the control module is configured as follows:

[0010] Obtain a reference conversion result, which is determined based on the first conversion result of at least one historical first conversion cycle that is consecutive to the current first conversion cycle;

[0011] Based on the difference between the first conversion result and the reference conversion result in the current first conversion cycle, the target conversion result is determined to be either the first conversion result or the second conversion result in the current first conversion cycle.

[0012] Optionally, the control module is configured as follows:

[0013] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the target conversion result is determined to be the first conversion result in the current first conversion cycle.

[0014] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a first difference threshold, the target conversion result is determined to be the second conversion result.

[0015] Optionally, the control module is further configured to:

[0016] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the reference conversion result is updated to the first conversion result in the current first conversion cycle.

[0017] Optionally, the first analog-to-digital conversion module is configured to be reset upon completion of conversion in each first conversion cycle.

[0018] Optionally, the second Σ-Δ analog-to-digital converter module is configured as follows:

[0019] During the conversion of the input signal within a first number of second conversion cycles, if the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a second difference threshold, then no reset is performed.

[0020] Optionally, the control module is configured as follows:

[0021] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the second difference threshold, the second Σ-Δ analog-to-digital conversion module is controlled to reset.

[0022] Optionally, when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a second difference threshold, the state of the input signal is taken as the target state;

[0023] The second Σ-Δ analog-to-digital converter module is also configured to:

[0024] During the period when the input signal is continuously in the target state, a reset is performed when the input signal conversion is completed within a second number of consecutive second conversion cycles, wherein the second number is an integer greater than or equal to the first number.

[0025] Optionally, the control module is configured as follows:

[0026] During the period when the input signal is continuously in the target state, the second conversion cycle completed by the second Σ-Δ analog-to-digital converter is counted. When the count is greater than or equal to the second number, the second Σ-Δ analog-to-digital converter is controlled to be reset.

[0027] Optionally, the control module is further configured to:

[0028] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than the third difference threshold, the second Σ-Δ analog-to-digital conversion module is enabled.

[0029] Optionally, the control module is further configured to:

[0030] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the third difference threshold, the second Σ-Δ analog-to-digital conversion module is shut down.

[0031] Optionally, the first analog-to-digital conversion module can be any one of the following circuit types or a combination of multiple circuit types: Σ-Δ ADC, successive approximation ADC, scintillation ADC, and pipelined ADC.

[0032] According to another aspect of this application, a control method for an analog-to-digital conversion circuit is provided, the analog-to-digital conversion circuit including a first analog-to-digital conversion module, a second Σ-Δ analog-to-digital conversion module, and a control module, the method comprising:

[0033] The first analog-to-digital converter module is controlled to periodically convert the input signal according to the first conversion cycle and output the first conversion result;

[0034] The second Σ-Δ analog-to-digital converter module is controlled to convert the input signal within a first number of second conversion cycles and output a second conversion result, wherein the first number is an integer greater than 1;

[0035] The control module determines the target conversion result of the input signal based on the second conversion result and at least two of the first conversion results.

[0036] According to another aspect of this application, a chip is provided, including the analog-to-digital conversion circuit described above.

[0037] According to another aspect of this application, an electronic device is provided, including the analog-to-digital conversion circuit described above.

[0038] The analog-to-digital (ADC) circuit provided in this application includes a first ADC module, a second Σ-Δ ADC module, and a control module. The first ADC module outputs a first conversion result obtained by converting the input signal for each first conversion cycle. The second Σ-Δ ADC module outputs a second conversion result obtained by converting the input signal for multiple second conversion cycles. The control module determines the target conversion result of the input signal based on the two conversion results. If the input signal is a DC signal or a signal with a gradually changing amplitude, the quantization error of the second conversion result is smaller, resulting in a smaller quantization error in the target conversion result of the input signal, thereby improving the conversion accuracy of the ADC circuit. Attached Figure Description

[0039] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A schematic diagram of an analog-to-digital converter circuit provided according to an exemplary embodiment of this application is shown;

[0041] Figure 2 A schematic diagram of an analog-to-digital converter circuit provided according to an exemplary embodiment of this application is shown;

[0042] Figure 3 A schematic diagram illustrating the operation of an analog-to-digital converter circuit provided according to an exemplary embodiment of this application is shown.

[0043] Figure 4 A flowchart of a control method for an analog-to-digital conversion circuit provided according to an exemplary embodiment of this application is shown. Detailed Implementation

[0044] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0045] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0046] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0047] The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0048] This application provides an analog-to-digital converter circuit that can be integrated into a chip or disposed in an electronic device.

[0049] Reference Figure 1 The schematic diagram of the analog-to-digital converter circuit shown includes a first analog-to-digital converter module, a second Σ-Δ analog-to-digital converter module, and a control module. The first and second Σ-Δ analog-to-digital converter modules are connected in parallel, with their input terminals both capable of receiving input signals and their output terminals both capable of being connected to the control module.

[0050] The first analog-to-digital converter module can be configured to periodically convert the input signal according to a first conversion cycle and output the first conversion result.

[0051] The second Σ-Δ analog-to-digital converter module can be configured to convert the input signal within a first number of second conversion cycles and output a second conversion result, wherein the first number can be an integer greater than 1. The second conversion cycle can be the same as or different from the first conversion cycle.

[0052] The control module can be configured to determine the target conversion result of the input signal based on the second conversion result and at least two first conversion results. Specifically, it can determine whether the input signal is a DC signal with a constant amplitude (or a very gradual change) based on at least two first conversion results, and then confirm the target conversion result in the last first conversion result and the second conversion result. Wherein, when the input signal is not a DC signal, the aforementioned at least two first conversion results may include the first conversion result of the current first conversion cycle and the first conversion result of the previous first conversion cycle. When the input signal is a DC signal, the aforementioned at least two first conversion results may include the first conversion result of the current first conversion cycle and the first conversion result of any one or more previous first conversion cycles.

[0053] The second Σ-Δ analog-to-digital conversion module can be implemented based on the principle of Σ-Δ averaging, and can be a Σ-Δ ADC or its derivative circuit. This embodiment does not limit the specific circuit type used in the second Σ-Δ analog-to-digital conversion module.

[0054] Optionally, the first analog-to-digital conversion module can be any one of the following circuit types or a combination of multiple circuit types: Σ-Δ ADC, successive approximation ADC, scintillation ADC, and pipelined ADC.

[0055] In one implementation, the circuit structures of the first analog-to-digital converter module and the second Σ-Δ analog-to-digital converter module can be different; that is, the first analog-to-digital converter module can be a non-Σ-Δ analog-to-digital converter module.

[0056] As another implementation, the first analog-to-digital conversion module and the second Σ-Δ analog-to-digital conversion module have the same circuit structure. On this basis, the uniformity of the conversion results can be guaranteed, which makes it easier for subsequent circuits to process the target conversion results output by the analog-to-digital conversion circuit.

[0057] In one possible implementation, the input signal can be a voltage signal, and the analog-to-digital converter (ADC) circuit can convert the voltage signal of the input circuit. For example, in a battery power management system, the current to be detected can be converted into a corresponding voltage signal, which is then input into the ADC circuit. After conversion by the ADC circuit, the conversion result is output, and the average current over a period of time can be determined based on the conversion result. This embodiment does not limit the specific application scenario of the ADC circuit.

[0058] In the analog-to-digital conversion circuit provided in this application, the input signal can be connected to the first analog-to-digital conversion module and the second Σ-Δ analog-to-digital conversion module, and the input signal can be converted by the first analog-to-digital conversion module and the second Σ-Δ analog-to-digital conversion module.

[0059] Taking a Σ-Δ ADC as an example, in the first analog-to-digital conversion module, the modulation code for the current clock cycle can be determined based on the modulation code determined in the previous clock cycle and the current input signal. The modulation code referenced in the first clock cycle after the first analog-to-digital conversion module is reset can be an initial value, for example, 0. After n clock cycles, i.e., after n samples, the n modulation codes can be converted, and the average of the n samples is used as the corresponding first conversion result. Here, n is a positive integer, which can refer to the oversampling ratio (OSR).

[0060] In this embodiment, the aforementioned n clock cycles are referred to as one first conversion cycle. That is, the first analog-to-digital converter (ADC) module can be used to perform general conversion processing on the input signal, and output the corresponding first conversion result upon completion of the conversion in each first conversion cycle. Optionally, the first ADC module can be configured to reset upon completion of the conversion in each first conversion cycle.

[0061] Similarly, the second Σ-Δ analog-to-digital converter module can also be used to perform conversion processing on the input signal. In this embodiment, the conversion period of the second Σ-Δ analog-to-digital converter module is referred to as the second conversion period. The second conversion period can be the same as or different from the first conversion period described above.

[0062] The second Σ-Δ analog-to-digital converter (ADC) module can also output the corresponding second conversion result after the first number of second conversion cycles are completed. Unlike the first ADC module, the second Σ-Δ ADC module does not need to be reset after completing one second conversion cycle. Furthermore, in the next second conversion cycle, the modulation code referenced in the first clock cycle can be the last modulation code of the previous second conversion cycle. After the first number of second conversion cycles, the second conversion result output by the second Σ-Δ ADC module can be the conversion result obtained by converting the input signal within the aforementioned first number of second conversion cycles. Based on this, if the input signal is a DC signal or a signal with a flat amplitude, where the amplitude remains almost constant, the more second conversion cycles there are, the more samples are used to calculate the average value, and the smaller the quantization error. In this embodiment, multiple second conversion cycles can be equivalent to a conversion cycle with a longer duration and more clock cycles than the first conversion cycle.

[0063] Finally, in the control module, it can determine whether the input signal is a DC signal or whether the amplitude change of the input signal is gradual based on the first conversion results of at least two consecutive first conversion cycles. If so, the second conversion result output by the second Σ-Δ analog-to-digital converter module can be selected as the target conversion result of the input signal; otherwise, the first conversion result output by the first analog-to-digital converter module can be selected as the target conversion result of the input signal. Based on this, for DC signals or input signals with gradual amplitude changes, the analog-to-digital converter circuit can output a second conversion result with smaller quantization error, thereby improving conversion accuracy.

[0064] In some embodiments, the target transformation result can be determined by referring to the transformation result; correspondingly, the control module can be configured as follows:

[0065] Obtain the reference conversion result;

[0066] Based on the difference between the first conversion result and the reference conversion result in the current first conversion cycle, the target conversion result is determined to be either the first conversion result or the second conversion result.

[0067] The reference conversion result can be determined based on the first conversion result of at least one historical first conversion cycle that is consecutive to the current first conversion cycle. As an example, the reference conversion result corresponding to the third first conversion cycle can be determined based on the first conversion result of the previous first conversion cycle (i.e., the second first conversion cycle), or it can be determined based on the first conversion results of the previous two first conversion cycles (i.e., the first and second first conversion cycles).

[0068] In one possible implementation, the first conversion result of the previous first conversion cycle can be used as the reference conversion result of the current first conversion cycle, and the difference between the first conversion result of the current first conversion cycle and the reference conversion result can be calculated. Based on this difference, it can be determined whether the input signal is a DC signal, or whether the change in the signal amplitude of the input signal is gradual, thereby selecting the first conversion result or the second conversion result as the target conversion result.

[0069] Specifically, the conversion result can be determined using a first difference threshold, and the corresponding control module can be configured as follows:

[0070] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the first difference threshold, the target conversion result is determined as the first conversion result;

[0071] If the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than the first difference threshold, the target conversion result is determined as the second conversion result.

[0072] In other words, if the absolute value of the difference between the two is greater than a preset first difference threshold, the input signal can be considered not to be a DC signal or a signal with a gradually changing amplitude, but rather a changing signal, such as a fluctuating signal or a periodic signal. In this case, the real-time requirements for conversion are high, and the first conversion result is output as the target conversion result. If the absolute value of the difference between the two is less than or equal to the preset first difference threshold, the input signal can be considered to be a DC signal or a signal with a gradually changing amplitude, and the second conversion result is output as the target conversion result, improving the conversion accuracy through the second Σ-Δ analog-to-digital conversion module.

[0073] Optionally, the control module can also be configured to update the reference conversion result to the first conversion result of the current first conversion cycle when the difference between the first conversion result and the reference conversion result of the current first conversion cycle is greater than a first difference threshold. In other words, the control module determines whether the input signal is not a DC signal or a signal with a gently changing amplitude based on whether the difference between the first conversion results of any two adjacent first conversion cycles is greater than the first difference threshold.

[0074] In one possible implementation, when the control module determines that the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the reference conversion result can be updated to the current first conversion result. This allows the system to determine whether the input signal is a DC signal or a signal with a gradually changing amplitude based on the first conversion result in the next first conversion cycle. When the control module determines that the difference between the first conversion result and the reference conversion result is not greater than the first difference threshold, the reference conversion result does not need to be updated, thus saving system resources.

[0075] The reset process of the second Σ-Δ analog-to-digital converter module is described below.

[0076] Optionally, the second Σ-Δ analog-to-digital converter module can be configured to not reset during the conversion of the input signal within a first number of second conversion cycles if the difference between the first conversion result of the current first conversion cycle and the reference conversion result is not greater than a first difference threshold. That is, the reset status of the second Σ-Δ analog-to-digital converter module is adapted to the input signal. If the input signal is a DC signal or a signal with a gradually changing amplitude, the second Σ-Δ analog-to-digital converter module may not reset, thereby performing one conversion on the input signal within multiple second conversion cycles to obtain a conversion result corresponding to the average value of the input signal within multiple second conversion cycles.

[0077] Optionally, the second Σ-Δ analog-to-digital converter module can be reset by the control module. Accordingly, the control module can be configured to reset the second Σ-Δ analog-to-digital converter module when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the second difference threshold.

[0078] The second difference threshold can be preset, and can be the same as or different from the first difference threshold. This embodiment does not limit this. In this embodiment, the second difference threshold is used to determine whether the second Σ-Δ analog-to-digital conversion module needs to be reset.

[0079] In other words, if the absolute value of the difference between the two is greater than the preset second difference threshold, it can be considered that the input signal at this time is not a DC signal or a signal with a smooth change in signal amplitude, such as a fluctuating signal. Then, the control module can send a reset signal to the second Σ-Δ analog-to-digital converter module to control the second Σ-Δ analog-to-digital converter module to reset.

[0080] Based on this, when the input signal is a DC signal or a signal with a gradual change in amplitude, the second Σ-Δ analog-to-digital converter module does not need to be reset when the conversion of a second conversion cycle is completed. When the amplitude of the input signal changes significantly, the second Σ-Δ analog-to-digital converter module can be reset.

[0081] Optionally, for ease of explanation, the state of the input signal is defined as the target state when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than the first difference threshold. The target state indicates that the input signal at this time is a DC signal or a signal with a smooth amplitude change. Correspondingly, the state of the input signal is defined as the non-target state when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the first difference threshold. The non-target state indicates that the input signal at this time is neither a DC signal nor a signal with a smooth amplitude change.

[0082] Based on this, the second Σ-Δ analog-to-digital converter module can also be configured to reset when the input signal is converted within a second number of consecutive second conversion cycles during the period when the input signal is continuously in the target state, where the second number is an integer greater than or equal to the first number mentioned above.

[0083] The input signal being continuously in the target state can mean that, in at least two consecutive first conversion cycles, the difference between the first conversion result and the reference conversion result is not greater than a first difference threshold.

[0084] If the second Σ-Δ analog-to-digital converter (ADC) module is not reset for an extended period during the time interval corresponding to at least two consecutive first conversion cycles, it may affect the circuit performance. Therefore, the maximum number of consecutive conversion cycles that the second Σ-Δ ADC module can perform (i.e., the aforementioned second number) can be preset, or the upper limit of the number of bit widths of code values ​​that the filter in the second Σ-Δ ADC module can process can be preset to the aforementioned second number. When the consecutive conversion reaches this number, the second Σ-Δ ADC module can be reset, thereby avoiding too many consecutive conversion cycles. As an example, the aforementioned second number can be set according to the upper limit of the number of bit widths of code values ​​that the filter in the second Σ-Δ ADC module can process. For example, if the second Σ-Δ ADC module performs n' samplings and generates n' modulation codes in each second conversion cycle, and the digital filter in the second Σ-Δ ADC module can process a maximum of m bits of modulation codes, then the aforementioned second number can be less than or equal to m / n'. In this way, after the second number of second conversion cycles, the number of bit widths of the continuously generated modulation codes will not exceed the processing range of the filter, ensuring the normal operation of the filter.

[0085] Optionally, the counting can be performed by a control module. Correspondingly, the control module can be configured to count the second conversion cycle completed by the second Σ-Δ analog-to-digital converter during the period when the input signal is continuously in the target state. When the count is greater than or equal to the second number mentioned above, the second Σ-Δ analog-to-digital converter is controlled to reset.

[0086] In one possible implementation, while the input signal remains in the target state, the control module can count the second conversion cycles completed by the second Σ-Δ analog-to-digital converter (ADC). Each time the second Σ-Δ ADC completes a second conversion cycle, the count is incremented by 1. When the count is greater than or equal to a second number, the control module can send a reset signal to the second Σ-Δ ADC to reset it and clear the count. Alternatively, the count can be set to 0 when the input signal transitions from the target state to a non-target state, i.e., when the difference between the first conversion result of the current first conversion cycle and the reference conversion result is greater than a first difference threshold. This approach avoids the second Σ-Δ ADC operating for too many conversion cycles.

[0087] Alternatively, the control module can be configured to count the modulation code determined by the second Σ-Δ analog-to-digital converter module during the period when the input signal is continuously in the target state, and control the second Σ-Δ analog-to-digital converter module to reset when the count is greater than or equal to the second number mentioned above.

[0088] In one possible implementation, while the input signal remains in the target state, the control module can count the modulation code determined by the second Σ-Δ analog-to-digital converter (ADC). Each time the second Σ-Δ ADC determines a modulation code, the count is incremented by 1. When the count is greater than or equal to a second number, i.e., when the processing limit of the filter in the second Σ-Δ ADC is reached, the control module can send a reset signal to the second Σ-Δ ADC to reset it and clear the count to zero. Alternatively, the count can be set to 0 when the input signal transitions from the target state to a non-target state, i.e., when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold. This also helps prevent the second Σ-Δ ADC from operating for too many conversion cycles.

[0089] Optionally, the control module can control whether the second Σ-Δ analog-to-digital converter (ADC) module is enabled. Correspondingly, the control module can also be configured to enable the second Σ-Δ ADC module when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a third difference threshold. That is, if the input signal is a DC signal or a signal with a gradually changing amplitude, the second Σ-Δ ADC module can be enabled, thereby improving the conversion accuracy.

[0090] Alternatively, the control module can be configured to shut down the second Σ-Δ analog-to-digital converter module when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a third difference threshold. In other words, if the input signal at this time is not a DC signal or a signal with a gradually changing amplitude, the second Σ-Δ analog-to-digital converter module can be shut down, thereby reducing power consumption.

[0091] The third difference threshold mentioned above can be the same as or different from the first or second difference threshold mentioned above.

[0092] The embodiments of this application can achieve at least the following beneficial effects:

[0093] The analog-to-digital (ADC) circuit provided in this application includes a first ADC module, a second Σ-Δ ADC module, and a control module. The first ADC module outputs a first conversion result obtained by converting the input signal for each first conversion cycle. The second Σ-Δ ADC module outputs a second conversion result obtained by converting the input signal for multiple second conversion cycles. The control module determines the target conversion result of the input signal based on the two conversion results. If the input signal is a DC signal or a signal with a gradually changing amplitude, the quantization error of the second conversion result is smaller, resulting in a smaller quantization error in the target conversion result of the input signal, thereby improving the conversion accuracy of the ADC circuit.

[0094] This application provides a specific analog-to-digital conversion circuit, and the principle of improving conversion accuracy is introduced with reference to this analog-to-digital conversion circuit.

[0095] Taking the first analog-to-digital conversion module, which is also a Σ-ΔADC, as an example, refer to... Figure 2 The schematic diagram of the analog-to-digital converter circuit shown can be composed of two Σ-Δ ADCs and a control module (corresponding to the control module mentioned above). Figure 2 One of the Σ-Δ ADCs is called ISD_ADC1 (corresponding to the first analog-to-digital conversion module mentioned above), and the other Σ-Δ ADC is called ISD_ADC2 (corresponding to the second Σ-Δ analog-to-digital conversion module mentioned above).

[0096] The circuit structures of ISD_ADC1 and ISD_ADC2 can be identical. Taking a first-order differential incremental Σ-Δ ADC as an example, they can include a first amplification unit 201, a second amplification unit 202, a third amplification unit 203, a summing unit 204, an integrator unit 205, a quantizer 206, and a filter 207. The input terminal of the first amplification unit 201 can receive the input voltage Vin, and its output terminal is connected to the first input terminal of the summing unit 204. The amplification factor can be 'a' (a can take any value). The first input terminal of the summing unit 204 is connected to the output terminal of the first amplification unit 201; its second input terminal is connected to the output terminal of the third amplification unit 203; and its output terminal is connected to the input terminal of the second amplification unit 202. The input terminal of the second amplification unit 202 can be connected to the output terminal of the summing unit 204, and its output terminal is connected to the input terminal of the integrator unit 205. The amplification factor can be 'b' (b can take any value). The input of the integrator 205 is connected to the output of the second amplification unit 202, and its output is connected to the input of the quantizer 206. The input of the quantizer 206 is connected to the output of the integrator 205, and its output is connected to the input of the third amplification unit 203 and the input of the filter 207. The input of the third amplification unit 203 can be connected to the output of the quantizer 206, and its output is connected to the input of the control module. The amplification factor can be c (c can take any value). The input of the filter 207 can be connected to the output of the quantizer 206, and its output is connected to the input of the control module. Specifically, the output of ISD_ADC1 outputs Out1 (corresponding to the first conversion result mentioned above), and the output of ISD_ADC2 outputs Out2 (corresponding to the second conversion result mentioned above).

[0097] The input of the control module is connected to the output of ISD_ADC1 and ISD_ADC2. The output is used to output the final conversion result Out of the Σ-Δ analog-to-digital converter (corresponding to the target conversion result mentioned above). The control module can output reset signals Reset1 and Reset2. Reset1 is used to control the reset of ISD_ADC1, and Reset2 is used to control the reset of ISD_ADC2.

[0098] The implementation principle of this circuit is as follows:

[0099] Reference Figure 3 The schematic diagram of the analog-to-digital converter circuit shows that when the circuit is powered on and initialized, the control module initializes Temp (corresponding to the above reference conversion result) to 0, initializes Num (corresponding to the above count) to 0, and sends reset signals Reset1 and Reset2 to ISD_ADC1 and ISD_ADC2 respectively to control ISD_ADC1 and ISD_ADC2 to reset.

[0100] ISD_ADC1 and ISD_ADC2 simultaneously sample the input signal Vin n times, converting Vin into n PDM (Pulse Duration Modulation) codes D[0], D[1], ..., D[n-1]. Let the PDM code of ISD_ADC1 be D1 and the PDM code of ISD_ADC2 be D2. The filter of ISD_ADC1 can convert D1[0], D1[1], ..., D1[n-1] into the corresponding first conversion result Out1, and the filter of ISD_ADC2 can convert D2[0], D2[1], ..., D2[n-1] into the corresponding second conversion result Out2.

[0101] Assuming that ISD_ADC1 and ISD_ADC2 have the same conversion period, both consisting of n clock cycles, and that ISD_ADC2 does not reset within Num conversion cycles, then according to the conversion principle of a first-order differential incremental Σ-Δ ADC for DC signals, we can obtain:

[0102]

[0103]

[0104] Where Vref is the reference voltage of the analog-to-digital converter circuit. At this time, the quantization error of Out1 is... The quantization error of Out2 is

[0105] From the expressions for ΔQ1 and ΔQ2, it can be seen that when Num > 1 (i.e., ISD_ADC2 is not reset), max(ΔQ2) < max(ΔQ1), which means that the quantization error of ISD_ADC2 is less than that of ISD_ADC1, and the conversion accuracy is higher than that of ISD_ADC1.

[0106] Reference Figure 3 As shown in the workflow, after ISD_ADC1 outputs Out1, the control module can compare Out1 and Temp.

[0107] If the input signal is being converted for the first time, the absolute value of the difference between Out1 and Temp can be greater than the threshold Vth (corresponding to the first and second difference thresholds mentioned above, where the first and second difference thresholds are the same). Then, the control module can set Out to Out1 and output it, set Temp to Out1, set Num to 0, and reset ISD_ADC1 and ISD_ADC2.

[0108] After this, ISD_ADC1 and ISD_ADC2 can enter the next conversion cycle and repeat the above process to continue converting the input signal Vin.

[0109] If the absolute value of the difference between Out1 and Temp is not greater than the threshold Vth, the input signal can be considered a DC signal. In this case, the control module can either set Out to Out2 and output it after ISD_ADC2 outputs, or use the previous Out2 as the Out output; reset ISD_ADC1, but not ISD_ADC2; increment Num by 1, and determine whether Num is greater than or equal to Nth (corresponding to the second number mentioned above). If Num ≥ Nth, then clear Num to zero, reset ISD_ADC2, and enter the next conversion cycle; otherwise, directly enter the next conversion cycle. Temp can remain unchanged or be set to Out1.

[0110] If the absolute value of the difference between Out1 and Temp is greater than the threshold Vth, the input signal can be considered not to be a DC signal. At this time, the control module can clear Num to zero, set Out to Out1 and output it, set Temp to Out1, reset ISD_ADC1 and ISD_ADC2, and enter the next conversion cycle.

[0111] Through the above workflow, ISD_ADC1 can output the conversion result Out1 for one conversion cycle. When the input signal includes a DC signal, ISD_ADC2 can output the conversion result Out2 obtained by converting the input signal over multiple conversion cycles. Furthermore, the control module can output Out1 when the input signal is not a DC signal and Out2 when the input signal is a DC signal. Since the quantization error of Out2 output by the control module is smaller than that of the unselected Out1 when the input signal is a DC signal, the conversion accuracy of the analog-to-digital converter circuit can be improved.

[0112] This application also provides a control method for an analog-to-digital converter circuit, which can be used to control the aforementioned analog-to-digital converter circuit. The specific processing of the control method is the same as described above, and will not be repeated in this embodiment.

[0113] Reference Figure 4 The flowchart of the control method for the analog-to-digital converter circuit shown is as follows:

[0114] Step 401: Control the first analog-to-digital conversion module to periodically convert the input signal according to the first conversion cycle, and output the first conversion result;

[0115] Step 402: Control the second Σ-Δ analog-to-digital converter module to convert the input signal within a first number of second conversion cycles and output the second conversion result, wherein the first number is an integer greater than 1;

[0116] Step 403: The control module determines the target conversion result of the input signal based on the second conversion result and at least two first conversion results.

[0117] Optionally, determining the target conversion result of the input signal based on the second conversion result and at least two of the first conversion results includes:

[0118] Obtain a reference conversion result, which is determined based on the first conversion result of at least one historical first conversion cycle that is consecutive to the current first conversion cycle;

[0119] Based on the difference between the first conversion result and the reference conversion result in the current first conversion cycle, the target conversion result is determined to be either the first conversion result or the second conversion result in the current first conversion cycle.

[0120] Optionally, determining the target conversion result as either the first conversion result or the second conversion result of the current first conversion period based on the difference between the first conversion result and the reference conversion result in the current first conversion period includes:

[0121] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the target conversion result is determined to be the first conversion result in the current first conversion cycle.

[0122] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a first difference threshold, the target conversion result is determined to be the second conversion result.

[0123] Optionally, the method further includes:

[0124] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the reference conversion result is updated to the first conversion result in the current first conversion cycle.

[0125] Optionally, the method further includes:

[0126] The first analog-to-digital conversion module is reset when the conversion of each conversion cycle is completed.

[0127] Optionally, during the conversion of the input signal within a first number of second conversion cycles, if the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a second difference threshold, then the second Σ-Δ analog-to-digital conversion module is not reset.

[0128] Optionally, the method further includes:

[0129] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the second difference threshold, the second Σ-Δ analog-to-digital conversion module is reset by the control module.

[0130] Optionally, when the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a second difference threshold, the state of the input signal is taken as the target state;

[0131] The method further includes:

[0132] During the period when the input signal is continuously in the target state, when the second Σ-Δ analog-to-digital converter completes the conversion of the input signal within a second consecutive number of second conversion cycles, the second Σ-Δ analog-to-digital converter is controlled to be reset, wherein the second number is an integer greater than or equal to the first number.

[0133] Optionally, during the period when the input signal is continuously in the target state, when the second Σ-Δ analog-to-digital converter completes the conversion of the input signal within a second consecutive number of second conversion cycles, controlling the second Σ-Δ analog-to-digital converter to reset includes:

[0134] During the period when the input signal is continuously in the target state, the control module counts the second conversion cycle completed by the second Σ-Δ analog-to-digital converter module. When the count is greater than or equal to the second number, the second Σ-Δ analog-to-digital converter module is controlled to reset.

[0135] Optionally, the method further includes:

[0136] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than the third difference threshold, the control module enables the second Σ-Δ analog-to-digital conversion module.

[0137] Optionally, the method further includes:

[0138] When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the third difference threshold, the control module controls the second Σ-Δ analog-to-digital conversion module to shut down.

[0139] Optionally, the first analog-to-digital conversion module can be any one of the following circuit types or a combination of multiple circuit types: Σ-Δ ADC, successive approximation ADC, scintillation ADC, and pipelined ADC.

[0140] In this embodiment, the analog-to-digital conversion circuit includes a first analog-to-digital conversion module, a second Σ-Δ analog-to-digital conversion module, and a control module. The first analog-to-digital conversion module outputs a first conversion result obtained by converting the input signal for each first conversion cycle. The second Σ-Δ analog-to-digital conversion module outputs a second conversion result obtained by converting the input signal for multiple second conversion cycles. The control module determines the target conversion result for the input signal based on the two conversion results. If the input signal is a DC signal or a signal with a gradually changing amplitude, the quantization error of the second conversion result is smaller, resulting in a smaller quantization error in the target conversion result of the input signal, thereby improving the conversion accuracy of the analog-to-digital conversion circuit.

[0141] This application also provides a chip, including the analog-to-digital conversion circuit provided in this application embodiment. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. By configuring the above-mentioned analog-to-digital conversion circuit, the conversion accuracy of the analog-to-digital conversion circuit is improved, thereby correspondingly improving the chip's performance.

[0142] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. By configuring the aforementioned analog-to-digital conversion circuit, the conversion accuracy of the analog-to-digital conversion circuit is improved, thereby correspondingly improving the performance of the electronic device.

[0143] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes a first analog-to-digital conversion module, a second Σ-Δ analog-to-digital conversion module, and a control module; The first analog-to-digital converter module is configured to periodically convert the input signal according to a first conversion period and output a first conversion result; The second Σ-Δ analog-to-digital converter module is configured to convert the input signal within a first number of second conversion cycles and output a second conversion result, wherein the first number is an integer greater than 1; The control module is configured to determine a target conversion result of the input signal based on the second conversion result and at least two first conversion results, including: acquiring a reference conversion result, the reference conversion result being determined based on the first conversion result of at least one historical first conversion cycle that is continuous with the current first conversion cycle; and determining the target conversion result as either the first conversion result or the second conversion result of the current first conversion cycle based on the difference between the first conversion result of the current first conversion cycle and the reference conversion result.

2. The analog-to-digital converter circuit according to claim 1, characterized in that, The control module is configured as follows: When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the target conversion result is determined to be the first conversion result in the current first conversion cycle. When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a first difference threshold, the target conversion result is determined to be the second conversion result.

3. The analog-to-digital converter circuit according to claim 1, characterized in that, The control module is also configured to: When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than a first difference threshold, the reference conversion result is updated to the first conversion result in the current first conversion cycle.

4. The analog-to-digital converter circuit according to claim 1, characterized in that, The first analog-to-digital conversion module is configured to be reset when the conversion of each first conversion cycle is completed.

5. The analog-to-digital converter circuit according to any one of claims 1-4, characterized in that, The second Σ-Δ analog-to-digital converter module is configured as follows: During the conversion of the input signal within a first number of second conversion cycles, if the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than a second difference threshold, then no reset is performed.

6. The analog-to-digital converter circuit according to claim 5, characterized in that, The control module is configured as follows: When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the second difference threshold, the second Σ-Δ analog-to-digital conversion module is controlled to reset.

7. The analog-to-digital converter circuit according to claim 5, characterized in that, When the difference between the first conversion result in the current first conversion cycle and the reference conversion result is not greater than the second difference threshold, the state of the input signal is taken as the target state; The second Σ-Δ analog-to-digital converter module is also configured to: During the period when the input signal is continuously in the target state, a reset is performed when the input signal conversion is completed within a second number of consecutive second conversion cycles, wherein the second number is an integer greater than or equal to the first number.

8. The analog-to-digital converter circuit according to claim 7, characterized in that, The control module is configured as follows: During the period when the input signal is continuously in the target state, the second conversion cycle completed by the second Σ-Δ analog-to-digital converter is counted. When the count is greater than or equal to the second number, the second Σ-Δ analog-to-digital converter is controlled to be reset.

9. The analog-to-digital converter circuit according to claim 1, characterized in that, The control module is also configured to: When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is not greater than the third difference threshold, the second Σ-Δ analog-to-digital conversion module is enabled.

10. The analog-to-digital converter circuit according to claim 1, characterized in that, The control module is also configured to: When the difference between the first conversion result and the reference conversion result in the current first conversion cycle is greater than the third difference threshold, the second Σ-Δ analog-to-digital conversion module is shut down.

11. The analog-to-digital converter circuit according to claim 1, characterized in that, The first analog-to-digital conversion module is any one of the following circuit types or any combination of multiple circuit types: Σ-Δ ADC, successive approximation ADC, scintillation ADC, and pipelined ADC.

12. A control method for an analog-to-digital converter circuit, characterized in that, The analog-to-digital conversion circuit includes a first analog-to-digital conversion module, a second Σ-Δ analog-to-digital conversion module, and a control module; the method includes: The first analog-to-digital converter module is controlled to periodically convert the input signal according to the first conversion cycle and output the first conversion result; The second Σ-Δ analog-to-digital converter module is controlled to convert the input signal within a first number of second conversion cycles and output a second conversion result, wherein the first number is an integer greater than 1; The control module determines the target conversion result of the input signal based on the second conversion result and at least two first conversion results, including: obtaining a reference conversion result, the reference conversion result being determined based on the first conversion result of at least one historical first conversion cycle that is continuous with the current first conversion cycle; and determining the target conversion result as either the first conversion result or the second conversion result of the current first conversion cycle based on the difference between the first conversion result of the current first conversion cycle and the reference conversion result.

13. A chip, characterized in that, Includes the analog-to-digital converter circuit as described in any one of claims 1-11.

14. An electronic device, characterized in that, Includes the analog-to-digital converter circuit as described in any one of claims 1-11.

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