Structure for improving reliability of vertical power device and method of manufacturing the same

Abstract

The application discloses a structure for improving the reliability of a vertical power device, wherein a trench gate penetrating a channel region and a source region formed on the surface of the channel region are arranged in a device unit region, a second trench structure penetrating the channel region is arranged in a terminal region, a first thermal oxide layer covers all regions of the terminal region and the device unit region, in the terminal region, the first thermal oxide layer is directly used to perform thermal oxidation on the material of a first epitaxial layer and the material of a second conductive material layer, in the device unit region, the first thermal oxide layer is directly used to perform thermal oxidation on the material of the first epitaxial layer and the material of a gate conductive material layer, the interface characteristics between the material of the first thermal oxide layer and the first epitaxial layer and the continuous extension structure of the first thermal oxide layer without etching are used to improve the reliability of the vertical power device. The application further discloses a manufacturing method of the structure for improving the reliability of the vertical power device. The application can improve the reliability and reduce the process cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a structure for improving the reliability of a vertical power device. The present invention also relates to a method for manufacturing the structure for improving the reliability of a vertical power device. Background Art

[0002] To reduce their specific on-resistance or increase their power density, power devices typically adopt a vertical structure. This structure effectively utilizes its longitudinal drift region to withstand breakdown voltage. Compared to lateral devices, its unit cell size is not proportional to the breakdown voltage, which can effectively reduce on-resistance and increase current density.

[0003] However, for vertical devices, the terminal structure is still a lateral device and needs to withstand sufficient voltage. To ensure the voltage resistance of the terminal, various terminal structures have been proposed, such as field limiting rings and field plates.

[0004] The maximum terminal electric field strength is usually at the interface between silicon and the insulating layer above it (usually silicon dioxide). To ensure device reliability, the defect density at the interface needs to be reduced. For silicon power devices, the most common methods for reducing the interface defect density at the terminal include:

[0005] like Figure 1A to Figure 1B FIG. 1 is a schematic diagram of the device structure in each step of the method for manufacturing the field oxygen required for the terminal region of the first existing power device; the method includes the following steps:

[0006] like Figure 1A As shown, a semiconductor substrate 101 is provided, and the semiconductor substrate 101 includes a silicon substrate. An oxide layer 102 is formed on the semiconductor substrate 101 by a thermal oxidation process. The temperature of the thermal oxidation process is usually 900-1200°C, and the thickness of the oxide layer is usually between.

[0007] Afterwards, if Figure 1B As shown, a mask is used and a photolithography process is performed to define the terminal area and the device unit area. Figure 1B In the diagram, the termination region is located to the left of line AA, and the device unit region is located to the right of line AA. Typically, there is a transition region between the termination region and the device unit region, which is also part of the termination region. The device unit region is also commonly referred to as the active region or primitive cell region, and the device unit, or primitive cell, is formed in the device unit region.

[0008] Afterwards, etching is performed according to a photolithography process to remove the oxide layer 102 in the device unit region, while the oxide layer 102 in the terminal region remains.

[0009] After the oxide layer 102 in the device unit region is removed, the top surface of the semiconductor substrate 101 is exposed, so that the structure of the device unit, such as the gate structure, the channel region, the source region, etc., can be formed in the device unit region.

[0010] The oxide layer 102 in the terminal region can form a good interface with the semiconductor substrate 101, thereby reducing the interface defect density of the terminal.

[0011] As shown in FIG. 1, the device structure in the step of defining the field oxide formation region in the manufacturing method of the field oxide required by the terminal region in the prior first power device; comprising the steps of: Figure 2 First, a hard mask layer (HM) is deposited on the semiconductor substrate 201,

[0012] In the HM, the HM is composed of an oxide layer 202 (Oxide), a nitride layer 203 (Nitride), and an oxide layer 204. Figure 2 A mask (Mask) is used to define the terminal region and the device unit region by performing a photolithography process,

[0013] In the terminal region, the terminal region is located on the left side of the line AA, and the device unit region is located on the right side of the line AA; then, the HM is etched to remove the HM in the terminal region, and the HM of the active region is exposed. Figure 1B Then, a layer of oxide layer is generated by thermal oxidation. By taking advantage of the characteristic that oxygen (Oxygen) cannot diffuse in the Nitride, the oxide layer produced is only in the terminal region. The second prior method is compared with the first prior method described above, the profile of the oxide layer in the terminal region is smoother, and the stress is smaller.

[0014] However, both of the prior two methods have a disadvantage that an additional mask is required, which increases the cost of the process.

[0015] SUMMARY The technical problem to be solved by the present application is to provide a structure for improving the reliability of a vertical power device, which can reduce the defect density between the epitaxial layer material of the terminal structure and the top oxide layer and prevent the top oxide layer of the epitaxial layer material of the terminal structure from being patterned and etched, so as to achieve the best reliability of the device and reduce the process cost. To this end, the present application also provides a manufacturing method of a structure for improving the reliability of a vertical power device.

[0016] To solve the above technical problem, the structure for improving the reliability of a vertical power device provided by the present application comprises a device unit region and a terminal region, and the terminal region surrounds the periphery of the device unit region.

[0017]

[0018] ​A channel region of a second conductivity type is formed in a surface region of the first epitaxial layer of the first conductivity type.

[0019] The first epitaxial layer at the bottom of the channel region serves as a drift region.

[0020] A back electrode region is formed at the bottom of the drift region, and a back electrode formed by a back metal layer is formed on the back surface of the back electrode region.

[0021] A plurality of device units in parallel are formed in the device unit region; each of the device units includes a trench gate.

[0022] The trench gate includes a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench, and a gate conductive material layer filled in the gate trench; the gate trench passes through the channel region, and the surface of the channel region covered by the gate conductive material layer is used to form a conductive channel.

[0023] Each of the device units further includes a source region of the first conductivity type heavily doped, which is formed on the surface of the channel region and self-aligned with the side surface of the corresponding trench gate.

[0024] A plurality of second trench structures are included in the termination region, the second trench structure includes a second trench, a second dielectric layer formed on the inner side surface of the second trench, and a second conductive material layer filled in the second trench; the second trench passes through the channel region.

[0025] Each of the gate trenches and each of the second trenches are arranged in parallel.

[0026] A first thermal oxide layer covers all regions of the termination region and the device unit region; in the termination region, the first thermal oxide layer directly thermally oxidizes the material of the first epitaxial layer and the material of the second conductive material layer in the surface region of the channel region to form; in the device unit region, the first thermal oxide layer directly thermally oxidizes the material of the first epitaxial layer in the surface region of the source region, the material of the first epitaxial layer in the surface region of the channel region outside the source region, and the material of the gate conductive material layer to form.

[0027] The composition structure of the lateral voltage-resistant termination structure includes a plurality of the second trench structures arranged in parallel, the channel region, the drift region, and the first thermal oxide layer; the interface characteristics between the first thermal oxide layer and the material of the first epitaxial layer, and the continuous extension structure of the first thermal oxide layer without etching in the termination region and the device unit region are used to improve the reliability of the vertical power device.

[0028] A further improvement is that the impurities in the channel region and the source region are advanced by a thermal process of thermal oxidation of the first thermal oxide layer.

[0029] A further improvement is that the thickness of the first thermal oxide layer meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer.

[0030] Alternatively, the first thermal oxide layer serves as the bottom portion of the interlayer film, a deposited oxide layer is further formed on the surface of the first thermal oxide layer, and the interlayer film is formed by stacking the first thermal oxide layer and the deposited oxide layer.

[0031] A further improvement is that the gate conductive material layer is connected to the gate composed of the front metal layer through a corresponding through hole passing through the interlayer film at the top.

[0032] The source region is connected to the source electrode formed by the front metal layer through the corresponding through hole on the top.

[0033] The second conductive material layer is a floating structure or the second conductive material layer is connected to the back electrode.

[0034] A further improvement is that the vertical power device is a vertical super junction power device, and a super junction structure is formed in the drift region. The super junction structure is composed of alternating second conductive type columns formed in selected areas of the drift region and first conductive type columns formed in the drift region located between the second conductive type columns.

[0035] A further improvement is that the second conductive type column extends downward from the top surface of the first epitaxial layer on which the trench gate, the second trench structure, the channel region and the source region are formed, and the second conductive type column includes a superimposed structure of a second conductive type ion implantation region or includes a second conductive type epitaxial layer filled in a super junction trench.

[0036] A further improvement is that the vertical power device includes a MOSFET or an IGBT, and the MOSFET includes a trench gate MOSFET or an SGT MOSFET.

[0037] A further improvement is that the gate trench and the second trench have a process structure formed simultaneously using the same process.

[0038] The gate dielectric layer and the second dielectric layer are made of the same material and are formed simultaneously.

[0039] The gate conductive material layer and the second conductive material layer are made of the same material and are formed at the same time.

[0040] A further improvement is that the gate conductive material layer is made of polysilicon.

[0041] To solve the above technical problems, the present invention provides a method for manufacturing a structure for improving the reliability of a vertical power device, comprising the following steps:

[0042] A semiconductor substrate is provided, wherein a first epitaxial layer doped with a first conductivity type is formed on a front surface of the semiconductor substrate.

[0043] At the same time, a plurality of trench gates are formed in the device unit region and a plurality of second trench structures are formed in the terminal region, wherein the terminal region surrounds the periphery of the device unit region; the trench gates include a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; the second trench structure includes a second trench, a second dielectric layer formed on the inner surface of the second trench, and a second conductive material layer filled in the second trench; each of the gate trenches and each of the second trenches is arranged in parallel.

[0044] Ion implantation of a second conductive type is performed to form a channel region in the surface area of ​​the first epitaxial layer in the device unit region and the terminal region; the gate trench passes through the channel region, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a conductive channel; the second trench passes through the channel region.

[0045] Ions heavily doped with the first conductivity type are implanted into the surface of the channel region in the selected region of the device cell region to form a source region of each device cell. The source region is self-aligned with the side surface of the corresponding trench gate.

[0046] Thermal oxidation is performed to form a first thermal oxide layer, which covers the entire area of ​​the terminal region and the device unit region. In the terminal region, the first thermal oxide layer is directly thermally oxidized to the material of the first epitaxial layer in the surface area of ​​the channel region and the material of the second conductive material layer; in the device unit region, the first thermal oxide layer is directly thermally oxidized to the material of the first epitaxial layer in the surface area of ​​the source region, the material of the first epitaxial layer in the surface area of ​​the channel region outside the source region, and the material of the gate conductive material layer; the terminal structure with lateral voltage resistance comprises a plurality of laterally arranged second trench structures, the channel region, the drift region and the first thermal oxide layer, and the reliability of the vertical power device is improved by utilizing the interface characteristics between the materials of the first thermal oxide layer and the first epitaxial layer and the continuous extension structure of the first thermal oxide layer without etching in the terminal region and the device unit region.

[0047] A further improvement is that the impurities in the channel region and the source region are advanced by a thermal process of thermal oxidation of the first thermal oxide layer.

[0048] A further improvement is that the ion implantation in the channel region adopts a general implantation or a selective ion implantation defined by a photoresist.

[0049] The ion implantation in the source region adopts selective ion implantation defined by a photomask.

[0050] A further improvement is that the thickness of the first thermal oxide layer meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer;

[0051] Or, also include:

[0052] A deposited oxide layer is formed on the surface of the first thermal oxide layer by adopting a CVD deposition process, and the first thermal oxide layer and the deposited oxide layer are stacked to form the interlayer film.

[0053] Further improvements include:

[0054] A through hole is formed through the interlayer film.

[0055] A front metal layer is formed and patterned to form a source electrode and a gate electrode.

[0056] The gate conductive material layer is connected to the gate through the corresponding through hole on the top.

[0057] The source region is connected to the source electrode through the corresponding through hole at the top.

[0058] The second conductive material layer is a floating structure or the second conductive material layer is connected to the back electrode.

[0059] A further improvement is that the vertical power device is a vertical super junction power device, and further comprises the following steps after the source region is formed and before the first thermal oxide layer is formed:

[0060] A super junction structure is formed in the drift region, wherein the super junction structure is formed by alternatingly arranging second conductive type columns formed in selected areas of the drift region and first conductive type columns formed in the drift region between the second conductive type columns.

[0061] A further improvement is that the second conductive type pillars are formed by multiple second conductive type ion implantations.

[0062] Alternatively, the step of forming the second conductive type column includes:

[0063] forming a super junction trench;

[0064] A second conductive type epitaxial layer is filled in the super junction trench to form a second conductive type pillar.

[0065] A further improvement is that the vertical power device includes a MOSFET or an IGBT, and the MOSFET includes a trench gate MOSFET or an SGT MOSFET.

[0066] A further improvement is that the gate conductive material layer is made of polysilicon.

[0067] In the terminal structure of the present invention, the oxide layer on the top of the epitaxial layer adopts a first thermal oxide layer that fully covers the terminal area and the device unit area. The thermal oxidation process can minimize the interface defects between the first thermal oxide layer and the material of the bottom first epitaxial layer; at the same time, the first thermal oxide layer does not adopt a graphic process, so that the first thermal oxide layer has no interface in the lateral extension direction, for example, there is no interface between the terminal area and the device unit area, such as an interface formed by etching. In this way, the quality of the first thermal oxide layer can be guaranteed, so that the quality of the first thermal oxide layer reaches the best quality. The reduction of interface defects and the improvement of the quality of the first thermal oxide layer can simultaneously improve the reliability of the device, so that the reliability of the device reaches the best state.

[0068] In addition, the first thermal oxide layer of the present invention does not require a patterning process and can save a photolithography process, which can also reduce process costs.

[0069] In addition, the first thermal oxide layer of the present invention can be directly used as a component of the interlayer film, so that the deposition of the interlayer film with a partial thickness does not need to be performed or only needs to be performed, which can further reduce the process cost.

[0070] In addition, the thermal oxidation process of the first thermal oxide layer of the present invention can also oxidize the top region of the gate conductive material layer of the trench gate, which can repair the morphology of the gate conductive material layer and thus optimize the gate leakage.

[0071] In addition, the thermal process of the thermal oxidation process of the first thermal oxide layer of the present invention can directly serve as the thermal process for advancing the ion implantation of impurities in the channel region and the source region, thereby achieving the sharing of the thermal process and further reducing the process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0073] Figure 1A-1B It is a schematic diagram of the device structure in each step of the method for manufacturing the field oxygen required for the terminal region of the first existing power device;

[0074] Figure 2 A schematic diagram of the device structure in the step of defining the field oxygen forming region in the method for manufacturing the field oxygen required for the terminal region of the second existing power device;

[0075] Figure 3A2. It is a schematic diagram of the structure before the first thermal oxide layer is formed in the structure for improving the reliability of a vertical power device according to the first embodiment of the present invention;

[0076] Figure 3B 2. It is a schematic diagram of the structure after the first thermal oxide layer is formed in the structure for improving the reliability of a vertical power device according to the first embodiment of the present invention;

[0077] Figure 4 This is a schematic structural diagram before the first thermal oxide layer is formed in the structure for improving the reliability of a vertical power device according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0078] like Figure 3A , which is a schematic structural diagram of the structure before the first thermal oxide layer 17 is formed in the structure for improving the reliability of the vertical power device according to the first embodiment of the present invention; Figure 3B As shown, it is a schematic diagram of the structure after the first thermal oxide layer 17 is formed in the structure for improving the reliability of the vertical power device in the first embodiment of the present invention, and the structure on the top of the first thermal oxide layer 17 is omitted; in the structure for improving the reliability of the vertical power device in the embodiment of the present invention, the vertical power device includes a device unit area and a terminal area, and the terminal area surrounds the peripheral side of the device unit area. Figure 3A In FIG, the terminal region is located on the left side of line AA, and the device unit region is located on the right side of line AA.

[0079] A channel region 15 doped with the second conductivity type is formed in the surface region of the first epitaxial layer 12 a doped with the first conductivity type.

[0080] The first epitaxial layer 12 a at the bottom of the channel region 15 serves as the drift region 12 .

[0081] A back electrode region 11 is formed at the bottom of the drift region 12, and a back electrode formed from a back metal layer is formed on the back side of the back electrode region 11. In the first embodiment of the present invention, the vertical power device is a MOSFET, the back electrode region 11 is a drain region heavily doped with the first conductivity type, and the back electrode is a drain. In other embodiments, the vertical power device can also be an IGBT, the back electrode region 11 is a collector region heavily doped with the second conductivity type, and the back electrode is a collector.

[0082] Furthermore, in some embodiments, taking an N-type MOSFET as an example, the semiconductor substrate is a heavily doped N-type substrate. It is desirable that the doping concentration of the semiconductor substrate be as high as possible, the resistivity be as low as possible, and the thickness of the semiconductor substrate be as thin as possible. This not only reduces the substrate resistance but also helps reduce the thermal resistance of the chip. Currently, for phosphorus-doped semiconductor substrates, the substrate resistivity can reach 0.7 mΩ*cm, while for arsenic-doped semiconductor substrates, the substrate resistivity can reach 1.1 mΩ*cm. The thinnest semiconductor substrate thickness currently available is 30 μm.

[0083] The first epitaxial layer 12a is set according to the requirements of the drift region 12. The doping concentration and thickness of the drift region 12 determine the breakdown voltage of the device. The higher the breakdown voltage required by the device, the thicker the drift region 12 and the higher the resistivity of the drift region 12. For a 600V device, the resistivity of the drift region 12 is usually around 13Ω*cm, and the thickness of the drift region 12 is usually around 50μm.

[0084] In the first embodiment of the present invention, the first epitaxial layer 12a is formed on the surface of the semiconductor substrate. The back electrode region 11 is a heavily doped region of the first conductivity type formed on the back side of the drift region 2 after the back side of the semiconductor substrate is thinned. In some embodiments, the semiconductor substrate adopts a heavily doped structure of the first conductivity type, so that the back electrode region 11, i.e., the drain region, is directly composed of the semiconductor substrate after the back side is thinned. In some embodiments, it is also possible that: the doping concentration of the semiconductor substrate does not meet the requirements of the heavily doped first conductivity type of the back electrode region 11, and the back electrode region 11 is composed of a back ion implantation region that is heavily doped with the first conductivity type after the back side of the semiconductor substrate is thinned.

[0085] A plurality of device units connected in parallel are formed in the device unit region; each device unit includes a trench gate. The step size of the device unit is the sum of the width of the trench gate and the spacing between the trench gates.

[0086] The trench gate includes a gate trench, a gate dielectric layer 13 formed on the inner side surface of the gate trench, and a gate conductive material layer 14 filled in the gate trench; the gate trench passes through the channel region 15, and the surface of the channel region 15 covered by the gate conductive material layer 14 is used to form a conductive channel. In the first embodiment of the present application, the MOSFET is a trench gate MOSFET. The trench gate is formed by only stacking the gate dielectric layer 13 and the gate conductive material layer 14 in the gate trench. In other embodiments, the MOSFET can also be a shield gate trench (SGT) MOSFET, and in the gate trench, a shield electrode conductive material layer is further formed, a shield dielectric layer is isolated between the shield electrode conductive material layer and the gate trench, and a gate-to-gate dielectric layer is isolated between the shield electrode conductive material layer and the gate conductive material layer 14. The gate structure of the SGT MOSFET can be a left-right structure or an up-down structure. For details, refer to the structure of the existing SGT MOSFET, and the gate structure of the SGT MOSFET will not be described in detail in the present application.

[0087] Each device unit further includes a first-conductive-type heavily doped source region 16 formed on the surface of the channel region 15 and self-aligned with the side surface of the corresponding trench gate. In some embodiments, a first-conductive-type heavily doped cutoff region 16a is formed on the outermost side of the termination region, and the cutoff region 16a is usually formed at the same time as the source region 16, and in this case, the doping process conditions are the same. In some embodiments, the cutoff region 16a is independent of the formation process of the source region 16, and the doping process conditions are also independent of each other.

[0088] The termination region includes a plurality of second trench structures, and each second trench structure includes a second trench, a second dielectric layer 13a formed on the inner side surface of the second trench, and a second conductive material layer 14a filled in the second trench; the second trench passes through the channel region 15.

[0089] Each gate trench and each second trench are arranged in parallel.

[0090] In the first embodiment of the present application, the gate trench and the second trench have a process structure formed at the same time by using the same process. In some embodiments, the width of the second trench is the same as the width of the gate trench, and the pitch of the second trench is the same as the pitch of the gate trench. In some embodiments, the width of the second trench and the width of the gate trench are independent of each other, and the pitch of the second trench and the pitch of the gate trench are independent of each other.

[0091] In the first embodiment of the present application, the gate dielectric layer 13 and the second dielectric layer 13a are formed at the same time and have the same material. In some embodiments, the gate dielectric layer 13 adopts an oxide layer.

[0092] The gate conductive material layer 14 and the second conductive material layer 14a are made of the same material and are formed simultaneously. In some embodiments, the gate conductive material layer 14 is made of heavily doped polysilicon of the first conductivity type.

[0093] In some embodiments, the width of the trench, ie, the gate trench or the second trench, is typically 0.3 μm, the width between trenches is 0.7 μm, the corresponding pitch is 1.0 μm, and the depth of the trench is also typically 1.0 μm.

[0094] After the trench etching is completed, an oxide layer is grown as the gate dielectric layer 13 and the second dielectric layer 13a. The oxide is usually grown by thermal oxidation and has a thickness of between.

[0095] Figure 3A In the embodiment, the top surface of the first epitaxial layer 12a is indicated by a mark 301, and the first thermal oxide layer 17 is formed on the top surface of the first epitaxial layer 12a indicated by the mark 301. Figure 3B As shown, the first thermal oxide layer 17 covers the entire area of ​​the terminal region and the device unit region. In the terminal region, the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a in the surface region of the channel region 15 and the material of the second conductive material layer 14a. In the device unit region, the first thermal oxide layer 17 is formed by directly thermally oxidizing the material of the first epitaxial layer 12a in the surface region of the source region 16, the material of the first epitaxial layer 12a in the surface region of the channel region 15 outside the source region 16, and the material of the gate conductive material layer 14. Figure 3B As shown, thermal oxidation causes a certain loss in the thickness of the first epitaxial layer 12a. After the first thermal oxide layer 17 is formed, the top surface of the first epitaxial layer 12a is lowered from the position indicated by mark 301 to the position indicated by mark 302. The first thermal oxide layer 17 formed by this thermal oxidation has an optimal interface structure and minimal defects.

[0096] The terminal structure with lateral voltage resistance comprises a plurality of laterally arranged second trench structures, a channel region 15, a drift region 12 and a first thermal oxide layer 17. The reliability of the vertical power device is improved by utilizing the interface characteristics between the materials of the first thermal oxide layer 17 and the first epitaxial layer 12a and the continuous extension structure of the first thermal oxide layer 17 without etching in the terminal region and the device unit region.

[0097] In some embodiments, taking the material of the first epitaxial layer 12a as silicon, the first thermal oxide layer 17 consumes the platform area (Mesa) between the trench, that is, the gate trench or the second trench, and the consumption ratio is approximately Oxide will consume It also consumes a certain amount of polysilicon; this needs to be considered in the design.

[0098] Some typical conditions for thermal oxidation of the first thermal oxide layer 17 may be:

[0099] A.980℃ temperature, growth thickness is

[0100] B.1050℃ temperature, growth thickness is

[0101] C.980℃ temperature, growth thickness is

[0102] In the first embodiment of the present invention, the impurities in the channel region 15 and the source region 16 are introduced by a thermal oxidation process of the first thermal oxide layer 17 .

[0103] In some embodiments, the thickness of the first thermal oxide layer 17 satisfies the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer 17; for example, if the thickness is greater than The first thermal oxide layer 17 can directly serve as an interlayer film. In some embodiments, the first thermal oxide layer 17 can serve as the bottom portion of the interlayer film, and a deposited oxide layer is also formed on the surface of the first thermal oxide layer 17, and the first thermal oxide layer 17 and the deposited oxide layer are stacked to form an interlayer film. The deposited oxide layer of the ILD is usually composed of PSG+BPSG. In the prior art, the ILD is formed directly on the surface of the first epitaxial layer 12 by depositing an oxide layer, but the deposited oxide will have more defects at the interface between the silicon and oxide in the terminal area, which has a relatively poor impact on the long-term reliability of the product. The first thermal oxide layer 17 in the first embodiment of the present invention can eliminate the problem of a large number of interface defects caused by the contact between the deposited oxide layer of the ILD and the first epitaxial layer 12.

[0104] The gate conductive material layer 14 is connected to the gate composed of the front metal layer through the corresponding through-hole penetrating the interlayer film on the top.

[0105] The source region 16 is connected to the source electrode formed by the front metal layer through the corresponding via hole on the top.

[0106] The second conductive material layer 14a is a floating structure or the second conductive material layer 14a is connected to the back electrode.

[0107] In the first embodiment of the present invention, the vertical power device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the vertical power device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0108] In the terminal structure of the first embodiment of the present invention, the oxide layer on the top of the epitaxial layer adopts the first thermal oxide layer 17 that fully covers the terminal area and the device unit area. The thermal oxidation process can minimize the interface defects between the first thermal oxide layer 17 and the material of the first epitaxial layer 12a at the bottom; at the same time, the first thermal oxide layer 17 does not adopt a graphical process, so that the first thermal oxide layer 17 has no interface in the lateral extension direction, for example, there is no interface between the terminal area and the device unit area, such as an interface formed by etching. In this way, the quality of the first thermal oxide layer 17 can be guaranteed, so that the quality of the first thermal oxide layer 17 reaches the best quality. The reduction of interface defects and the improvement of the quality of the first thermal oxide layer 17 can simultaneously improve the reliability of the device and achieve the best reliability of the device.

[0109] In addition, the first thermal oxide layer 17 of the first embodiment of the present invention does not require a patterning process and can save a photolithography process, which can also reduce the process cost.

[0110] In addition, the first thermal oxide layer 17 of the first embodiment of the present invention can be directly used as a component of the interlayer film, so that there is no need to deposit an interlayer film or only a partial thickness of the interlayer film is deposited, which can further reduce the process cost.

[0111] In addition, the thermal oxidation process of the first thermal oxide layer 17 of the first embodiment of the present invention can also oxidize the top region of the gate conductive material layer 14 of the trench gate, which can repair the morphology of the gate conductive material layer 14 and thus optimize the gate leakage.

[0112] In addition, the thermal process of the thermal oxidation process of the first thermal oxide layer 17 in the first embodiment of the present invention can directly serve as the thermal process for advancing the ion implantation of impurities in the channel region 15 and the source region 16, thereby achieving the sharing of the thermal process and further reducing the process cost.

[0113] like Figure 4 FIG. 1 is a schematic diagram of a structure before the first thermal oxide layer is formed in a structure for improving the reliability of a vertical power device according to a second embodiment of the present invention; the difference from the structure for improving the reliability of a vertical power device according to the first embodiment of the present invention is as follows:

[0114] In the structure for improving the reliability of vertical power devices according to the second embodiment of the present invention, the vertical power devices are vertical super junction power devices, and a super junction structure is formed in the drift region 12. The super junction structure is formed by alternating second conductive type columns 18 formed in selected areas of the drift region 12 and first conductive type columns formed in the drift region 12 located between the second conductive type columns 18.

[0115] The second conductive type pillar 18 extends downward from the top surface of the first epitaxial layer 12 a where the trench gate, the second trench structure, the channel region 15 and the source region 16 are formed, ie, the surface corresponding to the mark 301 .

[0116] In some embodiments, the second conductive type column 18 includes a superposition structure of second conductive type ion implantation regions. For example, taking a typical 80V N-type super junction (SJ) MOSFET as an example, the P column, i.e., the second conductive type column 18, is implanted 5 to 10 times, with a single ion implantation dose of 3e12 to 1e13 cm 2 The implanted impurity is Boron, with an implant energy between 100 and 3500 keV. During the process implementation, the P column is placed after the ion implantation of the NP region (source region 16) to minimize thermal processes and reduce lateral diffusion of the P column, thereby increasing the conductive channel in the N-type drift region.

[0117] In some embodiments, the second conductivity type pillar 18 may include a second conductivity type epitaxial layer filled in the super junction trench. The super junction structure formed by filling the super junction trench can be applied to higher super junction devices, for example, a 600V SJ MOSFET.

[0118] The vertical power device formed by the method for manufacturing a structure for improving the reliability of a vertical power device according to the first embodiment of the present invention includes a MOSFET or an IGBT. The following description will take the formation of a MOSFET as an example. The method for manufacturing a structure for improving the reliability of a vertical power device according to the embodiment of the present invention includes the following steps:

[0119] like Figure 3A As shown, a semiconductor substrate is provided, and a first epitaxial layer 12a doped with a first conductivity type is formed on the front surface of the semiconductor substrate. In some embodiments, the semiconductor substrate adopts a heavily doped structure of the first conductivity type, so that the back electrode region 11 is directly formed after the back surface of the semiconductor substrate is thinned.

[0120] At the same time, multiple trench gates are formed in the device cell region and multiple second trench structures are formed in the terminal region, with the terminal region surrounding the periphery of the device cell region. The trench gates include a gate trench, a gate dielectric layer 13 formed on the inner surface of the gate trench, and a gate conductive material layer 14 filled in the gate trench. The second trench structure includes a second trench, a second dielectric layer 13a formed on the inner surface of the second trench, and a second conductive material layer 14a filled in the second trench. Each gate trench and each second trench are arranged in parallel. In some embodiment methods, the formation process of the trench gates and the second trench structure includes the following steps:

[0121] Typically, a hard mask layer is formed before trench etching, and then photolithography is performed to define the formation areas of the gate trench and the second trench. The hard mask layer and the first epitaxial layer 12a are then etched in sequence to form the gate trench and the second trench.

[0122] Then, a gate dielectric layer 13 is formed on the inner surface of the gate trench and a second dielectric layer 13a is formed on the inner surface of the second trench. Preferably, both the gate dielectric layer 13 and the second dielectric layer 13a are oxide layers formed by thermal oxidation growth.

[0123] Afterwards, polysilicon filling and etching back are performed, forming polysilicon located only in the gate trench and the second trench. The polysilicon on the surface of the terrace area between the trenches is removed. The gate conductive material layer 14 is composed of the polysilicon formed in the gate trench, and the second conductive material layer 14a is composed of the polysilicon formed in the second trench.

[0124] Ions of the second conductivity type are implanted to form a channel region 15 in the surface area of ​​the first epitaxial layer 12a in the device cell region and the terminal region. A gate trench passes through the channel region 15, and the surface of the channel region 15 laterally covered by the gate conductive material layer 14 is used to form a conductive channel. A second trench passes through the channel region 15. In the first embodiment of the present invention, ion implantation of the channel region 15 is performed using a blanket implant. In other embodiments, selective ion implantation defined by a photoresist may also be employed.

[0125] Ions of the first conductivity type are heavily doped to form source regions 16 for each device cell in the surface area of ​​the channel region 15 within selected regions of the device cell region. Source regions 16 are self-aligned with the side surfaces of the corresponding trench gates. Ion implantation of source regions 16 utilizes selective ion implantation defined by a photoresist. In some exemplary methods, the ion implantation of source regions 16 also simultaneously forms a stop region 16a at the outermost periphery of the termination region.

[0126] like Figure 3B As shown, thermal oxidation is performed to form a first thermal oxide layer 17, and the first thermal oxide layer 17 covers the entire area of ​​the terminal region and the device unit region. In the terminal region, the first thermal oxide layer 17 is directly formed by thermally oxidizing the material of the first epitaxial layer 12a in the surface region of the channel region 15 and the material of the second conductive material layer 14a; in the device unit region, the first thermal oxide layer 17 is directly formed by thermally oxidizing the material of the first epitaxial layer 12a in the surface region of the source region 16, the material of the first epitaxial layer 12a in the surface region of the channel region 15 outside the source region 16, and the material of the gate conductive material layer 14; the component structure of the lateral voltage-resistant terminal structure includes a plurality of laterally arranged second trench structures, the channel region 15, the drift region 12 and the first thermal oxide layer 17, and the reliability of the vertical power device is improved by utilizing the interface characteristics between the first thermal oxide layer 17 and the material of the first epitaxial layer 12a and the continuous extension structure of the first thermal oxide layer 17 without etching in the terminal region and the device unit region.

[0127] In the method of the first embodiment of the present invention, the impurities in the channel region 15 and the source region 16 are advanced by thermal oxidation of the first thermal oxide layer 17. This not only saves one annealing process but also prevents excessive diffusion of impurities in the channel region 15 and the source region 16.

[0128] In the method of the first embodiment of the present invention, thermal oxidation causes a loss in the thickness of the first epitaxial layer 12a. For example, the top surface of the first epitaxial layer 12a is lowered from the position indicated by mark 301 to the position indicated by mark 302. Simultaneously, thermal oxidation also causes a loss in the material of the gate conductive material layer 14 and the second conductive material layer 14a, such as polysilicon. In actual processes, this loss needs to be taken into account in the design.

[0129] In some embodiment methods, the thickness of the first thermal oxide layer 17 meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer 17 .

[0130] In some embodiments, after forming the first thermal oxide layer 7 , the method further includes:

[0131] A deposited oxide layer is formed on the surface of the first thermal oxide layer 17 using a CVD deposition process. The first thermal oxide layer 17 and the deposited oxide layer are stacked to form an interlayer film. The deposited oxide layer is usually formed by stacking phosphorus glass (PSG) and boron phosphorus glass (BPSG).

[0132] After the interlayer film is formed, it also includes:

[0133] A through hole is formed through the interlayer film.

[0134] The thickness of the first thermal oxide layer 17 meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer 17. In some embodiments, the first thermal oxide layer 17 serves as the bottom portion of the interlayer film, and a deposited oxide layer is further formed on the surface of the first thermal oxide layer 17. The first thermal oxide layer 17 and the deposited oxide layer are stacked to form the interlayer film.

[0135] A front metal layer is formed and patterned to form a source electrode and a gate electrode.

[0136] The gate conductive material layer 14 is connected to the gate through a corresponding through hole on the top.

[0137] The source region 16 is connected to the source electrode through a corresponding via at the top.

[0138] After that, the backside process is carried out, which includes:

[0139] The semiconductor substrate is thinned. In the first embodiment of the present application, the semiconductor substrate is heavily doped with the first conductive type, and the back electrode region 11 is directly formed by the thinned semiconductor substrate. In some embodiments, after the semiconductor substrate is thinned, ion implantation of the first conductive type is performed to form the back electrode region 11.

[0140] The back surface of the back electrode region 11 is formed with a back surface metal layer to form a back electrode.

[0141] The second conductive material layer 14a is in a floating structure or connected to the back electrode.

[0142] The first embodiment of the present application is further described below with reference to an N-type MOSFET and parameters.

[0143] The semiconductor substrate is a heavily doped N-type substrate. The doping concentration of the semiconductor substrate is as high as possible, the resistivity is as low as possible, and the thickness of the semiconductor substrate can be as thin as possible, which not only reduces the substrate resistance, but also helps to reduce the thermal resistance of the chip.

[0144] Currently, the resistivity of a phosphorus-doped semiconductor substrate can reach 0.7 mΩ*cm, and the resistivity of an arsenic-doped semiconductor substrate can reach 1.1 mΩ*cm. The thinnest semiconductor substrate currently available is 30 μm thick.

[0145] The first epitaxial layer 12a is set according to the requirements of the drift region 12. The doping concentration and thickness of the drift region 12 determine the breakdown voltage of the device. The higher the required breakdown voltage of the device, the thicker the thickness of the drift region 12, and the higher the resistivity of the drift region 12. For a 600V device, the resistivity of the drift region 12 is usually around 13Ω*cm, and the thickness of the drift region 12 is usually around 50μm.

[0146] In the first embodiment of the present application, only two photomasks are used for the N-type MOSFET.

[0147] The trenches, i.e. the gate trenches and the second trenches, need to be defined using a photomask. Etching is performed under the definition of the photomask to form the trenches. Typically, a hard mask layer (HM) is formed before the etching process of the trenches. The hard mask layer is usually an oxide layer.

[0148] In some embodiments, the width of the trench is usually 0.3μm, the width between the trenches is 0.7μm, the corresponding pitch is 1.0μm, and the depth of the trench is usually 1.0μm.

[0149] After the trench etching, a layer of oxide is grown as gate dielectric 13 and second dielectric layer 13a. The oxide is usually thermal oxide growth, the thickness is usually between

[0150] Then N type heavily doped poly is filled in the trench, and then etch back is performed to fill the trench with poly, while leaving no poly in the mesa region between the trenches.

[0151] Then the channel region is implanted, and for some products, the channel can also be implanted using a photomask.

[0152] Then a photomask is used to perform the source NP implantation.

[0153] For conventional trench MOSFETs, the next step is to deposit the interlayer dielectric (ILD), which is usually composed of PSG + BPSG. However, the deposited oxide has a higher number of defects at the interface between the silicon and the oxide in the termination region, which is not good for long-term reliability. In the first embodiment of the present application, after the ion implantation in the source region 16, a layer of thermal oxide, i.e. the first thermal oxide layer 17, is grown. This first thermal oxide layer 17 will consume the mesa region between the trenches, i.e. the gate trenches or the second trenches. The consumption ratio is approximately of oxide will consume of silicon. At the same time, a certain amount of poly will also be consumed; this needs to be considered in the design.

[0154] Some typical conditions for the thermal oxidation of the first thermal oxide layer 17 can be:

[0155] A. Temperature of 980°C, growth thickness of

[0156] B. Temperature of 1050°C, growth thickness of

[0157] C. Temperature of 980°C, growth thickness of

[0158] The benefits of the first embodiment of the present application are:

[0159] A. The interface between the silicon, i.e. the first epitaxial layer 12, and the oxide, i.e. the first thermal oxide layer 17, in the termination region is produced by thermal oxidation, and the quality of the interface is well guaranteed.

[0160] ​B. This grown oxide will not undergo any subsequent etching process; the quality of the oxide layer is greatly guaranteed.

[0161] C. The grown oxide will directly serve as part of the ILD. Under certain conditions, the ILD can be completely replaced by the grown oxide, eliminating the need for subsequent oxide layer deposition.

[0162] D. The profile of the trench gate polysilicon is repaired after thermal oxidation, which helps to optimize the gate leakage of the device.

[0163] After forming the first thermal oxide layer 17, the next step is to form an interlayer film, that is, an ILD, which depends on the thickness of the first thermal oxide layer 17. If the thickness of the first thermal oxide layer 17 is not enough, the ILD can be deposited. If the thickness is greater than The first thermal oxide layer 17 may also be directly used as the ILD.

[0164] Then, through-hole (CT) etching, metal deposition, etc. are performed to form a complete trench MOSFET.

[0165] The method of the first embodiment of the present invention is also applicable to SGT MOSFETs, SJ MOSFETs, IGBTs, and other applications. The method of the first embodiment of the present invention directly thermally grows a thick layer of oxide after NP formation and before CT formation. This reduces the number of defects at the terminal silicon-oxide interface and eliminates the need for additional photoresist plates, thus improving product reliability.

[0166] The second embodiment of the present invention provides a method for manufacturing a structure for improving the reliability of a vertical power device. The vertical power device that can be formed includes a vertical super junction power device. The differences from the method of the first embodiment of the present invention include:

[0167] like Figure 4 As shown, in the method of the second embodiment of the present invention, after the source region 16 is formed and before the first thermal oxide layer 17 is formed, the following steps are further included:

[0168] A super junction structure is formed in the drift region 12 , which is formed by alternating second conductivity type columns 18 formed in selected areas of the drift region 12 and first conductivity type columns formed in the drift region 12 between the second conductivity type columns 18 .

[0169] In some embodiments, the second-conductivity-type column 18 is formed by multiple second-conductivity-type ion implantations. In a typical 80V SJ MOSFET, the P column, i.e., the second-conductivity-type column 18, is formed by 5-10 ion implantations, each with a dose of 3e12-1e13cm 2 In the implementation of the process, the P column is placed after the N P in order to minimize the thermal process and reduce the lateral diffusion of the P column, thereby increasing the conductive channel of the N-type drift region.

[0170] In some embodiments, the step of forming the second-conductivity-type column 18 can also include:

[0171] forming a super-junction trench;

[0172] filling the super-junction trench with a second-conductivity-type epitaxial layer to form the second-conductivity-type column 18.

[0173] The method of filling the super-junction trench enables the second-conductivity-type column 18 to have a greater depth, and is suitable for the fabrication of vertical super-junction power devices with higher voltage resistance, such as a 600V SJ MOSFET.

[0174] The above detailed description of the present application is based on specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered within the scope of the present application.

Claims

1. A structure for improving the reliability of a vertical power device, characterized in that: The vertical power device includes a device unit region and a terminal region, wherein the terminal region surrounds the periphery of the device unit region; A channel region doped with a second conductivity type is formed in a surface region of the first epitaxial layer doped with the first conductivity type; The first epitaxial layer at the bottom of the channel region serves as a drift region; A back electrode region is formed at the bottom of the drift region, and a back electrode formed of a back metal layer is formed on the back of the back electrode region; A plurality of device units connected in parallel are formed in the device unit area; each of the device units includes a trench gate; The trench gate includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; the gate trench passes through the channel region, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a conductive channel; Each of the device units further includes a source region heavily doped with the first conductivity type, wherein the source region is formed on the surface of the channel region and self-aligned with the side surface of the corresponding trench gate; The terminal region includes a plurality of second trench structures, wherein the second trench structures include second trenches, a second dielectric layer formed on inner surfaces of the second trenches, and a second conductive material layer filled in the second trenches; The second trench passes through the channel region; Each of the gate trenches and each of the second trenches are arranged in parallel; A first thermal oxide layer covers the entire region of the terminal region and the device cell region. In the terminal region, the first thermal oxide layer is formed by directly thermally oxidizing the material of the first epitaxial layer and the material of the second conductive material layer in the surface region of the channel region. In the device cell region, the first thermal oxide layer is formed by directly thermally oxidizing the material of the first epitaxial layer in the surface region of the source region, the material of the first epitaxial layer in the surface region of the channel region outside the source region, and the material of the gate conductive material layer. The terminal structure with lateral voltage resistance comprises a plurality of laterally arranged second trench structures, the channel region, the drift region, and the first thermal oxide layer. The reliability of the vertical power device is improved by utilizing the interface characteristics between the materials of the first thermal oxide layer and the first epitaxial layer and the continuous extension structure of the first thermal oxide layer without etching in the terminal region and the device unit region. The impurities in the channel region and the source region are advanced by a thermal process of thermal oxidation of the first thermal oxide layer; The thickness of the first thermal oxide layer meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer; Alternatively, the first thermal oxide layer serves as the bottom portion of the interlayer film, a deposited oxide layer is further formed on the surface of the first thermal oxide layer, and the interlayer film is formed by stacking the first thermal oxide layer and the deposited oxide layer.

2. The structure for improving the reliability of a vertical power device according to claim 1, wherein: The gate conductive material layer is connected to the gate composed of the front metal layer through the corresponding through hole passing through the interlayer film at the top; The source region is connected to the source electrode composed of the front metal layer through the corresponding through hole on the top; The second conductive material layer is a floating structure or the second conductive material layer is connected to the back electrode.

3. The structure for improving reliability of a vertical power device according to claim 1, wherein: The vertical power device is a vertical super junction power device, and a super junction structure is formed in the drift region. The super junction structure is composed of alternating second conductive type columns formed in selected areas of the drift region and first conductive type columns formed in the drift region located between the second conductive type columns.

4. The structure for improving the reliability of a vertical power device according to claim 3, wherein: The second conductive type column extends downward from the top surface of the first epitaxial layer on which the trench gate, the second trench structure, the channel region and the source region are formed, and the second conductive type column includes a superimposed structure of a second conductive type ion implantation region or includes a second conductive type epitaxial layer filled in a super junction trench.

5. The structure for improving the reliability of a vertical power device according to claim 1 or 3, wherein: The vertical power device includes a MOSFET or an IGBT, and the MOSFET includes a trench gate MOSFET or an SGT MOSFET.

6. The structure for improving reliability of a vertical power device according to claim 1, wherein: The gate trench and the second trench have a process structure formed simultaneously by the same process; The gate dielectric layer and the second dielectric layer are made of the same material and are formed at the same time; The gate conductive material layer and the second conductive material layer are made of the same material and are formed at the same time.

7. The structure for improving the reliability of a vertical power device according to claim 6, wherein: The gate conductive material layer is made of polysilicon.

8. A method for manufacturing a structure for improving the reliability of a vertical power device, characterized in that: The steps include: Providing a semiconductor substrate, wherein a first epitaxial layer doped with a first conductivity type is formed on a front surface of the semiconductor substrate; Simultaneously, a plurality of trench gates are formed in the device unit region and a plurality of second trench structures are formed in the terminal region, wherein the terminal region surrounds the periphery of the device unit region; the trench gates include a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; The second trench structure includes a second trench, a second dielectric layer formed on an inner surface of the second trench, and a second conductive material layer filled in the second trench; Each of the gate trenches and each of the second trenches are arranged in parallel; Performing ion implantation of a second conductivity type to form a channel region in the surface area of ​​the first epitaxial layer in the device cell region and the terminal region; the gate trench passes through the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel; The second trench passes through the channel region; Performing ion implantation of a first conductive type heavy dopant into a surface area of ​​the channel region in a selected area of ​​the device unit region to form a source region of each device unit, wherein the source region and the side surface of the corresponding trench gate are self-aligned; Performing thermal oxidation to form a first thermal oxide layer, wherein the first thermal oxide layer covers the entire region of the terminal region and the device unit region, and in the terminal region, the first thermal oxide layer is formed by directly thermally oxidizing the material of the first epitaxial layer and the material of the second conductive material layer in the surface region of the channel region; In the device cell region, the first thermal oxide layer is formed by directly thermally oxidizing the material of the first epitaxial layer in the surface region of the source region, the material of the first epitaxial layer in the surface region of the channel region outside the source region, and the material of the gate conductive material layer; the component structure of the lateral voltage-resistant terminal structure includes a plurality of laterally arranged second trench structures, the channel region, the drift region, and the first thermal oxide layer, and utilizes the interface characteristics between the materials of the first thermal oxide layer and the first epitaxial layer and the continuous extension structure of the first thermal oxide layer without etching in the terminal region and the device cell region to improve the reliability of the vertical power device; The impurities in the channel region and the source region are advanced by a thermal process of thermal oxidation of the first thermal oxide layer; The thickness of the first thermal oxide layer meets the thickness requirement of the interlayer film, and the interlayer film is composed of the first thermal oxide layer; Or, also include: A deposited oxide layer is formed on the surface of the first thermal oxide layer by adopting a CVD deposition process, and the first thermal oxide layer and the deposited oxide layer are stacked to form the interlayer film.

9. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 8, wherein: The ion implantation in the channel region adopts general implantation or selective ion implantation defined by a photomask; The ion implantation in the source region adopts selective ion implantation defined by a photomask.

10. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 8, wherein: Also includes: forming a through hole through the interlayer film; forming a front metal layer and patterning the front metal layer to form a source electrode and a gate electrode; The gate conductive material layer is connected to the gate through the corresponding through hole on the top; The source region is connected to the source electrode through the corresponding through hole at the top; The second conductive material layer is a floating structure or the second conductive material layer is connected to a back electrode.

11. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 8, wherein: The vertical power device is a vertical super junction power device, and further comprises the following steps after the source region is formed and before the first thermal oxide layer is formed: A super junction structure is formed in the drift region, wherein the super junction structure is formed by alternatingly arranging second conductive type columns formed in selected areas of the drift region and first conductive type columns formed in the drift region between the second conductive type columns.

12. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 11, wherein: The second conductive type pillar is formed by multiple second conductive type ion implantations; Alternatively, the step of forming the second conductive type column includes: forming a super junction trench; A second conductive type epitaxial layer is filled in the super junction trench to form a second conductive type pillar.

13. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 8 or 11, wherein: The vertical power device includes a MOSFET or an IGBT, and the MOSFET includes a trench gate MOSFET or an SGT MOSFET.

14. The method for manufacturing a structure for improving reliability of a vertical power device according to claim 8, wherein: The gate conductive material layer is made of polysilicon.

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