Method for manufacturing a semiconductor substrate and semiconductor substrate

Abstract

The application discloses a semiconductor substrate manufacturing method and a semiconductor substrate, and belongs to the semiconductor field. Two single crystal silicon wafers coated with adhesive phosphorus source are pressed in a back-to-back manner to obtain a laminated silicon wafer, the laminated silicon wafer is put into a diffusion furnace for multi-stage heating, the adhesive phosphorus source on the laminated silicon wafer is reacted to generate phosphorus and silicon dioxide, the phosphorus is diffused into the laminated silicon wafer, the two single crystal silicon wafers form a bonding and an N+ layer under the diffusion of the silicon dioxide and the phosphorus, and a bonded substrate is obtained. The silicon-silicon bonding and diffusion are formed in one step, and the process flow is greatly simplified. When the phosphorus is diffused into the laminated silicon wafer, the diffusion is carried out from the middle interlayer, so that the N-layer thickness of the substrate can reach an ideal state as much as possible, and finally, the device substrate can meet the performance requirement of a product device and the thickness requirement.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for fabricating a semiconductor substrate and a semiconductor substrate. Background Technology

[0002] Semiconductors are materials whose conductivity at room temperature falls between that of conductors and insulators. They are used in integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, and high-power power conversion. For example, diodes are devices made using semiconductors. A semiconductor substrate is an essential component in the fabrication of semiconductor devices.

[0003] Currently, triple diffusion is commonly used to obtain semiconductor substrates. Triple diffusion includes processes such as phosphorus pre-diffusion, phosphorus re-diffusion, and single-sided grinding to remove the diffusion layer. Through triple diffusion, substrates containing both N- and N+ layers can be obtained. However, this method is complex and cannot simultaneously meet the requirements of subsequent processes and device performance. Therefore, there is an urgent need for a semiconductor fabrication method that is simpler and can simultaneously meet the requirements of subsequent processes and device performance. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method for manufacturing a semiconductor substrate and a semiconductor substrate, which can greatly simplify the process flow and the semiconductor substrate manufactured can meet both the performance requirements of the product device and the thickness requirements.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor substrate, the method comprising:

[0007] A layer of viscous phosphorus source is coated on the back of the monocrystalline silicon wafer;

[0008] Two single-crystal silicon wafers coated with a sticky phosphorus source are pressed together in a back-to-back manner to obtain a laminated silicon wafer.

[0009] The laminated silicon wafer is placed in a diffusion furnace and heated and diffused in a multi-stage heating manner to cause the viscous phosphorus source to react and generate phosphorus and silicon dioxide, and to allow the phosphorus to diffuse into the laminated silicon wafer to form bonding and N+ layers, thereby obtaining a bonding substrate.

[0010] The bonding substrate is thinned to obtain the device substrate.

[0011] Thus, after laminating two single-crystal silicon wafers with a sticky phosphorus source on their back sides together to form a laminated silicon wafer, the laminated silicon wafer is placed in a diffusion furnace for multi-stage heating. This allows the sticky phosphorus source on the laminated silicon wafer to react and generate phosphorus and silicon dioxide, and the phosphorus diffuses into the laminated silicon wafer. Under the action of silicon dioxide and phosphorus diffusion, the two single-crystal silicon wafers form bonding and N+ layers, resulting in a bonding substrate. Furthermore, thinning the bonding substrate yields the device substrate. This one-step silicon-silicon bonding and diffusion process greatly simplifies the process flow. Moreover, when phosphorus diffuses into the laminated silicon wafer, it diffuses from the middle interlayer, allowing the N- layer thickness of the substrate to reach an ideal state. This ensures that the final device substrate meets both the performance requirements and thickness requirements of the product device.

[0012] In one possible implementation, the viscous phosphorus source comprises a phosphorus-containing compound, a viscous compound, and purified water, wherein the phosphorus-containing compound is decomposable and free of metal ions, and the viscous compound is viscous and volatile.

[0013] Thus, the viscous compound can increase the viscosity of the phosphorus source, increase the phosphorus source content coated on the single crystal silicon wafer, and the volatile viscous compound can be completely volatilized when heated in the subsequent diffusion furnace, avoiding the residue from affecting the substrate performance, and to a certain extent ensuring the performance of the device substrate.

[0014] Furthermore, the decomposability of phosphorus-containing compounds can promote phosphorus formation and increase the substrate fabrication rate. Since phosphorus-containing compounds contain no metal ions, they can, to some extent, avoid the impact of metal ion doping on the substrate structure and performance, thus contributing to improved performance of the final substrate.

[0015] In one possible implementation, the step of heating and diffusing the laminated silicon wafer in a multi-stage heating manner to cause the viscous phosphorus source to react and generate phosphorus and silicon dioxide, and to diffuse phosphorus into the laminated silicon wafer to form bonding and N+ layers, thereby obtaining a bonded substrate, includes:

[0016] The laminated silicon wafer is heated to a first temperature and heated for a first duration, causing the phosphorus-containing compound to release water and a phosphorus-free compound, thereby generating a phosphoric acid-containing mixture at the contact point of the two monocrystalline silicon wafers of the laminated silicon wafer.

[0017] The laminated silicon wafer is heated at a second temperature and heated for a second duration to allow the adhesive compound coated on the laminated silicon wafer to completely evaporate; wherein the first temperature is lower than the second temperature.

[0018] The laminated silicon wafer is heated at a third temperature and heated for a third duration, so that the products of the phosphoric acid mixture decompose into react with the single crystal silicon wafer to obtain phosphorus and silicon dioxide, and the phosphorus diffuses into the single crystal silicon wafer to form a bonding and N+ layer between the two single crystal silicon wafers to obtain a bonding substrate; wherein the third temperature is greater than the second temperature.

[0019] Thus, the laminated silicon wafer is heated at a first temperature and for a first duration, causing the phosphorus-containing compounds on the wafer to release water and phosphorus-free compounds, generating a phosphoric acid mixture to prepare for subsequent bonding and diffusion. The laminated silicon wafer is then heated at a second temperature and for a second duration, causing the sticky compounds on the wafer to completely volatilize, preventing any residue from affecting subsequent bonding and diffusion. The laminated silicon wafer is then heated at a third temperature and for a third duration, causing the products from the decomposition of the phosphoric acid mixture to react with the single-crystal silicon wafer to produce phosphorus and silicon dioxide. The phosphorus then diffuses into the single-crystal silicon wafer, forming a bonding layer and an N+ layer between the two single-crystal silicon wafers, resulting in a bonding substrate. This achieves silicon-silicon bonding and diffusion in a single step.

[0020] In one possible implementation, the volume ratio of the viscous compound in the viscous phosphorus source to the purified water is 20% to 80%.

[0021] Thus, the volume ratio of the viscous compound to pure water determines the viscosity of the viscous phosphorus source. By adjusting the viscosity of the phosphorus source, the total amount of source on the laminated silicon wafer can be controlled, thereby adapting to the substrate thickness and performance requirements of different devices and improving adaptability.

[0022] In one possible implementation, the second temperature is lower than the boiling point of the viscous compound.

[0023] In this way, by controlling the second temperature below the boiling point, the high-temperature carbonization of the viscous compound is avoided, and the viscous compound is allowed to completely volatilize. To a certain extent, this can prevent the residual viscous compound and its related products from affecting subsequent bonding and diffusion.

[0024] In one possible implementation, the first temperature is 130°C to 140°C, and the second temperature is 150°C to 190°C.

[0025] Thus, controlling the first temperature at 130℃~140℃ allows the phosphorus-containing compounds to react fully, releasing as much water and phosphorus-free compounds as possible. Controlling the second temperature at 150℃~190℃ allows the viscous compounds to volatilize as much as possible, avoiding residues and carbonization. At the same time, it allows the diffusion furnace to gradually increase the temperature from the first temperature to the second temperature, simplifying the bonding diffusion process.

[0026] In one possible implementation, the phosphorus-containing compound includes either ammonium dihydrogen phosphate or diammonium hydrogen phosphate.

[0027] Thus, both ammonium dihydrogen phosphate and diammonium hydrogen phosphate can simultaneously meet the requirements of being decomposable and free of metal ions, and are reasonably priced and readily available.

[0028] In one possible implementation, the viscous compound comprises ethylene glycol.

[0029] Thus, ethylene glycol, with its volatility and viscosity, can meet the requirements of viscous compounds.

[0030] In one possible implementation, the thickness of the viscous phosphorus source coated on the monocrystalline silicon wafer is 0.5 μm to 3 μm.

[0031] Thus, by adjusting the thickness of the viscous phosphorus source coated on the monocrystalline silicon wafer, the adaptability can be improved to meet the different thickness requirements of the substrate N-layer.

[0032] Secondly, embodiments of this application provide a semiconductor substrate manufactured using a semiconductor substrate fabrication method as described in any possible implementation of the first aspect.

[0033] Furthermore, the technical effects of the semiconductor substrate described in the second aspect can be referred to the technical effects of the semiconductor substrate fabrication method described in any implementation of the first aspect, and will not be repeated here. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A schematic flowchart of a method for fabricating a semiconductor substrate provided in an embodiment of this application is shown.

[0036] Figure 2 A schematic diagram of the bonding substrate provided in an embodiment of this application is shown.

[0037] Figure 3 A schematic diagram of the structure of the device substrate provided in an embodiment of this application is shown.

[0038] Figure 4 A schematic diagram of the structure of the laminated silicon wafer provided in an embodiment of this application is shown.

[0039] Figure 5 It shows Figure 1 A flowchart illustrating some sub-steps of step S15.

[0040] Explanation of reference numerals in the attached figures: 100-Laminated silicon wafer; 10-Single crystal silicon wafer; 20-Phosphorus source layer; 30-Binding substrate; 40-Device substrate; 50-N-layer; 60-N+ layer. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0042] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0043] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] Currently, the methods for obtaining semiconductor substrates typically include: (i) triple diffusion; (2) other bonding methods; and (3) directly purchasing epitaxial wafers.

[0045] Triple diffusion, which includes phosphorus pre-diffusion, phosphorus re-diffusion, and single-sided grinding to remove the diffusion layer, can create the required N- and N+ layers for the substrate. However, the substrate (also known as a silicon wafer) obtained by triple diffusion is thin, making it unusable in subsequent processing or resulting in a high breakage rate. To achieve the required substrate thickness, the N-layer thickness must be increased, leading to higher resistivity and impacting product performance.

[0046] Other bonding methods for silicon-silicon bonding require two clean, flat silicon wafers that can be connected to each other through surface chemical bonds under certain conditions. These methods typically use polished silicon wafer interfaces, making the manufacturing process complex. Furthermore, if doping of the bonding interface is also required, complex processes such as pre-expansion or implantation are necessary beforehand.

[0047] However, directly purchasing epitaxial wafers for processing presents a high cost problem.

[0048] Based on the above considerations, this application provides a method for fabricating a semiconductor substrate, which can greatly simplify the process flow and produce a semiconductor substrate that can meet both the performance requirements of the product device and the thickness requirements.

[0049] In one possible implementation, a method for fabricating a semiconductor substrate is provided, referring to... Figure 1 This may include the following steps.

[0050] S11, a layer of sticky phosphorus source is coated on the back of a single crystal silicon wafer.

[0051] S13, two single-crystal silicon wafers coated with a sticky phosphorus source are pressed together in a back-to-back manner to obtain a laminated silicon wafer.

[0052] S15, the laminated silicon wafer is placed in a diffusion furnace and heated and diffused in a multi-stage heating manner to make the viscous phosphorus source react to generate phosphorus and silicon dioxide, and to make the phosphorus diffuse into the laminated silicon wafer to form bonding and N+ layers, thus obtaining a bonding substrate.

[0053] S17, the bonding substrate is thinned to obtain the device substrate.

[0054] Both the bonding substrate 30 and the device substrate 40 include an N- layer 50 and an N+ layer 60. The structure of the bonding substrate 30 can be as follows: Figure 2 As shown, the structure of the device substrate 40 can be as follows: Figure 3 As shown.

[0055] The back side can be any rough surface of the monocrystalline silicon wafer 10, and the structure of the laminated silicon wafer 100 can be as follows: Figure 4 As shown, the laminated silicon wafer 100 includes a single-crystal silicon wafer 10 and a phosphorus source layer 20 between the layers of the single-crystal silicon wafer 10. The device substrate 40 can be a diode substrate, a MOSFET substrate, a thyristor substrate, etc. Furthermore, only heating is required in step S15.

[0056] It should be noted that the back side of the single-crystal silicon wafer 10 in S11 is rough, that is, the single-crystal silicon wafer 10 at this time is a silicon wafer that has not undergone polishing or other processes.

[0057] Due to the characteristics of phosphorus sources, after two monocrystalline silicon wafers 10 with adhesive phosphorus sources coated on their back sides are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100, the laminated silicon wafer 100 is placed in a diffusion furnace for multi-stage heating, which causes the adhesive phosphorus sources on the laminated silicon wafer 100 to undergo a chemical reaction, generating phosphorus and silicon dioxide at the contact points of the two monocrystalline silicon wafers 10 in the laminated silicon wafer 100.

[0058] At high temperatures, phosphorus atoms diffuse from the gas into the laminated silicon wafer 100, specifically from the contact area between the two single-crystal silicon wafers 10. This diffusion of phosphorus and silicon dioxide results in the formation of a bonding layer and an N+ layer 60 between the two single-crystal silicon wafers 10, thus obtaining a bonding substrate 30. Further thinning of the bonding substrate 30 yields the device substrate 40.

[0059] This allows for one-step silicon bonding and diffusion, greatly simplifying the substrate fabrication process. Furthermore, when phosphorus diffuses into the laminated silicon wafer 100, it diffuses from the middle interlayer, which allows the N-layer 50 thickness of the substrate to reach an ideal state as much as possible. This ensures that the final device substrate 40 meets both the performance requirements and thickness requirements of the product device.

[0060] To avoid unnecessary impurities in the resulting bonding substrate 30 and device substrate 40, and to achieve bonding and diffusion in a single step, strict requirements are placed on the setting of the viscous phosphorus source. In one possible embodiment, the viscous phosphorus source may include a phosphorus-containing compound, a viscous compound, and pure water. The phosphorus-containing compound is decomposable and free of metal ions, while the viscous compound is viscous and volatile.

[0061] A viscous phosphorus source is a solution made by dissolving a pure phosphorus-containing compound without metal ions in pure water and adding a certain amount of viscous compound.

[0062] The viscosity of the viscous phosphorus source is affected by the viscosity of the viscous phosphorus source, which in turn affects the amount of viscous phosphorus source coated on the monocrystalline silicon wafer 10. For example, the higher the viscosity, the greater the amount of viscous phosphorus source coated on the monocrystalline silicon wafer 10.

[0063] The viscosity of the phosphorus source is increased by the viscosity of the viscous compound, thereby increasing the phosphorus source content coated on the single-crystal silicon wafer 10. Due to the volatility of the viscous compound, it can be completely volatilized during subsequent diffusion furnace heating, avoiding the impact of residual viscous compound on the substrate performance and ensuring the performance of the device substrate 40 to a certain extent.

[0064] Furthermore, the decomposability of phosphorus-containing compounds can rapidly promote phosphorus formation, thereby increasing the substrate fabrication rate. Since phosphorus-containing compounds contain no metal ions, there is no metal ion doping that could affect the substrate structure and performance, thus contributing to improved performance of the final substrate.

[0065] The choice of viscous compound can be flexible; for example, it can be ethylene glycol or isopropyl ketone. In this embodiment, no specific limitation is made.

[0066] The phosphorus-containing compound can be flexibly selected, for example, it can be, but is not limited to, any one of: ammonium dihydrogen phosphate (NH4H2PO4) and diammonium hydrogen phosphate ((NH4)2HPO4). In this embodiment, no specific limitation is made.

[0067] In a viscous phosphorus source, the content of phosphorus-containing compounds, viscous compounds, and purified water affects the viscosity of the viscous compounds and the total amount of phosphorus source coated on the single-crystal silicon wafer 10, which in turn affects the thickness of the N+ layer 60 in the final bonding substrate 30 and device substrate 40. Therefore, the content of phosphorus-containing compounds, viscous compounds, and purified water in the viscous phosphorus source can be adjusted according to requirements.

[0068] In one possible implementation, the volume ratio between the viscous compound and pure water in the viscous phosphorus source can be 20% to 80%.

[0069] Furthermore, the resistivity of the pure water can be greater than 18 MΩ·CM, meaning that the water in the viscous phosphorus source is ultrapure water. This avoids the introduction of other substances or ions into the viscous phosphorus source, reducing the interference and impact of impurities.

[0070] In order to make the viscous phosphorus source have good viscosity without being too viscous, in one possible embodiment, the viscosity range of the viscous phosphorus source can be 1 mPa·s to 25 mPa·s.

[0071] By controlling the volume ratio of viscous compound and pure water in the viscous phosphorus source to 20% to 80%, the viscosity range of the viscous phosphorus source can be controlled between 1 mPa.s and 25 mPa.s. This avoids insufficient viscosity or excessive viscosity of the viscous phosphorus source and can adapt to the needs of different products and devices.

[0072] In addition, in practical scenarios, the volume ratio between the viscous compound and pure water in the viscous phosphorus source can be adjusted according to the performance requirements of the product device to adjust the viscosity of the viscous phosphorus source, thereby controlling the total amount of source on the laminated silicon wafer 100, so as to adapt to the thickness and performance requirements of the N-layer 50 and N+ layer 60 of the substrate of the product device.

[0073] Furthermore, in step S11, the thickness of the film formed by the viscous phosphorus source coated on each single-crystal silicon wafer 10 can be 0.5 μm to 3 μm.

[0074] The thicker the film formed by the viscous phosphorus source coated on the single-crystal silicon wafer 10, the more phosphorus and silicon dioxide are generated in the subsequent heating diffusion (i.e., step S15), the larger the area of ​​phosphorus diffusion forming the N+ layer 60, and the greater the thickness of the N+ layer 60. Therefore, an appropriate thickness can be selected according to the requirements of the N- layer 50 and the N+ layer 60 of the substrate.

[0075] For example, if the product requires a relatively large thickness of the N-layer on the substrate, the thickness of the film formed by the viscous phosphorus source coated on each single-crystal silicon wafer can be 0.5 μm. If the product requires a relatively small thickness of the N-layer on the substrate, the thickness of the film formed by the viscous phosphorus source coated on each single-crystal silicon wafer can be 3 μm. If the product requires a moderate thickness of the N-layer on the substrate, the thickness of the film formed by the viscous phosphorus source coated on each single-crystal silicon wafer can be 2 μm.

[0076] By limiting the thickness of the film formed by the viscous phosphorus source coated on each single-crystal silicon wafer, the bonding and diffusion effect is avoided if the source film is too thin, and the phosphorus source is wasted if the source film is too thick.

[0077] In step S13, in order to compact the two single-crystal silicon wafers, a fixing device can be used to fix or clamp the stacked silicon wafers without damaging the structure of the stacked silicon wafers, and then place them into the diffusion furnace in a fixed state.

[0078] For step S15, as one implementation method, refer to Figure 5 This can be further implemented as follows:

[0079] S151, the laminated silicon wafer is heated to a first temperature and heated for a first duration, causing the phosphorus-containing compound to release water and a phosphorus-free compound, thereby generating a phosphoric acid-containing mixture at the contact point of the two monocrystalline silicon wafers of the laminated silicon wafer.

[0080] S152, the laminated silicon wafer is heated at a second temperature and heated for a second duration to allow the adhesive compound coated on the laminated silicon wafer to completely evaporate.

[0081] S153, the laminated silicon wafer is heated at a third temperature and heated for a third duration, so that the products of the phosphoric acid mixture decompose and react with the single crystal silicon wafer to obtain phosphorus, and the phosphorus diffuses into the single crystal silicon wafer to form a bonding and N+ layer between the two single crystal silicon wafers, thus obtaining a bonding substrate.

[0082] The first temperature is lower than the second temperature, and the third temperature is higher than the second temperature.

[0083] In the first heating stage, the laminated silicon wafer 100 is heated at a first temperature and for a first duration, causing the phosphorus-containing compound on the laminated silicon wafer 100 to release water and phosphorus-free compound, generating a phosphoric acid-containing mixture, in preparation for subsequent bonding and diffusion.

[0084] In the second heating stage, the laminated silicon wafer 100 is heated at a second temperature and for a second time to completely volatilize the sticky compounds on the silicon wafer, so as to avoid the sticky compound residue affecting the subsequent bonding diffusion.

[0085] In the third heating stage, the stacked silicon wafer 100 is heated at a third temperature and for a third duration, so that the products of the phosphoric acid mixture decompose and react with the single crystal silicon wafer 10 to obtain phosphorus and silicon dioxide, and the phosphorus diffuses into the single crystal silicon wafer 10 to form a bonding and N+ layer 60 between the two single crystal silicon wafers 10, thus obtaining a bonding substrate 30.

[0086] In the third stage, the chemical reaction that yields phosphorus and silicon dioxide can be represented as: P2O5 + Si → P + SiO2. Therefore, while silicon dioxide and phosphorus are being generated, phosphorus diffuses into the back side of the single-crystal silicon wafer 10, forming a bond and an N+ layer 60 between the two single-crystal silicon wafers 10.

[0087] It should be noted that SiO2 is an atomic compound, with each silicon atom bonded to four oxygen atoms, and each oxygen atom bonded to two silicon atoms. The smallest ring in the bonded crystal consists of 12 atoms, namely 6 silicon atoms and 6 oxygen atoms. Each silicon atom is shared by 12 rings, and the ratio of silicon to oxygen atoms in the bonded crystal is 1:2.

[0088] In steps S151 to S153 above, since the first temperature is lower than the second temperature and the third temperature is higher than the second temperature, the production personnel only need to control the diffusion furnace to run a gradually increasing temperature program and set the heating time of each heating stage to achieve silicon-silicon bonding and diffusion in one step, and obtain the bonding substrate in one step.

[0089] It should be noted that the second temperature is lower than the boiling point of the viscous compound.

[0090] By controlling the second temperature below the boiling point, the high-temperature carbonization of the viscous compound is avoided, and the viscous compound is allowed to completely volatilize. To a certain extent, this can prevent the residual viscous compound and its related products from affecting subsequent bonding and diffusion.

[0091] The heating temperature of the laminated silicon wafer 100 in each stage of the diffusion furnace can vary depending on the composition of the viscous phosphorus source. That is, the specific value of the first temperature can change with the phosphorus-containing compound, and similarly, the specific value of the second temperature can also change with the viscous compound. The third temperature is the temperature corresponding to the diffusion process, which usually does not change and will not be described further in this embodiment.

[0092] It should be understood that when the temperature required for the selected phosphorus-containing compound to decompose and release water and phosphorus-free compounds is greater than the volatilization temperature of the selected viscous compound, that is, when the first temperature is greater than the second temperature, the second temperature can be used first to completely volatilize the viscous compound, and then the temperature can be raised to the first temperature to decompose the phosphorus-containing compound and release water and phosphorus-free compounds.

[0093] When the phosphorus-containing compound is ammonium dihydrogen phosphate (NH4H2PO4) and the viscous compound is ethylene glycol (CH2OH)2, the first temperature can be 130℃~140℃, the second temperature can be 150℃~190℃, and the third temperature can be 1260℃~1280℃. The first time duration can be 10min~60min, the second time duration can be 10min~60min, and the third time duration can be 10h~100h.

[0094] The value of the third duration can be adjusted according to the requirements of the diffusion depth.

[0095] In the first stage, the diffusion furnace is heated to 130℃~140℃ and held at that temperature for 10min~60min, causing the ammonium dihydrogen phosphate in the viscous phosphorus source on the laminated silicon wafer 100 to release ammonia (a phosphorus-free compound) and water, generating a mixture of ammonium metaphosphate and phosphoric acid (i.e., a phosphoric acid compound). The mixture of ammonium metaphosphate and phosphoric acid is located at the contact position of the two monocrystalline silicon wafers 10.

[0096] In the second stage, the diffusion furnace is heated to 150℃~190℃ and kept at that temperature for 10min~60min to allow the ethylene glycol in the viscous phosphorus source coated on the laminated silicon wafer 100 to completely evaporate.

[0097] In the third stage, the diffusion furnace is heated to 1260℃~1280℃ and kept at a constant temperature for 10h~100h. This allows the mixture of ammonium phosphate and phosphoric acid to decompose into P2O5, which then reacts with silicon (monocrystalline silicon wafer 10) in the process of "P2O5+Si---P+SiO2". As silicon dioxide is generated, the generated phosphorus diffuses into the silicon wafer, forming a bond between the two monocrystalline silicon wafers 10.

[0098] After step S15, the uncoated source surfaces of the bonded silicon wafers are easily separated, while the coated source surfaces are bonded together, thus achieving the diffusion of phosphorus in the intermediate interlayer and forming the N+ layer 60, thereby obtaining the ideal thicknesses of the N- layer 50 and the N+ layer 60.

[0099] In step S17, any thinning process can be used for thinning, which will not be described in detail in this embodiment.

[0100] After obtaining the device substrate 40, different types of impurities can be doped into the N- layer 50 or N+ layer 60 of the device substrate 40 (i.e., the device can be modulated by ion implantation, diffusion carrying source, etc. to achieve N-type or P-type doping) to fabricate the device with the required electrical characteristics.

[0101] Taking diodes as an example, P-type impurities of a certain concentration and depth can be diffused into the N- layer, and then the N+ layer can be thinned to complete the grinding of the auxiliary surface. This achieves the thin-film processing required for the device while also achieving high-concentration doping on the back side.

[0102] Compared with traditional substrate fabrication methods, the semiconductor substrate fabrication method provided in this application completes silicon-silicon bonding and diffusion in one step by coating a sticky phosphorus source onto a single-crystal silicon wafer, pressing the coated surface together, and then placing it in a diffusion furnace for staged heating. This greatly simplifies the substrate fabrication process and can replace epitaxial wafers, reducing manufacturing costs.

[0103] In practical applications, the applicant fabricated device substrate 40 under the following different conditions.

[0104] Example 1

[0105] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with a volume ratio of ethylene glycol to purified water of 20%, to make a sticky phosphorus source.

[0106] (2) A 0.5 μm thick viscous phosphorus source is coated on the back side of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0107] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 130°C, keep the temperature constant for 10 minutes, and carry out the first stage of heating.

[0108] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 150°C, keep the temperature constant for 10 minutes, and carry out the second stage of heating.

[0109] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1260°C and kept at a constant temperature for 10 hours. The bonding substrate 30 is obtained after the heating is completed.

[0110] (6) Thinning the bonding substrate 30 to obtain the device substrate 40.

[0111] Example 2

[0112] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with the volume ratio of ethylene glycol to purified water being 50%, to make a sticky phosphorus source.

[0113] (2) A 2µm thick viscous phosphorus source is coated on the back side of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0114] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 130°C, keep the temperature constant for 60 minutes, and carry out the first stage of heating.

[0115] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 150°C and keep it at a constant temperature for 60 minutes to carry out the second stage of heating.

[0116] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1260°C and kept at a constant temperature for 100 hours. The bonding substrate 30 is obtained after the heating is completed.

[0117] Example 3

[0118] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with the volume ratio of ethylene glycol to purified water being 50%, to make a sticky phosphorus source.

[0119] (2) A 3µm thick viscous phosphorus source is coated on the back of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0120] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 140°C, keep the temperature constant for 60 minutes, and carry out the first stage of heating.

[0121] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 190°C and keep it at a constant temperature for 60 minutes to carry out the second stage of heating.

[0122] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1280°C and kept at a constant temperature for 10 hours. The bonding substrate 30 is obtained after the heating is completed.

[0123] Example 4

[0124] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with the volume ratio of ethylene glycol to purified water being 80%, to make a sticky phosphorus source.

[0125] (2) A 3µm thick viscous phosphorus source is coated on the back of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0126] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 135°C, keep the temperature constant for 60 minutes, and carry out the first stage of heating.

[0127] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 170°C and keep it at a constant temperature for 60 minutes to carry out the second stage of heating.

[0128] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1270°C and kept at a constant temperature for 50 hours. The bonding substrate 30 is obtained after the heating is completed.

[0129] Example 5

[0130] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with a volume ratio of ethylene glycol to purified water of 40%, to make a sticky phosphorus source.

[0131] (2) A 1µm thick viscous phosphorus source is coated on the back side of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0132] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 135°C, keep the temperature constant for 30 minutes, and carry out the first stage of heating.

[0133] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 170°C and keep it at that temperature for 40 minutes before proceeding with the second stage of heating.

[0134] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1270°C and kept at a constant temperature for 30 hours. The bonding substrate 30 is obtained after the heating is completed.

[0135] Example 6

[0136] (1) Use ammonium dihydrogen phosphate, ethylene glycol and purified water, with the volume ratio of ethylene glycol to purified water being 60%, to make a sticky phosphorus source.

[0137] (2) A viscous phosphorus source with a thickness of 2.5 μm is coated on the back side of each of the two single-crystal silicon wafers 10, and the two coated single-crystal silicon wafers 10 are pressed together in a back-to-back manner to obtain a laminated silicon wafer 100.

[0138] (3) Place the laminated silicon wafer 100 into the diffusion furnace, control the temperature of the diffusion furnace to 130°C, keep the temperature constant for 40 minutes, and carry out the first stage of heating.

[0139] (4) After the first stage of heating is completed, control the diffusion furnace to heat up to 160°C and keep it at a constant temperature for 40 minutes to carry out the second stage of heating.

[0140] (5) After the second stage of heating is completed, the diffusion furnace is heated to 1275°C and kept at a constant temperature for 80 hours. After heating is completed, the bonding substrate 30 is obtained.

[0141] Based on the same inventive concept as the above-described semiconductor substrate fabrication method, in one possible embodiment, this application also provides a semiconductor substrate, referring to... Figure 3 The semiconductor substrate includes an N-layer 50 and an N+ layer 60.

[0142] The semiconductor substrate is a device substrate 40 fabricated using any of the possible embodiments of the semiconductor substrate fabrication methods described above.

[0143] The aforementioned semiconductor substrate is fabricated using a semiconductor substrate fabrication method, which involves silicon-silicon bonding and diffusion in a one-step process. This method features low cost and thickness and performance that meet device requirements.

[0144] For details on the specific implementation of semiconductor substrates, please refer to the implementation of semiconductor substrate fabrication methods mentioned above, which will not be repeated here.

[0145] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor substrate, characterized in that, The method includes: A layer of viscous phosphorus source is coated on the back side of a single-crystal silicon wafer; wherein the viscous phosphorus source includes a phosphorus-containing compound, a viscous compound and pure water, the phosphorus-containing compound is decomposable and free of metal ions, and the viscous compound is viscous and volatile. Two single-crystal silicon wafers coated with a sticky phosphorus source are pressed together in a back-to-back manner to obtain a laminated silicon wafer. The laminated silicon wafer is placed in a diffusion furnace and heated at a first temperature for a first duration, so that the phosphorus-containing compound releases water and a phosphorus-free compound, thereby generating a phosphoric acid-containing mixture at the contact point of the two monocrystalline silicon wafers of the laminated silicon wafer. The laminated silicon wafer is heated at a second temperature and heated for a second duration to allow the adhesive compound coated on the laminated silicon wafer to completely evaporate; wherein the first temperature is lower than the second temperature. The laminated silicon wafer is heated at a third temperature and heated for a third duration, so that the products of the phosphoric acid mixture decompose into react with the single crystal silicon wafer to obtain phosphorus and silicon dioxide, and the phosphorus diffuses into the single crystal silicon wafer to form a bonding and N+ layer between the two single crystal silicon wafers to obtain a bonding substrate; wherein the third temperature is higher than the second temperature. The bonding substrate is thinned to obtain the device substrate.

2. The method for fabricating a semiconductor substrate according to claim 1, characterized in that, The volume ratio of the viscous compound in the viscous phosphorus source to the purified water is 20% to 80%.

3. The method for fabricating a semiconductor substrate according to claim 1, characterized in that, The second temperature is lower than the boiling point of the viscous compound.

4. The method for fabricating a semiconductor substrate according to claim 1, characterized in that, The first temperature is 130℃~140℃, and the second temperature is 150℃~190℃.

5. The method for fabricating a semiconductor substrate according to claim 1, characterized in that, The phosphorus-containing compound includes either ammonium dihydrogen phosphate or diammonium hydrogen phosphate.

6. The method for fabricating a semiconductor substrate according to claim 1, characterized in that, The viscous compound includes ethylene glycol.

7. The method for fabricating a semiconductor substrate according to any one of claims 1 to 6, characterized in that, The thickness of the viscous phosphorus source coated on the monocrystalline silicon wafer is 0.5 mm. ~3 .

8. A semiconductor substrate, characterized in that, It is manufactured using the method for fabricating a semiconductor substrate as described in any one of claims 1 to 7.

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