Chip-on-chip memory and logic for genome annotation

Abstract

Memory and logic devices formed in a wafer-on-wafer manner enable high bandwidth transfer of data directly between a memory die and a logic die. A logic die bonded to a memory die via a wafer-on-wafer bonding process can receive a signal indicative of a gene sequence from the memory die and through wafer-on-wafer bonding. The logic die can also perform genome annotation logic operations to attach biological information to the gene sequence. Annotated gene sequences can be provided as output.

Description

Technical Field

[0001] The present disclosure relates generally to memory, and more particularly to apparatus and methods associated with the use of on-wafer memory and logic, such as for genome annotation. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can provide persistent data by saving stored data when not powered and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc.

[0003] Memories are also used as volatile and non-volatile data storage devices for various electronic applications including, but not limited to, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells may be arranged in an array, where the array is used in a memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an apparatus in the form of a system including a memory device and a logic device.

[0005] Figure 2A is a top view of a memory die according to several embodiments of the present disclosure.

[0006] Figure 2B is a top view of a logic wafer according to several embodiments of the present disclosure.

[0007] Figure 2C is a cross section of a portion of a memory wafer bonded to a logic wafer according to several embodiments of the present disclosure.

[0008] Figure 2D A portion of a bonded wafer including memory dies and logic dies after dicing is illustrated according to several embodiments of the present disclosure.

[0009] Figure 3A A circuit diagram illustrating a memory die according to several embodiments of the present disclosure.

[0010] Figure 3B Circuit diagrams illustrating memory bank groups according to several embodiments of the present disclosure.

[0011] Figure 3C A memory bank according to several embodiments of the present disclosure is described.

[0012] Figure 3D A memory bank according to several embodiments of the present disclosure is described.

[0013] Figure 3E Memory tiles according to several embodiments of the present disclosure are described.

[0014] Figure 3F A portion of a memory tile according to several embodiments of the present disclosure is described.

[0015] Figure 3G A portion of a memory tile according to several embodiments of the present disclosure is described.

[0016] Figure 4A is a block diagram of an example of a memory-logic architecture according to several embodiments of the present disclosure.

[0017] Figure 4B yes Figure 4A Block diagram of the first part of the architecture illustrated in .

[0018] Figure 4C yes Figure 4A Block diagram of the second part of the architecture illustrated in .

[0019] Figure 5 is a flow chart corresponding to a method for annotating a genomic sequence using a memory die and a logic die, according to several embodiments of the present disclosure.

[0020] Figure 6 is a flow chart corresponding to a method for performing high data volume operations using a memory die and a logic die according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The present disclosure includes devices and methods related to memory and logic formed in a wafer-on-wafer manner and routing signals between memory dies and logic dies for performing logic operations (e.g., annotating genomic sequences). Logic operations (e.g., arithmetic, flow control, and combinatorial operations) may consist of basic logic operations such as AND, OR, NOR, XOR, etc. and are typically performed on a logic die. In contrast, memory operations (e.g., load, store, etc.) are typically performed on a memory die. Inexpensive and energy-efficient logic devices have been proposed. Such devices may benefit from being tightly coupled to a memory device. The logic device may be an artificial intelligence (AI) accelerator, such as a deep learning accelerator (DLA).

[0022] AI refers to the ability to improve a machine, for example, by "learning" (e.g., by storing patterns and / or examples that can be used to take action at a later time). Deep learning refers to the ability of a device to learn from data provided only as examples. Deep learning may be a subset of AI. Neural networks, as well as other types of networks, may be classified as deep learning. Low-power, inexpensive designed deep learning accelerators may be implemented in Internet of Things (IOT) devices. DLA may process and make intelligent decisions at runtime. Memory devices including edge DLA may also be deployed in remote locations without the need for cloud or offload capabilities. Deep learning may be implemented using multiplication operations.

[0023] A three-dimensional integrated circuit (3D IC) is a metal-oxide semiconductor (MOS) IC that is fabricated by stacking semiconductor wafers or dies and interconnecting them vertically using, for example, through-silicon vias (TSVs) or metal connections to act as a single device to achieve performance improvements at reduced power and a smaller footprint compared to conventional two-dimensional processes. Examples of 3D ICs include hybrid memory cubes (HMCs) and high-bandwidth memory (HBM), among others.

[0024] Memory devices that use 3D ICs to implement coupled memory dies and logic dies can benefit from efficient data transfer between the memory die and the logic die. Transferring data from the memory die to the logic die can include transferring data from the memory die to a global data bus and transferring data from the global data bus to the logic die. However, transferring data from the global data bus to the logic die may be inefficient.

[0025] Methods for manufacturing 3D ICs may include monolithic die-on-die, die-on-wafer, chip-on-wafer, and wafer-on-wafer. Monolithic manufacturing of 3D ICs involves providing a first layer of circuitry and / or electronic components, depositing semiconductor materials (e.g., silicon) on the first layer, and forming a second layer of circuitry / components on the first layer and / or electronic components by processing the deposited semiconductive materials. Die-on-die, die-on-wafer, and chip-on-wafer processes include cutting one or both of the wafers before bonding. This may require alignment and bonding of individual components formed on different wafers. In contrast, the wafer-on-wafer method forms 3D ICs by constructing electronic components on two separate semiconductor wafers that are then aligned, bonded, and cut to form 3DICs. Although the processes for manufacturing 3D ICs are useful, they may present various challenges. For example, the process may require expensive and time-consuming alignment and bonding operations.

[0026] Aspects of the present disclosure address the above and other shortcomings. For example, at least one embodiment of the present disclosure may provide high bandwidth via a wide bus between a memory die and a logic die bonded by a wafer-on-wafer bonding process. Although a wide bus may provide high bandwidth between a memory die and a logic die, the memory die may also operate according to a standardized input / output interface with a host, thereby providing flexibility in using the memory. Various embodiments may be useful for artificial intelligence accelerators, machine learning, graphic analysis, databases, fluid dynamics or other memory bandwidth intensive applications, image processing, language processing, virtual or augmented implementation applications, genomics, proteomics, and the like.

[0027] Compared to some previous approaches, embodiments of the present disclosure can provide greater bandwidth from memory within a fixed power envelope. For example, drones typically have limited power and available space. At least one embodiment of the present disclosure can provide improved inference based on video obtained by the drone within the limited power and space envelope. Another example implementation is to provide power and thermal mitigation relative to multiple standard memory packages (e.g., Graphics Double Data Rate 6 (GDDR6) packages) on a common circuit board. Other advantages include improved high-end performance with reduced power consumption in a relatively inexpensive package (e.g., more sensors can be added to an autonomous vehicle while still operating within a given power envelope).

[0028] Genome annotation may refer to the assignment of possible roles or functions to a string of nucleotides by using multiple lines of evidence to identify regions of interest. Genome annotation may consist of three main steps. The first step may be to identify portions of the genome that do not encode proteins, often called introns. The second step may be to identify or predict functional elements of the genome. The third step may be to attach biological information to the identified elements.

[0029] Certain aspects of genome annotation may be referred to as structure-based annotation. Structural annotation may be related to identifying where a region of interest (usually a gene) is located in a gene sequence or genome and what it is made of. For example, structural annotation may identify the location of exons and introns, the location of untranslated regions, the location of open reading frames, the location of any regulatory motifs, or the overall gene structure of a specific portion of a gene sequence. Structural annotation may be beneficial because two genes with similar structures provide good indications that the two genes may have similar functions.

[0030] Other aspects of genome annotation may be referred to as functional annotation or identifying the function of the resulting protein or peptide. Predictions may be made about the function of annotated gene sequences based on known functions of similar proteins or peptides. Portions of annotated gene sequences may be searched against known sequences with known functions.

[0031] An example implementation of one or more embodiments of the present disclosure is in a data center. Embodiments of the present disclosure can improve those efficiencies of various applications. Logic and memory dies formed in a wafer-on-wafer manner can be combined in a network (e.g., a mesh network) and scaled up to execute various applications. Examples include Type 2 accelerator cards that run training applications (e.g., real-time business center data, operations on databases, etc.) and other examples. The efficiency of processes running in a data center is important for cost and energy efficiency. A compute express link (CXL) card can incorporate several logic and memory dies bonded in a wafer-on-wafer manner.

[0032] An example implementation of one or more embodiments of the present disclosure is in a 5G infrastructure. Smaller sized antennas with improved capabilities (e.g., improved antenna alignment or steering, network intrusion detection, low bandwidth links among 5G towers) may be provided to enable group intelligence and status (e.g., detecting multiple intrusions across towers as evidence of a concentrated attack), improving mobility by passing inferred status of mobile devices between 5G towers over the network, etc. For example, 5G towers may be equipped with cameras for additional municipal infrastructure awareness applications. Rather than using 5G bandwidth to transmit camera data over the network, camera data is processed locally via memory die and logic die bonded in a wafer-on-wafer manner to perform municipal infrastructure awareness applications without degrading the performance of the 5G antenna. Such embodiments may also provide a lower power solution to handle camera data compared to using a separate dedicated DLA to handle camera data. For example, the DLA may use 3 watts, the memory may use 2 watts, and the processor may use 1 watt to perform analysis on the camera data. However, according to the present disclosure, a memory die and a logic die (eg, a DLA in this example) bonded in a wafer-on-wafer manner can operate at 3 watts and replace separate memory and accelerator devices, saving 2 watts in this example.

[0033] An example implementation of one or more embodiments of the present disclosure is in providing privacy for speech recognition applications. Typically, according to some previous approaches, speech recognition is performed by sending data from a local sensor to a server via a network (e.g., a public network), where powerful processing can be performed to provide speech recognition functionality. However, according to at least one embodiment of the present disclosure, a greater bandwidth provided between a memory die and a logic die (e.g., a speech recognition die in this example) can allow speech recognition (or at least a portion thereof) to be performed with greater locality to the sensor, thereby potentially avoiding exposure via the network.

[0034] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 202 refers to Figure 2A "02" in , and similar components in Figure 4B 402. Similar elements within the figures may be referred to by hyphens and additional numbers or letters. Figure 2A 216-1, 216-2 in FIG. It should be understood that the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, it should be understood that the proportions and relative scales of the elements provided in the figures are intended to illustrate certain embodiments of the present invention and should not be considered as intended to be limiting.

[0035] Figure 1 1 is a block diagram of an apparatus in the form of a system 100 including a memory die 102 and a logic die 104. In this example, the system 100 includes a memory die 102 and a logic die 104. Figure 1 1. System 100 includes a memory die 102 coupled to a logic die 104 (not explicitly illustrated in the figure). Memory die 102 and logic die 104 may have various interfaces, such as input / output (IO) interface 112 (e.g., for exchanging signals indicating data) and control interface (e.g., for exchanging control signals). System 100 may be part of a personal laptop computer, a desktop computer, a digital camera, a mobile phone, a memory card reader, a server, or a device with Internet of Things (IoT) capabilities, as well as various other types of systems.

[0036] The memory die may include a memory device 106 coupled to a control circuit system 110 and a data path 108 of the memory die 102, which may include one or more memory arrays, memory banks, etc. The logic die 104 may include a logic device 113 and a control circuit system 111 coupled thereto. The logic device 113 may be an artificial intelligence (AI) accelerator, which is also referred to herein as a deep learning accelerator (DLA) as an example. The logic device 113 may be coupled to one or more of the interfaces between the logic die 104 and the memory die 102, and thus to the data path 108 of the memory die 102. As used herein, for example, the memory die 102, the memory device 106, the logic die 104, and / or the logic device 113 may also be individually considered to be a "device."

[0037] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory device 106 may be a DRAM array, an SRAM array, an STT RAM array, a PCRAM array, a TRAM array, an RRAM array, a NAND flash array, a NOR flash array, and / or a 3D cross point array. As an example, memory device 106 may be referred to herein as a DRAM array. Memory device 106 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines).

[0038] Although not explicitly stated, the memory die 102 includes address circuitry to latch address signals provided via a host interface. For example, the host interface may include a physical interface that employs a suitable protocol (e.g., a data bus, an address bus, and a command bus or a combined data / address / command bus). This protocol may be custom or proprietary, or the host interface may employ a standardized protocol, such as a peripheral component interconnect express (PCIe), a Gen-Z interconnect, a cache coherent interconnect for accelerators (CCIX), or the like. The host interface may be coupled to a memory device 106 (e.g., to an array of memory cells on the memory device 106). The address signal is received and decoded by a row decoder and a column decoder to access the memory device 106. Data may be read from the memory device 106 by sensing voltage and / or current changes on a sense line using a sense circuitry. The sense circuitry may be coupled to the memory device 106. Each memory device 106 and the corresponding sense circuitry may constitute a memory bank of the memory die 102. For example, the sense circuitry may include a sense amplifier that may read and latch a page (e.g., a row) of data from the memory device 106. IO circuitry 112 may be used for bidirectional data communication with logic die 104 along data path 108. Read / write circuitry is used to write data to or read data from memory device 106. The read / write circuitry may include various drivers, latch circuitry, and the like.

[0039] The control circuit system 110 can decode the signal provided by the host. The signal can be a command provided by the host. These signals can include a chip enable signal, a write enable signal, and an address latch signal for controlling the operation performed on the memory device 106, and the operation includes a data read operation, a data write operation, and a data erase operation. In various embodiments, the control circuit system 110 is responsible for executing instructions from the host. The control circuit system 110 may include a state machine, a sequencer, and / or some other type of control circuit system, which can be implemented in the form of hardware, firmware, or software or any combination of the three. In some examples, the host may be a controller external to the memory die 102. For example, the host may be a memory controller coupled to the processing resources of the computing device. Data can be provided to and / or from the logic die 104 via the data lines that couple the logic die 104 to the IO circuit system 112.

[0040] Logic device 104 may include its own control circuitry 111. Control circuitry 111 may control logic device 104. Logic device 113 may be controlled by control circuitry 111. In some embodiments, logic device 113 may also be controlled by control circuitry 110 of memory device 102. For example, control circuitry 110 may provide signaling to row decoders and column decoders to cause data to be transferred from memory array 102 to logic device 113 to provide input to logic die 104 and / or an artificial neural network (ANN) hosted by logic device 113. Control circuitry 110 and / or control circuitry 111 may cause output of logic die 104 and / or logic device 113 to be provided to IO circuitry 112 and / or stored back to memory device 106.

[0041] Logic device 113 may implement an ANN model that may be trained by control circuit system 111 and / or by an external host (not explicitly described). For example, the host and / or control circuit system 111 may train an ANN model that may be provided to logic device 113. Logic device 113 may implement the trained ANN model as directed by control circuit system 111. The ANN may be trained to perform the desired function. In various examples, control circuit system 111 may also control the execution of operations on logic device 113. For example, control circuit system 111 may direct the execution of genome annotation operations and logic operations. For example, genome annotation operations and logic operations may be used by a DLA including an ANN and other implementations of the DLA.

[0042] According to some previous methods, after the memory die 102 is manufactured on the first wafer and the logic die 104 is manufactured on the second wafer, the first wafer and the second wafer may be cut (e.g., cut by a rotating saw blade along the cut lanes of the first wafer and the second wafer) to form the respective dies 102, 104. However, according to at least one embodiment of the present disclosure, after the dies 102, 104 are manufactured on the first wafer and the second wafer, and before cutting, the first wafer and the second wafer may be bonded together by a wafer-on-wafer bonding process. After the wafer-on-wafer bonding process, the dies 102, 104 may be singulated. As used herein, "singulation" refers to separating the bonded units into individual units. For example, a memory wafer may be bonded to a logic wafer in a face-to-face orientation, meaning that both of their respective wafers (substrates) are at the far end of the bond, while the memory die and the logic die are at the near end of the bond. This enables the individual memory die and the logic die to be singulated together into a single package after the memory wafer and the logic wafer are bonded together.

[0043] Figure 2A is a top view of a memory die according to several embodiments of the present disclosure. Figure 2Bis a top view of a logic wafer according to several embodiments of the present disclosure. As used in the present disclosure, the term "wafer" may include, but is not limited to, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. In addition, when reference is made to a "wafer" or "substrate" in the following description, previous process steps may have been used to form regions or junctions in the base semiconductor structure or foundation.

[0044] like Figure 2A to 2B As shown in FIG. 1 , the wafers 214 and 215 may have a circular peripheral edge. The wafers 214 and 215 may include a plurality of dies (e.g., Figure 2A The memory die 202 or Figure 2B 216-1, 216-2). As used herein, the cut lanes 216 may be referred to as saw cut lanes or scribe cut lanes. The cut lanes 216 may be paths along which a tool may cut in order to singulate the die. Prior to cutting, the cut lanes 216 may be etched to a particular depth to help guide the saw blade. Additionally, one or more side marks along the edge of the top of the wafers 214, 215 may be used to align the saw blade prior to cutting. In many cases, and as Figure 2A to 2B As shown in FIG. 2 , dies may be formed on wafers 214 , 215 such that streets 216 are formed in vertical rows and columns.

[0045] A die may include an electronic device. In some embodiments, each die on a particular wafer may be the same type of device. For example, Figure 2A Each die on the wafer 214 illustrated in FIG. 2 may be a memory die 202, and Figure 2B Each die on the wafer 215 illustrated in FIG. 2 may be a logic die 204. As used herein, an electronic device may include a transistor, a capacitor, a diode, a memory device, a processor, other devices, and / or an integrated circuit. Examples of logic die 204 include application specific integrated circuits (ASICs) such as DLAs, radio frequency communication circuits, gene sequencing circuits, gene annotation circuits, video or imaging circuits, audio circuits, sensor circuits, radar circuits, packet routing circuits, intrusion detection circuits, security monitoring circuits, cryptographic circuits, blockchain circuits, smart sensor circuits, 5G communication circuits, and the like.

[0046] Each memory die may include an array of memory cells configured on a die or chip and a local input / output (LIO) line for communicating data on the die or chip. In addition, each memory die may include a transceiver associated with (e.g., coupled to) the LIO line. The transceiver may be configured to selectively enable data to be transferred to one or more devices outside the die or chip. In addition, each memory die may include a memory-to-logic circuit system coupled to the transceiver and configured to be coupled to the logic die via wafer-on-wafer bonding. In some embodiments, more than one of the memory dies shares the memory-to-logic circuit system. In some embodiments, at least one memory-to-logic circuit system is configured to be coupled to the logic die via wafer-on-wafer bonding.

[0047] The test infrastructure may be formed to be associated with the wafers 214, 215 and / or the dies 202, 204. Embodiments of the present disclosure may be implemented without requiring changes to the manufacture and / or use of the test infrastructure. If a test on an individual die 202, 204 indicates that the die is bad, then according to some previous approaches, the die 202, 204 will not be used in an electronic device. However, according to at least one embodiment of the present disclosure, the die 202, 204 may be discarded as appropriate so that the remainder of the wafers 214, 215 may be used. The corresponding die 202, 204 corresponding to the bad memory die 202, 204 may be disabled.

[0048] In some previous methods, after the electronic devices are fabricated on the wafers 214, 215, the wafers 214, 215 may be cut (e.g., by a rotating saw blade along the cut 216). However, according to at least one embodiment of the present disclosure, after the devices are fabricated on the wafers 214, 215, and before cutting, the wafers 214, 215 may be bonded together by a wafer-on-wafer bonding process. After the wafer-on-wafer bonding process, the dies may be singulated. The memory wafer 214 may be bonded to the logic wafer 215 in a face-to-face orientation, meaning that their respective substrates (wafers) are both at the far end of the bond, while the memory die and the logic die are at the near end of the bond.

[0049] In some embodiments, the size of the devices on the first wafer 214 is the same as the size of the devices on the second wafer 215. The scribe lines 216 on the first wafer 214 may be in the same relative positions as the scribe lines 216 on the second wafer 215. This enables the individual memory dies 202 and logic dies 204 to be singulated together into a single package after the wafers 214, 215 are bonded together.

[0050] Although not explicitly stated, in some embodiments, the sizes of the devices on the first wafer 214 and the second wafer 215 are proportionally different. For example, the logic die 204 on the second wafer 215 may have the same footprint as the four memory dies 202 on the first wafer 214. When the wafers 214, 215 are bonded together, the four memory dies 202 and one logic die 204 may be singulated into a single package. As another example, the memory die 202 on the first wafer 214 may have the same footprint as the four logic dies 204 on the second wafer 215. When the wafers 214, 215 are bonded together, the four logic dies 204 and one memory die 202 may be singulated into a single package, which may be referred to as a network-on-wafer package. Embodiments are not limited to a die size ratio of 4:1.

[0051] Embodiments that include differently sized memory dies 202 and logic dies 204 may further benefit from the testing described above. For example, for logic dies 204 that are smaller than the memory dies 202, the dies 202, 204 may be tested and the wafers 214, 215 may be rotated before bonding so that the maximum possible number of known good logic dies 204 are bonded to the known good memory dies 202. Similarly, for memory dies 202 that are smaller than the logic die 204, the dies 202, 204 may be tested and the wafers 214, 215 may be rotated before bonding so that the maximum possible number of known good memory dies 202 are bonded to the known good logic die 204. Different memory dies 214 and logic dies 215 may be mixed and matched to provide the maximum combination of known good memory dies 202 and logic dies 204, regardless of whether the dies 202, 204 are differently sized.

[0052] Whichever wafer 214, 215 includes the smaller devices will have some cuts 216 that are not desired to be cut. Additional connections (e.g., metal layers) may be formed across these cuts 216 because the cuts will not be cut. The additional connections across the cuts 216 may be used to connect multiple individual memory dies 202 or logic dies 204 to each other prior to the wafer-on-wafer bonding process. Such embodiments may thus create a wafer-level network of memory dies 202 or logic dies 204. In at least one embodiment, the first wafer 214 may include multiple networked memory dies 202 forming a wafer-level memory device. For example, the network may be a peer-to-peer network.

[0053] Figure 2C2 is a cross-section of a portion of a memory wafer 214 bonded to a logic wafer 215 according to several embodiments of the present disclosure. The memory wafer 214 may include a plurality of memory dies formed thereon. Each memory die may have a memory device formed thereon. The memory device may include an array of memory cells. The memory wafer 214 includes a memory-to-logic circuitry 222 formed thereon. In some embodiments, each memory die has a discrete memory-to-logic circuitry 222 formed thereon. The memory-to-logic circuitry 222 may be coupled to the array of memory cells. The memory-to-logic circuitry 222 is configured to provide electrical connections for the transfer of data and / or control signals between at least one memory die of the memory wafer 214 and at least one logic die of the logic wafer 215. In at least one embodiment, the memory-to-logic circuitry may include only two additional metal layers in addition to the metal layers typically included with DRAM memory dies.

[0054] The logic wafer 215 may include a plurality of logic dies formed thereon. Each logic die may include a logic device formed thereon. The logic device may include a logic circuit system configured to perform logic operations on data. The logic wafer 215 may include a logic to memory circuit system 224 formed thereon. In some embodiments, each logic die has a discrete logic to memory circuit system 224 formed thereon. The logic to memory circuit system 224 may be coupled to the logic circuit system. The logic to memory circuit system 224 is configured to provide an electrical connection for the transmission of data and / or control signals between at least one logic die of the logic wafer 215 and at least one memory die of the memory wafer 214. The bond 220 is formed between the memory to logic circuit system 222 of the memory wafer 214 and the logic to memory circuit system 224 of the logic wafer 215 in a wafer-on-wafer bonding process. The bond 220 may be referred to herein as a hybrid bond or wafer-on-wafer bonding. The bond 220 may include one or more of a metal bond and a direct dielectric-dielectric bond. Bond 220 enables the transfer of electrical signals between logic-to-memory circuitry 224 and memory-to-logic circuitry 222 .

[0055] Memory to logic circuitry 222 may be configured to transfer signals indicative of data between the memory cell array and logic to memory circuitry 224 via junction 220. Logic to memory circuitry 224 may be configured to transfer signals indicative of data between logic circuitry and memory to logic circuitry 222 via junction 220.

[0056] The memory-to-logic circuitry 222 and / or the junction 220 of the memory wafer 214 may include a bonding pad at a transceiver, which may be associated with a LIO prefetch bus and / or a sense amplifier (sense amplifier / sense amp) strip. In one example, a sense amplifier strip includes 188 LIO connection pairs covering 9 array cores, and 9216 pairs per channel. In another example, a sense amplifier strip includes 288 LIO connection pairs, and 4608 pairs per channel. Embodiments are not limited to these specific examples. The transceiver is described in more detail herein. The interconnect load of the junction 220 may be less than 1.0 femtofarad and 0.5 ohm. In an example implementation, the maximum number of memory rows that can be activated at one time (e.g., 32 rows) can be activated and a signal indicating data is transmitted to the corresponding logic die of the logic wafer 215 via the junction 220. The memory-to-logic circuitry 222 and / or the bonding 220 may include at least one power supply and at least one ground connection per transceiver (e.g., sense amplifier stripe). In at least one embodiment, the power supply connections are such that they allow multiple memory rows to be activated at one time. In one example, the wafer-on-wafer bonding provides 256k data connections at a 1.2 micron pitch.

[0057] In some embodiments, the bond 220 may include analog circuitry (e.g., a jumper) without transistors in the path between the memory die 202 and the logic die 204. One die 202, 204 may drive a signal therebetween, and the other die 202, 204 may sink a signal therebetween (e.g., rather than passing a signal between the die 202, 204 via a logic gate). In at least one embodiment, the bond 220 may be formed by a low temperature (e.g., room temperature) bonding process. In some embodiments, the bond 220 may be further processed with an annealing step (e.g., at 300 degrees Celsius).

[0058] Although not explicitly illustrated, in at least one embodiment, a redistribution layer can be formed between memory die 214 and logic die 215. The redistribution layer can enable compatibility of a single memory design to multiple ASIC designs. The redistribution layer can enable memory technology to scale without having to shrink logic design at the same rate as memory technology (e.g., circuitry on memory die 202 can be formed at a different resolution than circuitry on logic die 204 without having to adjust the bond 220 and / or other circuitry between memory die 202 and logic die 204).

[0059] Figure 2DA portion of a bonded wafer including a memory die 202 and a logic die 204 after dicing according to several embodiments of the present disclosure is illustrated. The memory die 202 is illustrated as being bonded to a substrate 218, however, in at least one embodiment, the logic die 204 may be bonded to the substrate 218 instead of the memory die 202. The substrate 218, the memory die 202, the bond 220, and the logic die 204 may form a system 220 configured to perform one or more desired functions, such as an integrated circuit. Although not explicitly illustrated, the substrate 218 may include additional circuitry to operate, control, and / or communicate with the memory die 202, the logic die 204, and / or an off-chip device.

[0060] According to at least one embodiment of the present disclosure, the typical functionality of memory die 202 is unchanged for typical memory operations. However, data may alternatively be transferred directly from memory die 202 to logic die 204 via bond 220, rather than being routed through the typical input / output circuitry of memory die 202. For example, a test mode and / or refresh cycle of memory die 202 may be used to transfer data to and from logic die 204 via bond 220 (e.g., via the LIO of memory die 202). Using refresh cycles for an example existing DRAM memory device, with 8 rows active per bank and a refresh cycle time of 80 nanoseconds (compared to 60 nanoseconds for a single row), the bandwidth would be 443 GBytes / second for 4 parallel banks and 16 nanoseconds of bank sequencing. However, in accordance with at least one embodiment of the present disclosure, using wafer-on-wafer bonding 220, with 32 rows per bank active, for 32 parallel banks, the refresh cycle time can approach 60 nanoseconds, and without bank sequencing, the bandwidth is 5 terabytes / second at 8 watts. This significant bandwidth for sending data from a memory device would overwhelm a typical interface and / or host device. However, certain logic devices, such as DLAs, can be configured to use the data bandwidth via the connection provided by bonding 220. The reduced off-chip movement of data can help reduce the power consumption associated with operating memory in this manner.

[0061] Although not explicitly illustrated, multiple memory dies 202 may be stacked on top of each other via bonds similar to bond 220. Such additional memory die 202 may include a memory die similar to bond 220. Figure 2C2. Alternatively or in addition, TSVs may be used to communicate data between or through the stacked memory dies 202. Bond pads between the stacked memory dies 202 may be at locations replicated on the stacked memory dies 202 in a vertical orientation (as illustrated) so that the stacked memory dies 202 are aligned. The stacked memory dies 202 may be formed by conventional processes or by wafer-on-wafer bonding (between different memory dies) in different embodiments.

[0062] Although not explicitly illustrated, a die (e.g., memory die 202 (as illustrated) or logic die 204) bonded to substrate 218 may have TSVs formed therein to enable connectivity with circuitry external to memory die 202 and logic die 204. TSVs may also be used to provide power and ground contacts. TSVs typically have greater capacitance and greater spacing than contacts provided by wafer-on-wafer bonding and do not have much bandwidth.

[0063] Although not explicitly illustrated, in some embodiments, additional components may be bonded to system 200. For example, a thermal solution component may be bonded to the top of logic die 204 to provide cooling for system 200. The physical close connection between logic die 204 and memory die 202 may generate heat. The thermal solution may help to dissipate heat for system 200.

[0064] Although not explicitly stated, in some embodiments, an additional component (non-volatile memory) may be coupled to the system 200 (e.g., to persistently store the model of the ANN). However, in some embodiments, non-volatile memory is unnecessary because the model may be relatively small and updated frequently.

[0065] Figure 3A A circuit diagram illustrating a memory die 302 according to several embodiments of the present disclosure. The example memory die 302 includes 16 memory banks 328 arranged in a bank group 326 consisting of 4 banks. Each bank group 326 is coupled to a global data bus 330 (e.g., a 256-bit wide bus). The embodiments are not limited to these specific examples. The global data bus 330 can be modeled as a charging / discharging capacitor. The global data bus 330 can conform to a memory standard for sending data from the memory die 302 via an IO bus. However, although Figure 3A Although not explicitly illustrated in FIG. 3 , in accordance with at least one embodiment of the present disclosure, memory die 302 may include additional transceivers for communicating data with the logic die via on-wafer bonding.

[0066] Figure 3BA circuit diagram illustrating a memory bank group 326 according to several embodiments of the present disclosure. The memory bank group 326 may include four memory banks 328 (as illustrated) or another number of banks. Each memory bank 328 may include a respective global input / output (IO) line 332 that is ultimately connected to a global IO bus 330. In this example, the memory bank group 326 is capable of transferring 256 bits at a time.

[0067] Figure 3C Memory banks 328 are illustrated according to several embodiments of the present disclosure. Memory banks 328 include a number of memory tiles 334, each of which includes a corresponding number of LIO lines 336 represented by filled dots on a die or chip. Although only four filled dots are illustrated, the four filled dots may represent any number of LIO lines (e.g., 32 LIO lines). Each tile 334 may include a corresponding array of memory cells configured on a die or chip coupled to sense lines and access lines of the die or chip. The memory cell array may include a number of memory cell rows and a number of memory cell columns (e.g., 1024 x 1024). For example, each tile may include 32 LIO lines 336. In some embodiments, each LIO line 336 may be coupled to a corresponding global IO line 332 (e.g., 32 LIOs may be coupled to 32 global IO lines). Each subset of sense lines is coupled to a corresponding IO line, and the LIO lines 336 in each tile are coupled to a corresponding global IO line 332. In some embodiments, each global IO line 332 is coupled to a corresponding transceiver (e.g., Figure 3C For example, there may be a respective transceiver 338 associated with each tile 334 and coupled to a corresponding global IO line 332. In some embodiments, each LIO line 336 may have a separate transceiver or circuitry connected to a transceiver that multiplexes a certain number of LIO lines 336. This embodiment is Figure 3D In the description.

[0068] The slice block may be coupled to a global I / O line (e.g., an I / O bus). LIO lines 336 may be coupled to global I / O lines 332 for communicating data on a die or chip via global I / O bus 330. Each transceiver may be selectively enabled to transmit off-chip data (e.g., transmitted to a logic die via wafer-on-wafer bonding), rather than to a corresponding global IO line 332. As used herein, the communication of data on a die or chip means that a signal indicating data is transmitted within a memory die or memory chip. As used herein, the communication of data to one or more devices outside a die or chip means that a signal indicating data is transmitted between a memory die or memory chip and a logic die or logic chip. Multiple sense amplifiers may be multiplexed into a single transceiver 338. Each transceiver 338 may be coupled to a corresponding contact with a corresponding logic die via wafer-on-wafer bonding. Wafer-on-wafer bonding provides sufficiently fine spacing control to allow such contacts, which would otherwise be impossible.

[0069] In at least one embodiment, the transceiver 338 may receive an enable / disable command from a corresponding logic die coupled thereto (e.g., instead of receiving a command from a host). In some embodiments, the enable / disable command may be received by multiple transceivers 338 (e.g., the enable / disable command may cause a signal indicating data to be transmitted from a specific row in each memory bank 328 via the corresponding transceiver 338). The control and operation of multiple transceivers 338 is similar to having thousands of memory controllers, except that they transmit data instead of controlling all operations. For example, this operation may be beneficial for applications involving a large number of parallel memory access operations. For an example memory device configured to include 8 kilobit rows, each transceiver 338 may pre-fetch 256 bits of data. Therefore, each transceiver 338 may be bound with 256 bits. In other words, for every 8 kilobits of data stored, at least one embodiment of the present disclosure may transmit 256 bits of data (in this example architecture). In contrast, according to some previous approaches with similar architectures, a typical memory interface (eg, via global IO) would only be able to transfer 256 bits for 4 Gigabits of data stored.

[0070] Figure 3D 328 according to several embodiments of the present disclosure. Figure 3C , the memory bank 328 contains a certain number of memory tiles. Figure 3D The tiles are not individually drawn or listed in FIG. Each tile includes a respective number of LIO lines 336 represented by filled dots. The LIO lines 336 are coupled to respective global IO lines 332 via multiplexers 339. In addition, respective transceivers 338 are coupled to each of the LIO lines 336 so that signals indicating data can be compared. Figure 3CThe embodiments described in

[0044] transfer finer granularity between the memory die and the logic die.

[0071] Each respective transceiver 338 is coupled to a respective LIO line 336 and thereby to the global IO line 332 and the memory to logic circuitry (eg, Figure 2C 2. The transceiver 338 is configured to provide a first electrical connection between the corresponding LIO line 336 and the global IO line 332 and a second electrical connection between the corresponding LIO line 336 and the memory-to-logic circuitry.

[0072] Figure 3E A memory tile 334 is illustrated according to several embodiments of the present disclosure. The memory tile 334 includes memory cells 340 that are programmable to store different states. Each memory cell 340 is programmable to store two states, denoted as logic 0 and logic 1. In some cases, the memory cell 340 is configured to store more than two logic states. The memory cell 340 may include a capacitor to store a charge representing a programmable state; for example, a charged capacitor and an uncharged capacitor may represent two logic states. DRAM architectures may typically use this design, and the capacitors employed may include a dielectric material having a linear electrical polarization property.

[0073] Operations such as reading and writing can be performed on the memory cell 340 by activating or selecting the appropriate access line 342 and sense line 344. Activating or selecting the access line 342 or sense line 344 can include applying a voltage potential to the corresponding line. The access line 342 and sense line 344 can be made of conductive materials. In some examples, the access line 342 and sense line 344 are made of metal (e.g., copper, aluminum, gold, tungsten, etc.). Each row of memory cells 340 is connected to a single access line 342, and each column of memory cells 340 is connected to a single sense line 344. The intersection of the access line 342 and the sense line 344 can be referred to as the address of the memory cell 340.

[0074] In some architectures, the storage component (e.g., capacitor) of cell 340 can be electrically isolated from the digit line by a selection device. Access line 342 can be connected to the selection device and can control the selection device. For example, the selection device can be a transistor, and access line 342 can be connected to the gate of the transistor. Activating access line 342 creates an electrical connection between the capacitor of memory cell 340 and its corresponding sense line 344. Sense line 344 can then be accessed to read or write to memory cell 340.

[0075] Access to memory cells 340 may be controlled by row decoders 346 and column decoders 350. For example, row decoder 346 may receive a row address from memory controller 310 and activate the appropriate access line 342 based on the received row address. Similarly, column decoder 350 receives a column address from memory controller 310 and activates the appropriate sense line 344. Thus, by activating access line 342 and sense line 344, memory cells 340 may be accessed. Column decoder 350 may be coupled to each subset of sense lines 344 and corresponding LIO lines.

[0076] After access, the memory cell 340 may be read or sensed by a sensing component 348. For example, the sensing component 348 may compare the signal (e.g., voltage) of the associated sense line 344 to a reference signal (not shown) in order to determine the stored state of the memory cell 340. If the sense line 344 has a voltage higher than the reference voltage, the sensing component 348 may determine that the stored state in the memory cell 340 is a logical 1, and vice versa. The sensing component 348 may be coupled to the sense lines 344, and each subset of the sense lines 344 is coupled to a respective LIO line 336 for communicating data on a die or chip.

[0077] The sensing component 348 may include various transistors or amplifiers in order to detect and amplify the difference in the signal, which may be referred to as latching. In some cases, the sensing component 348 may include or be referred to as a sense amplifier. The sensing component 348 may represent a stripe of multiple sense amplifiers. The detected logic state of the memory cell 340 may then be output by the column decoder 350 and output to the LIO line 336. In some embodiments, a transceiver may be coupled to each respective sense amplifier and configured to retrieve data from the sense amplifier.

[0078] However, in accordance with at least one embodiment of the present disclosure, memory controller 310 may send a signal to transceiver 338 to selectively route the signal indicating the data off-chip (e.g., to the logic die "to DLA") instead of to the normal IO path (e.g., via LIO line 336). Memory controller 310 may cause transceiver 338 to allow the signal indicating the data to continue on the typical path (e.g., via LIO line 336) or to be sent to the logic die bonded in a wafer-on-wafer manner via the bonds and contacts described herein. The illustrated path from transceiver 338 ("to DLA") is between the memory tile 334 and the corresponding logic die ( Figure 3D336). The embodiments of the present disclosure may retain the functionality and fabrication of a standardized memory interface while allowing the functionality and fabrication of an additional high bandwidth interface from the memory die to the logic die via wafer-on-wafer bonding. The transceiver 338 may extract a signal indicative of data from near the sensing component 348 and transmit it to the logic die. The transceiver 338 may be coupled to a host interface (e.g., via LIO line 336). The transceiver 338 may be configured to select a data output path for the memory array between the host interface and the memory-to-logic circuitry.

[0079] In some embodiments, transceivers 338 may be coupled between column decoders 350 and respective LIO lines 336. Furthermore, in some embodiments, transceivers 338 may be embedded in column decoders 350. Control circuitry (e.g., memory controller 310) coupled to respective transceivers 338 may be configured to send control signals to transceivers 338 to selectively enable communication of data to one or more devices off-die or chip.

[0080] Memory cells 340 may be set or written to by activating associated access lines 342 and sense lines 344. Activating access lines 342 electrically connects the memory cells 340 of the corresponding row to their respective sense lines 344. Memory cells 340 may be written to (logical values ​​may be stored in) by controlling associated sense lines 344 when access lines 342 are activated. Column decoder 350 may accept data to be written to memory cells 340, for example, via LIO lines 336.

[0081] However, according to at least one embodiment of the present disclosure, the transceiver 338 may be configured to enable communication of data from a die to one or more devices off-chip. For example, the control circuit system (e.g., the memory controller 310) may be configured to send a signal to the transceiver 338 to enable communication of data to one or more devices off-die or off-chip by selectively routing a signal indicating data to or from off-chip (e.g., from a logic die) instead of from a normal IO path (e.g., via LIO line 336). The memory controller 310 may cause the transceiver 338 to allow the signal indicating data to be received from a typical path (e.g., via LIO line 336) or from a logic die bonded in a wafer-on-wafer manner via the bonding and contacts described herein. In some embodiments, the communication of data on a die or chip may occur on a first portion of a memory device, and the communication of data to one or more devices off-die or off-chip may occur simultaneously on a second portion of the memory device. The operation of the first portion of the memory device may be independent of the operation of the second portion of the memory device. In some embodiments, the memory device may be a DRAM memory device.

[0082] The memory device may include a multiplexer coupled to the sense line 344. The memory device may also include a transceiver 338 configured to receive a control signal that switches the memory device between a first operating mode and a second operating mode. In the first operating mode, the transceiver 338 may be configured to enable communication of data on a die or chip. In some embodiments, communication of data to one or more devices outside the die or chip may be disabled in the first operating mode. In the second operating mode, the transceiver 338 may be configured to enable communication of data to one or more devices outside the die or chip. In some embodiments, communication of data on the die or chip may be disabled in the second operating mode.

[0083] The memory controller 310 may be configured to operate the transceiver 338 in a first mode to route signals indicative of data from an array external to the memory device via the global IO lines (downstream of the LIO lines 336). The memory controller 310 may be configured to operate the transceiver 338 in a second mode to route signals indicative of data from the array to the logic die via the memory-to-logic circuitry.

[0084] In some embodiments, a signal indicating data corresponding to the transmission of data to one or more devices outside the die or chip travels through an LIO line. The LIO line can couple the memory die to the circuit system outside the memory die (e.g., coupled to the DLA). The signal indicating the data can be transmitted between the memory die and the circuit system outside the memory die through the LIO line. In some embodiments, the bandwidth of the transmission of data to one or more devices outside the die or chip can be greater than the bandwidth of the transmission of data on the die or chip. The bandwidth of the transmission of data to one or more devices outside the die or chip can be greater than the transmission of data on the die or chip, because the transmission of data to one or more devices outside the die or chip can involve more LIO lines than the transmission of data on the die or chip. For example, multiple LIO lines can be used to transmit data outside the chip. However, one LIO line (at a time) can be used to transmit data on the chip. In addition, the sense amplifier of the memory die can be directly coupled to the circuit system outside the memory die. In such embodiments, data can be transmitted off the chip at the speed at which the data leaves the sense amplifier. However, the data transmitted on the chip can travel at the speed of the bandwidth of the global IO.

[0085] In some memory architectures, accessing a memory cell 340 may degrade or damage the stored logic state, and a rewrite or refresh operation may be performed to return the original logic state to the memory cell 340. In DRAM, for example, a capacitor may be partially or completely discharged during a sensing operation, thereby destroying the stored logic state. In addition, activating a single access line 342 may cause all memory cells in a row to discharge; therefore, some or all memory cells 340 in a row may need to be rewritten. Some memory architectures including DRAM may lose their stored states over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become uncharged over time through leakage current, resulting in the loss of stored information. The logic state may be rewritten during a rewrite operation or refreshed during a refresh operation.

[0086] The control circuitry (e.g., memory controller 310) can control the operation (e.g., reading, writing, rewriting, refreshing, etc.) of the memory cells 340 through various components (e.g., row decoders 346, column decoders 350, and sensing components 348). The memory controller 310 can generate row and column address signals in order to activate the desired access lines 342 and sense lines 344. The memory controller 310 can also generate and control various voltage potentials used during the operation of the memory tile 334. For example, the memory controller 310 can operate a selection component to isolate the sense line 344 during sensing (e.g., isolating it from the corresponding capacitor). In general, the amplitude, shape, or duration of the applied voltages discussed herein can be adjusted or changed and can be different for various operations used to operate the memory array. In addition, one, multiple, or all memory cells 340 within a memory tile 334 can be accessed simultaneously; for example, multiple or all cells of the memory tile 334 can be accessed simultaneously during a reset operation in which all memory cells 340 or a group of memory cells 340 are set to a single logic state.

[0087] In some embodiments, an apparatus (e.g., a memory device) may be configured to simultaneously access a first access line in a row of a first tile and a second access line in the same row of a second tile for communication of data. In this context, "same row" means that the rows correspond to each other in position (e.g., if the tiles are positioned side by side, the rows are arranged in a row). It does not necessarily mean that the rows are physically connected to each other. In addition, the memory device may be configured to simultaneously access a first access line in a first row of a first tile and a second access line in a second row of a second tile for communication of data. In this context, the first and second rows do not correspond to each other in position (e.g., if positioned side by side, they are not arranged in a row). The memory device may also be configured to access each tile synchronously or asynchronously. As used herein, asynchronously accessing each tile means accessing different tiles at different times. Asynchronously accessing tiles can avoid larger power spikes that may be caused by accessing a specific amount of tiles at the same time.

[0088] exist Figures 3C to 3E In the embodiment of , the transceiver 338 that controls the transmission of signals indicating data between the memory die and the logic die is located on the memory die. Figures 3F to 3G In an embodiment of the present invention, transceiver 365 is located on the logic die. Transceiver 365 on the logic die can be coupled to logic-to-memory circuitry (e.g., logic-to-memory circuitry 224 illustrated in FIG. 2 ) and to logic circuitry. Transceiver 365 can be configured to select a data output path for a memory array between a host interface of a memory device and a memory-to-logic circuitry (e.g., memory-to-logic circuitry 222 illustrated in FIG. 2 ).

[0089] Figure 3F A portion of a memory tile according to several embodiments of the present disclosure is illustrated. The portion of the tile includes sense amplifiers 363-1, 363-2, ..., 363-N, 363-N+1, 363-N+2, ..., 363-M, 363-M+1, 363-M+2, ..., 363-P and multiplexers 364-1, 364-2, ..., 364-S. The portion of the tile also includes a multiplexer 339 of the memory die. For clarity, Figure 3F It has been simplified to focus on the components and circuitry of the memory die and logic die that are particularly relevant to the present disclosure.

[0090] Multiplexer 339 is distinguished from transceivers 365-1, 365-2, ..., 365-S. Multiplexer 339 can be configured to receive a signal from LIO line 336. Multiplexer 339 selects a portion of LIO line 336. Multiplexer 339 can amplify the signal received from the selected portion of LIO line 336. Multiplexer 339 can also cause the amplified signal to be transmitted via global IO line 332. Multiplexer 339 can also receive a signal from global IO line 332 and reduce the received signal. Multiplexer 339 can further transmit the reduced signal to LIO line 336. Despite having the same name ("multiplexer"), multiplexer 339 is different from multiplexer 364 and has different functions from multiplexer 364.

[0091] Transceivers 365 - 1 , 365 - 2 , . . . , 365 -S may also receive a signal, select a portion of the signal, amplify the portion of the signal, and transmit the amplified signal. However, transceivers 365 - 1 , 365 - 2 , . . . , 365 -S may transmit the amplified signal to a logic die instead of global IO line 332 .

[0092] The memory die may include sense amplifiers 363, multiplexers 364, and multiplexers 339. The memory die may also include LIO lines 336 and global IO lines 332.

[0093] In various examples, wafer-on-wafer bonding 320 may couple the output of sense amplifier 333 to transceiver 365 of the logic die. Transceiver 365 may be controlled by the logic die to cause the output of sense amplifier 363 to be provided to the circuitry of the logic die. For example, transceiver 365-1 may cause the signal output from sense amplifiers 363-1, 363-2, ..., 363-N to be provided to the circuitry of the logic die downstream of transceiver 365-1. Although a single transceiver 365-1 is shown, transceiver 365-1 may represent multiple transceivers such that each of the outputs of sense amplifiers 363-1, 363-2, ..., 363-N is concurrently provided to the circuitry downstream of multiple transceivers of the logic die. Transceiver 365-2 may cause the output of sense amplifiers 363-N-1, 363-N+2, ..., 363-M to be provided to the circuitry of the logic die. Transceiver 365 -S may cause the outputs of sense amplifiers 363 -M+1, 363 -M+2, ..., 363 -P to be provided to the circuitry of the logic die.

[0094] The control circuitry of the logic die (e.g. Figure 1The control circuit system 111 described in association may send a signal to the transceiver 365 to selectively route the signal indicating the data off-chip (e.g., to a logic die). The illustrated path of the transceiver 365 from the sense amplifier 363 to the logic die is a representation of the electrical path between the memory die and the logic die. Embodiments of the present disclosure may preserve the functionality and fabrication of a standardized memory interface while allowing the functionality and fabrication of an additional high-bandwidth interface from the memory die to the logic die via wafer-on-wafer bonding 320.

[0095] In various examples, each of the transceivers 365 may be coupled to a plurality of sense amplifiers 363. For example, transceiver 365-1 may be coupled to sense amplifiers 363-1, 363-2, ..., 363-N. Transceiver 365-2 may be coupled to sense amplifiers 363-N+1, 363-N+2, ..., 363-M. Transceiver 365-S may be coupled to sense amplifiers 363-M+1, 363-M+2, ..., 363-P. In various examples, each of the transceivers 365 may direct a plurality of signals. For example, transceiver 365-1 may simultaneously direct signals provided from sense amplifiers 363-1, 363-2, ..., 363-N. Transceiver 365-2 may simultaneously redirect signals provided from sense amplifiers 363-N+1, 363-N+2, ..., 363-M. Transceiver 365 -S may simultaneously direct signals provided from sense amplifiers 363 -M+1, 363 -M+2, ..., 363 -P.

[0096] The control circuitry of the logic die may cause a signal indicative of the data to be received at the logic die from a typical IO path including LIO line 336 using transceiver 365. The control circuitry of the memory die (e.g., Figure 1 The control circuit system 116 described in association may cause a signal indicating data to be provided by a typical input / output path utilizing LIO line 336, multiplexer 339, and global IO line 332. In various examples, transceiver 365 may route signals concurrently. For example, transceiver 365-1 may route signals between sense amplifiers 363-1, 363-2, ..., 363-N and a logic die concurrently with signal routing performed by transceiver 365-2, ..., and / or transceiver 365-S. In various examples, transceiver 365-1 may route signals between sense amplifiers 363-1, 363-2, ..., 363-N and a logic die concurrently.

[0097] Although not shown, transceivers of the logic die coupled to multiple memory devices may concurrently route signals from the memory die to the logic die. For example, transceiver 365 may route data concurrently with other transceivers coupled to different memory devices. The control circuit system may concurrently activate the rows of multiple memory devices to cause the corresponding sense amplifiers (e.g., including sense amplifier 363) to latch the signals. Transceivers coupled to different memory devices (e.g., including transceiver 365) may concurrently route signals from the sense amplifiers of the memory devices to the logic die. The logic die may concurrently receive a greater number of signals from the memory die via transceiver 365 than may be output via global IO line 332 or global bus. Similarly, the logic die may concurrently provide a greater number of signals to the memory die via transceiver 365 than may be achieved via global IO line 332 or global bus. Transceiver 365 may concurrently route signals with data routing performed by transceivers coupled to different memory banks via wafer-on-wafer bonding 320. In various examples, the memory die can concurrently output data to the global IO line 332 and the transceiver 365. For example, the control circuitry of the memory die can activate the LIO line 336 and the global IO line 332 through the control circuitry of the logic die concurrently with the activation of the transceiver 365 to output the signal to the logic die and through conventional IO circuitry including the global IO line 332.

[0098] In various examples, a signal may be provided to a logic die from a global bus of a memory die. A transceiver of a logic die coupled to a global bus may be configured to route data from a memory die to a logic die. For example, a transceiver of a logic die may be activated to route a signal from a global bus to a logic die. A transceiver configured to route a signal from a global bus to a logic die may be different from a transceiver configured to route a signal from an LIO line 336 to a logic die. Two independent paths may be provided for routing a signal from a memory die to a logic die. A first path may originate from an LIO line 336. A second path may originate from a global bus of a memory die. The first path may be utilized by activating one or more transceivers of a logic die. The second path may be utilized by activating one or more different transceivers of a logic die. In various examples, the number of signals that may be concurrently routed from an LIO line 336 to a logic die may be greater than the number of signals that may be concurrently routed from a global bus to a logic die.

[0099] Figure 3G A portion of a tile is illustrated according to several embodiments of the present disclosure. Figure 3F In contrast, the portion of the tile includes an LIO line 336 coupled to a transceiver 365 .

[0100] exist Figure 3G , sense amplifier 363 may output a plurality of signals. The signals may be output to multiplexer 364. For example, sense amplifiers 363-1, 363-2, ..., 363-N may output a first signal to multiplexer 364-1. Sense amplifiers 363-N+1, 363-N+2, ..., 363-M may output a second signal to multiplexer 364-2, and sense amplifiers 363-M+1, 363-M+2, ..., 363-P may output a signal to multiplexer 364-S. Each of multiplexers 364 may output a signal to LIO line 336.

[0101] For example, transceiver 365 may route a signal of LIO line 336 of a memory die to LIO line 337 of a logic die. In various examples, the memory die may activate multiplexer 339 to output a signal from LIO line 336 to global IO line 332 through the conventional IO circuitry of the memory device. The logic die may activate transceiver 365 concurrently with the activation of LIO line 336 and global IO line 332 to output data to the logic die concurrently with the output of the data via the IO circuitry of the memory die. For example, the control circuitry of the memory device may determine whether to output the data through the conventional IO circuitry of the memory device, and the control circuitry of the logic die may determine whether to output the data to the logic die.

[0102] Although a single transceiver 365 is shown, multiple transceivers can be used to route signals from multiple LIO lines of a memory die to a logic die. For example, a transceiver can be coupled to an LIO line of a memory device of a memory die. Another transceiver can be coupled to an LIO line of another memory device of a memory die. Each of the transceivers can route signals to the logic die by routing the signals to an LIO line 337 of the logic die. Each of the transceivers can route signals concurrently. In various examples, transceiver 365 can be coupled to a global IO line 332 instead of a sense amplifier 363 or an LIO line 336. Similarly, transceivers coupled to global IO lines can concurrently route signals to the logic die.

[0103] Figure 4A is a block diagram of an example of a memory-logic architecture according to several embodiments of the present disclosure. Figure 4B yes Figure 4A Block diagram of the first part of the architecture illustrated in . Figure 4C yes Figure 4A 4. The architecture includes a memory die 414 bonded to a logic die 415 in a wafer-on-wafer manner. In this example, singulated therefrom is a memory die 402 bonded to a logic die 404.

[0104] A portion of a memory die 402 is illustrated as a number of memory banks 428. In this example, there are 32 memory banks 428 per die 402, with each memory bank having a capacity of 1 Gigabit for a total capacity of 32 Gigabits of die. Each memory bank 428 is divided (e.g., logically divided) into 64 sectors 454, however embodiments are not limited to this particular example. Each sector has a capacity of 16 Mbits. The sectors 454 are arranged in rows 456.

[0105] A portion of logic die 404 is illustrated as forming a number of clusters 452 that form an on-chip network (e.g., a 1024-bit Advanced eXtensible Interface (AXI) network). In this example, logic die 404 includes 32 clusters (corresponding to 32 banks of memory die 402). However, in some embodiments, the ratio of banks to clusters is not 1:1. In this example, there are 1024 multiply-accumulators (MACs) per cluster operating at 1.2 gigahertz. Each cluster 452 is divided into 4 matrix-matrix units 458, however, embodiments are not limited to this particular example. As an example, one matrix-matrix unit 458 is illustrated.

[0106] In this non-limiting example, the memory die 402 is connected to the logic die 404 across 8 buses (GBUS) 453. Each GBUS 453 is coupled to 4 banks 428 in a column and has a bus width of 256 bits across 4 banks 428. For a full chip bandwidth of 256 Gigabytes per second, the bandwidth of each GBUS 453 is 32 Gigabytes per second. The memory capacity served by each GBUS 453 is 4 Gigabits (1 Gigabit per bank 428). Any data transferred to the logic die 404 can be used for any resource of the logic die 404 via the on-chip network architecture of the logic die 404.

[0107] Data may be exchanged between each of the four rows 456 of the section 454 of the memory bank 428 and a corresponding matrix-matrix unit 458. The matrix-matrix unit 458 may be included in the logic circuitry of the logic die 404. Figure 4C In the example illustrated in FIG. 4 , data from row 456 is provided to matrix-matrix unit 458. The connection between each segment 454 of row 456 and matrix-matrix unit 458 is a bus called LBUS. The width of the LBUS is 256 bits per segment 454, servicing a 16-megabit memory space. For a full chip bandwidth between 4.5 terabytes per second and 65 terabytes per second, the bandwidth is 32 gigabytes per second per LBUS. Each segment 454 can exchange data with a corresponding vector-vector unit 460.

[0108] Matrix-matrix unit 458 includes 16 vector-vector units 460 coupled to an SRAM buffer 462 of an on-chip network architecture connected to logic die 404. Each vector-vector unit 460 is coupled to a respective memory segment 454 and to one or more other vector-vector units 460. Each vector-vector unit 460 may be coupled to a respective LIO line of a memory device, at least one other vector-vector unit 460, and a buffer 462. Buffer 462 may be coupled to GBUS 453, which may be coupled to a global IO line of the memory device. The logic circuitry may exchange signals indicating data with the memory device via two different paths (GBUS 453 and LIO lines).

[0109] Figure 5 Flowcharts corresponding to methods for annotating genomic sequences using memory die and logic die according to several embodiments of the present disclosure. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0110] At operation 570, a signal indicative of a gene sequence may be received at the logic die from a memory die bonded to the logic die via a wafer-on-wafer bonding process and through wafer-on-wafer bonding. For example, the logic die may receive a signal indicative of data representing a gene sequence from a memory die and through wafer-on-wafer bonding using a bandwidth of 5 terabytes per second and using a power requirement of 8 watts. The gene sequence may be a deoxyribonucleic acid (DNA) sequence, a ribonucleic acid (RNA) sequence, or another type of sequence.

[0111] At operation 572, a genome annotation logic operation may be performed at the logic die to attach biological information to the gene sequence. The biological information attached to the gene sequence may include introns, exons, intron-exon boundaries, regulatory sequences, repetitive sequences, gene names, open reading frames, untranslated regions, and protein products. In some embodiments, the logic die may perform genome annotation logic operations on an amount of data greater than the amount of data transferred to the host as part of a single host memory access request. The method may also include predicting protein products based on given environmental conditions. In some embodiments, the method may include distinguishing multiple genes with overlapping reading frames. The method may also include comparing the annotated genome sequence with a previously completed known annotated genome.

[0112] At operation 574, the annotated gene sequence may be provided as an output. The method may include transmitting a signal indicative of the annotated gene sequence to a host via an output other than wafer-on-wafer bonding as part of providing the annotated gene sequence. In some embodiments, the method may include generating a visual representation of the annotated gene sequence and providing the visual representation of the annotated gene sequence to a user via a user interface.

[0113] Figure 6 It is a flowchart corresponding to a method for performing high data volume operations using a memory die and a logic die according to several embodiments of the present disclosure. At operation 680, a signal indicating input data can be received from a memory die by wafer-on-wafer bonding at the logic die. The memory die is bonded to the logic die via a wafer-on-wafer bonding process. In some embodiments, the input data can be received from the LIO line of the memory die by wafer-on-wafer bonding. At operation 682, a large processing bandwidth logic operation performed by a host can be accelerated via a logic circuit system of the logic die. At operation 684, the acceleration can be completed by performing a large data volume operation on the input data. At operation 686, the processed input data can be transferred to the memory die via wafer-on-wafer bonding for exchange with the host via input / output instead of wafer-on-wafer bonding. The large processing bandwidth logic operation performed at operation 682 is large relative to the processing capacity of the logic circuit system of the logic die. The large data bandwidth logic operation performed at operation 684 is large relative to the data input / output capacity of one or more processors of the host.

[0114] An example of a large processing bandwidth logic operation is a fluid dynamics analysis operation. An example of a large data bandwidth operation is a description of a fluid flow. A fluid flow description may refer to an operation that provides a description of the movement of a fluid under certain environmental conditions.

[0115] An example of a large processing bandwidth logical operation is a graph analysis operation. An example of a large data bandwidth operation is a node relationship operation. A node can be a data point representing any entity determined by the user. For example, a node can be a business product, a customer, or a specific service.

[0116] An example of a large processing bandwidth logical operation is a natural language processing operation. An example of a large data bandwidth operation is a speech recognition operation.

[0117] An example of a large processing bandwidth logical operation is an image processing operation. An example of a large data bandwidth logical operation is an image rendering operation.

[0118] Other examples of big data bandwidth logic operations include blockchain operations, facial recognition operations, augmented reality operations, and network traffic intrusion detection operations.

[0119] The specific numbers and connections described herein are examples for explanation purposes. Different numbers and arrangements of the explicitly enumerated components can be provided by one of ordinary skill in the art upon reading and understanding the present disclosure.

[0120] As used herein, "a number of" something may refer to one or more of such things. For example, a number of memory devices may refer to one or more memory devices. "A plurality of" something means two or more.

[0121] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of the various embodiments of the present disclosure. It should be understood that the above description has been made in an illustrative and not restrictive manner. A person of ordinary skill in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein after reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of the present disclosure should be determined by reference to the attached claims and the full range of equivalents to which such claims are entitled.

[0122] In the foregoing detailed description, various features are grouped together in a single embodiment in order to simplify the disclosure. The disclosed method should not be interpreted as reflecting the intention that the disclosed embodiments of the present disclosure must use more features than those explicitly recited in each claim. Specifically, as reflected in the appended claims, the inventive subject matter does not have all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A method comprising: receiving a signal indicative of a gene sequence from the memory die and through wafer-on-wafer bonding at a logic die bonded to the memory die via a wafer-on-wafer bonding process; performing genome annotation logic operations at the logic die to attach biological information to the gene sequence; and The annotated gene sequences are provided as output. 2 . The method of claim 1 , wherein providing the annotated gene sequence comprises transmitting a signal indicative of the annotated gene sequence to a host via an output other than wafer bonding on the wafer.

3. The method of claim 1, wherein the biological information attached to the gene sequence comprises introns, exons, intron-exon boundaries, regulatory sequences, repetitive sequences, gene names, open reading frames, untranslated regions, and protein products.

4. The method of claim 3, further comprising predicting the protein product based on given environmental conditions.

5. The method of claim 1, further comprising using overlapping reading frames to distinguish multiple genes.

6. The method of claim 1, further comprising comparing the annotated gene sequence to a previously completed known annotated genome.

7. The method according to claim 1, further comprising: generating a visual representation of the annotated gene sequence; and The visual representation of the annotated gene sequence is provided to a user via a user interface.

8. A method comprising: receiving, at a logic die bonded to the memory die via a wafer-on-wafer bonding process, a signal indicative of input data from the memory die and through wafer-on-wafer bonding; and The high processing bandwidth logic operations performed by the host are accelerated via the logic circuitry of the logic die by: performing large data bandwidth logical operations on the input data; and transferring processed input data to the memory die via the wafer-on-wafer bonding for exchange with the host via input / output instead of the wafer-on-wafer bonding; wherein the large processing bandwidth logic operations are large relative to a processing capability of the logic circuitry of the logic die; and The high processing bandwidth logic operations are large relative to data input / output capabilities of one or more processors of the host.

9. The method of claim 8, wherein receiving the input data comprises receiving the input data from a plurality of local input / output lines of the memory die through the on-wafer wafer bonding.

10. The method of claim 8, wherein the large processing bandwidth logic operation comprises a fluid dynamics analysis operation.

11. The method of claim 8, wherein the large processing bandwidth logic operation comprises a graphics analysis operation; and The big data bandwidth logical operation includes a node relationship operation.

12. The method of claim 8, wherein the large processing bandwidth logic operation comprises an image processing operation; and The large data bandwidth logical operations include image shading operations.

13. The method of claim 8, wherein the large processing bandwidth logic operations include natural language processing operations.

14. The method of claim 8, wherein the big data bandwidth logic operations include blockchain operations.

15. The method of claim 8, wherein the large data bandwidth logic operation comprises a facial recognition operation.

16. The method of claim 8, wherein the large data bandwidth logic operations include augmented reality operations.

17. The method of claim 8, wherein the large data bandwidth logic operation comprises a network traffic intrusion detection operation.

18. An apparatus comprising: A memory die comprising: Memory array; a plurality of local input / output lines LIO coupled to the memory array; and a global input / output line coupled to the plurality of LIOs and to a host interface; a logic die bonded to the memory die via a wafer-on-wafer bonding process, the logic die comprising logic circuitry configured to: receiving a signal indicative of data from the memory die and through wafer on wafer bonding to the plurality of LIOs, wherein the data comprises genetic sequence data; performing genome annotation logic operations to append biological information to the gene sequence data; and Annotated gene sequences are generated based on the genome annotation logical operations.

19. The apparatus of claim 18, wherein the logic circuitry is configured to perform the genome annotation logic operation on an amount of data that is greater than an amount of data transferred across the host interface as part of a single host memory access request.

20. The apparatus of claim 18, wherein the gene sequence is a deoxyribonucleic acid (DNA) sequence or a ribonucleic acid (RNA) sequence.

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