Chip packaging method and chip packaging structure

Abstract

The embodiments of the present invention provide a chip packaging method and a chip packaging structure, which relate to the field of integrated circuit packaging. A QFN lead frame is provided, and a base island and a first pin form a preset height difference. A crystal grain and a passive device are embedded in the base island of the lead frame, and a first plastic encapsulation layer is provided, and a surface RDL where a functional surface of the crystal grain is located is provided to realize the connection between the pins of the crystal grain and the passive device and the first pin. The present invention combines the QFN lead frame with the fan-out packaging technology to realize the multi-device SIP type QFN chip packaging. The packaged chip prepared by the present invention inherits the heat dissipation function of QFN, based on the advancement of fan-out packaging, reduces heat generation, and provides a top heat dissipation design of the package body, and the heat dissipation function is more powerful. The crystal grain and the like are embedded in the lead frame, and the thickness of each RDL and plastic encapsulation layer in the packaging structure is easy to control. The QFN chip prepared by the present invention can reduce the overall thickness.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging, and in particular to a chip packaging method and a chip packaging structure. Background Art

[0002] Electronic products have always evolved towards smaller size, lighter weight, faster speed, higher frequency, lower cost and higher reliability.

[0003] The traditional QFN (Quad Flat No-leads Package) is based on a QFN lead frame with the base island flush with the pin height, with die bonding, wire bonding and plastic encapsulation performed on the base island.

[0004] The traditional QFN packaging process cannot achieve SIP packaging (System in Package). The traditional QFN heat dissipation design optimization can only rely on plastic packaging materials, but the improvement of plastic packaging materials' heat dissipation performance cannot keep up with the demand. Summary of the invention

[0005] The object of the present invention is to provide a chip packaging method and a chip packaging structure, which can greatly improve the heat dissipation performance of the packaged chip on the basis of reducing the chip thickness and realize SIP packaging of multiple devices at the same time.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a chip packaging method, the chip packaging method comprising the following steps:

[0008] A QFN lead frame is provided; wherein the QFN lead frame comprises a base island and a plurality of first pins; the first pins are arranged around the side of the base island; the base island and the first pins have a preset height difference;

[0009] Embedding at least one die into the QFN lead frame, with the back side of the die in contact with the first surface of the base island; wherein the die and the base island are bonded to form a base island structure, and the base island structure is flush with the vertical height of the first pin;

[0010] Preparing a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and exposes the first surface of the first pin and the second pin of the die;

[0011] At least one RDL layer is prepared on the surface where the functional surface of the die is located; wherein the second pin of the die and the first surface of the first pin are connected through the RDL layer; the functional surface of the die is the surface on which the second pin is arranged on the die;

[0012] Preparing a second plastic encapsulation layer on the RDL layer to obtain a board-level package; the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin;

[0013] The board-level package is cut along the cutting lines to separate at least one chip.

[0014] In a second aspect, the present application further provides a chip packaging structure, wherein the chip packaging structure is prepared by any one of the methods in the first aspect above;

[0015] Wherein, the chip packaging structure includes a QFN lead frame; the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; the base island and the first pin have a preset height difference.

[0016] The beneficial effects of the embodiments of the present invention include, for example:

[0017] The embodiments of the present invention provide a chip packaging method and a chip packaging structure, which relate to the field of integrated circuit packaging. The fan-out packaging of the chip is realized based on the QFN lead frame, wherein the base island and the first pin in the QFN lead frame form a preset height difference, so that the chiplet / die (referred to as the grain) and the passive device can be embedded on the base island of the lead frame, and a first plastic encapsulation layer is set. Then, RDL is formed on the interface formed by the functional surface of the grain (or passive device), the first pin and the plastic encapsulation material, thereby realizing the connection between the device and the first pin. The present invention combines the QFN lead frame with the fan-out packaging technology to realize the multi-device SIP type QFN chip packaging. The QFN lead frame in the present invention inherits the heat dissipation function of the QFN chip. Based on the advancement of fan-out packaging, the heat generation is further reduced, and the heat dissipation design of the top of the chip can also be realized, which is more powerful than the heat dissipation function of the traditional QFN chip. The die is embedded in the QFN lead frame, and the thickness of each layer in the package chip structure, such as the RDL layer or the second plastic packaging layer, is easy to control, thereby reducing the thickness of the QFN chip product as a whole. In the present invention, the RDL layer is preferably one layer, and is a board-level package with high processing efficiency and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0019] Figure 1One of the step flow charts of a chip packaging method provided by an embodiment of the present invention;

[0020] Figure 2 Schematic diagram (cross-sectional view) of the structure of a QFN lead frame in an embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the structure of transferring the QFN lead frame to the carrier board in an embodiment of the present invention;

[0022] Figure 4 This is one of the structural schematic diagrams of the crystal grains in the embodiment of the present invention;

[0023] Figure 5 This is the second structural schematic diagram of the crystal grain in the embodiment of the present invention;

[0024] Figure 6 This is one of the flow charts of step S2 in an embodiment of the present invention;

[0025] Figure 7 This is one of the structural schematic diagrams of the die being bonded to the base island in an embodiment of the present invention;

[0026] Figure 8 This is one of the flow charts of step S3 in an embodiment of the present invention;

[0027] Fig. 9 This is one of the structural schematic diagrams of the preparation of the first plastic sealing layer in an embodiment of the present invention;

[0028] Fig.10 The second structural schematic diagram of the preparation of the first plastic sealing layer in an embodiment of the present invention;

[0029] Fig.11 This is one of the flow charts of step S4 in an embodiment of the present invention;

[0030] Fig.12 This is one of the structural schematic diagrams of preparing the RDL layer in an embodiment of the present invention;

[0031] Fig.13 This is a schematic diagram of the structure after the second plastic sealing layer is prepared in an embodiment of the present invention;

[0032] Fig.14 This is one of the schematic diagrams of the structure of the chip particle in the embodiment of the present invention;

[0033] Fig.15 This is a second flow chart of step S2 in an embodiment of the present invention;

[0034] Fig.16 A schematic diagram of the structure of transferring a die to a carrier board in an embodiment of the present invention;

[0035] Fig.17It is a schematic diagram of the structure after the die is transferred to the QFN lead frame in an embodiment of the present invention;

[0036] Fig.18 It is a schematic diagram of the structure after removing the carrier board and the temporary bonding adhesive layer in an embodiment of the present invention;

[0037] Fig.19 This is a second flow chart of step S3 in an embodiment of the present invention;

[0038] Fig. 20 This is the second structural schematic diagram of preparing the RDL layer in an embodiment of the present invention;

[0039] Fig.21 This is a second flow chart of step S4 in an embodiment of the present invention;

[0040] Fig. 22 This is the third structural diagram of preparing the RDL layer in an embodiment of the present invention;

[0041] Fig.23 This is the second structural schematic diagram of the chip particle in the embodiment of the present invention;

[0042] Fig.24 This is the third structural schematic diagram of the chip particle in the embodiment of the present invention;

[0043] Fig.25 Schematic diagram of the process of step S5 in an embodiment of the present invention;

[0044] Fig.26 This is the fourth structural schematic diagram of the chip particle in the embodiment of the present invention.

[0045] Icon: 10-QFN lead frame; 1-base island; 2-first pin; 20-die; 21-second pin; 22-carrier; 30-first plastic layer; 40-RDL layer; 41-passivation layer; 31-second plastic layer; 50-metal layer; 60-metal column. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0050] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0051] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0052] In this article, the term "die" is also called chiplet or die, which refers to any type of semiconductor chip (chip) or integrated circuit chip that implements a specific function, and also refers to any type of semiconductor die (die) or integrated circuit die that implements a specific function.

[0053] In this article, the term "chiplet" refers to the packaging structure obtained after the chiplet or die is integrated and packaged through advanced packaging technology and then cut along the cutting lines.

[0054] As used herein, the term “RDL (ReDistribution Layer)” refers to a redistribution layer, which is a metal layer used to redistribute electrical connections.

[0055] As described in the prior art, QFN (Quad Flat No-leads Package) is a leadless package with good heat dissipation performance. There is a large exposed heat dissipation pad at the center of the bottom of the package. The heat dissipation pad is part of the internal thick copper frame structure, which is called the QFN lead frame base island in this article. DFN package (Dual Flat No-lead Package) is a branch of QFN package and also has excellent heat dissipation characteristics.

[0056] In traditional QFN packaging, the height of the base island is flush with the height of the pins, and the gold wire has an upward curvature, so the chip after packaging is thicker.

[0057] Based on this, the embodiments of the present application provide a chip packaging method and a chip packaging structure, which can greatly improve the heat dissipation performance of the packaged chip on the basis of reducing the chip thickness, and at the same time realize SIP packaging of multiple devices.

[0058] Please refer to Figure 1 The present invention provides a chip packaging method, comprising the following steps:

[0059] S1. Provide a QFN lead frame; wherein the QFN lead frame includes a base island and a plurality of first pins; the first pins are arranged around the side of the base island; and there is a preset height difference between the base island and the first pins;

[0060] S2, embedding at least one die into the QFN lead frame, with the back side of the die in contact with the first surface of the base island; wherein the die and the base island are bonded to form a base island structure, and the base island structure is flush with the vertical height of the first pin;

[0061] S3, preparing a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and exposes the first surface of the first pin and the second pin of the die;

[0062] S4, preparing at least one RDL layer on the surface where the functional surface of the grain is located; wherein the second pin of the grain and the first surface of the first pin are connected through the RDL layer; wherein the functional surface of the grain is the surface on which the second pin is arranged on the grain;

[0063] S5, preparing a second plastic encapsulation layer on the RDL layer to obtain a board-level package; the second plastic encapsulation layer covers the RDL layer, the functional surface of the die, and the first surface of the first pin;

[0064] S6, cutting the panel-level package along the cutting path to separate at least one chip.

[0065] The following is an exemplary description of a chip packaging method provided by the present application:

[0066] Embodiment 1

[0067] As an optional implementation method, please continue to refer to Figure 1 , the method comprising:

[0068] S1. Provide a QFN lead frame; wherein the QFN lead frame includes a base island and a plurality of first pins; the first pins are arranged around the side of the base island; and there is a preset height difference between the base island and the first pins.

[0069] In this embodiment, please refer to Figure 2 , the QFN lead frame 10 includes a base island 1 and a plurality of first pins 2, and the first pins 2 are arranged around the side of the base island 1, presenting a form of surrounding the base island 1. In an achievable embodiment, the structure of the QFN lead frame 10 may be consistent with the structure and layout of the lead frame unit in the prior art, that is, the layout between the QFN lead frame 10 and the support frame, the connecting ribs, and the cutting path is not limited in this application, and it is only necessary to make the base island 1 and the first pin 2 have a preset height difference. In this embodiment, the height difference can make the base island structure formed by the grain and the base island flush with the vertical height of the first pin after the grain is embedded in the QFN lead frame. Among them, in this embodiment, the preset height difference between the base island and the first pin is greater than the thickness of the grain. In an achievable method, the difference of the preset height difference is 0.05-0.3mm. In another achievable method, the QFN lead frame 10 can be replaced by a DFN lead frame.

[0070] S2, embed at least one die into the QFN lead frame, and the back of the die contacts the first surface of the base island; wherein the die and the base island are bonded to form a base island structure, and the base island structure is flush with the vertical height of the first pin. In this embodiment, the die 20 is bonded to the first surface of the base island 1, and the back of the die 20 needs to contact the first surface of the base island 1. Figure 7 The die 20 is provided with pin pads, which are arranged on the functional surface of the die 20 and are used to connect to an external circuit. Figure 4 , a metal column, for example, a metal copper column, is arranged on the pin pads of the die 20, and the thickness of the metal copper column can be 10-80um. Figure 4 The crystal grain 20 shown. The crystal grain 20 without the metal pillar is shown in FIG. Figure 5 , the thickness of the pin pads does not exceed 2um. In this embodiment, continue to refer to Figure 4For the convenience of description, the pin pads provided on the die 20 and the metal copper pillars provided thereon are collectively referred to as the second pins 21. The pins on the QFN lead frame 10 are referred to as the first pins 2. The surface of the die 20 provided with the second pins 21 is referred to as the functional surface of the die 20. The functional surface facing away from the die 20 is referred to as the back surface of the die 20.

[0071] In one achievable manner, reference Figure 6 The step of embedding at least one die into the QFN lead frame, wherein the back side of the die contacts the first surface of the base island is as follows:

[0072] SA21. Provide a carrier board and set a temporary bonding adhesive layer on the carrier board;

[0073] SA22, transferring the QFN lead frame to the carrier board; wherein the second surface of the base island is bonded to the temporary bonding adhesive layer; and the second surface of the first pin is bonded to the temporary bonding adhesive layer;

[0074] SA23, setting patch glue on the first surface of the base island;

[0075] SA24, bonding the die to the QFN lead frame, wherein the back side of the die is bonded to the first surface of the base island by using patch adhesive.

[0076] Please refer to Figure 3 , provide a carrier board 22, and set a temporary bonding adhesive layer on the carrier board 22. Transfer the QFN lead frame 10 to the temporary bonding adhesive layer, and at this time, the second surface of the base island 1 and the second surface of the first pin 2 are in contact with the temporary bonding adhesive layer. Please continue to refer to Figure 7 , the die 20 is transferred to the QFN lead frame 10, and the back side of the die 20 is in contact with the first surface of the base island 1. A patch adhesive may be provided on the first surface of the base island 1 to fix the die 20 on the QFN lead frame.

[0077] In another feasible method, the die 20 may be replaced by a passive device. If the passive device is packaged, the functional surface of the passive device needs to be retained, and the five surfaces of the passive device other than the functional surface need to be insulated.

[0078] S3. Prepare a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and exposes the first surface of the first pin and the second pin of the die.

[0079] Please refer to Figure 8 The steps of preparing the first plastic encapsulation layer on the QFN lead frame include:

[0080] SA31, a first plastic encapsulation layer is arranged on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and covers the functional surface of the die and the first pin;

[0081] SA32, grinding and exposing the first surface of the first pin and the second pin of the die.

[0082] In this embodiment, please refer to Fig. 9 After the die 20 is bonded to the QFN lead frame 10 , a first plastic encapsulation layer 30 needs to be prepared on the surface of the QFN lead frame. The plastic encapsulation layer fills the gap between the base island 1 and the first pin 2 and covers the functional surface of the die 20 .

[0083] Please note that please refer to Fig.10 , the first plastic layer 30 cannot cover the first surface of the first pin 2 and the second pin 21 of the die 20, so as to ensure that there is no plastic encapsulation material residue on the surface of the second pin 21 of the die 20 and the first pin 2 used to set the RDL layer 40 in the QFN lead frame 10. The present application does not limit the method of ensuring that there is no plastic encapsulation material residue on the surface of the second pin 21 of the die 20 and the first pin 2 used to set the RDL layer 40 in the QFN lead frame 10. Any solution that can achieve the above precautions falls within the limitations of the present application. For example, ion etching, grinding and other methods.

[0084] S4, preparing at least one RDL layer on the surface where the functional surface of the die is located; wherein the second pin of the die and the first surface of the first pin are connected through the RDL layer; wherein the functional surface of the die is the surface on which the second pin is arranged on the die.

[0085] In this embodiment, please refer to Fig.11 The step of preparing at least one RDL layer on the functional surface of the die 20 includes:

[0086] SA41, sputtering a seed layer on the surface where the functional surface of the grain is located; wherein the seed layer covers the functional surface of the grain, the first surface of the first pin, and the surface of the first plastic packaging layer;

[0087] SA42. Perform pattern electroplating on the seed layer to achieve electrical connection between the second pin and the first pin.

[0088] In this embodiment, please refer to Fig.12, a seed layer can be directly sputtered on the surface where the functional surface of the grain 20 is located, and then the seed layer is subjected to pattern electroplating to achieve electrical connection between the second pin 21 and the first pin 2. That is, a photosensitive film is coated on the surface of the seed layer away from the grain 20, and operations such as exposure, development, and pattern electroplating are performed, and then the film is stripped and the excess seed layer is etched to form an RDL layer, so that the second pin 21 on each grain 20 is effectively connected to the first pin 2. Among them, the RDL layer 40 includes at least one layer, and can be as many as six layers.

[0089] In this embodiment, there is no limit on the number of the RDL layer 40. In the fan-out package based on the QFN lead frame, the RDL layer 40 is selected as one layer, and a board-level package is adopted, which has high processing efficiency and can compete with the traditional QFN packaging process in cost.

[0090] S5. Prepare a second plastic encapsulation layer on the RDL layer to obtain a board-level package; the second plastic encapsulation layer covers the RDL layer, the functional surface of the die, and the first surface of the first pin.

[0091] Please refer to Fig.13 In this embodiment, the second plastic sealing layer 31 may be made of a plastic sealing material with good thermal conductivity, such as epoxy plastic sealing material, high thermal conductivity insulating adhesive, PP sheet with glass fiber, laminated material, etc.

[0092] In another feasible method, the second plastic encapsulation layer 31 may also include a highly thermally conductive insulating adhesive and a thermally conductive metal foil arranged in sequence. The composition of the second plastic encapsulation layer in the present application may be a combination of appropriate plastic encapsulation materials based on actual effects and costs.

[0093] S6, cutting the panel-level package along the cutting path to separate at least one chip.

[0094] In this embodiment, please refer to Fig.14 After the RDL layer 40, the functional surface of the die 20 and the surface of the first pin 2 are covered by the second plastic encapsulation layer 31, the metal surface of the board-level package needs to be exposed before the die 20 is cut along the cutting path and at least one chip is separated. In this embodiment, the second surface of the first pin 2 and the second surface of the base island 1 can be exposed by removing the carrier and the temporary bonding layer. Solderable silver or tin with a thickness of about 10um can also be electroplated on the metal surface.

[0095] In summary, please continue to refer to Fig.14 Based on a chip packaging method provided in the first embodiment, a chip packaging structure in this embodiment is:

[0096] A QFN lead frame; wherein the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; and there is a preset height difference between the base island and the first pin.

[0097] The die is located on the first surface of the base island in the QFN lead frame.

[0098] A first plastic encapsulation layer is located between the base island and the first pin in the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin.

[0099] An RDL layer is located on the functional surface of the die; the second pin of the die is connected to the metal surface of the first pin through the RDL layer; wherein the functional surface of the die is the surface on which the second pin is arranged on the die.

[0100] A second plastic encapsulation layer is located on the RDL layer; wherein the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin.

[0101] Embodiment 2

[0102] The difference between the second embodiment and the first embodiment is that the second embodiment adopts a packaging process in which the functional surface of the die is fixed on the carrier board with the QFN lead frame facing downward, while the first embodiment adopts a packaging process in which the functional surface of the die is fixed on the base island with the QFN lead frame facing upward.

[0103] As an optional implementation method, the method includes:

[0104] S1. Provide a QFN lead frame; wherein the QFN lead frame includes a base island and a plurality of first pins; the first pins are arranged around the side of the base island; and there is a preset height difference between the base island and the first pins.

[0105] The QFN lead frame 10 in this embodiment can refer to the description in the first embodiment, which will not be repeated here.

[0106] S2, embedding at least one die into the QFN lead frame, with the back of the die in contact with the first surface of the base island; wherein the die and the base island are bonded to form a base island structure, and the base island structure is flush with the vertical height of the first pin. The difference between the second embodiment and the previous embodiment is that a different method is used to embed the die 20 into the QFN lead frame 10.

[0107] In this embodiment, please refer to Fig.15 The step of embedding at least one die into the QFN lead frame, wherein the back side of the die contacts the first surface of the base island is as follows:

[0108] SB21. Provide a carrier board and set a temporary bonding adhesive layer on the carrier board.

[0109] SB22, transferring at least one die to a carrier board; wherein a functional surface of the die is bonded to the temporary bonding layer.

[0110] SB23, set patch glue on the back of the die.

[0111] SB24, bonding the die to the QFN lead frame, wherein the back side of the die is bonded to the first surface of the base island by patch adhesive; and the first surface of the first pin is bonded to the temporary bonding adhesive layer.

[0112] In this embodiment, continue to refer to Figure 5 , Figure 5 : is a structural diagram of the grain 20. Among them, the grain 20 is provided with pin Pads, which are arranged on the functional surface of the grain 20 for connecting to an external circuit. In this embodiment, the thickness of the pin Pads on the grain 20 does not exceed 2um, and the pin Pads do not need to be provided with a metal column, thereby reducing costs. In this embodiment, for the convenience of description, the pin Pads provided on the grain 20 are referred to as second pins 21. The pins on the QFN lead frame 10 are referred to as first pins 2. The surface of the grain 20 on which the second pin 21 is provided is referred to as the functional surface of the grain 20. The functional surface away from the grain 20 is referred to as the back side of the grain 20.

[0113] Please refer to Fig.16 , provide a carrier 22, and set a temporary bonding layer on the carrier 22; transfer the die 20 to the carrier 22, and at this time, the functional surface of the die 20 is attached to the temporary bonding layer. Please refer to Fig.17 Then, the die 20 is bonded to the QFN lead frame 10, and the back of the die 20 is bonded to the first surface of the base island 1 by the patch adhesive. At the same time, the first surface of the first pin 2 is bonded to the temporary bonding adhesive layer. In this embodiment, the patch adhesive can be an insulating adhesive or silver paste with good thermal conductivity.

[0114] In another feasible method, the die 20 may be replaced by a passive device. If the passive device is packaged, the functional surface of the passive device needs to be retained, and the five surfaces of the passive device other than the functional surface need to be insulated.

[0115] S3. Prepare a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and exposes the metal surface of the base island and the first pin, and the second pin of the grain.

[0116] Please refer to Fig.19 The steps of preparing the first plastic encapsulation layer on the QFN lead frame include:

[0117] SB31. Disposing a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills a gap between the base island structure and the first pin;

[0118] SB32, grinding and exposing the second surface of the base island away from the die and the second surface of the first pin away from the carrier;

[0119] SB33, remove the carrier board and the temporary bonding adhesive layer to expose the second pin of the die and the first surface of the first pin.

[0120] In this embodiment, after obtaining the first plastic encapsulation layer 30, it is necessary to grind and expose the second surface of the base island and the second surface of the first pin, the purpose of which is to ensure the heat dissipation at the bottom of the chip and the solderability of the pins. Then remove the carrier 22 and the temporary bonding layer. This structure can be referred to Fig.18 At this time, there is no plastic packaging material left on the functional surface of the die and the first surface of the first pin, thereby avoiding the influence of the residue of the first plastic packaging layer on the electrical connection.

[0121] S4, preparing at least one RDL layer on the surface where the functional surface of the grain is located; wherein the second pin of the grain and the first surface of the first pin are connected through the RDL layer; wherein the functional surface of the grain is the surface on which the second pin is arranged on the grain.

[0122] In this embodiment, please continue to refer to Fig.11 The step of preparing at least one RDL layer on the functional surface of the die includes:

[0123] SA41, sputtering a seed layer on the surface where the functional surface of the grain is located; wherein the seed layer covers the functional surface of the grain, the first surface of the first pin, and the surface of the first plastic packaging layer;

[0124] SA42. Perform pattern electroplating on the seed layer to achieve electrical connection between the second pin and the first pin.

[0125] In this embodiment, reference Fig. 20 , a seed layer can be directly sputtered on the surface where the functional surface of the grain 20 is located, and then the seed layer is electroplated to achieve the electrical connection between the second pin 21 and the first pin 2. That is, a photosensitive film is coated on the surface of the seed layer away from the grain 20, and operations such as exposure, development, and pattern electroplating are performed, and then the film is stripped and the excess seed layer is etched to form a circuit pattern, that is, an RDL layer, so that the second pin 21 on each grain 20 is effectively connected to the first pin 2.

[0126] In this embodiment, there is no limit on the number of the RDL layer 40. In the fan-out package based on the QFN lead frame, the RDL layer 40 is selected as one layer, and a board-level package is adopted, which has high processing efficiency and can compete with the traditional QFN packaging process in cost.

[0127] In this embodiment, since the RDL layer is obtained by directly sputtering the seed layer, the heat dissipation process on the top of the chip can be further performed on this basis. The present invention can refer to the fifth embodiment.

[0128] S5. Prepare a second plastic packaging layer on the RDL layer to obtain a board-level package; the second plastic packaging layer covers the RDL layer, the functional surface of the die, and the first surface of the first pin.

[0129] In this embodiment, the second plastic sealing layer 31 may be made of a plastic sealing material with good thermal conductivity, such as epoxy plastic sealing material, high thermal conductivity insulating adhesive, PP sheet with glass fiber, laminated material, etc.

[0130] In another feasible method, the second plastic encapsulation layer 31 may also include a highly thermally conductive insulating adhesive and a thermally conductive metal foil arranged in sequence. The composition of the second plastic encapsulation layer in the present application may be a combination of appropriate plastic encapsulation materials based on actual effects and costs.

[0131] S6, cutting the panel-level package along the cutting path to separate at least one chip.

[0132] In this embodiment, please continue to refer to Fig.14 , the chip packaging structure is similar to that of the first embodiment, and its specific structure is not described here. It should be noted that in the first embodiment, the first surface of the first pin 2 and the second pin 21 of the die 20 are polished and exposed through step SA32. Since the second pin 21 in the first embodiment includes a metal column of about 10-80um, when the second pin 21 of the die 20 is polished and exposed, a certain thickness of the first plastic encapsulation layer still exists on the functional surface of the die 20. In the second embodiment, there is no first plastic encapsulation layer residue on the functional surface of the die 20.

[0133] Embodiment 3

[0134] The difference between the third embodiment and the second embodiment is that the third embodiment, based on the QFN lead frame, adopts a packaging process in which the functional surface of the grain is fixed on the carrier with downward facing. When preparing the RDL layer, the seed layer is not directly sputtered, but a passivation layer is first prepared on the functional surface of the grain, and then the subsequent preparation of the second plastic encapsulation layer and the dicing process are completed in sequence.

[0135] Please refer to Fig.21 The step of preparing at least one RDL layer on the functional surface of the die includes:

[0136] SB41, preparing a passivation layer on the surface where the functional surface of the grain is located; wherein the passivation layer covers the functional surface of the grain, the first surface of the first pin and the surface of the first plastic packaging layer;

[0137] SB42, performing photolithography on the surface of the passivation layer away from the crystal grain to expose the first pin and the second pin of the crystal grain;

[0138] SB43, sputtering a seed layer on the surface of the passivation layer away from the grains; and performing pattern electroplating based on the seed layer to achieve electrical connection between the second pin and the first pin.

[0139] In this embodiment, a passivation layer 41 is prepared on the surface where the functional surface of the grain 20 is located, and the passivation layer 41 can be a photosensitive interface material. The passivation layer 41 covers the functional surface of the grain 20, the first surface of the first pin 2, and the surface of the first plastic layer 30 away from the grain 20. It can be understood that the passivation layer 41 needs to cover the surface where the functional surface of the grain 20 is located. The passivation layer 41 is then exposed / developed to expose the second pin 21 on the grain 20 and the first surface of the first pin 2. A seed layer is then prepared on the passivation layer 41. The seed layer can be made by sputtering, that is, Ti, Cu and other metal materials are sputtered on the surface of the passivation layer 41 away from the grain 20 to obtain a seed layer. The RDL layer is formed after electroplating the seed layer pattern, stripping the film and etching the excess seed layer. Please refer to Fig. 22 , Fig. 22 is a structural diagram of the RDL layer prepared according to the above steps.

[0140] In the third embodiment, according to the above chip packaging method, please refer to Fig.23 , the chip packaging structure includes:

[0141] A QFN lead frame; wherein the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; and there is a preset height difference between the base island and the first pin.

[0142] The die is located on the first surface of the base island in the QFN lead frame.

[0143] A first plastic encapsulation layer is located between the base island and the first pin in the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin and exposes the metal surfaces of the base island and the first pin.

[0144] A passivation layer is located on the functional surface of the die away from the first surface of the base island; wherein the passivation layer covers the functional surface of the die, the first surface of the first pin and the surface of the first plastic packaging layer.

[0145] The RDL layer is located on the passivation layer away from the functional surface of the crystal grain; the metal surface of the second pin and the first pin of the crystal grain are connected through the RDL layer; wherein the functional surface of the crystal grain is the surface on which the second pin is arranged on the crystal grain.

[0146] A second plastic encapsulation layer is located on the passivation layer away from the RDL layer; wherein the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin.

[0147] Embodiment 4

[0148] The difference between the fourth embodiment and the first embodiment is that the second embodiment, based on the QFN lead frame, adopts a packaging process in which the functional surface of the die is fixed on the base island with the functional surface facing upwards. Instead of directly sputtering the seed layer, a passivation layer is first prepared on the functional surface of the die, and then the subsequent preparation of the second plastic sealing layer and the dicing process are completed in sequence. This embodiment provides a chip packaging method, please continue to refer to Fig.21 In the fourth embodiment, the chip packaging structure prepared according to the above chip packaging method is shown in FIG. Fig.24 In this embodiment, the structure of the chip packaging structure is similar to that of the third embodiment. The chip packaging structure includes:

[0149] A QFN lead frame; wherein the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; and there is a preset height difference between the base island and the first pin.

[0150] The die is located on the first surface of the base island in the QFN lead frame.

[0151] A first plastic encapsulation layer is located between the base island and the first pin in the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin and exposes the metal surfaces of the base island and the first pin.

[0152] A passivation layer is located on the functional surface of the die away from the first surface of the base island; wherein the passivation layer covers the functional surface of the die, the first surface of the first pin and the surface of the first plastic packaging layer.

[0153] The RDL layer is located on the passivation layer away from the functional surface of the crystal grain; the metal surface of the second pin and the first pin of the crystal grain are connected through the RDL layer; wherein the functional surface of the crystal grain is the surface on which the second pin is arranged on the crystal grain.

[0154] A second plastic encapsulation layer is located on the passivation layer away from the RDL layer; wherein the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin.

[0155] It should be noted that the difference between the chip packaging structure and the third embodiment is that a certain thickness of the first plastic packaging layer residue still exists on the functional surface of the die 20. However, in the third embodiment, there is no such residue on the functional surface of the die 20.

[0156] Embodiment 5

[0157] The difference between the fifth embodiment and the second embodiment is that the second embodiment, based on the QFN lead frame, adopts a packaging process in which the functional surface of the die is fixed on the carrier board with the die facing downward, and directly sputters the seed layer to prepare the RDL layer. The chip top heat dissipation design is performed on the RDL layer, which can greatly improve the heat dissipation performance.

[0158] See also Fig.25, preparing a second plastic encapsulation layer on the RDL layer to obtain a board-level package including:

[0159] SB51, preparation of thermally conductive copper pads on the functional surface of the grain;

[0160] SB52, sequentially arrange a PP sheet and a copper foil on the RDL layer, and press them together to obtain a second plastic sealing layer and a copper foil layer on its surface; wherein the second plastic sealing layer covers the RDL layer and the first surface of the first pin;

[0161] SB53, grooves are provided on the second plastic sealing layer and the copper foil layer on the surface thereof to expose the thermal conductive copper pads;

[0162] SB54, providing a seed layer on the surface where the groove is located;

[0163] SB55, forming a metal column by electroplating to fill the groove, and thickening the copper foil layer on the surface of the second plastic packaging layer by electroplating to obtain a metal layer.

[0164] In this embodiment, please refer to Fig.26 , when preparing the RDL layer, thermally conductive copper pads can be processed on the functional surface of the grain at the same time to prepare metal pillars 60 on the functional surface of the grain 20. The metal pillars 60 are composed of thermally conductive copper pads and metal materials for electroplating and filling holes. The metal material can be a metal material with good thermal conductivity, such as copper. The metal pillars 60 can quickly conduct the heat on the grain to the upper surface of the chip grain. In this embodiment, a PP sheet and copper foil can be pressed on the RDL layer, and laser drilling can be performed after the PP sheet is solidified to form blind holes to expose the surface of the thermally conductive copper pads. A seed layer is processed on the surface where the blind hole is located, and the holes are filled with electroplating to form metal pillars. At the same time, the copper foil on the surface of the PP sheet is thickened by electroplating to obtain a metal layer 50. The metal layer 50 can be a composite metal layer of copper and tin, which is used for heat dissipation on the top of the chip. The seed layer is formed by sputtering copper or chemical copper deposition. In this embodiment, please continue to refer to Fig.26 , the chip packaging structure includes:

[0165] A QFN lead frame; wherein the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; and there is a preset height difference between the base island and the first pin.

[0166] The die is located on the first surface of the base island in the QFN lead frame.

[0167] A first plastic encapsulation layer is located between the base island and the first pin in the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin and exposes the metal surfaces of the base island and the first pin.

[0168] An RDL layer is located on the functional surface of the die away from the first surface of the base island; the second pin of the die is connected to the metal surface of the first pin through the RDL layer; wherein the functional surface of the die is the surface of the die where the second pin is arranged.

[0169] Metal pillars located in the RDL layer away from the functional surface of the die;

[0170] A second plastic encapsulation layer is located on the RDL layer away from the functional surface of the die; wherein the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin, and wraps the metal column.

[0171] The metal layer is located on the second plastic encapsulation layer away from the functional surface of the crystal grain, wherein the metal layer covers a portion of the surface of the second plastic encapsulation layer away from the functional surface of the crystal grain, and the second plastic encapsulation layer is exposed around the metal layer.

[0172] In this embodiment, the copper pillar method can also be used. That is, when preparing the RDL layer, copper pads are processed on the functional surface of the grain, copper pillars are grown on the copper pads, the laminated materials are pressed, ion etching or grinding is performed to expose the copper pillar surface, and then a copper layer is sputtered on the copper pillar surface and the laminated material surface, and finally the surface copper layer is thickened by electroplating.

[0173] In addition, an embodiment of the present application further provides a method for preparing a QFN lead frame, the method for preparing the QFN lead frame comprising:

[0174] A metal belt is provided; the metal belt can be made of copper with a thickness of 0.1-1 mm.

[0175] The metal strip is etched to obtain a QFN lead frame 10, wherein a preset height difference is provided between the base island 1 and the first pin 2 in the QFN lead frame 10, so that the overall height of the base island 1 after bonding the die 20 is flush with the height of the first pin 2. In an achievable embodiment, the QFN lead frame is processed by selective wet etching.

[0176] Specifically, a photosensitive wet film can be rolled on the surface of the metal strip, and pre-curing can be completed at a temperature of 80-85 degrees and a time of 5-10 minutes to form an anti-corrosion photosensitive film, and then the anti-corrosion photosensitive film is exposed and developed. Among them, after development, only the second surface of the base island 1 in the lead frame needs to retain the anti-corrosion photosensitive film. The first pin 2 in the lead frame needs to retain the anti-corrosion photosensitive film on the upper and lower surfaces. In this embodiment, the thickness of the copper layer of the base island 1 can be controlled by controlling the spray pressure, solution concentration, solution temperature, walking speed and other parameters during etching in the etching process. Among them, in order to make the base island 1 and the first pin 2 have a preset height difference, the copper layer thickness of the base island 1 can be etched to be lower than the first pin 2, thereby forming a height difference. In another feasible method, the traditional QFN lead frame processed by the existing etching technology can be processed by a precision machine tool for controlled depth milling, and a certain thickness of the copper layer of the base island 1 can be removed, so that the height difference between the base island 1 and the first pin 2 meets the preset height difference, for example, in the range of 0.05-0.3mm.

[0177] In this embodiment, the second surface of the base island 1 and the connecting ribs may be partially etched within a range of about 0.15 mm around the second surface of the base island 1 to increase the bonding strength between the second surface of the base island 1 and the plastic encapsulation layer and prevent the connecting ribs from being exposed at the bottom of the chip after plastic encapsulation.

[0178] In another feasible embodiment, the metal strip is punched, and then the punched metal strip is subjected to controlled depth milling by a precision machine tool to obtain the QFN lead frame 10 .

[0179] It should be noted that the present application does not limit the preparation process of the QFN lead frame 10 , as long as the QFN lead frame 10 can be prepared and the overall height of the base island 1 after the die 20 is bonded is flush with the height of the first pin 2 .

[0180] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0181] In summary, the embodiments of the present invention provide a chip packaging method and a chip packaging structure, which relate to the field of integrated circuit packaging. A QFN lead frame is provided, in which a base island and a first pin form a preset height difference. By embedding a die and a passive device into the base island of the lead frame, a plastic encapsulation layer is sequentially arranged, and then RDL is formed on the interface formed by the die functional surface, the passive device, the first pin and the plastic encapsulation material, so as to realize the connection between the device and the first pin.

[0182] The present invention combines the QFN lead frame with the fan-out packaging technology to realize the multi-device SIP type QFN chip packaging. The present invention uses a QFN lead frame and inherits the heat dissipation function of the QFN; based on the advancement of the fan-out packaging, the heat generation is further reduced. And a top heat dissipation design of the package body is provided. Therefore, the packaged chip prepared based on the present invention has a more powerful heat dissipation function. Since the grains and the like are embedded in the lead frame, and the thickness of the RDL layer or the second plastic sealing layer can be controlled during preparation, the overall thickness of the chip can be reduced by 0.05-0.2mm. On the other hand, the fan-out package RDL layer in the present invention is generally one layer, and it is a board-level package with high processing efficiency, so the cost can compete with the traditional QFN package.

[0183] Among them, the present invention is also applicable to TOLL packaging products by embedding the die into the lead frame and combining it with the fan-out packaging technology.

[0184] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging method, characterized in that: Applied to system-level packaging, the chip packaging method comprises the following steps: A QFN lead frame is provided; wherein the QFN lead frame comprises a base island and a plurality of first pins; the first pins are arranged around the side of the base island; the base island and the first pins have a preset height difference; Embed at least one die into the QFN lead frame, with the back of the die in contact with the first surface of the base island; wherein the die and the base island are bonded to form a base island structure, and the base island structure is flush with the vertical height of the first pin; a preset height difference between the base island and the first pin is greater than a thickness of the die; and the preset height difference is 0.05-0.3 mm; Preparing a first plastic encapsulation layer on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and exposes the first surface of the first pin and the second pin of the die; At least one RDL layer is prepared on the surface where the functional surface of the die is located; wherein the second pin of the die and the first surface of the first pin are connected through the RDL layer; the functional surface of the die is the surface on which the second pin is arranged on the die; Preparing a second plastic encapsulation layer on the RDL layer to obtain a board-level package; the second plastic encapsulation layer covers the RDL layer, the functional surface of the die and the first surface of the first pin; The board-level package is cut along the cutting lines to separate at least one chip.

2. The chip packaging method according to claim 1, characterized in that: The step of embedding at least one die into the QFN lead frame, wherein the back surface of the die contacts the first surface of the base island, comprises: Providing a carrier board, and setting a temporary bonding adhesive layer on the carrier board; Transferring at least one die to the carrier; wherein the functional surface of the die is bonded to the temporary bonding layer; Disposing patch adhesive on the back side of the die; The die is bonded to the QFN lead frame, wherein the back surface of the die is bonded to the first surface of the base island via the patch adhesive; and the first surface of the first pin is bonded to the temporary bonding adhesive layer.

3. The chip packaging method according to claim 2, characterized in that: The step of preparing a first plastic encapsulation layer on the QFN lead frame comprises: The first plastic encapsulation layer is disposed on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin; Grinding and exposing a second surface of the base island away from the die and a second surface of the first pin; The carrier board and the temporary bonding adhesive layer are removed to expose the second pin of the die and the first surface of the first pin.

4. The chip packaging method according to claim 1, characterized in that: The step of embedding at least one die into the QFN lead frame, wherein the back surface of the die contacts the first surface of the base island, further comprises: Providing a carrier board, and setting a temporary bonding adhesive layer on the carrier board; The QFN lead frame is transferred to the carrier; wherein the second surface of the base island is bonded to the temporary bonding adhesive layer; and the second surface of the first pin is bonded to the temporary bonding adhesive layer; Disposing patch adhesive on the first surface of the base island; The die is bonded to the QFN lead frame, wherein the back surface of the die is bonded to the first surface of the base island via the patch adhesive.

5. The chip packaging method according to claim 4, characterized in that: The step of preparing a first plastic encapsulation layer on the QFN lead frame comprises: The first plastic encapsulation layer is disposed on the QFN lead frame; wherein the first plastic encapsulation layer fills the gap between the base island structure and the first pin, and covers the die functional surface and the first pin; The first surface of the first pin and the second pin of the die are ground to expose the first surface of the first pin and the second pin of the die.

6. The chip packaging method according to claim 1, characterized in that: The step of preparing at least one RDL layer on the surface where the functional surface of the grain is located comprises: A passivation layer is prepared on the surface where the functional surface of the die is located; wherein the passivation layer covers the functional surface of the die, the first surface of the first pin, and the surface of the first plastic packaging layer; Performing photolithography on the surface of the passivation layer away from the crystal grain to expose the first pin and the second pin; A seed layer is sputtered on the passivation layer; and pattern electroplating is performed based on the seed layer to achieve electrical connection between the second pin and the first pin.

7. The chip packaging method according to claim 1, characterized in that: The step of preparing at least one RDL layer on the surface where the functional surface of the grain is located also includes: Sputtering a seed layer on the surface where the functional surface of the grain is located; wherein the seed layer covers the functional surface of the grain, the first surface of the first pin, and the surface of the first plastic packaging layer; The seed layer is subjected to pattern electroplating to achieve electrical connection between the second pin and the first pin.

8. The chip packaging method according to claim 7, characterized in that: The step of preparing a second plastic encapsulation layer on the RDL layer to obtain a board-level package comprises: Prepare thermally conductive copper pads on the functional surface of the grains; A PP sheet and a copper foil are sequentially arranged on the RDL layer, and pressed together to obtain a second plastic sealing layer and a copper foil layer on the surface thereof; wherein the second plastic sealing layer covers the RDL layer and the first surface of the first pin; Providing grooves on the second plastic packaging layer and the copper foil layer on the surface thereof to expose the thermal conductive copper pads; Disposing a sub-layer on the surface where the groove is located; The metal column is formed by electroplating to fill the groove, and the copper foil layer on the surface of the second plastic packaging layer is thickened by electroplating to obtain a metal layer.

9. A chip packaging structure, characterized in that: The chip packaging structure is prepared by any method of claims 1 to 8; Wherein, the chip packaging structure includes a QFN lead frame; the QFN lead frame includes a base island and a first pin; the first pin is arranged around the side of the base island; the base island and the first pin have a preset height difference.

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