A power grid synchronization frequency-locked loop based on a dual generalized integrator filter

Abstract

This invention provides a grid synchronization frequency-locked loop based on a dual generalized integrator filter (GIMF), belonging to the technical field of grid voltage and frequency signal detection and extraction. Addressing the shortcomings of conventional frequency-locked loops' poor frequency-locking performance under non-ideal grid conditions, this invention proposes a grid synchronization frequency-locked loop based on a dual GIMF. To enhance the frequency-locked loop's anti-disturbance performance, this invention designs a generalized integrator filter capable of filtering out the fundamental negative-sequence component of the grid, and thereby constructs and designs a frequency-locked loop based on the dual GIMF with DC offset cancellation function. Two frequency-locked loops based on the dual GIMF are connected in parallel to form a parallel dual GIMF frequency-locked loop. This designed frequency-locked loop is then incorporated into a three-phase grid-connected phase-locked loop (PLL), achieving the goal of accurately acquiring the grid voltage frequency and phase under non-ideal grid conditions. This invention is mainly used in grid-connected synchronization processes under non-ideal grid conditions.

Description

Technical Field

[0001] This invention belongs to the technical field of power grid voltage and frequency signal detection and extraction, and specifically relates to a power grid synchronization frequency locking loop based on a dual generalized integral filter. Background Art

[0002] Currently, to meet global energy policies, renewable energy sources have been widely integrated into the power grid through synchronous grid-connected converters. The high integration of renewable energy often results in areas with low short-circuit ratios, indicating an increase in the weak grounding of the grid. Weak grids typically refer to power systems with low short-circuit ratios, high equivalent grid impedance, significant sensitivity, and a high risk of voltage instability. In weak grids, grid information may experience smooth or abrupt changes after disturbances. For example, the grid may experience severe voltage drops, and short-circuit faults may occur in the power system, leading to drastic frequency and phase jumps. In these situations, the synchronization unit in the grid-connected converter plays a crucial role in maintaining system stability, especially under weak grid conditions where grid strength directly affects the function of the synchronization unit. Commonly used synchronization units include frequency-locked loops (LLLs) and phase-locked loops (PLLs).

[0003] However, in power grid synchronization, numerous synchronization-related problems must be addressed. One such problem is DC offset in grid voltage measurements, which has drawn attention in recent years to the design of simple, fast, and accurate frequency-locked loop (LLL) algorithms with DC offset suppression capabilities in grid-connected converters. Furthermore, harmonics during grid distortion also significantly impact grid synchronization; therefore, existing techniques for noise suppression from an LLL filtering perspective are insufficient. To enhance the noise suppression effect of LLL filters, it is necessary to develop an ideal LLL that simultaneously eliminates DC offset and harmonics. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the above-mentioned technologies and provide a power grid synchronization frequency locking loop based on a dual generalized integrator filter.

[0005] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0006] This invention proposes a power grid synchronization frequency locking loop based on a dual generalized integrator filter (DNGIF), which consists of a dual generalized integrator filter (DNGIF) and a frequency locking control unit.

[0007] The input signal u of the dual generalized integrator filter (DNGIF) is a sinusoidal signal with frequency ω, and its output signal is v. Da and v Db The synchronization error signal is ε v Synchronization error signal ε vWith one output signal v Db The product ε f The frequency error signal is used as the output of the frequency locking control unit, which is the estimated frequency. f To control the signal, an integrator with a negative feedback coefficient -γ continuously adjusts the deviation between the input signal frequency ω and the estimated frequency, thereby making the frequency error signal ε... f The input signal frequency ω is set to zero, ultimately making the input signal frequency ω equal to the estimated frequency, thus achieving frequency locking. The estimated frequency is input from the frequency locking control unit to the dual generalized integrator filter (DNGIF) as its resonant frequency. Implement frequency adaptive function.

[0008] The power grid synchronization frequency-locked loop (DNGIF) based on a dual generalized integrator filter FLL It consists of two cascaded generalized integrator filters (NGIFs) connected in parallel with a frequency-locked control unit, and its transfer function is:

[0009] and

[0010]

[0011] In the formula, u is the input of the dual generalized integrator filter, and v Da and v Db These are the two outputs of the dual generalized integrator filter. Let be the resonant frequency, s represent the s-domain, ξ is 0.7, and k is 3.

[0012] The generalized integrator filter (NGIF) consists of two integrators, two adders, four multipliers, and two constant proportional controllers. Its transfer function formula is as follows:

[0013] and

[0014]

[0015] In the formula, u is the input of the generalized integral filter (NGIF), and v a and v b These are the two outputs of the generalized integral filter (NGIF).

[0016] The beneficial effects of this invention are:

[0017] This invention proposes a power grid synchronization frequency-locking loop based on a dual generalized integrator filter. This loop can suppress DC offset and harmonics under non-ideal power grid conditions, while also significantly improving frequency locking accuracy under these conditions. Compared to other frequency-locking methods, this invention offers advantages such as a shorter adjustment cycle to power grid changes and stronger anti-interference capabilities. Attached Figure Description

[0018] Figure 1 The structure diagram of the generalized integrator filter (NGIF) provided by this invention is shown below;

[0019] Figure 2 The Bode plot of the transfer function of the generalized integrator filter (NGIF) provided by this invention;

[0020] Figure 3 The frequency-locked loop (DNGIF) based on a dual generalized integrator filter provided by this invention FLL Structural diagram;

[0021] Figure 4 The frequency-locked loop (DNGIF) based on a dual generalized integrator filter provided by this invention FLL Bode plot of the transfer function;

[0022] Figure 5 The frequency-locked loop (PDNGIF) based on parallel dual generalized integrator filters provided in this invention FLL The phase-locked loop structure diagram;

[0023] Figure 6 The frequency-locked loop (PDNGIF) based on parallel dual generalized integrator filters provided in this invention FLL Bode plot of the transfer function;

[0024] Figure 7 The PDNGIF provided by this invention FLL Bode plot of the transfer function of the filter composed of MAF;

[0025] Figure 8 This is a phase error diagram when the grid voltage undergoes a -40° phase jump in an embodiment of the present invention;

[0026] Figure 9 This is a frequency estimation diagram when the grid voltage undergoes a -40° phase jump in an embodiment of the present invention;

[0027] Figure 10 This is a phase error diagram when the grid voltage undergoes harmonic distortion and the frequency changes by +3Hz in an embodiment of the present invention;

[0028] Figure 11 This is a frequency estimation diagram when the grid voltage undergoes harmonic distortion and the frequency changes by +3Hz in an embodiment of the present invention;

[0029] Figure 12 This is a phase error diagram when different values ​​of DC offset voltage are injected into the grid voltage in an embodiment of the present invention;

[0030] Figure 13This is a frequency estimation diagram for different values ​​of DC offset voltage injected into the grid voltage in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] To make the technical problems solved by this invention, the technical solutions adopted, and the technical effects achieved clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings, not all of them.

[0032] To address the issue that conventional frequency-locked loops are easily affected by grid harmonics and DC offset voltage under non-ideal grid conditions, a grid synchronization frequency-locked loop based on a dual generalized integrator filter is proposed.

[0033] The implementation principle of this invention:

[0034] The grid synchronization frequency-locking loop based on the dual generalized integrator filter (DNGIF) consists of a dual generalized integrator filter (DNGIF) and a frequency-locking control unit.

[0035] The input signal u of the dual generalized integrator filter (DNGIF) is a sinusoidal signal with frequency ω, and its output signal is v. Da and v Db The synchronization error signal is ε v Synchronization error signal ε v With one output signal v Db The product ε f The frequency error signal is used as the output of the frequency locking control unit, which is the estimated frequency. f To control the signal, an integrator with a negative feedback coefficient -γ continuously adjusts the deviation between the input signal frequency ω and the estimated frequency, thereby making the frequency error signal ε... f The input signal frequency ω is set to zero, ultimately making the input signal frequency ω equal to the estimated frequency, thus achieving frequency locking. The estimated frequency signal is input to the dual generalized integrator filter (DNGIF) by the frequency locking control unit as its resonant frequency. Implement frequency adaptive function.

[0036] Under harsh, non-ideal grid conditions, conventional three-phase synchronous frequency-locking loops typically lack harmonic and DC offset voltage suppression capabilities, resulting in decreased frequency-locking accuracy. To overcome these problems under non-ideal grid conditions, this invention proposes a grid synchronous frequency-locking loop based on a dual generalized integrator filter (NGIF). First, a generalized integrator filter (NGIF) is proposed, and a frequency-locking loop based on a dual generalized integrator filter (DNGIF) is constructed and designed based on the NGIF. FLLThe frequency-locking loops of two dual generalized integrator filters are connected in parallel to form a parallel dual generalized integrator filter frequency-locking loop (PDNGIF). FLL ), will design PDNGIF FLL Integrating it into a QT1 type three-phase grid-connected phase-locked loop (PLL) achieves the goal of accurately obtaining the grid voltage frequency and phase under non-ideal grid conditions. The specific implementation steps are as follows:

[0037] 1) Implementation of Generalized Integral Filter

[0038] Since the fundamental negative-sequence component severely affects the frequency locking accuracy of the frequency-locking loop, it is necessary to effectively filter out the fundamental negative-sequence component and accurately extract the fundamental positive-sequence component. To achieve this, this invention proposes a generalized integral filter (NGIF), the structure of which is as follows: Figure 1 As shown;

[0039] Depend on Figure 1 The transfer function expression for NGIF can be obtained as follows:

[0040]

[0041] Where u is the input of NGIF, v a and v b For NGIF, ξ is 0.7, and k is 3. The Bode plots for NGIF-a and NGIF-b are as follows: Figure 2 As shown. From... Figure 2 It can be observed that NGIF-a can be regarded as a bandpass filter, and at frequency At that point, NGIF-a has a gain of 0dB and a phase of 0. Furthermore, NGIF-b can also be considered a low-pass filter at a frequency of... There is a 90° phase difference between NGIF-a and NGIF-b. Since NGIF-a has bandpass filter performance, and the DC offset component is concentrated at 0Hz in the αβ coordinate system, and the gain of NGIF-a at 0Hz is approximately -30dB, it can be assumed that NGIF-a can attenuate the DC component to zero. However, the gain of NGIF-b at 0Hz is approximately 0dB, therefore NGIF-b cannot filter out the DC component. Thus, NGIF-b may not be able to filter out the DC offset voltage.

[0042] 2) Implementation of frequency-locked loop based on dual generalized integrator filter

[0043] To eliminate the influence of DC offset components in the power grid on frequency locking accuracy and further improve the dynamic convergence time of the frequency locking loop, this invention proposes a frequency locking loop (DNGIF) based on dual generalized integrator filters by cascading two generalized integrator filters and combining them with a frequency locking control unit. FLL Its structure is as follows: Figure 3 As shown;

[0044] Figure 3 In DNGIF FLL The structure consists of two NGIF modules and one frequency-locked control unit. In the diagram, u represents the input signal; v Da and v Db ε is the output signal of the dual generalized integrator filter; k is the gain coefficient. v As the synchronization error signal, ε v With v b The product ε f The signal is the frequency error signal; γ is the feedback coefficient. The frequency of the input signal detected by the frequency-locked loop (FLL);

[0045] DNGIF can be obtained through calculation. FLL The transfer function is as follows:

[0046]

[0047] k is also taken as 3, DNGIF FLL-a and DNGIF FLL-b The Bode plot is as follows Figure 4 As shown. From... Figure 4 It can be observed that DNGIF FLL-a It can be considered as a bandpass filter, and at frequency DNGIF FLL-a The gain is 0dB and the phase is 0. Furthermore, DNGIF... FLL-b It can also be regarded as a bandpass filter, at frequency DNGIF FLL-a There is a 90° phase difference. Due to DNGIF FLL-a and DNGIF FLL-b Both possess bandpass filter performance, and their DC offset components are concentrated at 0Hz in the αβ coordinate system, while DNGIF... FLL-a and DNGIF FLL-b The gain values ​​at 0Hz are very low, which means they can be considered to attenuate the DC component to 0.

[0048] 3) Implementation of a phase-locked loop based on a parallel dual generalized integrator filter frequency-locked loop

[0049] Typically, frequency-locked loops (LLLs) can be used as pre-filters for phase-locked loops (PLLs) to extract the fundamental positive-sequence component. To reduce the interference of the fundamental negative-sequence component on the PLL's phase-locking accuracy in the αβ coordinate system, this invention employs a conventional method to combine two DNGIFs... FLL The parallel dual generalized integrator filter (PDNGIF) is proposed by combining parallel and cross operations. FLL )structure;

[0050] The proposed PDNGIF FLL By applying the structure to the control outer loop in a QT1-PLL, the phase-locked loop (PDNGIF) proposed in this invention can be obtained. FLL -PLL) structure, such as Figure 5 As shown. Figure 5 You can get PDNGIF FLL The operation expression is as follows

[0051]

[0052] Where v α v β， These are the α-axis and β-axis components of the input signal, respectively. and These represent the α-axis and β-axis components of the output signal containing the fundamental positive-sequence voltage component, respectively. To extract the fundamental positive-sequence component, a symmetric component method is used in the αβ coordinate system, implemented using the corresponding FPSC structure shown in the figure.

[0053] According to complex filter theory, PDNGIF FLL The mathematical expressions for the real and imaginary parts of the transfer function are as follows:

[0054]

[0055] From the above two equations, we can obtain PDNGIF. FLL The transfer function is

[0056]

[0057] Based on formula (8), PDNGIF is plotted. FLL The Bode plot of (s) is as follows Figure 4 As shown, k is 3 here;

[0058] observe Figure 4 It can be seen that, in the αβ coordinate system, PDNGIF FLL (s) The amplification factor at -50Hz is -∞, and the amplification factor at 0Hz is also -∞, indicating that the fundamental negative sequence component and DC offset component in the grid voltage can be amplified by PDNGIF. FLL (s) Suppression. PDNGIF at 50Hz FLL (s) The magnification is 0, which corresponds to a phase of 90°. This means that PDNGIF FLL (s) can accurately extract the fundamental positive sequence component, and the resulting -90° phase lag can be corrected by -90° phase compensation.

[0059] The phase-locked loop proposed in this invention is based on the QT1-PLL design. The inner loop of the QT1-PLL uses an average value filter (MAF) as its filter, while its control part uses a simplified proportional controller k. p Control is performed. The transfer function of the MAF is... In the formula T ω The time window parameter is set to 0.0033s in this invention.

[0060] Depend on Figure 5 It can be seen that the PDNGIF proposed by this invention FLL The transfer function of the filter composed of MAF is

[0061]

[0062] Based on formula (9), PDNGIF is plotted. FLL The Bode plot of the filter composed of MAF is as follows Figure 7 As shown. Figure 7 It can be seen that, in the dq coordinate system, the amplification factor of the filter is -∞ at -100Hz and also -∞ at 50Hz, indicating that the fundamental negative sequence component and DC offset component in the grid voltage can be filtered by PDNGIF. FLL Suppression. The amplification factor at -600Hz, -300Hz, 300Hz, and 600Hz is also -∞, indicating that it can filter out the main subharmonic voltages in the power grid. The filter amplification factor at 50Hz is 0, and its corresponding phase is such that the fundamental positive sequence component can be accurately and completely extracted, indicating that it can achieve the task of completely extracting the fundamental positive sequence component.

[0063] Thus, the structural design of the phase-locked loop based on the parallel dual generalized integrator filter frequency-locked loop is completed.

[0064] The following are specific implementation examples:

[0065] To verify the proposed PDNGIF FLL The effectiveness and superiority of the PLL were demonstrated through simulation analysis using MATLAB / Simulink. The simulation parameters were: rated amplitude of 1 p.u. for each phase voltage of the grid, rated grid voltage frequency of 50 Hz, and sampling period of 100 μs. To better simulate grid-connected fault environments, three operating conditions were set up: phase jump, frequency abrupt change under voltage distortion conditions, and DC offset voltage injection. Furthermore, to more comprehensively showcase PDNGIF... FLL The performance advantages of the PLL were verified through comparative experiments with DSOGI-PLL and MAF-PLL. The PDNGIF proposed in this invention... FLL- The PI control parameter of the PLL is k p =74.

[0066] The specific implementation results are as follows:

[0067] Figure 8 and Figure 9 These are the phase error and frequency estimation diagrams for a -40° phase jump in the grid voltage according to an embodiment of the present invention. Figure 8 and Figure 9 As can be seen, the PDNGIF proposed in this invention... FLL The transient settling times used by -PLL and DSOGI-PLL are basically the same, while the transient settling time of MAF-PLL is relatively long, and its excessively long dynamic response time cannot meet the grid connection requirements. Furthermore, regarding... Figure 8 As can be seen from the curves, the overshoot of DSOGI-PLL is much greater than that of the PDNGIF proposed in this invention. FLL -PLL, therefore PDNGIF FLL -PLL has better performance.

[0068] Figure 10 and Figure 11 These are the phase error and frequency estimation diagrams in the embodiments of the present invention when the grid voltage undergoes harmonic distortion and the frequency changes by +3Hz. Figure 10 and Figure 11 It can be seen that, due to PDNGIF FLL The filter units of the -PLL and MAF-PLL have harmonic cancellation capabilities, resulting in smoother curves. However, the DSOGI-PLL lacks harmonic cancellation, causing fluctuations in both its estimated frequency and phase error curves, indicating that it cannot function properly under these conditions. Furthermore, the figure also shows that the PDNGIF... FLL -PLL's dynamic settling time is significantly better than MAF-PLL's due to its superior performance.

[0069] Figure 12 and Figure 13 These are phase error and frequency estimation diagrams for different values ​​of DC offset voltage injected into the grid voltage in embodiments of the present invention. Figure 12 and Figure 13 It can be seen that, due to PDNGIF FLL Both the -PLL and MAF-PLL filter units have DC offset cancellation functionality, resulting in smoother frequency and phase estimation curves, indicating their ability to eliminate the impact of DC offset on the phase-locked loop (PLL) function. However, the DSOGI-PLL lacks DC offset cancellation, leading to significant oscillations in its frequency and phase estimation curves, thus preventing it from performing PLL functionality under these conditions. Furthermore, through... Figure 13 It can also be seen that the PDNGIF proposed in this inventionFLL - The adjustment time used by the PLL is relatively short. Therefore, this invention demonstrates the effectiveness of the PDNGIF proposed in this paper. FLL -PLL has the best performance.

[0070] pass Figures 8-13 The comparison shows that the phase-locked loop based on the dual generalized integrator filter frequency-locked loop proposed in this invention has good performance in terms of filtering capability and dynamic tracking of grid frequency and phase. It can eliminate the influence of harmonics and DC offset under non-ideal grid conditions and is suitable for grid-connected synchronous applications.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.

Claims

1. A power grid synchronization frequency-locked loop based on a dual generalized integrator filter, characterized in that: The power grid synchronization frequency-locking loop based on the dual generalized integrator filter (DNGIF) consists of a dual generalized integrator filter (DNGIF) and a frequency-locking control unit. The input signal u of the dual generalized integrator filter (DNGIF) is a sinusoidal signal with frequency ω, and its output signal is v. Da and v Db The synchronization error signal is ε v Synchronization error signal ε v With one output signal v Db The product ε f The frequency error signal is the output of the frequency locking control unit, which is the estimated frequency. The frequency locking control unit uses the frequency error ε as the frequency error signal. f To control the signal, an integrator with a negative feedback coefficient -γ continuously adjusts the deviation between the input signal frequency ω and the estimated frequency, thereby making the frequency error signal ε... f The frequency is equal to zero, ultimately making the input signal frequency ω equal to the estimated frequency, thus achieving frequency locking. The estimated frequency is input to the dual generalized integrator filter (DNGIF) by the frequency locking control unit as its resonant frequency. Implement frequency adaptive function; The dual generalized integrator filter (DNGIF) is composed of two generalized integrator filters (NGIF) cascaded together. The power grid synchronization frequency-locked loop (DNGIF) based on a dual generalized integrator filter FLL Its transfer function is and In the formula, u is the input of the dual generalized integrator filter, and v Da and v Db These are the two outputs of the dual generalized integrator filter. Let be the resonant frequency, s represent the s-domain, ξ is 0.7, and k is 3.

2. The power grid synchronization frequency-locked loop based on a dual generalized integrator filter according to claim 1, characterized in that: The generalized integrator filter (NGIF) consists of two integrators, two adders, four multipliers, and two constant proportional controllers. Its transfer function formula is as follows: and In the formula, u is the input of the generalized integral filter (NGIF), and v a and v b These are the two outputs of the generalized integral filter (NGIF).

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