Double-sided stacked fan-out packaging device and preparation method thereof

Abstract

The present invention discloses a double-sided stacked fan-out packaging device and a preparation method thereof, wherein the packaging device comprises a substrate with through holes; a stacked chip; an encapsulation material layer; a rewiring layer located on the encapsulation material layer; a first conductive structure, wherein the chip located on the first surface is electrically connected to the rewiring layer through the first conductive structure; and a second conductive structure that runs through the thickness direction of the substrate, wherein at least a portion of the second conductive structure is disposed in at least a portion of the through holes of the substrate, and the second conductive structure electrically connects the rewiring layers on the first surface and the second surface of the substrate. The solution of the embodiment of the present invention electrically connects the chips mounted on the two surfaces of the substrate through the second conductive structure disposed on the substrate. Compared with the TSV packaging process, it avoids making silicon through vias on the chip, reduces the packaging cost, and can effectively improve the packaging yield. Compared with the wire bonding packaging process, it avoids interconnecting the chips through a carrier and wires, thereby improving the transmission efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a double-sided stacked fan-out packaging device and a preparation method thereof. Background Art

[0002] With the development of science and technology, the amount of data transmission is becoming increasingly huge, which leads to an increasing demand for the capacity of electronic device memory. In order to meet the needs of high data transmission capacity and large storage capacity, the memory also needs to have a higher bandwidth and lower power consumption. In order to increase the bandwidth of the memory, the industry currently usually uses 3D stacking bonding packaging technology to prepare the packaging structure of the memory chip.

[0003] Among them, in the 3D stacking bonding packaging process, chip stacking is a more common packaging form, which stacks multiple chips by stacking bonding to form a chip packaging structure with higher interconnection density and performance. In the chip stacking packaging process, there are currently two more common ways to achieve interconnection between stacked chips: one is to bond the stacked chips layer by layer through wires on four sides, such as the packaging process used by LPDDR; the other is to interconnect the stacked chips through TSV (through silicon via) technology, such as the packaging process used by HBM. However, the method of interconnecting chips through wire bonding is prone to problems such as long signal transmission delay and limited bandwidth due to the long total length of the wires and the carrier board circuits, and this bonding method is costly and has poor heat dissipation. The TSV technology for chip interconnection requires the preparation of through silicon vias (TSV) and micro copper pillars on the chip. The process is complex and the packaging yield is low. In addition, the packaging process based on TSV technology also requires expensive materials such as NCF (non-conductive film) or NCP (non-conductive adhesive) and TCB bonder (thermal compression bonding equipment). The process cost is very high, the chip stacking bonding speed is extremely slow, and the overall packaging efficiency is also low. Summary of the invention

[0004] The embodiment of the present invention provides a new three-dimensional stacked fan-out packaging solution, which does not require the preparation of TSV vertical interconnect lines, nor does it require leads and carrier circuits. Therefore, it can further reduce packaging costs and improve packaging yield while ensuring high interconnection density and transmission performance.

[0005] In a first aspect, an embodiment of the present invention provides a double-sided stacked fan-out packaging device, comprising:

[0006] A substrate with a through hole, wherein stacked chips are arranged on a first surface and a second surface of the substrate;

[0007] an encapsulation material layer, which fills at least a portion of the through hole and encapsulates the chip and the substrate;

[0008] a redistribution layer located on the encapsulation material layer and electrically connected to the chip;

[0009] a first conductive structure in the encapsulation material layer on the first surface, wherein the chip on the first surface is electrically connected to the redistribution layer on the first surface through the first conductive structure;

[0010] A second conductive structure that penetrates the substrate in a thickness direction, wherein at least a portion of the second conductive structure is disposed in at least a portion of the through-holes of the substrate, and the second conductive structure electrically connects the rewiring layers of the first surface and the second surface of the substrate;

[0011] A package external pin pad disposed on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer; and

[0012] A BGA solder ball or a solder chip pin bump disposed on the package external pin pad and electrically connected to the package external pin pad.

[0013] In a second aspect, an embodiment of the present invention provides a method for preparing a double-sided stacked fan-out packaging device, comprising:

[0014] At least one layer of chips is mounted on the chip mounting areas on the first surface and the second surface of the substrate by stacking, wherein the substrate is provided with through holes penetrating the thickness direction of the substrate;

[0015] Covering a chip mounted on one surface of the substrate with a protective layer;

[0016] Using an encapsulation material to perform plastic encapsulation on a side of the substrate away from the protective layer, wherein during the plastic encapsulation process, the encapsulation material can flow through the through hole to the side of the substrate provided with the protective layer, so that the chips mounted on the two surfaces of the substrate can be simultaneously plastic encapsulated through a one-time plastic encapsulation process, wherein after the one-time plastic encapsulation process, the substrate and the chips mounted on the two surfaces of the substrate are all encapsulated by the encapsulation material except for the chip surface covered by the protective layer, and the through hole of the substrate is also filled with the encapsulation material;

[0017] Preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure located in the encapsulation material layer on the first surface and electrically connected to the chip mounted on the first surface, and a second conductive structure located in the encapsulation material of the through hole and penetrating the thickness direction of the substrate;

[0018] Removing the protective layer, wherein after removing the protective layer, the surface of the chip covered by the protective layer is exposed on the surface of the encapsulation material;

[0019] Prepare a rewiring layer electrically connected to the mounted chip through the conductive structure on the surface of the encapsulation material, wherein the rewiring layers on the first surface and the second surface of the substrate are electrically connected through the second conductive structure;

[0020] Preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer;

[0021] Prepare BGA solder balls or solder chip pin bumps on the package external pin pads.

[0022] In a third aspect, an embodiment of the present invention provides another method for preparing a packaged device, comprising:

[0023] Preparing a first through hole and a second through hole on the substrate, and preparing a conductive column in the first through hole;

[0024] At least one layer of chips is mounted on the chip mounting areas on the first surface and the second surface of the substrate respectively by stacking.

[0025] Covering a chip mounted on one surface of the substrate with a protective layer;

[0026] Using an encapsulation material to perform plastic encapsulation on a side of the substrate away from the protective layer, wherein during the plastic encapsulation process, the encapsulation material can flow through the second through hole to the side of the substrate provided with the protective layer, so that the chips mounted on the two surfaces of the substrate can be simultaneously plastic encapsulated through a single plastic encapsulation process, wherein after the single plastic encapsulation process, the substrate and the chips mounted on the two surfaces of the substrate are all encapsulated by the encapsulation material except for the chip surface covered by the protective layer, and the second through hole of the substrate is also filled with the encapsulation material;

[0027] Removing the protective layer, wherein after removing the protective layer, the surface of the chip covered by the protective layer is exposed on the surface of the encapsulation material;

[0028] Preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure located in the encapsulation material layer on the first surface and electrically connected to the chip mounted on the first surface, and a second conductive structure penetrating the thickness direction of the substrate, wherein the second conductive structure is located in a conductive column segment in the first through hole and an interconnection line segment located in the encapsulation material layer and electrically connected to the corresponding conductive column segment;

[0029] Prepare a rewiring layer electrically connected to the mounted chip through the conductive structure on the surface of the encapsulation material, wherein the rewiring layers on the first surface and the second surface of the substrate are electrically connected through the second conductive structure;

[0030] Preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer;

[0031] Prepare BGA solder balls or solder chip pin bumps on the package external pin pads.

[0032] The beneficial effects of the embodiments of the present invention are as follows: the solution provided by the embodiments of the present invention has stacked chips on both the first surface and the second surface of the substrate, thereby reducing the substrate warping caused by single-sided mounting during the preparation process, and improving the packaging yield and device stability of the packaged device; and, the solution of the embodiments of the present invention is to electrically connect the chips mounted on the two surfaces of the substrate through a second conductive structure arranged on the substrate and running through the thickness direction of the substrate, that is, the second conductive structure is directly and completely prepared in the encapsulation material of the through hole on the substrate (such as the preparation method described in the second aspect above) or the second conductive structure is that its conductive column section is prepared in the first through hole on the substrate, and its interconnection line section is prepared in the encapsulation material (such as the preparation method described in the third aspect above), thereby, compared with the existing TSV packaging process, it avoids the production of silicon-through-via vertical interconnection conductive channels on the chip by TSV technology, reduces the packaging cost, and can effectively improve the packaging yield, and compared with the existing wire bonding packaging process, it avoids the interconnection of chips through the carrier and the wires, shortens the data transmission time, and improves the transmission efficiency of the packaged device. Moreover, the embodiment of the present invention can realize one-time double-sided plastic sealing from the other side by covering one side of the substrate with a protective layer by opening a through hole on the substrate. Therefore, in the embodiment of the present invention, the substrate is tightly fixed in the packaging structure through the encapsulation material layer as a permanent substrate, so it is no longer necessary to peel off the substrate in the subsequent process, so the substrate can provide better mechanical strength support for the packaging structure, which further ensures the reliability of the packaging structure and simplifies the packaging process steps. At the same time, since the substrate in the embodiment of the present invention exists as a permanent substrate, the stacked chips in the embodiment of the present invention are directly mounted on the two surfaces of the substrate. Therefore, the solution of the embodiment of the present invention also avoids the process of using expensive NCF or NCP materials for filling and using expensive TCB equipment for debonding, further simplifies the packaging process steps and reduces the packaging cost. In addition, since the packaging structure prepared by the embodiment of the present invention in a three-dimensional stacking manner can integrate the required chips (including chip functions and chip quantity) according to the requirements, and the chips can be interconnected with high density through the first and second conductive structures and the rewiring layer, the preparation cost is low, and the prepared packaging device has a high transmission bandwidth and transmission rate, which can be widely used in memory. In the implementation case of the present invention, there are only through holes or vertical interconnection conductive columns on the substrate, and no interconnection lines need to be prepared. Compared with the substrate for wire bonding packaging (containing fine through-layer interconnection lines), the process is simple and the cost is low.Due to these characteristics of the substrate of the embodiment of the present invention, in a preferred embodiment, the substrate of the embodiment of the present invention can also be prepared with thicker thermal conductive materials, such as metal (copper, aluminum, etc.), ceramic (aluminum oxide, aluminum nitride, silicon carbide, etc.), composite materials (double-sided copper clad plates used in various printed circuit board industries, etc.), which has better heat dissipation effect than HBM packaging and wire bonding packaging processes. In addition, traditional packaging, HBM or wire bonding process packaging usually requires plastic sealing on both sides separately. In this plastic sealing method, after plastic sealing on one side, the warping degree of the packaging structure will be very large, which may easily lead to the inability to perform subsequent processes, and even lead to the inability to perform plastic sealing next time. In comparison, in the preparation process of the implementation case of the present invention, a protective layer is used to protect the chip on one side. Combined with the design of the through hole, the solution of the embodiment of the present invention can realize one-time double-sided plastic sealing on the other side, that is, only one plastic sealing on the other side can complete the plastic sealing on both sides at the same time, so that there is basically no substrate warping problem after plastic sealing, which reduces the difficulty of subsequent processes and reduces costs. In addition, the preparation process of the embodiment of the present invention also avoids the expensive temporary bonding materials and temporary bonding carriers used in the HBM packaging process, reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying any creative work.

[0034] Figure 1 Schematically shows a vertical cross-sectional view of a double-sided stacked fan-out packaging device according to an embodiment of the present invention;

[0035] Figure 2 A vertical cross-sectional view schematically shows a double-sided stacked fan-out packaging device according to another embodiment of the present invention;

[0036] Figure 3 A vertical cross-sectional view schematically shows a double-sided stacked fan-out package device according to another embodiment of the present invention;

[0037] Figure 4 Schematically showing a vertical cross-sectional view of a double-sided stacked fan-out packaging device according to yet another embodiment of the present invention;

[0038] Figure 5 Schematically shows an embodiment of the present invention Figure 4 A top view of a substrate used in the packaged device shown;

[0039] Figure 6Schematically shows a vertical cross-sectional view of a three-dimensional stacked fan-out packaging device according to an embodiment of the present invention;

[0040] Figure 7 Schematically shows an embodiment of the present invention Figure 1 A flow chart of a method for preparing a packaged device shown;

[0041] Figure 8 A vertical cross-sectional view of a chip structure before preparing pin bumps according to an embodiment of the present invention is schematically shown;

[0042] Fig. 9 A vertical cross-sectional view of a chip structure obtained after preparing pin bumps according to an embodiment of the present invention is schematically shown;

[0043] Fig.10 A vertical cross-sectional view of a chip structure before preparing pin bumps according to an embodiment of the present invention is schematically shown;

[0044] Fig.11 A vertical cross-sectional view of a chip structure obtained after preparing pin bumps according to an embodiment of the present invention is schematically shown;

[0045] Fig.12 A vertical cross-sectional view of a substrate obtained after a through hole is prepared on the substrate according to one embodiment of the present invention is schematically shown;

[0046] Fig.13 A vertical cross-sectional view of a package structure obtained after double-sided mounting of a chip on a substrate according to an embodiment of the present invention is schematically shown;

[0047] Fig.14 A vertical cross-sectional view of a package structure obtained after a chip on one side of a substrate is covered with a protective layer according to an embodiment of the present invention is schematically shown;

[0048] Fig.15 A vertical cross-sectional view of a packaging structure obtained after plastic packaging according to an embodiment of the present invention is schematically shown;

[0049] Fig.16 A vertical cross-sectional view of a packaging structure after blind vias and through vias are prepared according to an embodiment of the present invention is schematically shown;

[0050] Fig.17 A vertical cross-sectional view of a packaging structure after removing the protective layer according to an embodiment of the present invention is schematically shown;

[0051] Fig.18 A vertical cross-sectional view of a packaging structure after preparing a redistribution layer and packaging external pin pads according to an embodiment of the present invention is schematically shown;

[0052] Fig.19 A vertical cross-sectional view of a packaging structure obtained after preparing a BGA solder ball according to an embodiment of the present invention is schematically shown;

[0053] Fig. 20 A flow chart of a method for preparing a double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown;

[0054] Fig.21 schematically illustrates a vertical cross-sectional view of a substrate in some embodiments;

[0055] Fig. 22 A vertical cross-sectional view of a package structure obtained after mounting a chip on a substrate in some embodiments is schematically shown;

[0056] Fig.23 A vertical cross-sectional view of a package structure obtained after a chip on one side of a substrate is covered with a protective layer according to another embodiment of the present invention is schematically shown;

[0057] Fig.24 A vertical cross-sectional view of a package structure obtained after plastic encapsulation in some embodiments is schematically shown;

[0058] Fig.25 A flow chart of a method for preparing a double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown;

[0059] Fig.26 A vertical cross-sectional view of a packaging structure obtained after a protective layer is covered on a chip on one side of a substrate according to another embodiment of the present invention is schematically shown;

[0060] Fig. 27 A vertical cross-sectional view of a packaging structure after removing the protective layer according to another embodiment of the present invention is schematically shown;

[0061] Fig.28 A vertical cross-sectional view of a packaging structure obtained after preparing a third conductive structure according to an embodiment of the present invention is schematically shown;

[0062] Fig.29 A flow chart of a method for preparing a double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown;

[0063] Fig.30 schematically illustrates a vertical cross-sectional view of a substrate in some embodiments;

[0064] Fig.31A vertical cross-sectional view of a packaging structure obtained after a protective layer is covered on a chip on one side of a substrate according to another embodiment of the present invention is schematically shown;

[0065] Fig.32 A vertical cross-sectional view of a packaging structure obtained after preparing a conductive structure according to another embodiment of the present invention is schematically shown;

[0066] Fig.33 A vertical cross-sectional view of a substrate in some embodiments is schematically illustrated. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0069] It should also be noted that the terms used in this application are generally terms commonly used by those skilled in the art. If there is any inconsistency with the commonly used terms, the terms in this application shall prevail.

[0070] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only the way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. Moreover, the terms "include", "comprise", not only include those elements, but also include other elements that are not clearly listed, or also include elements inherent to such processes, methods, articles or equipment. In the absence of more restrictions, the elements limited by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0071] In this article, the term "chip" refers to any type of semiconductor chip (chip) or integrated circuit chip that implements a specific function, and also refers to any type of semiconductor die (die) or integrated circuit die that implements a specific function, which can be a single-layer chip or a vertically interconnected stacked chip.

[0072] Herein, the term "functional surface" refers to a surface of a chip where pin pads are arranged, and the term "non-functional surface" refers to another surface opposite to the functional surface.

[0073] In this article, the term "first surface" is only used to describe the surface of the substrate facing the package pin pad, and the term "second surface" is only used to describe the surface of the substrate away from the package pin pad. Therefore, it can be understood that when the setting position of the package pin pad changes, the position referred to by the first surface will also change accordingly, that is, the "first surface" should not be limited to the specific surface shown in the accompanying drawings.

[0074] In this article, the term "bottom chip" refers to the layer of chips in the area for mounting chips that is close to the substrate, the term "top chip" refers to the layer of chips that is farthest from the corresponding substrate surface and is stacked in the direction away from the substrate surface, and the term "upper chip" refers to the layers of chips that are stacked in the direction away from the substrate and located between the bottom chip and the top chip, which can refer to the layer of chips directly mounted on the bottom chip or the layer of chips mounted on a certain upper chip. For example, if four layers of chips are stacked on a certain surface of the substrate, such as the first surface, the bottom chip on this surface refers to the first layer of chips close to the surface of the substrate, the top chip refers to the fourth layer of chips farthest from the surface of the substrate, and the upper chip can refer to any layer of chips between the first layer chip and the fourth layer chip.

[0075] Herein, the term "bottom" refers to a direction toward a substrate surface, and "upper" refers to a direction away from a substrate surface.

[0076] By assembling individually designed computing units or functional units through advanced packaging technology, it is not only possible to ensure the yield of each unit by selecting the most suitable semiconductor process technology for each unit, but also to effectively reduce the design and manufacturing costs of the chip and shorten the chip R&D cycle. Among them, the three-dimensional stacking packaging process has attracted widespread attention because it can provide integrated chips with high interconnection density, high performance, low power consumption and high transmission rate. However, the current three-dimensional stacking packaging process mainly uses TSV interconnection technology and lead interconnection technology to achieve interconnection between stacked chips. Both TSV interconnection technology and lead interconnection technology have the problems of complex packaging process and high cost, and TSV interconnection technology will also lead to low packaging yield, while lead interconnection technology will also lead to low transmission rate. Based on this, the embodiment of the present invention aims to provide a new three-dimensional stacking packaging technology solution to reduce packaging costs, improve packaging yield and simplify packaging process while ensuring high chip interconnection density and integration and high data transmission rate.

[0077] The solution provided by the embodiment of the present invention will be described in detail below from the perspective of the structure of the packaging device.

[0078] Figure 1 A vertical cross-sectional view of a double-sided stacked fan-out packaging device 100 according to an embodiment of the present invention is schematically shown. Figure 1 As shown, the package device 100 provided by the embodiment of the present invention includes a substrate 1, chips 2 stacked on the first surface 2A and the second surface 1A of the substrate 1, respectively, an encapsulation material layer 4 coated on the substrate 1 and the chip 2, a rewiring layer 5 located on the encapsulation material layer 4, an external package pin pad 51 provided on the rewiring layer 5, and a solder ball 6 provided on the external package pin pad 51. Among them, pin pads 21 are provided on the functional surface of the chip 2. In a preferred embodiment, pin bumps can be provided on at least part of the pin pads 21 of at least part of the chip 2 for electrical connection of the corresponding chip, especially to electrically connect the chips of other layers other than the topmost chip, such as the bottom chip and the upper chip, with the rewiring layer. Figure 1As shown, in this embodiment, the stacked chips mounted on each surface of the substrate are two layers, and pin bumps 22 are set on part of the pin pads of the bottom chip 20, so that the bottom chip 20 can achieve electrical communication with the rewiring layer 5 through the pin bumps 22, so that the bottom chip 20 can achieve electrical communication with the outside through the rewiring layer 5 and the package external pin pads 51. The rewiring layer 5 includes an insulating material 8-0 and a package interconnection line 8-1 formed in the insulating material 8-0, wherein the package interconnection line is electrically connected to the pin bump 22 and / or the pin pad 21 of the chip through a conductive structure, and the package external pin pad 51 is located on the surface of the insulating material 8-0, which is electrically connected to at least part of the conductive structure through the package interconnection line of the rewiring layer, so that the package external pin pad 51 can achieve electrical communication with the pin bump 22 and / or the pin pad 21 of the chip through the package interconnection line and the conductive structure. The solder balls 6 are disposed on the package external pin pads 51 to achieve electrical conduction with the chip via the package external pin pads 51. In the package device 100 of the embodiment of the present invention, in particular, Figure 1 As shown, the conductive structure includes a first conductive structure 7 in the encapsulation material layer 4 on the first surface 2A and a second conductive structure 8 that runs through the thickness direction of the substrate, wherein the chip 2 on the first surface 2A is electrically connected to the package interconnection line in the rewiring layer 5 on one side of the first surface 2A through the first conductive structure, and the package interconnection line in the rewiring layer on the first surface 2A and the second surface 1A of the substrate is electrically connected through the second conductive structure 8. As a possible implementation, Figure 1 As shown, the chip 2 located on the second surface 1A can be directly electrically connected to the package interconnection line in the rewiring layer 5 on one side of the second surface 1A. Thus, the chip on the first surface of the substrate of the embodiment of the present invention can be electrically connected to the package external pin pad through the first conductive structure and the rewiring layer, and the chip on the second surface of the substrate can be electrically connected to the package external pin pad through the rewiring layer and the second conductive structure, so as to electrically connect the chips stacked on the two surfaces of the substrate with the outside, and also electrically connect the chips stacked on the two surfaces of the substrate, so as to use the stacked chips to provide the required functions for the corresponding application scenarios, such as storage capacity, computing power and data transmission capacity. Since the packaged device of this structure does not need to prepare silicon through vias on the chip, and does not need to interconnect the chips through leads and carriers, its data transmission rate and package yield are relatively high, and the package cost is also lower. In addition, since the packaged device of this structure contains a substrate as a support, the overall mechanical strength is higher, and it can be packaged on both sides of the substrate, and the chip integration is higher.

[0079] As a possible implementation, Figure 1As shown, the second conductive structure 8 on the substrate 1 is arranged in the encapsulation material 41 of the through hole 1-1 on the substrate. In this embodiment, each through hole on the substrate is used as both a circulation channel for the encapsulation material and a preparation channel for the second conductive structure. Therefore, all the through holes 1-1 on the substrate in this embodiment are filled with the encapsulation material 41 of the encapsulation material layer 4. The second conductive structure 8 can be arranged in the encapsulation material of each through hole to reduce the preparation cost of the second conductive structure and improve the packaging yield. Specifically, the through hole 1-1 opened on the substrate 1 is a through hole in the thickness direction of the substrate, which forms a fluid-connected space between the two surfaces of the substrate 1. Therefore, the setting of the through hole 1-1 also enables the encapsulation material layer 4 in the packaged device 100 of the embodiment of the present invention to be prepared at one time on one side of the substrate 1, that is, the two sides of the substrate are simultaneously encapsulated by one-time encapsulation, so as to further simplify the packaging process steps, reduce the cost of preparing the packaged device 100 and ensure the reliability of the packaged device.

[0080] Figure 2 A double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown. Figure 2 As shown, it is Figure 1 The difference between the packaged device shown in the figure is that, in this embodiment, the packaged device further comprises an insulating material layer 33 located on the second surface 1A of the substrate 1 and a third conductive structure 9 located in the insulating material layer 33, wherein the chip 2 located on the second surface 1A is electrically connected to the rewiring layer 5 on the second surface 1A through the third conductive structure 9. That is, in Figure 1 In the embodiment shown, the encapsulation material layer 4 of the second surface 1A is flush with the upper surface of the uppermost chip on the second surface, so the chip on the second surface 1A is directly electrically connected to the package interconnection line of the rewiring layer 5 on the second surface through its pin pads or pin bumps. Figure 2 In the illustrated embodiment, the insulating material layer 33 of the second surface 1A completely encapsulates the topmost chip on the second surface, so that the pin pads or pin bumps of the chip on the second surface 1A are electrically connected to the package interconnection lines of the redistribution layer 5 on the second surface through the third conductive structure 9.

[0081] Figure 3 A double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown. Figure 3 As shown, it is Figure 1The difference between the packaged devices shown is that, in this embodiment, a step structure 11 is further provided on the substrate 1, which is lower than the area for mounting the chip, so that the encapsulation material is more firmly fixed around the through hole to improve the reliability of the packaged device. In other embodiments, the step structure can also be set higher than the area for mounting the chip, that is, the area for mounting the chip on the substrate is designed as a concave structure to facilitate rapid mounting of the chip and reduce the size of the packaged device.

[0082] Figure 4 A double-sided stacked fan-out packaging device according to another embodiment of the present invention is schematically shown. Figure 4 As shown, it is Figure 1 The difference between the packaged device shown is that, in this embodiment, the through holes on the substrate include a first through hole 110 used as a preparation channel for the second conductive structure and a second through hole 111 used as a circulation channel for the encapsulation material, that is, there are two types of through holes on the substrate shown in this embodiment, one type of through hole has an electrical connection function, and the other type of through hole does not have an electrical connection function. Among them, the second conductive structure 8 includes a conductive column segment 80 located in the first through hole 110 and an interconnection line segment 81 located in the encapsulation material layer 4 and electrically connected to the corresponding conductive column segment 80. The first through hole 110 is filled with the conductive column segment 80 of the second conductive structure, and the second through hole 111 is filled with the encapsulation material of the encapsulation material layer 4. Preferably, Figure 5 Shows Figure 4 A top view of a substrate used in a packaged device as shown in FIG. Figure 5 As shown, in Figure 4 In the package device structure shown, the diameter of the first through hole 110 is smaller than the diameter of the second through hole 111, and the number and density of the first through holes 110 are greater than the number and density of the second through holes 111. Figure 1 In the packaged device of the embodiment shown, the second conductive structure is arranged in the encapsulation material of the through hole 1-1. Therefore, its depth is deep and it is difficult to fill the conductive material. This makes the ratio of the depth to the diameter of the second conductive structure not too large, thereby limiting the number and density of the second conductive structures. In addition, in order to take into account both the plastic encapsulation efficiency and the support firmness of the substrate, the diameter of the through hole 1-1 arranged on the substrate needs to be relatively large and the density cannot be too high, which further limits the number and density of the second conductive structures. Figure 1 In the implementation mode, the density of the second conductive structure cannot be very high, which will affect the interconnection density of the packaged device to a certain extent. Figure 4In the illustrated embodiment, the second conductive structure is divided into a conductive column segment 80 and an interconnection line segment 81. The conductive column segment 80 is disposed in the first through hole, and the interconnection line segment 81 is disposed on the encapsulation material. Therefore, the conductive column segment 80 of the second conductive structure can be prepared in advance before plastic encapsulation, thereby realizing the separation of the functions of the through holes, that is, separating the through holes used as the encapsulation material flow channel from the through holes used as the conductive structure channel. Thus, first through holes with smaller apertures and higher density can be made on the substrate to serve as channels for conductive interconnection. Furthermore, by designing the second conductive structure in sections, the depth of the interconnection line segment prepared on the encapsulation material can be reduced, thereby removing the limitation of the depth and diameter ratio of the second conductive structure on the density of the second conductive structure. Thus, the density of the second conductive structure can be further effectively improved, thereby achieving the effect of improving the interconnection density of the packaged device. Figure 4 It can be seen from the embodiments that the second conductive structure does not necessarily need to be entirely arranged in the encapsulation material of the through hole. As long as part of the sections are arranged in at least part of the through holes (that is, only the conductive column section is arranged in the first through hole) and part of the sections are arranged in the encapsulation material (that is, the interconnection line section is arranged in the encapsulation material), the effect of electrically connecting the rewiring layers of the first surface and the second surface can also be achieved, and a higher density second conductive structure can also be prepared.

[0083] As a preferred embodiment, Figure 4 As shown, the interconnection line segment located in the encapsulation material layer and electrically connected to the corresponding conductive column segment is coaxially electrically connected to the corresponding conductive column segment, thereby shortening the transmission distance of the second conductive structure and improving its transmission efficiency.

[0084] Of course, it is not difficult for those skilled in the art to understand that in any possible embodiment of the present invention, the through holes on the substrate can be set to include two types, one type of through holes has an electrical connection function, and the other type of through holes does not have an electrical connection function. Figure 1 In the embodiment shown, the through holes on the substrate can also be configured to include two types, one type of through holes having an electrical connection function, and the other type of through holes not having an electrical connection function. In this case, the second conductive structure can still be configured as Figure 1 The only difference between the illustrated method and the embodiment is that the second conductive structure can be prepared only on the plastic packaging material of a part of the through holes, while the second conductive structure may not be prepared on the plastic packaging material of another part of the through holes.

[0085] As a preferred embodiment, the substrate 1 in the embodiment of the present invention is a heat sink made of heat-conducting materials such as metal-based alloys, ceramics, graphene, etc. Since there are only through holes or vertically interconnected conductive column structures on the substrate of the embodiment of the present invention, it is not necessary to prepare interconnection lines on the substrate. Therefore, compared with the substrate for wire bonding packaging (containing fine layer interconnection lines), the substrate of the embodiment of the present invention has a simple process and low cost, and can be prepared using thicker heat-conducting materials, such as metals (copper, aluminum, etc.), ceramics (aluminum oxide, aluminum nitride, silicon carbide, etc.), composite materials (double-sided copper clad laminates used in various printed circuit board industries, etc.), etc. Compared with HBM packaging and wire bonding packaging processes, the substrate of the embodiment of the present invention using heat-conducting materials has a better heat dissipation effect, thereby enabling the packaged device to have a better heat dissipation performance. In addition, the substrate of the embodiment of the present invention is a permanent substrate for the packaged device (i.e., it does not need to be removed during the packaging process), so it can provide support and protection for the packaged device, so that the chip can be mounted directly on both surfaces of the substrate, thereby improving the chip integration of the packaged device.

[0086] As a possible implementation manner, the chip in the packaging device of the embodiment of the present invention is mounted on the chip mounting area on the first surface and the second surface of the substrate by means of a patch material. The patch material is preferably a thermally conductive material such as metal alloy solder, silver glue, nano silver glue, etc., to further improve the heat dissipation effect of the packaging device.

[0087] As a possible implementation, heat dissipation holes for heat dissipation between chips are also provided in the areas for mounting chips on the first surface and the second surface of the substrate. These heat dissipation holes are not filled with encapsulation materials, and thus can serve as channels for heat dissipation between chips to further improve the heat dissipation effect of the packaged device. In a preferred implementation, the heat dissipation holes can be further filled with thermally conductive materials such as copper to further improve the heat dissipation effect of the packaged device.

[0088] As a preferred embodiment, the pin bumps provided on at least part of the pin pads of at least part of the chips have different heights, so that after these chips are mounted on the substrate, the end surfaces of the free ends of the pin bumps of the chips mounted on the same surface of the substrate are located in the same plane, thereby facilitating the electrical connection between the chips and the packaging interconnect lines of the rewiring layer. More preferably, a chip without pin bumps can be mounted on the top layer of the corresponding surface of the substrate, that is, used as the top layer chip farthest from the corresponding surface of the substrate, and the height of the pin bumps of other chips can be designed so that after all chips are mounted on the corresponding substrate surface, the end faces of the free ends of the pin bumps of the chips mounted on the same surface of the substrate are flush with the functional surface of the chip on the surface farthest from the substrate (that is, flush with the functional surface of the top layer chip on the corresponding surface). In this way, the pin heights of the chips mounted on the corresponding surface of the substrate can be consistent, so that wiring can be directly performed on the pin pads and pin bumps of the chip after removing the protective layer, or the depth and size of the openings prepared on the encapsulation material layer and used as the first conductive structure or the third conductive structure are consistent, thereby making the process parameters of all openings, the process of filling conductive materials, etc. consistent, making the process simple, the process easy to control, and the process cost lower.

[0089] It should be noted that the above-mentioned packaging devices are only some embodiments of the embodiments of the present invention. It is not difficult for those skilled in the art to understand that some features of the above-mentioned packaging devices can be freely combined, such as the substrate may be provided with a step structure or may not be provided with a step structure, the number of layers of chips stacked on the substrate may be two layers, one layer, three layers or more layers, the number of layers and functions of chips mounted on the first surface and the second surface of the substrate may be the same or completely different, the area on the substrate where the chips are mounted may be provided with heat dissipation holes or may not be provided with heat dissipation holes, etc. It is obvious that more embodiments of packaging devices can be obtained through these free combinations and transformations, and the variations of these packaging devices should be deemed to be within the scope of protection of the present invention. It should also be noted that, as another variation of the embodiments of the present invention, the packaging device using the above-mentioned concept (i.e., the technical concept of packaging devices that do not use TSV technology and wire bonding technology for chip interconnection) may not mount chips on both sides of the first surface and the second surface of the substrate, but may mount chips on one side of the substrate to obtain a three-dimensional stacked packaging device with single-sided chips, such as Figure 6 The three-dimensional stacked package device obtained by single-sided chip mounting is shown in FIG. Figure 6 As shown, the chip mounted on one side of the substrate can achieve electrical communication with the external pin pads of the package only through the first conductive structure and the redistribution layer.

[0090] The method for preparing the packaging device with the above structure will be described in detail below with reference to the accompanying drawings.

[0091] Figures 7 to 19 Schematically shows Figure 1 The preparation method of the packaging device of the structure shown in FIG. Figure 7 As shown, the preparation method comprises:

[0092] Step S700: preparing pin bumps on at least part of the chips to be mounted;

[0093] Step S701: preparing a through hole on the substrate that penetrates the thickness direction of the substrate;

[0094] Step S702: mounting at least one layer of chips on the chip mounting areas on the first surface and the second surface of the substrate by stacking;

[0095] Step S703: Covering the chip mounted on one surface of the substrate with a protective layer;

[0096] Step S704: performing plastic encapsulation on the side of the substrate away from the protective layer with a sealing material, wherein during the plastic encapsulation process, the sealing material can flow through the through holes to the side of the substrate provided with the protective layer, so that the chips mounted on both surfaces of the substrate are simultaneously sealed by the sealing material during one plastic encapsulation process, and the through holes of the substrate are also filled with the sealing material during this plastic encapsulation process;

[0097] Step S705: preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure in the encapsulation material layer on the first surface that is electrically connected to the chip mounted on the first surface and a second conductive structure in the encapsulation material of the through hole that penetrates the thickness direction of the substrate;

[0098] Step S706: removing the protective layer;

[0099] Step S707: preparing a rewiring layer electrically connected to the mounted chip through the conductive structure on the surface of the encapsulation material, wherein the rewiring layers on the first surface and the second surface of the substrate are electrically connected through the second conductive structure;

[0100] Step S708: preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer;

[0101] Step S709: preparing BGA solder balls or soldering chip pin bumps on the package external pin pads.

[0102] In step S700, pin bumps are prepared on the pin pads on the functional surface of the chip, wherein the prepared pin bumps are used for electrical connection of the chip, such as for electrical connection between the chip and the rewiring layer or the first conductive structure. Therefore, the position for preparing the pin bumps can be selected according to the needs, and the embodiments of the present invention are not limited to this. It should be noted that in some embodiments, multiple chips may be stacked in multiple layers according to needs. In this case, in order to ensure that the chips of each layer can be conveniently electrically connected to the rewiring layer, the position of the pin pads of the corresponding chip can also be transferred through the RDL rewiring technology so that they are reset to the desired position. When preparing pin bumps for chips, pin bumps can be prepared on all chips or only on some chips. The embodiments of the present invention are not limited to this. For example, in Figure 1 In the package structure shown, pin bumps are prepared only on the bottom chip, and no pin bumps are prepared on the top chip. The top chip is electrically connected to the redistribution layer through the first conductive structure and its pin pads. For example, pin bumps are prepared on all pin pads of the chip. Figure 8 and 9 The schematic diagram shows the cross-sectional view of the chip before and after the preparation of the pin bump, as shown in FIG. Fig. 9 As shown, a pin bump 22 is prepared on the pin pad 21 of the chip 2. Since the pin bump has a certain height, the electrical connection between the corresponding layer chip and the rewiring layer can be conveniently achieved through the pin bump 22. For example, it is necessary to perform RDL rewiring on the chip first to transfer the position of the pin pad. Fig.10 and 11 The cross-sectional view of the chip before and after the pin bump is prepared is shown, wherein: Fig.10 The pin pads in the figure are the original pin pads on the chip. After rewiring, Fig.11 As shown, some new pin pads are added to the chip, and pin bumps 22 are prepared for some pin pads 21 according to requirements. In specific practice, the pin bumps 22 can be a metal column structure, and can be a micro copper column structure by way of example.

[0103] In step S701, the substrate can be a metal, ceramic or composite thermal conductive material, and a through hole can be prepared on the substrate by laser drilling. The through hole is used as a circulation channel for the encapsulation material and a channel for preparing the second conductive structure. The position and width of the through hole can be set according to demand. It should be noted that before preparing the through hole, it is necessary to reserve an area for chip mounting on the substrate, and prepare the through hole outside the area for chip mounting. In a preferred embodiment, heat dissipation holes can also be prepared in the area reserved for chip mounting. Fig.12 The cross-sectional view of the substrate obtained after preparing the through hole on the substrate is schematically shown, as shown in FIG. Fig.12 As shown, the substrate is formed with a region 1-2 for mounting a chip and a through hole 1-1. In other embodiments, a heat dissipation hole for heat dissipation of the chip can also be prepared on the region 1-2 for mounting a chip of the substrate. The top view of the substrate thus prepared is as shown in FIG. Fig.33 As shown, a square heat dissipation hole 121 is prepared on the area 1-2 where the chip is mounted. Since the heat dissipation hole 121 is covered by the mounted chip during the entire chip preparation process, it will not be filled with the encapsulation material and can be used as a heat dissipation channel to provide a good heat dissipation effect for the mounted chip. Of course, the heat dissipation hole is not limited to a square shape, but can also be other shapes, and the embodiment of the present invention is not limited to this.

[0104] In step S702, the chip can be mounted on the substrate prepared in step S701 in a stacked manner by using patch materials, wherein the chip is mounted in area 1-2 for mounting the chip, the functional surfaces of all chips are facing away from the substrate, and the chip is mounted so that the pin bumps of other chips mounted before the chip are exposed. Exemplarily, the patch material can be a thermally conductive patch glue such as metal alloy solder, silver glue, nano silver glue, etc. The chip mounted on the substrate can be one layer, or two or more layers. Taking two-layer double-sided mounting as an example, the cross-sectional view of the structure obtained after mounting the chip is as shown in FIG. Fig.13 As shown, two groups of two-layer stacked chips are mounted on the first surface 2A and the second surface 1A of the substrate 1, wherein the bottom layer chip is provided with pin bumps 22, and the top layer chip is not provided with pin bumps, and the functional surface of the chip faces upward so that the pin bumps or pin pads thereon can be used to achieve electrical connection. In order to facilitate the electrical connection of the bottom layer chip, as shown in FIG. Fig.13 As shown, the free end face 22A of the pin bump 22 on the bottom chip 20 is flush with the functional surface of the top chip 23. Preferably, when mounting the chip, the non-functional surface of the bottom chip 20 can be mounted on the chip mounting area 2-2 of the substrate using a mounting material, and the functional surface of the top chip can be mounted upward on the functional surface of the chip below it. When mounting, the pin bumps on the functional surfaces of the chips of each layer below the top chip need to be exposed to facilitate the electrical connection of the chips of each layer, such as Fig.13As shown, the two layers of chips are staggered and stacked, and the pin bumps 22 on the bottom chip 20 are not covered or blocked by the upper chip. It should be noted that if the position of the pin pads of the chip makes it easy to block the pin bumps of the chip below the topmost chip when the stack is mounted, the position of the pin pads on the corresponding chip can be adjusted by the rewiring process when preparing the pin bumps in step S700, so as to achieve the effect that the pin bumps of other layers of chips below the topmost chip after mounting can be exposed. In step S703, since a through hole is prepared on the substrate, it is only necessary to cover the chip mounted on one of the surfaces of the substrate with a protective layer to achieve a one-time double-sided plastic sealing from the other side. Among them, the covering protective layer can be a temporary carrier with a strippable material, or it can be a high temperature resistant protective film. When it is a high temperature resistant protective film, the thickness of the protective layer can be set to 50-300um. For example, the high temperature resistant protective film of the embodiment of the present invention can be a PI, Teflon or other thin film coated with a high temperature resistant adhesive film on the surface. Due to the improvement of the overall process, the embodiment of the present invention only needs to vacuum fix the protective layer at a fixed position in the plastic encapsulation mold during plastic encapsulation, and the covering protective layer does not need to be transferred or transported between other fine processes. Therefore, in the embodiment of the present invention, the covering protective layer does not need to use temporary bonding materials, but can use high-temperature resistant protective films or peelable materials. Since the temporary bonding material needs to be pre-bonded to the temporary carrier to avoid warping during the fine processing process, and the temporary bonding material needs to undergo multiple high-temperature and acid-base processes under the temporary bonding method, the requirements for the temporary bonding material's high temperature resistance, acid and alkali resistance, viscosity, and displacement control between the chip are relatively high, and double-sided bonding is required. Therefore, the price of plastic encapsulation protection using temporary bonding is very expensive. Compared with the temporary bonding packaging method, the protective layer covering the chip in the packaging method of the embodiment of the present invention only needs to withstand high temperature once. The surface used to protect the chip during plastic sealing does not need to be peeled off, and single-sided covering is sufficient. Therefore, the packaging cost can be effectively reduced. Moreover, since the high-temperature resistant protective film has been solidified when it is covered on the mounted chip, it can play a good role in fixing the chip during the plastic sealing process, avoiding the cumbersomeness of the temporary bonding material having to be set on the carrier board due to the easy movement of the temporary bonding material in the temporary bonding packaging method. Fig.14 The schematic diagram shows the effect of covering the chip on one side of the substrate with a protective layer, as shown in FIG. Fig.14As shown, the protective layer 3 is attached to the topmost chip on one side, and since the end surface of the free end of the pin bump 22 of the bottom chip 20 is flush with the functional surface of the topmost chip, the functional surface of the topmost chip and the pin bump 22 of the bottom chip are both attached to the protective layer 3. It should be noted that in other embodiments, pin bumps can also be prepared on the pin pads of the topmost chip, and the pin bumps of at least some chips are set to have different heights, so that the pin bumps of chips located at different layers after being mounted on the substrate have the same height, that is, the end surfaces of the free ends of the pin bumps of chips in different layers mounted on the same surface side are all located in the same plane, so as to facilitate the subsequent preparation of the rewiring layer.

[0105] In step S704, the plastic encapsulation is specifically performed from the side away from the protective layer. Since a through hole is provided on the substrate, the encapsulation material will flow from the side away from the protective layer to the other side of the substrate through the through hole, thereby realizing the plastic encapsulation of the two sides of the substrate at one time, and the substrate can be plastic encapsulated in the packaging device to improve the mechanical strength of the device. Fig.15 The plastic encapsulation effect of an embodiment is shown. Fig.15 As shown, after plastic encapsulation, the encapsulation material 41 fills the through hole 1-1 of the substrate 2 and simultaneously encapsulates the chips and substrate mounted on both surfaces of the substrate, wherein the encapsulation material on the side away from the protective layer completely encapsulates the chip and the substrate, while on the side with the protective layer, the surface of the encapsulation material is flush with the functional surface of the topmost chip mounted on this side.

[0106] In step S705, hole structures may be prepared on the encapsulation material of the through hole and the encapsulation material layer of the first surface, respectively, wherein the through hole may be prepared on the encapsulation material of the through hole, and the blind hole may be prepared on the encapsulation material layer of the first surface, and the position of the blind hole may correspond to the pin bump and / or pin pad of the corresponding chip. Afterwards, the corresponding conductive structure may be formed by filling the through hole and the blind hole with conductive material. Among them, the through hole may be prepared in the encapsulation material of the through hole by laser drilling, photolithography, dry etching, etc., and the blind hole may be prepared at the position corresponding to the pin bump and / or pin pad of the chip by laser drilling, photolithography, dry etching, grinding, etc. Fig.16 The effect diagram after preparing through holes and blind holes is shown, such as Fig.16As shown, a through hole 82 is prepared in the plastic encapsulation material of the through hole, which runs through the entire encapsulation material layer 4 in the thickness direction, and a blind hole 70 corresponding to the pin bumps and pin pads of the chip mounted on the first surface of the substrate is formed on the surface of the encapsulation material layer away from the protective layer. Therefore, a second conductive structure can be formed by filling a conductive material in the through hole 82, and a first conductive structure can be formed by filling a conductive material in the blind hole 70, and the chip mounted on the first surface of the substrate is electrically connected to the first conductive structure through its pin pads and pin bumps.

[0107] In step S706, according to the material properties of the selected protective layer, the protective layer can be removed in a manner suitable for the material properties. For example, the protective layer with corresponding properties can be removed by heating, chemical stripping, laser stripping, UV light stripping, heating and mechanical stripping, etc. The cross-sectional view of the intermediate structure obtained after removing the protective layer is shown in FIG. Fig.17 As shown, the first conductive structure 7 is electrically connected to the pin pads and pin bumps 22 of the chip mounted on the first surface, the pin bumps 22 of the chip mounted on the second surface and the pin pads of the topmost chip are exposed on the surface of the encapsulation material layer, and the second conductive structure 8 penetrates the encapsulation material layers 4 on both sides of the substrate.

[0108] In step S707, a rewiring layer can be prepared on the surface of the encapsulation material layer on both sides of the substrate, wherein the prepared rewiring layer includes an insulating material and a package interconnection line, the package interconnection line is prepared in the insulating material, and the package interconnection line is electrically connected to the first conductive structure and the second conductive structure respectively, and the package interconnection line is also electrically connected to the pin bump and pin pad of the chip exposed on the second surface. Thus, the rewiring layer on the first surface side can be electrically connected to the chip mounted on the first surface through the first conductive structure, and the rewiring layer on the second surface side can be directly electrically connected to the chip mounted on the second surface side through the package interconnection line and the pin pad and pin bump of the chip, and at the same time, the rewiring layer on the first surface side and the second surface side of the substrate can be electrically connected through the second conductive structure, so that the chips mounted on the substrate are all electrically connected to the rewiring layer. In step S708, a package external pin pad can be prepared on part of the package interconnection lines of the rewiring layer as needed, so that the chip can be electrically connected to the outside through the package external pin pad. Wherein, the package external pin pad can be prepared on the rewiring layer on the first surface side. Fig.18 The cross-sectional view of the intermediate structure with the rewiring layer and the package external pin pad is shown. Fig.18As shown, the rewiring layer 5 includes an insulating material 8-0 and a package interconnection line 8-1 arranged in the insulating material 8-0, the package interconnection line 8-1 of the rewiring layer 5 on the first surface 2A side is electrically connected to the chip mounted on the first surface through the first conductive structure 7, the package interconnection line 8-1 of the rewiring layer 5 on the second surface 1A side is directly electrically connected to the pin pad or pin bump 22 of the chip mounted on the second surface, the package interconnection line 8-1 of the rewiring layer 5 on the first surface and the second surface side is also electrically connected through the second conductive structure 8, some of the package interconnections of the rewiring layer 5 on the first surface side are provided with a package external pin pad 51 electrically connected to the package interconnection line, and the package external pin pad 51 is electrically connected to the corresponding chip via the rewiring layer 5 and the first conductive structure 7 and the second conductive structure 8.

[0109] In step S709, by preparing BGA solder balls or soldering chip pin bumps on the package external pin pads, the chip can be electrically connected to the outside through the BGA solder balls or soldering chip pin bumps, thereby achieving the required functions. Fig.19 The cross-sectional effect diagram of the intermediate structure prepared with BGA solder balls is shown, as Fig.19 As shown, a BGA solder ball 6 is arranged on the package external pin pad 51, and the BGA solder ball 6 is electrically connected with each chip through the package external pin pad 51, the rewiring layer 5, the first conductive structure 7 and the second conductive structure 8. Fig.19 As shown in FIG. 1 , in this example, two sets of chip stacks are mounted on the substrate. Therefore, the obtained package structure needs to be cut to obtain a single package device. Fig.19 The single packaged device obtained by cutting the package structure shown is Figure 1 Of course, it is not difficult to understand that when the chips mounted on the substrate are a single group or the obtained packaged device is a single packaged device, it is not necessary to perform cutting operations, and the final usable packaged device is obtained after the processing of step S709.

[0110] Fig. 20 Schematically shows Figure 3 The preparation method of the packaging device of the structure shown in FIG. Fig. 20 As shown, the preparation method is Figure 7 The preparation method shown in FIG. 1 is basically the same, the only difference being that, in step S7011, in addition to preparing a through hole penetrating the thickness direction of the substrate on the substrate, the method of the embodiment of the present invention also prepares a step structure on the substrate, and the intermediate structure obtained is as shown in FIG. Fig.21 As shown, at the edge of the chip mounting area 1-2 of the substrate, there is a step structure 11 lower than the surface of the mounting area 1-2. Therefore, after the chip is mounted in step S702, the structure obtained is as follows: Fig. 22As shown, after step S703, the structure obtained is as follows Fig.23 As shown, after step S704, the structure obtained is as follows Fig.24 As shown, the step structure 11 is encapsulated by the encapsulation material, so that the mounted chip can be encapsulated more firmly. Fig. 20 The structure of the final packaged device is as follows: Figure 3 As shown, the substrate includes a step structure 11, which is filled and encapsulated by an encapsulation material to more firmly encapsulate the chip on the substrate.

[0111] It should be noted that the step structure prepared on the substrate can be a step structure that is raised relative to the area 1-2 for mounting the chip, or a step structure that is recessed relative thereto. Figure 3 The step structure that is recessed relative to the area for mounting the chip is used as an example for illustration and description. Those skilled in the art should understand that it is also a feasible implementation scheme that the step structure is recessed relative to the area 1-2 for mounting the chip.

[0112] Fig.25 Schematically shows Figure 2 The preparation method of the packaging device of the structure shown in FIG. Fig.25 As shown, the preparation method is Figure 7 The preparation method shown is basically the same, the only difference is that the protective layer covered in step S703 is a protective layer including a strippable material and a carrier board. After the protective layer is stripped, an insulating material layer for encapsulating the chip on the second surface is further prepared on the encapsulation material layer on one side of the protective layer to form a second encapsulation material layer, and then a third conductive structure is further prepared on the insulating material layer. The intermediate structure obtained after step S703 is as follows Fig.26 As shown, the protective layer includes a strippable material layer 31 and a carrier 32. After the protective layer is removed in step S706, a layer of insulating material is further prepared on the second surface of the substrate through step 706A. The insulating material layer is covered on the chip mounted on the second surface of the substrate as a second encapsulation material layer. Therefore, before step S707, it is necessary to prepare a third conductive structure on the insulating material layer through step S707A to expose the pin pads and pin bumps of the chip mounted on the second surface of the substrate, so as to realize the electrical connection between the chip on the second surface and the rewiring layer. Therefore, in this embodiment, the intermediate structure obtained by the processing of step S706A is as follows: Fig. 27 As shown, it also includes an insulating material layer 33 as a second encapsulation material layer. The intermediate result obtained after the processing of step S707A is as follows Fig.28 As shown, there is also a third conductive structure 9. The preparation method of the third conductive structure is the same as that of the first conductive structure, so the relevant description above can be referred to and will not be repeated here.

[0113] Fig.29 Schematically shows Figure 4 The preparation method of the packaging device of the structure shown in FIG. Fig.29 As shown, the preparation method comprises:

[0114] Step S900: preparing pin bumps on at least part of the chips to be mounted;

[0115] Step S901: preparing a first through hole and a second through hole on the substrate that penetrate the thickness direction of the substrate, and preparing a conductive column in the first through hole;

[0116] Step S902: mounting at least one layer of chips on the chip mounting areas on the first surface and the second surface of the substrate by stacking;

[0117] Step S903: Covering the chip mounted on one surface of the substrate with a protective layer;

[0118] Step S904: performing plastic encapsulation on the side of the substrate away from the protective layer with a sealing material, wherein during the plastic encapsulation process, the sealing material can flow through the second through hole to the side of the substrate provided with the protective layer, so that the chips mounted on both surfaces of the substrate can be simultaneously sealed by the sealing material during one plastic encapsulation process, and the second through hole of the substrate is also filled with the sealing material during this plastic encapsulation process;

[0119] Step S905: removing the protective layer;

[0120] Step S906: preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure located in the encapsulation material layer on the first surface and electrically connected to the chip mounted on the first surface, and a second conductive structure penetrating the thickness direction of the substrate, wherein the second conductive structure includes a conductive column segment located in the first through hole and an interconnection line segment located in the encapsulation material layer and electrically connected to the corresponding conductive column segment;

[0121] Step S907: preparing a rewiring layer electrically connected to the mounted chip through the conductive structure on the surface of the encapsulation material, wherein the rewiring layers on the first surface and the second surface of the substrate are electrically connected through the second conductive structure;

[0122] Step S908: preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer;

[0123] Step S909: preparing BGA solder balls or soldering chip pin bumps on the package external pin pads.

[0124] In the above preparation method, the specific implementation of step S900, step S902, step S903, step S905, step S907, step S908 and step S909 can refer to the above description. It should be noted that the protective layer of step S903 can be either Figure 7 The protective layer described may also be Fig.25 The protective layer described in the present invention is not limited in this embodiment. The difference from the method described above is that in step S901, the through holes prepared on the substrate include two types, one is the second through hole used as a flow channel for the encapsulation material, and the other is the first through hole used as a conductive structure channel, and the first through hole is filled with a conductive column in step S901. Therefore, the structure of the substrate prepared in step S901 is as follows: Figure 5 and 30 As shown, Figure 5 is a top view of the prepared substrate, Fig.30 1 is a vertical cross-sectional view, and the substrate thus obtained includes a first through hole 110 and a second through hole 111. The first through hole 110 has a smaller aperture and a higher density, and the first through hole 110 is filled with a conductive column 80. In step S904, the encapsulation material flows to the other side of the substrate through the second through hole. Since the first through hole 110 has been filled with a conductive column, the first through hole will not be filled with the encapsulation material. Taking the protective layer used in step S903 as a protective layer including a strippable material layer and a carrier as an example, the structure obtained by step S904 is as follows: Fig.31 As shown in FIG. 1 , the conductive pillar 80 in the first through hole 110 is also completely encapsulated by the encapsulation material layer 4. Therefore, in this embodiment, when preparing the conductive structure in step S906, a through hole is prepared by laser drilling or the like at a position corresponding to the conductive pillar 80 in the encapsulation material layer 4 and filled with conductive material, thereby forming a second conductive structure including a conductive pillar segment and an interconnection line segment. The cross-sectional view of the structure obtained in step S906 is shown in FIG. Fig.32 As shown, the second conductive structure includes a conductive column segment 80 and an interconnection line segment 81, which are coaxially electrically connected to form a second conductive structure 8 that penetrates the substrate and the encapsulation material layer. The parts related to the first conductive structure and the third conductive structure can be referred to the above description and will not be repeated here. Fig.32 The structure shown in FIG. 1 can be obtained after subsequent processes such as preparing a rewiring layer. Figure 4 See the packaged device shown. Fig.32 As shown in the figure, in the method of the embodiment of the present invention, when preparing the second conductive structure in step S906, the depth of the through hole for the second conductive structure prepared on the encapsulation material layer 4 is relatively large. Figure 7The method shown is much smaller and, therefore, easier to fill with conductive material, thus making it possible to prepare a higher density of second conductive structures.

[0125] It can be understood that, in other implementations, the steps of the above-mentioned preparation method and the features of the packaging structure described in the embodiments of the present invention can also be freely combined in other ways according to needs to obtain different types of packaging structures, and the embodiments of the present invention are not regarded as limiting the combination of the preparation method steps and the packaging structure features.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A double-sided stacked fan-out packaging device, characterized in that: include: A substrate with through holes, wherein the substrate is a flat plate structure, and at least one group of stacked chips is disposed on the first surface and the second surface of the flat plate structure substrate, and each group of stacked chips includes at least two stacked chips, wherein the through holes include two types, one type of through holes has an electrical connection function, and the other type of through holes does not have an electrical connection function; an encapsulation material layer, which is filled in at least part of the through holes and encapsulates the chip and the substrate, wherein the through holes with electrical connection function in at least part of the through holes are simultaneously used as flow channels for the encapsulation material and preparation channels for the second conductive structure, and the at least part of the through holes are filled with the encapsulation material of the encapsulation material layer, and the second conductive structure is arranged in the encapsulation material of each through hole; a first conductive structure in the encapsulation material layer on the first surface, wherein each chip in the layer stack on the first surface is directly electrically connected to the redistribution layer on the first surface through the first conductive structure; A second conductive structure that runs through the thickness direction of the substrate, wherein at least a portion of the second conductive structure is disposed in the encapsulation material of the at least a portion of the through hole of the substrate, and the second conductive structure directly electrically connects the first surface of the encapsulation material layer with the rewiring layer of the second surface; A rewiring layer respectively located on the encapsulation material layer on the first surface and the encapsulation material layer on the second surface of the substrate, wherein the rewiring layers on the first surface and the second surface are formed after the second conductive structure is prepared, and the rewiring layer on the first surface is prepared to be directly electrically connected to each chip of the stacked layers on the first surface and the second conductive structure, and the rewiring layer on the second surface is prepared to be directly electrically connected to each chip of the stacked layers on the second surface and the second conductive structure; A package external pin pad disposed on a rewiring layer on the encapsulation material layer on the first surface of the substrate and electrically connected to the rewiring layer; and A BGA solder ball or a solder chip pin bump is disposed on the package external pin pad and is electrically connected to the package external pin pad.

2. The double-sided stacked fan-out packaging device according to claim 1, characterized in that: The through holes with electrical connection function on the substrate also include a first through hole that is only used as a preparation channel for the second conductive structure, and the through hole without electrical connection function on the substrate is a second through hole that is only used as a circulation channel for the encapsulation material, wherein the second conductive structure includes a conductive column segment located in the first through hole and an interconnect line segment located in the encapsulation material layer and electrically connected to the corresponding conductive column segment, the first through hole is filled with the conductive column segment of the second conductive structure, and the second through hole is filled with the encapsulation material of the encapsulation material layer.

3. The double-sided stacked fan-out packaging device according to claim 2, characterized in that: An interconnection line segment located in the encapsulation material layer and electrically communicating with a corresponding conductive pillar segment is coaxially electrically connected to the corresponding conductive pillar segment.

4. The double-sided stacked fan-out packaging device according to claim 2, characterized in that: The diameter of the first through hole is smaller than the diameter of the second through hole, and the number and density of the first through holes are greater than the number and density of the second through holes.

5. The double-sided stacked fan-out packaging device according to claim 1, characterized in that: The chip is mounted on the chip mounting area on the first surface and the second surface of the substrate through a patch material, and both the patch material and the substrate are made of heat-conducting materials.

6. The double-sided stacked fan-out packaging device according to claim 5, characterized in that: The areas on the first surface and the second surface of the substrate for mounting chips are also provided with heat dissipation holes for dissipating heat between chips.

7. The double-sided stacked fan-out packaging device according to claim 1, characterized in that: The packaged device further includes an insulating material layer located between the encapsulation material layer and the rewiring layer on the second surface of the substrate; as well as A third conductive structure is located in the insulating material layer on the second surface, wherein each chip in the stack located on the second surface is directly electrically connected to the redistribution layer on the second surface through the third conductive structure.

8. The double-sided stacked fan-out packaging device according to claim 1, characterized in that: The chip comprises pin pads, and at least some of the pin pads of at least some of the chips are provided with pin bumps; The free end surfaces of the pin bumps of the chip mounted on the same surface of the substrate are located in the same plane.

9. The double-sided stacked fan-out packaging device according to claim 8, characterized in that: No pin bumps are arranged on the functional surface of the topmost chip on the first surface and / or the second surface of the substrate, wherein the free end surfaces of the pin bumps of the chips mounted on the same surface of the substrate are flush with the functional surface of the topmost chip on that surface.

10. A method for preparing a double-sided stacked fan-out packaging device, characterized in that: The method comprises: At least one layer of chips is mounted on the chip mounting areas on the first surface and the second surface of the substrate by stacking, wherein the substrate is provided with through holes penetrating the thickness direction of the substrate; Covering a chip mounted on one surface of the substrate with a protective layer; Using an encapsulation material to perform plastic encapsulation on a side of the substrate away from the protective layer, wherein during the plastic encapsulation process, the encapsulation material can flow through the through hole to the side of the substrate provided with the protective layer, so that the chips mounted on the two surfaces of the substrate can be simultaneously plastic encapsulated through a one-time plastic encapsulation process, wherein after the one-time plastic encapsulation process, the substrate and the chips mounted on the two surfaces of the substrate are all encapsulated by the encapsulation material except for the chip surface covered by the protective layer, and the through hole of the substrate is also filled with the encapsulation material; Preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure in the encapsulation material layer on the first surface that is electrically connected to the chip mounted on the first surface and a second conductive structure in the encapsulation material in at least part of the through holes that penetrates the thickness direction of the substrate, thereby forming two types of through holes with and without electrical connection functions; Removing the protective layer, wherein after removing the protective layer, the surface of the chip covered by the protective layer is exposed on the surface of the encapsulation material; Prepare a rewiring layer on the surface of the encapsulation material, which is directly electrically connected to the mounted chip through the conductive structure, wherein the rewiring layers on the first surface and the second surface of the substrate are directly electrically connected through the second conductive structure; Preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer; Prepare BGA solder balls or solder chip pin bumps on the package external pin pads.

11. A method for preparing a double-sided laminated fan-out packaging device, characterized in that: The method comprises: Preparing a first through hole and a second through hole on the substrate, and preparing a conductive column in the first through hole; At least one layer of chips is mounted on the chip mounting areas on the first surface and the second surface of the substrate respectively by stacking. Covering a chip mounted on one surface of the substrate with a protective layer; The encapsulation material is used to perform plastic encapsulation on the side of the substrate away from the protective layer, wherein during the plastic encapsulation process, the encapsulation material can flow through the second through hole to the side of the substrate provided with the protective layer, so that the chips mounted on the two surfaces of the substrate can be simultaneously plastic encapsulated through a single plastic encapsulation process, wherein after the single plastic encapsulation process, the substrate and the chips mounted on the two surfaces of the substrate are all encapsulated by the encapsulation material except for the chip surface covered by the protective layer, and the second through hole of the substrate is also filled with the encapsulation material, thereby forming two types of through holes, namely, a first through hole with an electrical connection function and a second through hole without an electrical connection function; Removing the protective layer, wherein after removing the protective layer, the surface of the chip covered by the protective layer is exposed on the surface of the encapsulation material; Preparing a conductive structure on the encapsulation material, wherein the conductive structure includes a first conductive structure located in the encapsulation material layer on the first surface and electrically connected to the chip mounted on the first surface, and a second conductive structure penetrating the thickness direction of the substrate, wherein the second conductive structure includes a conductive column segment located in the first through hole and an interconnection line segment located in the encapsulation material layer and electrically connected to the corresponding conductive column segment; Prepare a rewiring layer on the surface of the encapsulation material, which is directly electrically connected to the mounted chip through the conductive structure, wherein the rewiring layers on the first surface and the second surface of the substrate are directly electrically connected through the second conductive structure; Preparing a package external pin pad on the redistribution layer on the first surface of the substrate and electrically connected to the redistribution layer; Prepare BGA solder balls or solder chip pin bumps on the package external pin pads.

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