An integrated passive device

Abstract

The embodiment of the present application provides an integrated passive device, comprising: a substrate; a grounded back metal layer formed on the bottom surface of the substrate; a capacitor lower plate located on the top surface of the substrate; a substrate contact via penetrating the substrate and connecting the capacitor lower plate and the back metal layer, wherein the back metal layer serves as a capacitor lower port; a capacitor dielectric layer formed on the capacitor lower plate; a capacitor upper plate formed on the capacitor dielectric layer; and a capacitor upper port formed at intervals above the capacitor upper plate and connected to the capacitor upper plate. The embodiment of the present application provides an integrated passive device to solve the technical problem that when a traditional two-port passive device is matched with a grounded active device in a circuit, additional inductance is introduced, thereby causing losses.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to an integrated passive device. Background Art

[0002] Existing integrated passive devices are mainly made of one or more resistors, capacitors and inductors on the substrate through semiconductor back-end processes to form passive devices such as filters. In order to meet the needs of matching in ceramic packaging tubes or MMIC circuits, integrated passive devices need to share the same ground with active devices. At present, with the development of technology, RF devices have higher and higher requirements for high performance and low cost of integrated passive devices.

[0003] Among existing integrated passive devices, capacitors, for example, have low capacitance density, high loss, and high cost, making it difficult to meet today's high performance and low cost requirements.

[0004] Existing integrated passive devices, such as Figure 1 As shown, it includes a glass substrate 4, a capacitor lower plate 11, a capacitor upper plate 21, and a capacitor dielectric layer 3; the capacitor lower plate 11 is connected to the first port 13 above through a first contact through hole 12, and the capacitor upper plate 21 is connected to the second port 23 above through a second contact through hole 24, a routing metal 22, and a third contact through hole 25. The first surface bonding portion 13 connected to the capacitor lower plate 11, the second surface bonding portion 23 connected to the capacitor upper plate 21, the top isolation layer 5 has a plurality of openings, the portion of the first surface bonding portion 13 exposed at the opening is used as the first port 131, and the portion of the second surface bonding portion 23 exposed at the opening is used as the second port 232. Figure 1 When the dual ports of the existing integrated passive device are set on the same side, when the application needs to be grounded together with the active device with the drain located on the back, an additional bonding line is required to connect the ground port (first port 131) to the circuit substrate. This additional bonding line will introduce inductance, thereby generating additional RF loss. Since the existing integrated passive device uses a glass substrate, the capacitance density is higher than that of the existing silicon-based capacitors and GaAs capacitors.

[0005] Existing silicon-based capacitors and GaAs capacitors are difficult to meet the high performance and low cost requirements of capacitors of integrated passive devices required for matching in ceramic packaging tube shells or MMIC circuits.

[0006] Therefore, when traditional two-port passive devices are matched with grounded active devices in a circuit, additional inductance is introduced, resulting in losses, which is a technical problem that technical personnel in this field urgently need to solve.

[0007] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0008] The embodiment of the present application provides an integrated passive device to solve the technical problem that when a traditional two-port passive device is matched with a grounded active device in a circuit, additional inductance is introduced, thereby causing loss.

[0009] The embodiment of the present application provides an integrated passive device, including:

[0010] substrate;

[0011] A grounded back metal layer formed on the bottom surface of the substrate;

[0012] A capacitor bottom plate, located on the top surface of the substrate;

[0013] A substrate contact through hole penetrates the substrate and connects the capacitor bottom plate and the back metal layer, wherein the back metal layer serves as a capacitor bottom port;

[0014] A capacitor dielectric layer formed on the capacitor lower plate;

[0015] A capacitor upper plate, formed on the capacitor dielectric layer;

[0016] The upper port of the capacitor is formed above the upper electrode plate of the capacitor and is connected to the upper electrode plate of the capacitor.

[0017] The embodiment of the present application adopts the above technical solution, which has the following technical effects:

[0018] The integrated passive device of the embodiment of the present application, the capacitor lower plate 3-1, the capacitor dielectric layer 4, and the capacitor upper plate 5 are arranged in sequence from bottom to top to form a capacitor. The capacitor lower plate 3-1 is formed on the top surface of the substrate 1, and the back metal layer 12 is formed on the bottom surface of the substrate 1. The substrate contact through hole 2 passes through the substrate 1 and connects the capacitor lower plate 3-1 and the back metal layer 12, and the back metal layer 12 serves as the capacitor lower port. The capacitor upper port is formed above the capacitor upper plate 5 and is connected to the capacitor upper plate 5. In this way, one of the two ports of the capacitor is located at the top, that is, the capacitor upper port, and the other port passes through the substrate and is located at the bottom, that is, the back metal layer 12 serving as the capacitor lower port. With such a structure, the two ports are arranged above and below, and the lower port can be directly connected to the circuit substrate without an additional bonding line, so as to achieve common ground with the active device, so that no additional inductance and loss are generated. Since the integrated passive device of the embodiment of the present application adopts a glass substrate, it has a higher capacitance density and lower loss than existing silicon-based capacitors and GaAs capacitors, and the cost of the integrated passive device on the glass substrate is lower than that of silicon-based and GaAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0020] Figure 1 is a schematic diagram of an existing integrated passive device;

[0021] Figure 2 A schematic diagram of an integrated passive device according to Embodiment 1 of the present application;

[0022] Figure 3 This is a schematic diagram of an integrated passive device according to Embodiment 2 of the present application;

[0023] Figure 4 This is a schematic diagram of an integrated passive device according to Embodiment 3 of the present application;

[0024] Figure 5 A schematic diagram of completing step S1 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0025] Figure 6 A schematic diagram of completing step S2 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0026] Figure 7 A schematic diagram of completing step S3 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0027] Figure 8 A schematic diagram of completing step S4 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of completing step S5 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0029] Fig.10 A schematic diagram of completing step S6 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0030] Fig.11 A schematic diagram of completing step S7 of the method for preparing an integrated passive device according to an embodiment of the present application;

[0031] Fig.12 This is a schematic diagram of completing step S8 of the method for preparing an integrated passive device according to an embodiment of the present application.

[0032] Reference numerals:

[0033] In the background technology:

[0034] Capacitor bottom plate 11, first contact through hole 12, first surface wiring portion 13, first port 131,

[0035] Capacitor upper plate 21, routing metal 22, second surface wiring portion 23, second port 232, second contact through hole 24, third contact through hole 25,

[0036] Capacitor dielectric layer 3, glass substrate 4, top isolation layer 5;

[0037] In this application:

[0038] Substrate 1, substrate contact via 2,

[0039] The capacitor lower plate 3-1, the second portion 3-2 of the first metal layer,

[0040] Capacitor dielectric layer 4,

[0041] Capacitor upper plate 5,

[0042] The first contact through hole 6-1, the third contact through hole 6-2,

[0043] The first part of the routing metal layer 7-1, the second part of the routing metal layer 7-2

[0044] Isolation layer 9, first isolation layer 9-1, second isolation layer 9-2, third isolation layer 9-3,

[0045] The second contact through hole 8-1, the fourth contact through hole 8-2,

[0046] The first part 10-1 of the surface bonding metal layer and the second part 10-2 of the surface bonding metal layer.

[0047] The first opening 11-1, the second opening 11-2,

[0048] Back metal layer 12,

[0049] A first moisture barrier layer 13 - 1 , a second moisture barrier layer 13 - 2 , and a first dielectric layer 14 - 1 . DETAILED DESCRIPTION

[0050] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0051] Embodiment 1

[0052] like Figure 2 As shown, the integrated passive device of the embodiment of the present application includes:

[0053] Substrate 1;

[0054] A grounded back metal layer 12 is formed on the bottom surface of the substrate 1;

[0055] The capacitor bottom plate 3-1 is located on the top surface of the substrate 1;

[0056] A substrate contact through hole 2 penetrates the substrate and connects the capacitor lower plate 3-1 and the back metal layer 12, wherein the back metal layer 12 serves as a capacitor lower port;

[0057] A capacitor dielectric layer 4 is formed on the capacitor lower plate 3-1;

[0058] A capacitor upper plate 5, formed on the capacitor dielectric layer 4;

[0059] The upper capacitor port is formed above the upper capacitor plate 5 and connected to the upper capacitor plate 5 .

[0060] The integrated passive device of the embodiment of the present application, the capacitor lower plate 3-1, the capacitor dielectric layer 4, and the capacitor upper plate 5 are arranged in sequence from bottom to top to form a capacitor. The capacitor lower plate 3-1 is formed on the top surface of the substrate 1, and the back metal layer 12 is formed on the bottom surface of the substrate 1. The substrate contact through hole 2 passes through the substrate 1 and connects the capacitor lower plate 3-1 and the back metal layer 12, and the back metal layer 12 serves as the capacitor lower port. The capacitor upper port is formed above the capacitor upper plate 5 and is connected to the capacitor upper plate 5. In this way, one of the two ports of the capacitor is located at the top, that is, the capacitor upper port, and the other port passes through the substrate and is located at the bottom, that is, the back metal layer 12 serving as the capacitor lower port. With such a structure, the two ports are arranged above and below, and the lower port can be directly connected to the circuit substrate without an additional bonding line, so as to achieve common ground with the active device, so that no additional inductance and loss are generated. Since the integrated passive device of the embodiment of the present application adopts a glass substrate, it has a higher capacitance density and lower loss than existing silicon-based capacitors and GaAs capacitors, and the cost of the integrated passive device on the glass substrate is lower than that of silicon-based and GaAs.

[0061] Specifically, in application, the grounded back metal layer 12 of the integrated passive device of the embodiment of the present application shares a common ground with the active device.

[0062] Specifically, Figure 2 As shown, the size of the capacitor upper plate 5 is smaller than the capacitor dielectric layer 4 .

[0063] The size of the capacitor upper plate 5 is smaller than the capacitor dielectric layer 4 due to processing considerations, and the size of the capacitor upper plate 5 determines the capacitance value. The center position of the capacitor upper plate 5 is consistent with the center position of the capacitor dielectric layer 4.

[0064] Specifically, the depth of the substrate contact through hole 2 ranges from greater than or equal to 100 micrometers to less than or equal to 500 micrometers, and the diameter of the top surface of the substrate contact through hole 2 ranges from greater than or equal to 20 micrometers.

[0065] Specifically, one or more substrate contact through holes 2 may be provided under the same capacitor lower plate 3-1. When there are multiple substrate contact through holes 2, the spacing between the top ends of the substrate contact through holes 2 is greater than or equal to 10 microns.

[0066] In implementation, such as Figure 2 As shown, the substrate contact via 2 and the capacitor dielectric layer 4 are staggered.

[0067] Specifically, Figure 2 As shown, the capacitor lower plate 3-1 is larger than the capacitor dielectric layer 4, and a portion of the capacitor lower plate 3-1 overlaps with the capacitor dielectric layer 4, and another portion does not overlap with the capacitor dielectric layer 4 and serves as a connecting portion of the capacitor lower plate;

[0068] The substrate contact through hole 2 is located below the connecting portion of the capacitor lower plate.

[0069] The staggered arrangement of the substrate contact through hole 2 and the capacitor dielectric layer 4 can make the capacitor dielectric layer 4 have a higher flatness.

[0070] Specifically, Figure 2 As shown, the distance L between the substrate contact through hole 2 and the capacitor dielectric layer 4 is in the range of greater than or equal to 10 microns.

[0071] Specifically, Figure 2 As shown, the capacitor dielectric layer 4 is larger than the capacitor upper plate 5;

[0072] Alternatively, the capacitor dielectric layer 4 and the capacitor upper plate 5 have the same size.

[0073] In implementation, such as Figure 2 As shown, the integrated passive components also include:

[0074] A patterned first metal layer is formed on the substrate 1, wherein a portion of the first metal layer serves as a capacitor lower plate 3-1;

[0075] A first isolation layer 9-1, covering the first metal layer, the capacitor dielectric layer 4, and the capacitor upper plate 5;

[0076] The first contact through hole 6 - 1 is on the capacitor upper plate 5 and penetrates the first isolation layer 9 - 1 .

[0077] In implementation, such as Figure 2 As shown, the integrated passive components also include:

[0078] A second isolation layer 9-2, located on the first isolation layer 9-1;

[0079] A patterned routing metal layer is formed on the first isolation layer 9-1 and in the second isolation layer 9-2, wherein the portion of the routing metal layer located above the upper electrode plate is the first portion 7-1 of the routing metal layer;

[0080] The second contact through hole 8-1 is formed in the first portion 7-1 of the routing metal layer at a position offset from the upper electrode plate and penetrates the second isolation layer 9-2.

[0081] Specifically, the first contact via 6-1 and the second contact via 8-1 are in the lateral direction (ie Figure 3 There is a spacing between them (in the left and right directions), that is, the first contact through hole 6-1 and the second contact through hole 8-1 are staggered in the lateral direction, and the value range of the spacing between the first contact through hole 6-1 and the second contact through hole 8-1 is greater than or equal to 5 microns.

[0082] The first contact via 6 - 1 and the second contact via 8 - 1 are staggered in the lateral direction, which can improve the flatness of the integrated passive device.

[0083] In implementation, such as Figure 2 As shown, the integrated passive components also include:

[0084] A third isolation layer 9-3, covering the second isolation layer 9-2;

[0085] A patterned surface bonding metal layer is formed on the second isolation layer 9-2 and in the third isolation layer 9-3, wherein a portion of the surface bonding metal layer located above the second contact through hole 8-1 is a first portion 10-1 of the surface bonding metal layer, and a position of the third isolation layer located above the first portion of the surface bonding metal layer has a first opening 11-1;

[0086] Among them, the first part 10-1 of the surface bonding metal layer is located at the position of the first opening 11-1 as the upper port of the capacitor; the first opening 11-1 and the capacitor dielectric layer 4 are staggered, so that the part of the first part 10-1 of the surface bonding metal layer exposed from the first opening 11-1 is staggered with the capacitor dielectric layer 4.

[0087] Specifically, the first opening 11-1 and the second contact through hole 8-1 are in the lateral direction (ie Figure 3 There is a spacing between the first opening 11-1 and the second contact through hole 8-1 (in the left and right directions), that is, the first opening 11-1 and the second contact through hole 8-1 are staggered in the lateral direction; the value range of the spacing between the first opening 11-1 and the second contact through hole 8-1 is greater than or equal to 5 microns.

[0088] The first opening 11 - 1 and the second contact through hole 8 - 1 are staggered in the lateral direction, which can improve the flatness of the integrated passive device.

[0089] In this way, the portion of the first portion 10 - 1 of the surface bonding metal layer exposed from the first opening 11 - 1 has a higher flatness.

[0090] In implementation, such as Figure 2 As shown, the first opening 11 - 1 and the substrate contact through hole 2 are respectively located on two sides of the capacitor dielectric layer 4 .

[0091] This arrangement allows the first opening 11-1, the substrate contact through hole 2, and the capacitor dielectric layer 4 to be staggered, so that the portion of the first portion 10-1 of the surface bonding metal layer exposed from the first opening 11-1 has a higher flatness, and the capacitor dielectric layer 4 also has a higher flatness.

[0092] Specifically, Figure 2As shown, the first isolation layer 9 - 1 , the second isolation layer 9 - 2 , and the third isolation layer 9 - 3 constitute the isolation layer 9 .

[0093] In an implementation, the substrate is a glass substrate.

[0094] Compared with silicon-based substrates and GaAs substrates, glass substrates have lower costs.

[0095] In an implementation, the first metal layer is a first metal layer of copper or aluminum.

[0096] Specifically, the portion other than the lower plate of the capacitor in the first metal layer is the second portion 3-2 of the first metal layer, and the second portion of the first metal layer includes an inductor and / or a resistor; the portion other than the first portion 7-1 of the routing metal layer in the routing metal layer is the second portion 7-2 of the routing metal layer; the portion other than the first portion 10-1 of the surface bonding metal layer in the surface bonding metal layer is the second portion 10-2 of the surface bonding metal layer.

[0097] The distance between the capacitor bottom plate 3 - 1 and the second portion 3 - 2 of the first metal layer is greater than or equal to 3 micrometers to avoid mutual influence.

[0098] In implementation, such as Figure 2 As shown, the integrated passive components also include:

[0099] A third contact through hole 6-2, which is on the second portion 3-2 of the first metal layer and penetrates the first isolation layer 9-1, and the third contact through hole 6-2 is connected to the second portion 7-2 of the routing metal layer;

[0100] The fourth contact through hole 8-2 is formed on the second part 7-2 of the routing metal layer and penetrates the second isolation layer 9-2. The fourth contact through hole 8-2 is connected to the second part 10-2 of the surface wiring metal layer. The third isolation layer has a second opening 11-2 at a position above the second part 10-2 of the surface wiring metal layer.

[0101] Actual test results show that the capacitance density and Q value of capacitors based on glass substrates are better than those of silicon-based high-voltage grounding capacitors and GaAs IPDs.

[0102]

[0103] Among them, GaAs_IPD is a gallium arsenide integrated passive device.

[0104] The method for preparing the integrated passive device of the embodiment of the present application comprises the following steps:

[0105] like Figure 5As shown, step S1: forming a substrate through hole on a substrate 1 by using the TGV technology; wherein the TGV technology is Through Glass Via technology.

[0106] like Figure 6 As shown, step S2: filling metal in the substrate through hole to form a substrate contact through hole 2;

[0107] like Figure 7 As shown, step S3: on the substrate 1, a first dielectric layer 14-1 is formed by a spin coating process or a CVD and etching process, and a first metal layer pattern is left, and then a first metal layer is formed by electroplating and CMP process, wherein the first metal layer includes a capacitor lower plate 3-1 and a second portion 3-2 of the first metal layer;

[0108] The material of the first dielectric layer 14-1 may be Polymide; if the passive device includes a capacitor, the first metal layer may be copper or aluminum; if the passive device includes an inductor or a resistor, the first layer of metal may be copper. The above are the steps when the first metal layer is copper. Polymide is polyimide; CVD is the full name of Chemical Vapor Doping; PVD is the full name of Physical Vapor Deposition; CMP is the full name of Chemical-Mechanical Planarization. If the first metal layer is aluminum, the steps are changed to: forming a patterned first metal layer through a PVD process, and then forming the first dielectric layer 14-1 through a spin coating process or a CVD and etching process;

[0109] If 3-1 is aluminum and 3-2 is copper, the process steps are: form a patterned first metal layer 3-1 through a PVD process, then form a first dielectric layer 14-1 through a spin coating process or a CVD and etching process, and leave a second part 3-2 of the first metal layer, and then form a second part 3-2 of the second metal layer through an electroplating process.

[0110] like Figure 8 As shown, step S4: if the passive device includes a capacitor, a capacitor dielectric layer 4 of the capacitor is formed on the first metal layer by CVD and etching processes, and then a second metal layer is formed on the capacitor dielectric layer 4 by PVD and etching processes to serve as the capacitor upper plate 5;

[0111] The material of the capacitor dielectric layer 4 is generally silicon nitride, and the thickness is selected according to the capacitor pressure requirements, which is greater than or equal to 100 nanometers and less than or equal to 1000 nanometers.

[0112] like Fig. 9As shown, step S5: forming a second dielectric layer by spin coating process, and leaving a metal through hole groove for connecting the first contact through hole 6-1 and the third contact through hole 6-2 of the routing metal layer; the second dielectric layer material can be Polymide; the first dielectric layer and the second dielectric layer together serve as the first isolation layer 9-1;

[0113] like Fig.10 As shown, step S6: forming a wiring metal layer by PVD or sputtering, electroplating or other processes, and then forming a third dielectric layer as a second isolation layer 9-2 by spin coating, and leaving a metal through hole groove connecting the second contact through hole 8-1 and the fourth contact through hole 8-2 of the wiring metal layer;

[0114] The routing metal layer includes a routing metal layer first portion 7-1 and a routing metal layer second portion 7-2;

[0115] like Fig.11 As shown, step S7: forming a surface wire bonding metal layer by PVD, sputtering, electroplating or other processes, wherein the surface wire bonding metal layer includes a first surface wire bonding metal layer portion 10-1 and a second surface wire bonding metal layer portion 10-2;

[0116] Then, a fourth dielectric layer is formed as the third isolation layer 9-3 by a spin coating process, leaving the first opening 11-1 and the second opening 11-2 for wire bonding, and removing part of the first dielectric layer to form a scribe line. To optimize the device's WireBonding capability, the metal area exposed in the first opening 11-1 and the second opening 11-2 area in the surface metal wire bonding layer can be gold plated.

[0117] like Fig.12 As shown, step S8: forming a back metal layer 12 by PVD or sputtering process, and forming a pattern by etching process. The back metal layer can be selected from one or more combinations of copper, nickel and gold.

[0118] Embodiment 2

[0119] The integrated passive device of the embodiment of the present application is based on the first embodiment. Figure 3 As shown, it also includes:

[0120] The first moisture barrier layer 13-1 is located in the first isolation layer 9-1, and the first moisture barrier layer covers the capacitor lower plate 3-1, the capacitor dielectric layer 4, the capacitor upper plate 5, and the capacitor lower plate 3-1;

[0121] The first contact hole 6 - 1 penetrates the first moisture barrier layer 13 - 1 .

[0122] To prevent the device from being corroded by water vapor during operation and causing premature failure, a dielectric layer can be deposited as a first moisture barrier layer 13 - 1 after forming the capacitor upper plate 5 . The first moisture barrier layer can be silicon nitride.

[0123] The reason and significance of setting the first moisture barrier layer 13-1 is that the material of the first isolation layer 9-1 is usually easy to absorb water vapor and affect the performance of the capacitor. The first moisture barrier layer 13-1 is set to isolate the capacitor dielectric layer 4 to reduce the impact of water vapor absorbed by the first isolation layer 9-1 on the capacitor dielectric layer 4.

[0124] Embodiment 3

[0125] The integrated passive device of the embodiment of the present application is based on the first embodiment. Figure 4 As shown, the integrated passive components also include:

[0126] A second moisture barrier layer 13-2 is located in the third isolation layer 9-3, and the second moisture barrier layer covers the surface bonding metal layer and the junction between the surface bonding metal layer and the second isolation layer 9-2;

[0127] The first opening 11 - 1 penetrates the second moisture barrier layer 13 - 2 .

[0128] Optionally, in order to optimize the ability of the device to block water vapor, a dielectric layer may be deposited on the wire bonding metal layer as the second moisture barrier layer 13 - 2 , and the second moisture barrier layer 13 - 2 may be silicon nitride.

[0129] The reason and significance of setting the second moisture barrier layer 13-2 is that the material of the third isolation layer 9-3 is usually easy to absorb water vapor, which affects the performance of the capacitor. The second moisture barrier layer 13-2 is set to isolate the capacitor dielectric layer 4 to reduce the water vapor absorbed by the third isolation layer 9-3 from entering the capacitor dielectric layer 4 located in the lower layer, thereby affecting the capacitor dielectric layer 4.

[0130] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0131] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0132] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0133] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0134] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0135] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. An integrated passive device, characterized in that: include: Substrate (1); A grounded back metal layer (12) formed on the bottom surface of the substrate (1); A capacitor bottom plate (3-1) located on the top surface of the substrate (1); A substrate contact through hole (2) penetrates the substrate and connects the capacitor bottom plate (3-1) and the back metal layer (12), wherein the back metal layer (12) serves as a capacitor bottom port, so that the capacitor bottom plate and an active device with a drain located on the back are grounded together; A capacitor dielectric layer (4) formed on the capacitor lower plate (3-1); A capacitor upper plate (5) formed on the capacitor dielectric layer (4); An upper capacitor port, spaced apart and formed above the upper capacitor plate (5) and connected to the upper capacitor plate (5); The capacitor lower electrode plate (3-1) is larger than the capacitor dielectric layer (4), and a portion of the capacitor lower electrode plate (3-1) overlaps with the capacitor dielectric layer (4), while another portion does not overlap with the capacitor dielectric layer (4) and serves as a connecting portion of the capacitor lower electrode plate; The substrate contact through hole (2) is located below the connecting portion of the capacitor lower plate; There is a distance between the substrate contact through hole (2) and the capacitor dielectric layer (4); The substrate is a glass substrate; Integrated passive components also include: A patterned first metal layer is formed on the substrate (1), wherein a portion of the first metal layer serves as a capacitor lower plate (3-1); A first isolation layer (9-1), covering the first metal layer, the capacitor dielectric layer (4), and the capacitor upper plate (5); A first contact through hole (6-1) is located above the capacitor upper plate (5) and penetrates the first isolation layer (9-1); A first moisture barrier layer (13-1) is located inside the first isolation layer (9-1), and the first moisture barrier layer covers the capacitor lower plate (3-1), the capacitor dielectric layer (4), and the capacitor upper plate (5); Wherein, the first contact through hole (6-1) penetrates the first moisture barrier layer (13-1); Integrated passive components also include: a second isolation layer (9-2), located on the first isolation layer (9-1); A patterned routing metal layer is formed on the first isolation layer (9-1) and in the second isolation layer (9-2), wherein the portion of the routing metal layer located above the upper electrode plate is the first portion (7-1) of the routing metal layer; A second contact through hole (8-1), formed on the first portion (7-1) of the routing metal layer and penetrating the second isolation layer (9-2); The first contact through hole (6-1) and the second contact through hole (8-1) are staggered in a lateral direction; Integrated passive components also include: a third isolation layer (9-3), located on the second isolation layer (9-2); A patterned surface bonding metal layer is formed on the second isolation layer (9-2) and in the third isolation layer (9-3), wherein a portion of the surface bonding metal layer located above the second contact through hole (8-1) is a first portion (10-1) of the surface bonding metal layer, and a position of the third isolation layer located above the first portion of the surface bonding metal layer has a first opening (11-1); Wherein, the area where the first part (10-1) of the surface bonding metal layer is exposed from the first opening (11-1) is the capacitor surface bonding area, and the capacitor surface bonding area serves as the capacitor upper port; The first opening (11-1) and the capacitor dielectric layer (4) are staggered, so that the portion of the first portion (10-1) of the surface bonding metal layer exposed from the first opening (11-1) is staggered with the capacitor dielectric layer (4); The first opening (11-1) and the second contact through hole (8-1) are staggered in a lateral direction; The first opening (11-1) and the substrate contact through hole (2) are respectively located on two sides of the capacitor dielectric layer (4).

2. The integrated passive device according to claim 1, characterized in that: The substrate contact through hole (2) and the capacitor dielectric layer (4) are staggered.

3. The integrated passive device according to claim 2, characterized in that: The value range of the spacing L between the substrate contact through hole (2) and the capacitor dielectric layer (4) is greater than or equal to 10 micrometers.

4. The integrated passive device according to claim 3, characterized in that: Also includes: A second moisture barrier layer (13-2) is located in the third isolation layer (9-3), and the second moisture barrier layer covers the surface bonding metal layer and the junction between the surface bonding metal layer and the second isolation layer (9-2); Wherein, the first opening (11-1) penetrates the second moisture barrier layer (13-2).

5. The integrated passive device according to claim 3, characterized in that: The first metal layer is a first metal layer of copper or aluminum.

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