A self-test framework and method suitable for boundary scan analog test card

Abstract

The present invention discloses a self-detection framework and method suitable for a boundary scan simulation test card. The scheme of the present invention provides a self-detection framework suitable for a boundary scan simulation test card, the framework includes at least one boundary scan controller, and at least one boundary scan simulation test card electrically connected to the boundary scan controller; the clock signal end and the state signal end of the boundary scan controller are respectively and sequentially electrically connected to connectors respectively arranged at two ends of the boundary scan simulation test card; the connectors are also electrically connected with a level control unit for realizing self-detection of the boundary scan simulation test card; and the method corresponding to the self-detection framework can solve the problem that the IO of the boundary scan chip of the DUMMY card with different level standards can stably drive the DUMMY card self-detection logic circuit, so as to realize the self-detection of the boundary scan simulation test card.

Description

Technical Field

[0001] The invention belongs to the technical field of boundary scan testing, and in particular relates to a self-detection framework and method suitable for a boundary scan simulation test card. Background Art

[0002] Self-detection of the analog test card is a crucial technology for boundary scan testing. Simple and efficient self-detection is a topic that engineers have been studying. In patent CN2023107828479, a boundary scan chain self-detection logic circuit and self-detection method, it is disclosed that the IO other than the DUMMY card is used to control the boundary scan chain self-detection by cascading multiple DUMMY cards. However, this patented method needs to rely on the IO resources of the controller and the implementation process is complicated.

[0003] There is a boundary scan chip on the DUMMY card, which is the basis of normal boundary scan testing. The chip may be FPGA, ARM, etc. For normal boundary scan testing, the IO of the boundary scan chip of the DUMMY card is usually used for external testing (Extest testing). If this limitation can be overcome, one or two IOs out of more than one hundred or even hundreds of boundary scan chips can be controlled through JTAG to realize self-detection logic. Except for one or two IOs required for self-detection, other IOs are used for normal boundary scan testing, that is, self-detection and normal boundary scan testing are completed step by step, which will get rid of the limitation of using IOs other than the DUMMY card to control the self-detection logic. In addition, the self-detection and normal boundary scan tests of the DUMMY card are closely combined, and only JTAG needs to be controlled. Instructions and data can be flexibly adjusted through the host computer, and no additional wiring is required on the outside of the DUMMY card, which has better compatibility and versatility. However, when the IO of the boundary scan chip is controlled through JTAG, its IO may change with the update of each data, resulting in incorrect self-detection.

[0004] In addition, if the power is not turned off, the self-test may fail due to the looseness of a JTAG signal line. If the power is not turned off, after the problem is found and solved, it is necessary to be able to re-self-test to ensure that the first test is completed. The second and subsequent self-tests cannot be performed, and it is impossible to achieve repeated self-testing and confirmation of boundary scan chain failures. After the boundary scan chip is powered on, there are three default states of its IO, the first is weak pull-up, the second is high resistance, and the third is weak pull-down. In the prior art, it is impossible to overcome the influence of the default level of the boundary scan chip after power-on on the self-test logic architecture, and it is also impossible to achieve self-testing of the boundary scan chip IO in all three default states.

[0005] The self-test needs to support the self-test of the cascade chain composed of the same DUMMY card or different DUMMY cards, and ensure that the self-test method is applicable to the cascade of DUMMY cards with different boundary scan chips, and has generality, so a tight self-test logic architecture and the support of the self-test method are required. However, in the prior art, it is impossible to meet the compatibility of the IO level self-test of the boundary scan chip of different DUMMY cards, and it is also impossible to solve the problem that the IO of the boundary scan chip of different level standards DUMMY cards can stably drive the DUMMY card self-test logic circuit to achieve self-test.

[0006] Therefore, in view of the technical problems and defects of the above process being complicated, resulting in incorrect self-detection, inability to achieve repeated re-self-detection and confirmation of boundary scan chain faults, and inability to meet the compatibility of IO level self-detection of different DUMMY card boundary scan chips, it is urgently necessary to design and develop a self-detection architecture and method suitable for boundary scan simulation test cards. Summary of the invention

[0007] In order to overcome the shortcomings and difficulties of the above-mentioned prior art, the purpose of the present invention is to provide a self-detection architecture and method suitable for a boundary scan simulation test card, which can meet the compatibility of IO level self-detection of different DUMMY card boundary scan chips, and can solve the problem that the IO of different level standard DUMMY card boundary scan chips can stably drive the DUMMY card self-detection logic circuit, thereby realizing the self-detection of the boundary scan simulation test card.

[0008] The first object of the present invention is to provide a self-test framework applicable to a boundary scan analog test card; the second object of the present invention is to provide a self-test method applicable to a boundary scan analog test card;

[0009] The first object of the present invention is achieved as follows: the framework includes at least one boundary scan controller, and at least one boundary scan simulation test card electrically connected to the boundary scan controller;

[0010] The clock signal end and the status signal end of the boundary scan controller are electrically connected to the connectors respectively arranged at the two ends of the boundary scan simulation test card; a level control unit for realizing self-detection of the boundary scan simulation test card is also electrically connected between the connectors.

[0011] Further, the connector includes a first point-1 connector and a first point-2 connector; the clock signal of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector respectively; the status signal end of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector respectively; the data input end of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector in sequence; the data output end of the first point-2 connector is electrically connected to the level control unit and the first point-1 connector in sequence.

[0012] Furthermore, at least one boundary scan chip is arranged in the level control unit; the boundary scan chip is electrically connected to a NAND gate and at least two single-pole double-throw switches in sequence through an arranged comparator.

[0013] Further, the single-pole double-throw switch includes a first point-1 single-pole double-throw switch and a first point-2 single-pole double-throw switch; the output signal end of the boundary scan chip is connected to the single-pole end A of the first point-1 single-pole double-throw switch; the first IO end of the boundary scan chip is respectively connected to one end of the first point-1 resistor and the first positive input end of the first point-2 comparator; the other end of the first point-1 resistor is respectively connected to the reserve power supply end and one end of the first point-2 resistor; the other end of the first point-2 resistor is respectively connected to the second IO end of the boundary scan chip and the second positive input end of the first point-2 comparator; the first negative input end of the first point-2 comparator is respectively connected to one end of the first point-3 resistor and one end of the first point-5 resistor; the other end of the first point-3 resistor is respectively connected to the power supply end and one end of the first point-4 resistor; the other end of the first point-4 resistor is respectively connected to the second negative input end of the first point-2 comparator and one end of the first point-6 resistor; the other end of the first point-5 resistor and the other end of the first point-6 resistor are commonly grounded;

[0014] The first output end of the first point two comparator is connected to the first A end of the NAND gate; the second output end of the first point two comparator is connected to the second A end of the NAND gate; the second B end of the NAND gate is respectively connected to the first Y end of the NAND gate, the S end of the single pole of the first point one single-pole double-throw switch, and the S end of the single pole of the first point two single-pole double-throw switch; the first B end of the NAND gate is connected to the second Y end of the NAND gate; the first B end of the single pole of the first point one single-pole double-throw switch is connected to the A end of the single pole of the first point two single-pole double-throw switch; the second B end of the single pole of the first point one single-pole double-throw switch is connected to the data input end of the first point two connector; the second B end of the single pole of the first point two single-pole double-throw switch is connected to the data output end of the first point two connector; the NAND gate, the single pole of the first point one single-pole double-throw switch and the single pole of the first point two single-pole double-throw switch share a power supply end.

[0015] Furthermore, the model of the boundary scan chip is LFE3-35EA-8FN484C; the model of the comparator is LM393DR; the model of the NAND gate is SN74LVC2G132DCUR; and the model of the single-pole double-throw switch is 74CBTLV3257PW,118.

[0016] The second object of the present invention is achieved by: the method is applied to a self-test framework suitable for a boundary scan analog test card; the method comprises the following steps:

[0017] Performing self-detection reset processing on the boundary scan chain, setting the first IO terminal of the first boundary scan simulation test card to 1 and the second IO terminal to 0; and maintaining the first IO terminal of the first boundary scan simulation test card to 1 and setting the second IO terminal to 1;

[0018] Performing a self-test on the first boundary scan simulation test card, wherein the content of the test is an IDcode self-test of the boundary scan chip of the first boundary scan simulation test card;

[0019] After the first boundary scan simulation test card self-detects normal, the second boundary scan simulation test card is turned on through the first boundary scan simulation test card, and the IR instruction and DR data of the external test of the first boundary scan simulation test card are sent, and the first IO terminal of the boundary scan simulation test card ((DUMMY card)) is set to 0, while the second IO terminal is kept at 1;

[0020] After the second boundary scan simulation test card is switched on, the Bypass instruction of the first boundary scan simulation test card and the IDcode instruction of the second boundary scan simulation test card are sent from right to left in sequence;

[0021] After the second boundary scan simulation test card self-detects normally, the Bypass instruction of the first boundary scan simulation test card + the IR instruction of the external test of the second boundary scan simulation test card are sent from right to left through JTAG, and then 1-bit data + the Extest test data of the second boundary scan simulation test card are sent from right to left, and the first IO terminal of the second boundary scan simulation test card is set to 0, while keeping the second IO terminal at 1;

[0022] Send the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the IDcode instruction of the third boundary scan simulation test card from right to left; then send 32-bit data;

[0023] From right to left, send the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the Extest instruction of the third boundary scan simulation test card, and then send two bits of data + the Extest data of the third boundary scan simulation test card from right to left, cut through the next level fourth boundary scan simulation test card, and so on, until the self-test completes the last boundary scan simulation test card.

[0024] Further, the self-detection reset processing of the boundary scan chain is performed, the first IO terminal of the first boundary scan simulation test card is set to 1, and the second IO terminal is set to 0; and the first IO terminal of the first boundary scan simulation test card is kept at 1, and the second IO terminal is set to 1, and further includes:

[0025] First, an IR instruction of an Extest test of a boundary scan chip of a first boundary scan simulation test card is sent through JTAG; wherein the content of the IR instruction is 11010101;

[0026] Sending DR data of the Extest test of the boundary scan chip of the first boundary scan simulation test card;

[0027] The DR data is parsed and sent from right to left by the host computer, sent down in binary format by the controller, and updated after the sending is completed, thus completing the configuration.

[0028] Furthermore, the self-detection of the first boundary scan simulation test card includes self-detection of the IDcode of the boundary scan chip of the first boundary scan simulation test card, and further includes:

[0029] Send the IR instruction of the IDcode test of the first boundary scan simulation test card, send it from right to left, and then send 32 bits of data; wherein the content of the IR instruction is 00011001;

[0030] Determine whether the IDcode data pushed out by the first boundary scan simulation test card is abnormal, if yes, re-self-check, otherwise execute the next step.

[0031] Furthermore, after the second boundary scan simulation test card is switched on, the Bypass instruction of the first boundary scan simulation test card and the IDcode instruction of the second boundary scan simulation test card are sent sequentially from right to left, further comprising:

[0032] Determine whether the IDcode data pushed out by the second boundary scan simulation test card is abnormal, if yes, re-self-check, otherwise execute the next step.

[0033] Further, the method of sending the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the IDcode instruction of the third boundary scan simulation test card in sequence from right to left; and then sending 32-bit data, also includes:

[0034] Determine whether the IDcode data pushed out by the third boundary scan simulation test card is abnormal, if yes, re-self-check, otherwise execute the next step.

[0035] The present invention provides a self-detection framework suitable for a boundary scan simulation test card, wherein the framework comprises at least one boundary scan controller and at least one boundary scan simulation test card electrically connected to the boundary scan controller; a clock signal end and a state signal end of the boundary scan controller are electrically connected to connectors respectively arranged at two ends of the boundary scan simulation test card in sequence; a level control unit for realizing self-detection of the boundary scan simulation test card is also electrically connected between the connectors; and a method corresponding to the self-detection framework can solve the problem that the IO of a boundary scan chip of a DUMMY card with different level standards can stably drive a DUMMY card self-detection logic circuit, thereby realizing self-detection of the boundary scan simulation test card.

[0036] That is to say, the scheme of the present invention can realize the close combination of the self-test of the DUMMY card and the normal boundary scan test, and only needs to control JTAG. The instructions and data can be flexibly adjusted by the host computer, and no additional wiring is required on the outside of the DUMMY card, which has better compatibility and versatility; moreover, the correctness and stability of the self-test logic architecture and method can be guaranteed. In addition, the self-test of this scheme adds a reset function, that is, the reset self-test logic is realized by controlling the IO of the boundary scan chip through JTAG; in the case of power failure, after the problem is found and solved, it can be self-tested again, ensuring that the first test is completed, and the second and more self-tests can be performed, so as to facilitate the repeated self-test and confirmation of the boundary scan chain fault. After the boundary scan chip is powered on, the influence of the default level of the boundary scan chip after power-on on the self-test logic architecture is overcome, ensuring that the boundary scan chip IO can perform self-test in the three default states, and the self-test logic and method are applicable to general boundary scan chips.

[0037] The self-detection scheme supports the self-detection of the cascade chain composed of the same DUMMY card or different DUMMY cards. The self-detection method is applicable to the cascade of DUMMY cards with different boundary scan chips and is general. It can also meet the compatibility of the IO level self-detection of different DUMMY card boundary scan chips, and solve the problem that the IO of the DUMMY card boundary scan chip with different level standards can stably drive the DUMMY card self-detection logic circuit to achieve self-detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of a self-test framework suitable for a boundary scan simulation test card of the present invention;

[0040] Figure 2 This is a schematic diagram of a self-test logic architecture of a DUMMY card according to an embodiment of the present invention, which is suitable for a boundary scan analog test card;

[0041] Figure 3 Schematic diagram of the self-test logic architecture of three DUMMY cards in the embodiment of the self-test architecture suitable for a boundary scan analog test card of the present invention;

[0042] Figure 4 A schematic flow chart of a self-detection method applicable to a boundary scan simulation test card of the present invention;

[0043] In the figure: J1.1-first point one connector; J1.2-first point two connector; K1.1-first point one single-pole double-throw switch; K1.2-first point two single-pole double-throw switch; R1.1-first point one resistor; R1.2-first point two resistor; R1.3-one end of the first point three resistor; R1.4-first point four resistor; R1.5-first point five resistor; R1.6-first point six resistor; IO1-first IO end of the boundary scan chip; IO2-second IO end of the boundary scan chip;

[0044] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0045] In order to better understand the purpose, technical solutions and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0046] The present invention may also be implemented or applied through other different specific examples, and the details in this specification may also be modified and changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0048] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. Secondly, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0049] The present invention will be further described below in conjunction with the accompanying drawings. Figure 1-3 As shown, the present invention provides a self-detection framework suitable for a boundary scan simulation test card, the framework includes at least one boundary scan controller, and at least one boundary scan simulation test card electrically connected to the boundary scan controller; the clock signal end and the status signal end of the boundary scan controller are electrically connected to the connectors respectively arranged at both ends of the boundary scan simulation test card in sequence; the connectors are also electrically connected with a level control unit for realizing self-detection of the boundary scan simulation test card.

[0050] The connector includes a first point-1 connector and a first point-2 connector; the clock signal of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector respectively; the state signal end of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector respectively; the data input end of the first point-1 connector is electrically connected to the level control unit and the first point-2 connector in sequence; the data output end of the first point-2 connector is electrically connected to the level control unit and the first point-1 connector in sequence. At least one boundary scan chip is arranged in the level control unit; the boundary scan chip is electrically connected to a NAND gate and at least two single-pole double-throw switches in sequence through a set comparator. The single-pole double-throw switch comprises a first point-one single-pole double-throw switch and a first point-two single-pole double-throw switch; the output signal end of the boundary scan chip is connected to the single-pole end A of the first point-one single-pole double-throw switch; the first IO end of the boundary scan chip is respectively connected to one end of the first point-one resistor and the first positive input end of the first point-two comparator; the other end of the first point-one resistor is respectively connected to the reserve power supply end and one end of the first point-two resistor; the other end of the first point-two resistor is respectively connected to the second IO end of the boundary scan chip and the second positive input end of the first point-two comparator;

[0051] The first negative input terminal of the first point two comparator is connected to one end of the first point three resistor and one end of the first point five resistor respectively; the other end of the first point three resistor is connected to the power supply terminal and one end of the first point four resistor respectively; the other end of the first point four resistor is connected to the second negative input terminal of the first point two comparator and one end of the first point six resistor respectively; the other end of the first point five resistor and the other end of the first point six resistor are grounded together; the first output terminal of the first point two comparator is connected to the first A terminal of the NAND gate; the second output terminal of the first point two comparator is connected to the second A terminal of the NAND gate; the second B terminal of the NAND gate is connected to the first Y terminal of the NAND gate, the S terminal of the single pole of the first point one single-pole double-throw switch, and the S terminal of the single pole of the first point two single-pole double-throw switch respectively; the first B terminal of the NAND gate is connected to the second Y terminal of the NAND gate;

[0052] The first B end of the single pole of the single pole double throw switch at the first point one is connected to the A end of the single pole of the single pole double throw switch at the first point two; the second B end of the single pole of the single pole double throw switch at the first point one is connected to the data input end of the first point two connector; the second B end of the single pole of the single pole double throw switch at the first point two is connected to the data output end of the first point two connector; the NAND gate, the single pole of the single pole double throw switch at the first point one and the single pole of the single pole double throw switch at the first point two share a power supply end.

[0053] The model of the boundary scan chip is LFE3-35EA-8FN484C; the model of the comparator is LM393DR; the model of the NAND gate is SN74LVC2G132DCUR; and the model of the single-pole double-throw switch is 74CBTLV3257PW,118.

[0054] Specifically, in the embodiment of the present invention, in order to achieve the above technical purpose, the present invention adopts the following technical solution: the present invention sequentially sends the IR (instruction register) instruction and DR (data register) data of the IDcode test and the IR (instruction register) instruction and DR (data register) data of the Extest test through the JTAG port and combines the Bypass instruction to control the register bit step by step, complete the step-by-step conduction of the link and perform step-by-step self-detection. In the solution of the present invention, IR refers to the instruction register; DR refers to the data register; the external (Extest) test instruction and data are also defined in BSDL.

[0055] The link's step-by-step conduction content is: by sending the Extest test IR command and DR data, the state of two IOs of each DUMMY card boundary scan chip is changed step by step. The purpose is to control the boundary scan chain step by step. The two IOs are IO1 and IO2, of which IO1 is used to control the next level of DUMMY card to be switched on. The purpose of step-by-step self-detection is achieved by switching on step by step. IO2 is used for reset. Each DUMMY card in the boundary scan chain will have a reset IO2. The reset IO2 of all DUMMY cards are connected together throughout the entire self-detection link. In this way, the reset circuits are designed to be connected together, and any DUMMY card edge in the boundary scan chain can be controlled through JTAG. The IO2 of the boundary scan chip completes the reset of all DUMMY cards; considering that only the clock signal TCK, status signal TMS, and data input signal TDI of the first DUMMY card are always connected to the controller and will not be disconnected, and can be reset through JTAG control, while the TCK, TMS, and TDI of other DUMMY cards may not be connected, so only by controlling the boundary scan chip of the first DUMMY card to complete the reset can the stability of the reset be guaranteed. Considering the consistency of each DUMMY card, each DUMMY card must have the same design; the principle of reset is to release the latch state of all DUMMY cards that cut through the next level and release the link to the initial state without self-detection.

[0056] The present invention completes the reset through the first DUMMY card, that is, IO2 of DUMMY card 1. After the latch is released, the next level can be controlled through IO1 of the boundary scan chain DUMMY card 1, and then the second and subsequent self-tests can be performed, that is, the two IOs are controlled by JTAG, and self-tests can be performed again without power failure.

[0057] In JTAG mode, the normal boundary test will eventually be followed by the Extest test, which is also completed by sending instructions and data through JTAG. After the self-test is completed, the normal boundary scan test state is entered. Except for the two IOs occupied by the self-test, the other IOs can be used as IO resources for the Extest test as well as for the normal boundary scan test.

[0058] In order to ensure that the self-test is applicable to the DUMMY card designed with a general boundary scan chip, it is necessary to overcome the limitation of the default state of the IO of the boundary scan chip, so that it can be applicable to the three states of weak pull-up, high resistance and weak pull-down in the IO default state. Therefore, JTAG is first controlled to ensure that the initial self-test state of the boundary scan chain meets the requirements, and then the boundary scan chain is correctly and stably self-tested step by step. The IO1 of all DUMMY cards in the chain is kept at a high level state under the action of the pull-up resistor. Under this condition, after the IR instruction of the Extest test of the DUMMY card 1 boundary scan chip is sent through JTAG, the DR data of the Extest test is sent. The purpose is to set IO1 to 1 and IO2 to 0 to put the boundary scan chain in a reset state. At this time, the initial latch state of the logic circuit composed of the NAND gate is released, and DUMMY card 1 is connected to the boundary scan chain. Then the second data is sent, keeping IO1 at 1 and IO2 at 0. Set to 1. The purpose of setting IO2 to 1 is to cancel the reset, thereby ensuring that the initial state of the boundary scan chain self-detection is correct and stable. Under this condition, first perform self-detection on DUMMY card 1. The method is to send the IR instruction for the IDcode test of DUMMY card 1, and then send 32-bit data. The data can be any 32-bit data, such as 32 1s, to deduce the IDcode data of the boundary scan chip of DUMMY card 1. The IDcode data of the DUMMY card is consistent with the definition in the BSDL file and is fixed. It does not change with the 32-bit data sent. If the IDcode data is correctly derived, that is, it is consistent with the definition in the BSDL file, it indicates that the link self-detection of DUMMY card 1 is faulty. If the IDcode data cannot be correctly derived, it indicates that DUMMY card 1 is faulty or the line connecting the controller to DUMMY card 1 is faulty. At this time, maintenance is carried out. After the maintenance is completed, self-detection is restarted from the beginning.

[0059] After DUMMY card 1 self-tests correctly, after sending the IR command of Extest test of DUMMY card 1, DR data is sent again, the purpose is to set IO1 of DUMMY card 1 to 0 and IO2 to 1. At this time, DUMMY card 1 is switched to the next level, and DUMMY card 2 is connected to the boundary scan chain. Under the action of latch logic, DUMMY card 2 remains connected. At this time, the switched link is the cascade link of DUMMY card 1 and DUMMY card 2. At this time, self-test of DUMMY card 2 is performed, and the IR command of IDcode test of DUMMY card 2 is sent. The Bypass instruction of DUMMY card 1 bypasses DUMMY card 1, and then sends the DR data of 32-bit IDcode test. The data sent can be any 32-bit data. The purpose is to derive the IDcode of DUMMY card 2. If it is correctly derived, it indicates that the link self-detection of DUMMY card 2 is normal. If the IDcode data cannot be correctly derived, it indicates that DUMMY card 2 is faulty or the line between DUMMY card 1 and DUMMY card 2 is faulty. At this time, maintenance is carried out. After the maintenance is completed, self-detection is restarted from the beginning.

[0060] After DUMMY card 2 self-detects correctly, it sends the IR command of DUMMY card 2's Extest test + the Bypass command of DUMMY card 1 from right to left, and then sends 1-bit data + DR data of DUMMY card 2's Extest test from right to left. The function of 1-bit data is that the DR register occupies one bit after DUMMY card 1 sends the Bypass command. If only the DR data of DUMMY card 2's Extest test is sent, the final data of DUMMY card 2 will be pushed less by 1 bit, and the configuration of IO1 and IO2 cannot be As expected, according to this method, IO1 of DUMMY card 2 can be set to 0 and IO2 to 1. At this time, DUMMY card 2 is switched to the next level. At this time, DUMMY card 1, DUMMY card 2 and DUMMY card 3 form a boundary scan chain. Under the action of latching, DUMMY cards 1 and 2 remain connected, and the self-test of the third DUMMY card is performed. From right to left, the Bypss instruction of DUMMY card 1 + the Bypass instruction of DUMMY card 2 + the IR instruction of the IDcode test of DUMMY card 3 are sent in sequence. The purpose is to bypass DUMMY card 1 and DUMMY card 2. Then 32-bit data is sent. The data sent can also be any 32-bit data. The IDcode of DUMMY card 3 is derived. If it is correctly derived, it indicates that there is no fault in the link self-test of DUMMY card 3. If the IDcode data cannot be correctly derived, it indicates that DUMMY card 3 is faulty or the line between DUMMY card 2 and DUMMY card 3 is faulty. At this time, maintenance is carried out. After the maintenance is completed, self-test is restarted from the beginning.

[0061] By analogy, when the self-test is determined to fail, the link is promptly repaired to ensure that each normal boundary scan test will not be unable to be correctly tested due to link failure, until the last DUMMY card is tested and the boundary scan chain is fully connected, then entering the normal boundary scan test state.

[0062] The IDcode of the boundary scan chip is 32 bits. When testing the IDcode, there is no need to consider the additional bit of the DR data bit after the Bypass instruction is sent. For each newly added DUMMY card, only 32 bits of data need to be sent to correctly derive the IDcode data of the last newly added DUMMY card.

[0063] After each self-test of a newly added DUMMY card, the IR command and DR data of the Extest test will be sent to this DUMMY card, and the DUMMY card before this DUMMY card will be bypassed. The purpose is to control only one DUMMY card to send the Extest test command and data to conduct the next level and do the IDcode self-test of the next level. There is a lot of Extest data, so the Bypass command is used, so there is no need to control the Extest data of more DUMMY cards. Each time the next level is turned on, only the configuration of the newly added DUMMY card to conduct the IO1 of the next level needs to be considered, which can simplify the amount of data sent and complete the self-test of the boundary scan chain step by step. Since the data register of each DUMMY card after the Bypass occupies 1 bit, it is necessary to consider how many DUMMY cards are Bypassed, which will occupy more register units, and then add a few bits of data to ensure that the DR data of the Extest of the controlled DUMMY card correctly enters the corresponding register unit, thereby completing the conduction of the next level and then performing self-test step by step.

[0064] The above self-test is completed in the form of serial vector format statements (SVF statements). The host computer presets the hexadecimal SVF statements in advance and can directly control JTAG to complete the self-test. The content of the self-test SVF statement is JTAG instructions or data, which is flexibly set according to the needs of self-test and executed in sequence, independent of normal testing. The IO1 and IO2 that complete the self-test can be any IO with output capability on the boundary scan chip. The SVF statement is executed through JTAG, and the corresponding instructions and data are sent in sequence to control the two IOs to achieve self-test.

[0065] The self-test of the DUMMY chain tests the IDcode of each DUMMY card in the boundary scan chain in turn. After testing the IDcode of each DUMMY card, the previous DUMMY card is bypassed, and the Extest instruction and data are sent to the DUMMY card whose IDcode has just been tested. The next-level DUMMY card is turned on to perform IDcode test on the next-level DUMMY card, and so on. It is ensured that the newly added DUMMY card is self-tested at all times. Through self-testing at each level, the faulty DUMMY card can be located, and the fault can be repaired and eliminated in time to improve production efficiency.

[0066] In the normal boundary scan test state, the register unit (INOUT cell) and control register unit (Controlcell) with input and output capabilities corresponding to the IO2 pin in the BSDL file of the boundary scan chip of each DUMMY card are changed to an internal register unit (Internal cell) and assigned a safety value. The safety value is 1 to ensure that IO2 does not output 0 when the data is updated. When performing normal testing according to the modified BSDL file, the link connection state will not be changed due to reset, and normal boundary scan testing can be performed stably. In addition, after the link is cut, changes in IO1 will not affect the link connection state, so IO1 does not need special processing.

[0067] like Figure 1As shown in the figure, it is the self-test logic architecture of a DUMMY card. The TCK, TMS, TDI and TDO signals of the boundary scan controller are connected to the connector J1.1 of DUMMY card 1 respectively. The connected signals are TCK1.1, TMS1.1, TDI1 and TDO_BACK1.2 respectively. Among them, TCK1.1 and TMS1.1 are connected to the connector J1.2 of DUMMY card 1. The signals are TCK1.2 and TMS1.2 respectively, which are the clock signal and status signal of the boundary scan chip JTAG respectively. The TDI1 signal of DUMMY card 1 is connected to the boundary scan chip U1.1 (model: LFE3-35EA-8F N484C) is connected to the input signal of the boundary scan chip JTAG. The chip JTAG output signal is TDO_OUT1, which is connected to the single-pole terminal A of the single-pole double-throw switch K1.1 after output. IO1 and IO2 of U1.1 are used for boundary scan self-detection, where IO1 is used to cut through the next level and IO2 is used to reset. The method is as follows: Comparator U1.2 (model: LM393DR) is a two-way comparator, where R1.3 and R1.4 have a resistance of 4.5kΩ, and R1.5 and R1.6 have a resistance of 1kΩ. The negative input terminals of the two comparators are divided by R1.3 and R1.5 and R1.4 and R1.6 respectively, and the voltage of 3.3V After the resistor voltage divider, the voltage of the two negative input terminals of the comparator is 0.6V. The IO high level standard of the boundary scan chip may be 1.05V to 3.3V. IO1 and IO2 are connected to the positive input terminals of the two comparators respectively. When IO1 and IO2 are at a high level output of 1.05V to 3.3V, they can be converted by the comparator to output a stable 3.3V high level to the NAND gate, thereby ensuring that the high level standard of the boundary scan chip from 1.05V to 3.3V can be stably self-detected. IO1 and IO2 are connected to two 2kΩ pull-up resistors R1.1 and R1.2 respectively. The pull-up power supply is the Bank power supply of the boundary scan chip. The Bank power supply The voltage is consistent with the high-level voltage output by IO1 and IO2. The pull-up resistor is selected to be smaller, 2kΩ, in order to adapt to general boundary scan chips. When the chip's IO pins are in the default weak pull-up, high-resistance or weak pull-down modes, the level of the positive input of the comparator can be guaranteed to be higher than 0.6V of the negative input, thereby ensuring that both outputs of the comparator are high under the default conditions. Only when IO1 or IO2 is controlled by JTAG to set one or both of these levels to low, the level of the positive input of the comparator is lower than 0.6V, and the comparator will output 0, thereby ensuring that the self-detection adapts to general boundary scan chips, and the three default modes can be realized.

[0068] The high and low levels of IO1 and IO2 will determine the high and low levels of comparator OUT1 and OUT2 respectively. First, IO1 is set to 1 and IO2 is set to 0. The OUT1 output of comparator U1.2 is 1 and the OUT2 output is 0. The corresponding outputs of inputs 1A and 1B of NAND gate U1.3 are 1Y, and the corresponding outputs of 2A and 2B are 2Y. According to the principle of NAND gate, since OUT2 output is 0 and 2A input is 0, 2Y output is 1. 2Y is connected to 1B input, and 1B input is 1. Since OUT1 output is 1 and OUT1 is connected to 1A of NAND gate, the states of 1A and 1B of NAND gate are both 1, so the state of 1Y is 0. 1Y controls the signal selection S input of the single-pole double-throw switch. When the S input is 0, A and B1 of single-pole double-throw switch K1.1 are connected. Only DUMMY card 1 is connected to the boundary scan chain. 1Y is connected to 2B, and the state of 2B is 0. It is known that the state of 2A is 0, so the state of 2Y is 1.

[0069] Then set IO2 to 1, that is, set OUT2 to 1, then 2A of the NAND gate is 1, 2B is 0, and the state of 2Y remains unchanged at 1. The purpose at this time is to cancel the reset of IO2.

[0070] At this time, the DUMMY card 1 can be self-tested, the IDcode of the DUMMY card 1 can be read, and it can be determined whether the DUMMY card 1 has passed the self-test.

[0071] Then set IO1 to 0, that is, set 1A to 0, and the state of 1Y changes from 0 to 1. At this time, the level of the single-pole end S input of the single-pole double-throw switch K1.1 changes from 0 to 1. At this time, the single-pole end A is connected to B2 and disconnected from B1. At this time, the link is connected to the next level, that is, DUMMY card 1 and the next DUMMY card (DUMMY card 2) form a boundary scan chain. At this time, the next DUMMY card (DUMMY card 2) can perform self-detection.

[0072] K1.1 and K1.2 are the same single-pole double-throw switches with the same control signal S. When A of K1.1 is connected to B1, A of K1.2 is disconnected from B2, thereby ensuring that when performing self-test on a single DUMMY card, path TDO1.1 can return to TDO_BACK1.2, and at the same time cut off the return path of the next-level TDO, thereby eliminating interference with the return path signal of TDO of the next-level DUMMY card; when A of K1.1 is connected to B2, the output path TDO_OUT1 of DUMMY card 1 is connected to TDO1.2, thereby conducting to the next level. At this time, A of K1.2 is also connected to B2, thereby ensuring that when the next level is conducted, the return path TDO_BACK1.1 of TDO is also automatically connected to TDO_BACK1.2, thereby ensuring the JTAG signal integrity of the boundary scan chain composed of two DUMMY cards.

[0073] The above is an explanation of the logical structure of a DUMMY card. Next, the self-test method is explained in detail through the SVF statement. The SVF statement can be changed through the upper computer. During the self-test, the controller controls JTAG to execute the SVF statement and send binary instructions and data to manipulate the boundary scan chip to achieve the purpose of self-test. In order to clearly show the implementation process of self-test, all instructions and data are not converted and described by hexadecimal SVF statements. They are all described in detail using binary data that can be recognized by the boundary scan chip, such as: DUMM The model of the boundary scan chip of Y card 1 is: LFE3-35EA-8FN484C. By looking up the BSDL of the chip, we can see that the IR instruction of the IDcode test is: 00011001, the DR data of the fixed 32-bit IDcode is: 00000001000000010010000001000011, the Bypass instruction is: 11111111, the Extest instruction is: 11010101, the cell length is 675, and the cell numbers are arranged from 674 to 0.

[0074] The cell numbered 575 is a Control cell, and the cell numbered 576 is an INOUT cell. The Control cell of 575 controls whether the cell of 576 outputs. The safety value of the 575Control cell is 1, that is, when the cell of 575 is configured to be 1 through JTAG serial data transmission, after the data is updated, the INOUT cell of 576 will not output. When the cell of 575 is configured to be 0 through JTAG serial data transmission, after the data is updated, the INOUT cell of 576 will output according to the data of 0 or 1 configured by 576, thereby realizing the control of the output 0 and 1 of the INOUT cell of 576. The 576INOUT cell corresponds to the IO pin W21 output of the boundary scan chip, and also corresponds to IO1 of the link architecture of the present invention.

[0075] Similarly, cell 671 is a control cell and cell 672 is an INOUT cell. Control cell 671 controls whether cell 672 outputs. The safety value of cell 671 is 1, that is, when cell 671 is configured to be 1 through JTAG serial data transmission, after the data is updated, INOUT cell 672 does not output. When cell 671 is configured to be 0 through JTAG serial data transmission, after the data is updated, INOUT cell 672 will output data 0 or 1 configured by 672, thereby enabling flexible output of 0 and 1 of INOUT cell 672. INOUT cell 672 corresponds to the output of IO pin F22 of the boundary scan chip, and also corresponds to IO2 of the link architecture of the present invention.

[0076] Since the TCK, TMS and TDI of the JTAG signals of DUMMY card 1 are all connected, the data returned by TDO is not concerned.

[0077] First, complete the reset of the initial state of self-test, and only set IO1 of DUMMY card 1 to 1 and IO2 to 0. The method is as follows: First, send the IR instruction of the Extest test of the boundary scan chip of DUMMY card 1 through JTAG. The content of the instruction is: 11010101, and then send the DR data of the Extest test of the boundary scan chip of DUMMY card 1. The content of the DR data needs to pay close attention to the configuration of the INOUT register bits of IO1 and IO2 and their Control cells. According to the BSDL file analysis of the boundary scan chip above, to set IO1 to 1, you need to set the Control cell of 575 cell is configured to 0, and INOUTcell of 576 is configured to 1, so that chip pin W21 can output 1, corresponding to IO1 described in the present invention; similarly, to set IO2 to 0, it is necessary to configure Controlcell of 671 to 0, and INOUTcell of 672 to 0, so that chip pin F22 can output 0, corresponding to IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 1 0 + 95 1s + 2 0s + 2 1s, which is in hexadecimal: 143 Fs + 1 7 + 23 Fs + 1 7 + 1 6, specifically:

[0078] 67FFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the host computer parses and sends these data from right to left, and delivers them in binary format through the controller. After the delivery is completed, it is updated and the configuration is completed.

[0079] After the configuration of setting IO1 of DUMMY card 1 to 1 and IO2 to 0 is completed, DUMMY card 1 has been reset and connected to the boundary scan chain. Next, the reset needs to be cancelled, that is, the state of IO1 remains unchanged, and the state of IO2 changes from 0 to 1, making the final preparation for self-test. Similarly, first send the IR instruction of the Extest test of the boundary scan chip of DUMMY card 1 through JTAG. The content of the instruction is: 11010101. To set IO1 to 1, the cell of 575 needs to be configured to 0 and the cell of 576 needs to be configured to 1, so that the chip pin W21 can keep outputting 1, corresponding to the IO1 described in the present invention; similarly, to set IO2 to 1, the Control of 671 is required cell is configured as 0, and INOUTcell of 672 is configured as 1, so that the chip pin F22 can output 1, corresponding to IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 1 0 + 95 1s + 1 0 + 3 1s, which is converted into hexadecimal: 143 Fs + 1 7 + 23 Fs + 2 7s, specifically:

[0080] 77FFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the host computer parses and sends these data from right to left, and delivers them in binary format through the controller. After the delivery is completed, it is updated and the configuration is completed.

[0081] The initial state of the self-test is ready. At this time, only DUMMY card 1 is connected to the boundary scan chain. The IDcode of DUMMY card 1 is pushed out to perform the self-test of DUMMY card 1. The method is as follows:

[0082] First send the IR command for IDcode test, the command is: 00011001, send it from right to left, and then send 32-bit data. The 32-bit data sent is any 32-bit data, such as sending 32 1s. The purpose is to extract the DR data of the 32-bit IDcode fixed by the boundary scan chip. The data is: 00000001000000010010000001000011. If it is correctly extracted, it indicates that DUMMY card 1 is normal. If it cannot be correctly extracted, it indicates that DUMMY card 1 is faulty or the JTAG connection between DUMMY card 1 and the controller is faulty. At this time, maintenance can be carried out. After the maintenance is completed, self-test can be performed again until the self-test of DUMMY card 1 is normal.

[0083] After the self-test of DUMMY card 1 is normal, the next level DUMMY card (DUMMY card 2) is connected through DUMMY card 1, and the IR instruction and DR data of the Extest test of DUMMY card 1 are sent, the purpose is to set IO1 of the DUMMY card to 0, while keeping IO2 to 1. Similarly, the IR instruction of the Extest test of the boundary scan chip of DUMMY card 1 is first sent through JTAG. The content of the instruction is: 11010101. To set IO1 to 0, the Control cell of 575 needs to be configured to 0, and the INOUTcell of 576 needs to be configured to 0, so that the chip pin W21 can keep outputting 0, corresponding to the IO1 described in the present invention; similarly, to keep IO2 to 1, the Control cell of 671 .... cell is configured as 0, and INOUTcell of 672 is configured as 1, so that the chip pin F22 can output 1, corresponding to IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 2 0s + 94 1s + 1 0 + 3 1s, which is converted into hexadecimal: 143 Fs + 1 7 + 1 E + 22 Fs + 2 7s, specifically:

[0084] 77FFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the host computer parses and sends these data from right to left, and delivers them in binary format through the controller. After the delivery is completed, it is updated and the configuration is completed.

[0085] Since IO1 is set to 0, the output OUT1 of the comparator U1.2 will change from 1 to 0, that is, 1A is 0, and since 1B is 1, the output of the NAND gate 1Y will change from 0 to 1, and the S signal of K1.1 and K1.2 will change from 0 to 1. The switches K1.1 and K1.2 are both connected to A and B2, and then the TDO of the boundary scan chip U1.1 is turned on to the next level. At the same time, the return path of TDO is also turned on. The two DUMMY cards form a DUMMY chain connected to the boundary scan chain, so that the next level (DUMMY card 2) can be self-detected.

[0086] There are two ways to get power from DUMMY card 1. One is to get power from the outside through an external 5V power supply, and the other is to get power from the DUT connector through the gold finger of the DUMMY card. The power obtained is converted into 3.3V, 1.8V and the power required by the Bank of FPGA. The 5V power supply runs through J1.1 and J1.2 of DUMM card 1 and is connected to the next level to power all DUMMY cards in the boundary scan chain, ensuring the normal power supply of all DUMMY cards. Patent No. (CN2024101487668) provides two compatible methods of getting power, which are applicable to the present invention and will not be described repeatedly.

[0087] like Figure 3 As shown, a DUMMY chain consisting of three identical DUMMY cards is used. The overall self-detection steps are now further explained in detail through the DUMMY chain.

[0088] Step 1: Reset the boundary scan chain self-detection, set IO1 of DUMMY card 1 to 1, and IO2 to 0.

[0089] First, send the IR instruction of the Extest test of the DUMMY card 1 boundary scan chip through JTAG. The content of the instruction is: 11010101, and then send the DR data of the Extest test of the DUMMY card 1 boundary scan chip. The content of the DR data needs to pay close attention to the configuration of the INOUT register bits and Control cells of IO1 and IO2. According to the BSDL file analysis of the above boundary scan chip, to set IO1 to 1, it is necessary to configure the Control cell of 575 to 0 and the INOUT cell of 576 to 1, so that the chip pin W21 can output 1, corresponding to the IO1 described in the present invention; similarly, to set IO2 to 0, it is necessary to configure the Control cell of 671 to 0 and the INOUT cell of 672 to 1. cell is configured as 0, so that the chip pin F22 can output 0, corresponding to IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 1 0 + 95 1s + 2 0s + 2 1s, which is in hexadecimal: 143 Fs + 1 7 + 23 Fs + 1 7 + 1 6, specifically:

[0090] 67FFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the upper computer parses and sends these data from right to left, and sends them down in binary through the controller. After sending, they are updated and the configuration is completed. Since IO2 is set to 0, OUT2 of DUMMY card 1 is 0, which is connected to the reset paths RST1, RST2 and RST3, and their states are all 0. The single-pole double-throw switches K1.1, K2.1, K3.1 of DUMMY cards 1, 2, 3 and the single-pole ends A of K1.2, K2.2, K3.2 of the boundary scan chain are all connected to the enable end B1, and A is disconnected from the enable end B2. At this time, TDI and TDO of DUMMY cards 1, 2, 3 are completely disconnected, and only the TDO output and return path of DUMMY card 1 are complete;

[0091] Step 2, keep IO1 of DUMMY card 1 as 1 and set IO2 to 1, the purpose is to cancel the reset, so that the DUMMY card 1 can be correctly and stably self-detected with the IDcode. Similarly, first send the IR instruction of the Extest test of the boundary scan chip of DUMMY card 1 through JTAG, the content of the instruction is: 11010101, to set IO1 to 1, it is necessary to configure the cell of 575 to 0 and the cell of 576 to 1, so that the chip pin W21 can keep outputting 1, corresponding to the IO1 described in the present invention; similarly, to set IO2 to 1, it is necessary to configure the Contor cell of 671 to 0 and the INOUT cell of 672 to 1, so that the chip pin F22 can output 1, corresponding to the IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 1 0 + 95 1s + 1 0 + 3 1s, which is converted into hexadecimal: 143 Fs + 1 7 + 23 Fs + 2 7s, specifically:

[0092] 77FFFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the host computer parses and sends these data from right to left, and delivers them in binary format through the controller. After the delivery is completed, it is updated and the configuration is completed;

[0093] Step 3, perform self-test of DUMMY card 1. The content of the self-test is the IDcode self-test of the boundary scan chip of DUMMY card 1. Send the IR command of the IDcode test of DUMMY card 1. The command is: 00011001, which is sent from right to left in sequence, and then send 32-bit data. For example, 32 1s are sent to deduce the IDcode of DUMMY card 1. The data is: 00000001000000010010000001000011. If it is correctly deduced, it indicates that the self-test of DUMMY card 1 is normal. If it cannot be correctly deduced, it indicates that the self-test of DUMMY card 1 is abnormal. Analyze the cause of the abnormality. It may be the link failure of DUMMY card 1 itself or the wiring failure between DUMMY card 1 and the controller. Stop for inspection. After the inspection is completed, restart the self-test from step 1 until the self-test of DUMMY card 1 is correct.

[0094] Step 4, after the self-detection of DUMMY card 1 is normal, DUMMY card 2 is then turned on through DUMMY card 1, and the IR instruction and DR data of the Extest test of DUMMY card 1 are sent, and IO1 of DUMMY1 card is set to 0 (through DUMMY card 2 driven by DUMMY card 1), while IO2 is kept at 1, the purpose is to cut through the DUMMY card 2 of the next level, cascade DUMMY card 2 into the link, and DUMMY1 and DUMMY card 2 form a boundary scan chain. Similarly, first send the IR instruction of the Extest test of the boundary scan chip of DUMMY card 1 through JTAG, the content of the instruction is: 11010101, to set IO1 to 0, it is necessary to configure the Control cell of 575 to 0, and configure the INOUTcell of 576 to 0, so that the chip pin W21 can keep outputting 0, corresponding to the IO1 described in the present invention; similarly, to keep IO2 to 1, it is necessary to configure the Control cell of 671 ... cell is configured as 0, and INOUTcell of 672 is configured as 1, so that the chip pin F22 can output 1, corresponding to IO2 described in the present invention; specifically, the DR data sent from left to right is: 575 1s + 2 0s + 94 1s + 1 0 + 3 1s, which is converted into hexadecimal: 143 Fs + 1 7 + 1 E + 22 Fs + 2 7s, specifically:

[0095] 77FFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the host computer parses and sends these data from right to left, and delivers them in binary format through the controller. After the delivery is completed, it is updated and the configuration is completed;

[0096] Step 5. After DUMMY card 2 is connected, the Bypass instruction of DUMMY card 1 and the IDcode instruction of DUMMY card 2 are sent from right to left. The instruction combination is: 11111111 (Bypass instruction of DUMMY card 2) + 00011001 (IDcode instruction of DUMMY card 2). Then 32-bit data is sent to push out the 32-bit data of DUMMY card 2. The purpose is to push out the IDcode of DUMMY card 2. The data is: 00000001000000010010000001000011. If it is pushed out correctly, it means that the self-detection of DUMMY card 2 is normal. If it cannot be pushed out correctly, it means that the self-detection of DUMMY card 2 is abnormal. The reason for the abnormality may be the link failure of DUMMY card 2 itself or the wiring failure between DUMMY card 2 and DUMMY card 1. Stop for maintenance. After the maintenance is completed, start the self-test again from step 1 until the self-detection of DUMMY card 2 is correct.

[0097] Step 6, after the self-detection of DUMMY card 2 is normal, similarly, first send the Bypass instruction of DUMMY card 1 + the IR instruction of Extest test of DUMMY card 2 from right to left through JTAG, and the instruction combination is: 11111111 (Bypass instruction of DUMMY card 1) + 11010101 (IR instruction of Extest test of DUMMY card 2), and then send 1-bit data + Extest test data of DUMMY card 2 from right to left, set IO1 of DUMMY card 2 to 0, and keep IO2 to 1. To set IO1 of DUMMY card 2 to 0, it is necessary to configure the Control cell of 575 of DUMMY card 2 to 0, and configure the INOUTcell of 576 to 0, so that the chip pin W21 can keep outputting 0, corresponding to the IO1 of DUMMY card 2 described in the present invention; similarly, to keep IO2 to 1, it is necessary to configure the Control cell of 671 cell is configured as 0, and INOUTcell of 672 is configured as 1, so that the chip pin F22 can output 1, corresponding to IO2 of DUMMY card 2 described in the present invention; in addition, considering that after DUMMY card 1 sends the Bypass instruction, DUMMY card 1 occupies 1 data register bit, so it is necessary to send one more bit. Specifically, the DR data sent from left to right is: 575 1s + 2 0s + 94 1s + 1 0 + 4 1s, which is converted into hexadecimal: 143 Fs + 1 7 + 1 E + 22 Fs + 1 7 + 1 F, specifically:

[0098] F7FFFFFFFFFFFFFFFFFFFFFFE7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, the upper computer parses and sends these data from right to left, and sends them down through the controller in binary. After sending, it is updated to complete the configuration; the purpose is to cut through the next level DUMMY card 3, cascade DUMMY card 3 into the link, and DUMMY1, DUMMY card 2 and DUMMY card 3 form a boundary scan chain;

[0099] Step 7. Send 11111111 (Bypass instruction of DUMMY card 1) + 11111111 (Bypass instruction of DUMMY card 2) + 00011001 (IDcode instruction of DUMMY card 3) from right to left, and then send 32-bit data. The purpose is to derive the IDcode data of DUMMY card 3. The data is: 00000001000000010010000001000011. If the deduction is correct, it indicates that the self-detection of DUMMY card 3 is normal. If it cannot be correctly deduced, it indicates that the self-detection of DUMMY card 3 is abnormal. Analyze the cause of the abnormality, it may be a link failure of DUMMY card 3 itself or a wiring failure between DUMMY card 3 and DUMMY card 2. Stop for maintenance. After the maintenance is completed, start self-detection again from step 1 until DUMMY card 3 self-detects correctly.

[0100] Step 8: Send the Bypass command of DUMMY card 1 + the Bypass command of DUMMY card 2 + the Extest command of DUMMY card 3 from right to left, and then send 2-bit data + the Extest data of DUMMY card 3 from right to left, and switch to the next level DUMMY card 4, and so on, until the last DUMMY card is tested by self-test. Figure 3 Only the cascade of three DUMMY cards is shown. In practice, there may be more than a dozen DUMMY cards in the self-detection cascade, and all of them can be implemented according to the method of the embodiment, and the method is consistent.

[0101] IO2 of the boundary scan chip of DUMMY card 1 plays a decisive role in self-testing. The reset paths of RST1, RST2 and RST3 of DUMMY card are connected together. Reset is controlled by IO2 of DUMMY card 1. After reset, reset is canceled. At this time, self-testing starts from DUMMY card 1. IO1 is set to 0 once, and the link is switched to the next level. As long as IO2 remains 1, under the latching action of the NAND gate, no matter how the level of IO1 changes, the switched-on state will not be changed. When reset is completed again through IO2 of DUMMY card 1, self-testing can be started again from DUMMY card 1.

[0102] After the self-test is completed, all the links composed of DUMMY cards are connected and enter the normal boundary scan test state. In the normal boundary scan test state, there is still a problem to be overcome, that is, it is necessary to ensure that the cascade state of all DUMMY cards that have been connected remains stable. The IO2 state used for reset must always be maintained at 1 to ensure that the cascade state of multiple DUMMY cards that have been connected after the self-test is completed remains stable. At this time, the pull-up resistors R1.2, R2.2 and R3.2 play an essential role. As long as IO2 is not output as 0, the IO2 pin can be maintained at a low level state, thereby ensuring the stability of the normal test and preventing the link composed of the DUMMY cards from being abnormal due to the reset pin IO2. In normal boundary scan test, all pins with output capability may output 0, so IO2 needs special processing, the method is as follows: in normal boundary scan test state, change the INOUT boundary INOUTcell and Control cell corresponding to the IO2 pin of the BSDL of the boundary scan chip of each DUMMY card to Internalcell and assign a safety value. The safety value is 1 to ensure that IO2 does not output 0. In this way, during normal testing, the link cut-in state after the self-detection is completed will not be changed due to reset, and normal boundary scan test can be carried out stably. IO1 does not need special processing, because after the link is cut, the change of 0 or 1 of IO1 will not affect the link cut-in state due to the effect of the NAND gate latch.

[0103] Beneficial effects of resetting IO2: 1. Resetting before self-testing can adjust the links of multiple DUMMY cards to a certain state, ensuring the correctness of the initial state of self-testing, and being compatible with general boundary scan chips. Effect 2. It can ensure that after each self-testing is completed, the latched state of the cut-through can be released, and the link self-test can be repeatedly performed again from step 1. When powered on, the link can be repeatedly self-tested, which is helpful for debugging to confirm self-testing failures, and will not be unable to self-test a second time because of the first self-testing.

[0104] Beneficial effects of comparators U1.2, U2.2, and U3.2: The supply voltage of the IO group (Bank, (Bank supply voltage determines IO level)) of the boundary scan chip may be between 1.05V and 3.3V, so the IO output high level of the boundary scan chip may be between 1.05V and 3.3V. The comparator input obtains 0.6V as a reference through voltage division. When IO1 and IO2 outputs are 0, the comparator OUT1 and OUT2 outputs are both 0. When IO1 and IO2 outputs are 1 and the level is between 1.05V and 3.3V, they can output a stable 3.3V level, thereby ensuring the stability of the self-detection logic architecture, which is suitable for the level-conduction self-detection logic circuit of a general boundary scan chip.

[0105] Beneficial effect 1 of NAND gates U1.3, U2.3, and U3.3: providing latch after IO1 changes from 1 to 0, the state of output 1Y will not change, thereby ensuring that the state of the next level will not change, providing favorable conditions for self-detection before normal boundary scan testing, Beneficial effect 2: The low-level signal of IO2 can release the latch, thereby creating favorable conditions for secondary self-detection.

[0106] The beneficial effect of connecting RST1 to RST3 together is that all DUMMY cards can be controlled by DUMMY card 1 to complete self-detection reset. The present invention is not limited to 3 DUMMY cards. There may be 4, 5 and more DUMMY cards, accompanied by RST4, RST5 and more reset pins, and the methods are the same.

[0107] The function of the single-pole double-throw switches K1.1 to K3.1 and K1.2 to K3.2 is either to keep the TDO of the current stage connected to the return path when IO1 is at a high level, or to turn on the next stage when a low-level signal of IO1 comes, and connect the TDO of the next stage to the return path to form a cascade chain.

[0108] There are two ways to draw power for the DUMMY card. One is to draw power from the outside through an external 5V power supply, and the other is to draw power from the DUT connector through the gold finger of the DUMMY card. The obtained power is converted into 3.3V, 1.8V and the power required by the IO group (Bank) of the FPGA. The 5V power supply runs through J1.1 and J1.2 of DUMM card 1, J2.1 and J2.2 of DUMMY card 2, and J3.1 and J3.2 of DUMMY card 3 to ensure the normal power supply of all DUMMY cards. Patent No. (CN2024101487668) provides two compatible methods of drawing power, which are applicable to the present invention and will not be described repeatedly.

[0109] IO1 and IO2 pins are IO pins of any boundary scan chip. IO1 and IO2 of different boundary scan chips may be different. According to the IR command and DR data of Extest test, the data of INOUTcell and corresponding Control cell can be configured reasonably. In addition, the cascade self-detection of different boundary scan chips is nothing more than the Bypass command or IDcode command sent by different boundary scan chips and the different 32-bit data launched. The self-detection is completed in combination with the corresponding BSDL, and the final self-detection effect is the same.

[0110] The instructions and data sent are configured by the host computer, parsed into binary by the controller, and sent to the boundary scan chain. The controller's JTAG signal starts from controlling DUMMY card 1.

[0111] To achieve the above purpose, Figure 4 As shown, the present invention also provides a self-test method applicable to a boundary scan analog test card, the method is applied to the self-test framework applicable to the boundary scan analog test card; the method comprises the following steps:

[0112] S1, performing self-detection reset processing on the boundary scan chain, setting the first IO terminal of the first boundary scan simulation test card to 1, and the second IO terminal to 0; and keeping the first IO terminal of the first boundary scan simulation test card to 1, and setting the second IO terminal to 1;

[0113] S2. Perform self-test on the first boundary scan simulation test card. The content of the test is the IDcode self-test of the boundary scan chip of the first boundary scan simulation test card. In the BSDL file of the boundary scan chip standard, the IDcode instruction and data are defined. The IDcode data is the inherent identification code of the boundary scan chip (device). Before doing the Extest test, the IDcode instruction will be sent from the TDI of the boundary scan chip, and then 32-bit data will be sent. The identification code of the boundary scan chip can be moved out from the TDO of the boundary scan chip. After being moved out, it is received by the controller and compared with the BSDL data defined in the BSDL file to determine whether the test is PASS. Different models of boundary scan chips have different IDcodes, but they are all 32 bits. It complies with the JTAG standard and follows the IEEE 1149 protocol.

[0114] S3. After the first boundary scan simulation test card self-detects normally, the second boundary scan simulation test card is turned on through the first boundary scan simulation test card, and the IR instruction and DR data of the external test of the first boundary scan simulation test card are sent, and the first IO terminal of the boundary scan simulation test card (DUMMY card) is set to 0, while the second IO terminal is kept at 1; wherein, the simulation test cards all refer to DUMMY cards.

[0115] S4. After the second boundary scan simulation test card is switched on, the Bypass instruction of the first boundary scan simulation test card + the IDcode instruction of the second boundary scan simulation test card are sent from right to left in sequence; the Bypass instruction is an instruction to bypass the boundary scan chip, which is also defined in the standard BSDL file. The Bypass instruction is sent from the TDI of the boundary scan chip. If the Bypass instruction is correctly moved into the Bypass register of the corresponding chip, the boundary scan chip of the DUMMY card where it is located will be bypassed, and the Extest test of the DUMMY card will be skipped. The bypassed boundary scan chip register only occupies 1 bit. It complies with the JTAG standard and follows the IEEE 1149 protocol.

[0116] S5, after the second boundary scan simulation test card self-detects normally, the Bypass instruction of the first boundary scan simulation test card + the IR instruction of the external test of the second boundary scan simulation test card are sent from right to left through JTAG, and then 1-bit data + Extest test data of the second boundary scan simulation test card are sent from right to left, and the first IO terminal of the second boundary scan simulation test card is set to 0, while keeping the second IO terminal at 1;

[0117] S6, sending the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the IDcode instruction of the third boundary scan simulation test card in sequence from right to left; and then sending 32-bit data;

[0118] S7. Send the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the Extest instruction of the third boundary scan simulation test card from right to left, and then send two bits of data + the Extest data of the third boundary scan simulation test card from right to left, and cut through the fourth boundary scan simulation test card of the next level, and so on, until the self-test is completed on the last boundary scan simulation test card.

[0119] The self-detection reset process is performed on the boundary scan chain, the first IO terminal of the first boundary scan simulation test card is set to 1, and the second IO terminal is set to 0; and the first IO terminal of the first boundary scan simulation test card is kept at 1, and the second IO terminal is set to 1, and the self-detection reset process is performed on the boundary scan chain, and the first IO terminal of the first boundary scan simulation test card is set to 1, and the second IO terminal is set to 1, and the self-detection reset process is performed on the boundary scan chain ...

[0120] S11, first send an IR instruction of the Extest test of the boundary scan chip of the first boundary scan simulation test card through JTAG; wherein the content of the IR instruction is 11010101;

[0121] S12, sending DR data of the Extest test of the boundary scan chip of the first boundary scan simulation test card;

[0122] S13, the DR data is parsed and sent from right to left by the host computer, and sent down in binary format through the controller. After the sending is completed, it is updated and the configuration is completed.

[0123] The self-detection of the first boundary scan simulation test card includes self-detection of the IDcode of the boundary scan chip of the first boundary scan simulation test card. The self-detection also includes:

[0124] S21, sending the IR instruction of the IDcode test of the first boundary scan simulation test card, sending it from right to left in sequence, and then sending 32-bit data; wherein the content of the IR instruction is 00011001;

[0125] S22, determining whether the IDcode data pushed out by the first boundary scan simulation test card is abnormal, if yes, re-self-checking, otherwise, executing the next step.

[0126] After the second boundary scan simulation test card is switched on, the Bypass instruction of the first boundary scan simulation test card and the IDcode instruction of the second boundary scan simulation test card are sent sequentially from right to left, and further comprising:

[0127] S41, determining whether the IDcode data pushed out by the second boundary scan simulation test card is abnormal, if yes, re-self-checking, otherwise, executing the next step.

[0128] The method includes sending the Bypass instruction of the first boundary scan simulation test card, the Bypass instruction of the second boundary scan simulation test card, and the IDcode instruction of the third boundary scan simulation test card in sequence from right to left; and then sending 32-bit data, further comprising:

[0129] S61, determining whether the IDcode data pushed out by the third boundary scan simulation test card is abnormal, if yes, re-self-checking, otherwise, executing the next step.

[0130] The present invention provides a self-detection framework suitable for a boundary scan simulation test card, wherein the framework comprises at least one boundary scan controller and at least one boundary scan simulation test card electrically connected to the boundary scan controller; a clock signal end and a state signal end of the boundary scan controller are electrically connected to connectors respectively arranged at two ends of the boundary scan simulation test card in sequence; a level control unit for realizing self-detection of the boundary scan simulation test card is also electrically connected between the connectors; and a method corresponding to the self-detection framework can solve the problem that the IO of a boundary scan chip of a DUMMY card with different level standards can stably drive a DUMMY card self-detection logic circuit, thereby realizing self-detection of the boundary scan simulation test card.

[0131] That is to say, the scheme of the present invention can realize the close integration of the self-test and normal boundary scan test of the DUMMY card, and it only needs to control JTAG. The instructions and data can be flexibly adjusted by the host computer and no additional wiring is required on the outside of the DUMMY card, which has better compatibility and versatility; moreover, it can ensure the correctness and stability of the self-test logic architecture and method.

[0132] In addition, the self-test of this solution adds a reset function, that is, the self-test logic of the reset is realized by controlling the IO of the boundary scan chip through JTAG; without power failure, after the problem is found and solved, the self-test can be re-performed to ensure that after the first test, the second and subsequent self-tests can be performed to facilitate repeated self-testing and confirmation of boundary scan chain faults. After the boundary scan chip is powered on, the influence of the default level of the boundary scan chip after power-on on the self-test logic architecture is overcome, ensuring that the boundary scan chip IO can perform self-testing in the three default states, and the self-test logic and method are applicable to general boundary scan chips.

[0133] The self-detection scheme supports the self-detection of the cascade chain composed of the same DUMMY card or different DUMMY cards. The self-detection method is applicable to the cascade of DUMMY cards with different boundary scan chips and is general. It can also meet the compatibility of the IO level self-detection of different DUMMY card boundary scan chips, and solve the problem that the IO of the DUMMY card boundary scan chip with different level standards can stably drive the DUMMY card self-detection logic circuit to achieve self-detection.

[0134] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A self-test architecture suitable for a boundary scan analog test card, characterized in that: The framework includes at least one boundary scan controller, and at least one boundary scan simulation test card electrically connected to the boundary scan controller; The clock signal terminal and the state signal terminal of the boundary scan controller are respectively and electrically connected to the connectors respectively arranged at the two ends of the boundary scan simulation test card; the connectors are also electrically connected to a level control unit for realizing self-detection of the boundary scan simulation test card; The connector comprises a first point one connector and a first point two connector; The clock signal of the first point one connector is electrically connected to the level control unit and the first point two connector respectively; the state signal end of the first point one connector is electrically connected to the level control unit and the first point two connector respectively; the data input end of the first point one connector is electrically connected to the level control unit and the first point two connector in sequence; The data output end of the first point two connector is electrically connected to the level control unit and the first point one connector in sequence; At least one boundary scan chip is arranged in the level control unit; The boundary scan chip is electrically connected to a NAND gate and at least two single-pole double-throw switches in sequence through a provided comparator; The single-pole double-throw switch comprises a first point-one single-pole double-throw switch and a first point-two single-pole double-throw switch; the output signal end of the boundary scan chip is connected to the single-pole end A of the first point-one single-pole double-throw switch; the first IO end of the boundary scan chip is respectively connected to one end of the first point-one resistor and the first positive input end of the first point-two comparator; the other end of the first point-one resistor is respectively connected to the reserve power supply end and one end of the first point-two resistor; the other end of the first point-two resistor is respectively connected to the second IO end of the boundary scan chip and the second positive input end of the first point-two comparator; The first negative input terminal of the first point two comparator is respectively connected to one end of the first point three resistor and one end of the first point five resistor; the other end of the first point three resistor is respectively connected to the power supply terminal and one end of the first point four resistor; the other end of the first point four resistor is respectively connected to the second negative input terminal of the first point two comparator and one end of the first point six resistor; the other end of the first point five resistor and the other end of the first point six resistor are commonly grounded; The first output terminal of the first point two comparator is connected to the first A terminal of the NAND gate; the second output terminal of the first point two comparator is connected to the second A terminal of the NAND gate; The second B end of the NAND gate is respectively connected to the first Y end of the NAND gate, the S end of the single pole of the first point one single-pole double-throw switch, and the S end of the single pole of the first point two single-pole double-throw switch; the first B end of the NAND gate is connected to the second Y end of the NAND gate; The first B end of the single pole of the single-pole double-throw switch at the first point 1 is connected to the A end of the single pole of the single-pole double-throw switch at the first point 2; the second B end of the single pole of the single-pole double-throw switch at the first point 1 is connected to the data input end of the first point 2 connector; the second B end of the single pole of the single-pole double-throw switch at the first point 2 is connected to the data output end of the first point 2 connector; The NAND gate, the first point one single-pole double-throw switch single-pole and the first point two single-pole double-throw switch single-pole share a power supply terminal; The model of the boundary scan chip is LFE3-35EA-8FN484C; The model of the comparator is LM393DR; the model of the NAND gate is SN74LVC2G132DCUR; and the model of the single-pole double-throw switch is 74CBTLV3257PW,118.

2. A self-test method suitable for a boundary scan analog test card, characterized in that: The method is applied to a self-test framework suitable for a boundary scan simulation test card as claimed in claim 1; the method comprises the following steps: Performing self-detection reset processing on the boundary scan chain, setting the first IO terminal of the first boundary scan simulation test card to 1 and the second IO terminal to 0; and maintaining the first IO terminal of the first boundary scan simulation test card to 1 and setting the second IO terminal to 1; Performing a self-test on the first boundary scan simulation test card, wherein the content of the test is an IDcode self-test of the boundary scan chip of the first boundary scan simulation test card; After the first boundary scan simulation test card self-detects normally, the second boundary scan simulation test card is turned on through the first boundary scan simulation test card, and the IR instruction and DR data of the external test of the first boundary scan simulation test card are sent, and the first IO terminal of the boundary scan simulation test card is set to 0, while the second IO terminal is kept at 1; After the second boundary scan simulation test card is switched on, the Bypass instruction of the first boundary scan simulation test card and the IDcode instruction of the second boundary scan simulation test card are sent from right to left in sequence; After the second boundary scan simulation test card self-detects normally, the Bypass instruction of the first boundary scan simulation test card + the IR instruction of the external test of the second boundary scan simulation test card are sent from right to left through JTAG, and then 1-bit data + the Extest test data of the second boundary scan simulation test card are sent from right to left, and the first IO terminal of the second boundary scan simulation test card is set to 0, while keeping the second IO terminal at 1; Send the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the IDcode instruction of the third boundary scan simulation test card from right to left; then send 32-bit data; From right to left, send the Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the Extest instruction of the third boundary scan simulation test card, and then send two bits of data + the Extest data of the third boundary scan simulation test card from right to left, cut through the next level fourth boundary scan simulation test card, and so on, until the self-test completes the last boundary scan simulation test card.

3. A self-test method suitable for a boundary scan simulation test card according to claim 2, characterized in that: The self-detection reset process is performed on the boundary scan chain, and the first IO terminal of the first boundary scan simulation test card is set to 1 and the second IO terminal is set to 0; and maintaining the first IO terminal of the first boundary scan simulation test card at 1 and setting the second IO terminal to 1, further comprising: First, an IR instruction of an Extest test of a boundary scan chip of a first boundary scan simulation test card is sent through JTAG; wherein the content of the IR instruction is 11010101; Sending DR data of the Extest test of the boundary scan chip of the first boundary scan simulation test card; The DR data is parsed and sent from right to left by the host computer, sent down in binary format by the controller, and updated after the sending is completed, thus completing the configuration.

4. A self-test method suitable for a boundary scan simulation test card according to claim 2, characterized in that: The self-detection of the first boundary scan simulation test card includes self-detection of the IDcode of the boundary scan chip of the first boundary scan simulation test card. The self-detection also includes: Send the IR instruction of the IDcode test of the first boundary scan simulation test card, send it from right to left, and then send 32 bits of data; wherein the content of the IR instruction is 00011001; Determine whether the IDcode data pushed out by the first boundary scan simulation test card is abnormal, if yes, re-self-check, otherwise execute the next step.

5. The self-detection method for a boundary scan simulation test card according to claim 2, characterized in that: After the second boundary scan simulation test card is turned on, the Bypass instruction of the first boundary scan simulation test card + the IDcode instruction of the second boundary scan simulation test card are sent from right to left in sequence, and it also includes: determining whether there is an abnormality in the IDcode data pushed out by the second boundary scan simulation test card, if so, re-self-checking, otherwise executing the next step.

6. A self-test method suitable for a boundary scan simulation test card according to claim 2, characterized in that: The Bypass instruction of the first boundary scan simulation test card + the Bypass instruction of the second boundary scan simulation test card + the IDcode instruction of the third boundary scan simulation test card are sent in sequence from right to left; Then send 32 bits of data, also including: Determine whether the IDcode data pushed out by the third boundary scan simulation test card is abnormal, if yes, re-self-check, otherwise execute the next step.

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