Integrated transceiver circuits

Abstract

The present application provides an integrated transceiver circuit, which can be used for signal transmission and reception between an external control device and an external diagnostic device. A transmission matrix and a receiving matrix are used to construct communication channels between each GPIO port of the external control device and any OBD end, and a driving circuit is set at the same time. On the one hand, the signal from the external control device is converted into an output driving signal with voltage, current and load that can be matched through the driving circuit and the differential impedance control unit, so as to achieve the transmission of the signal from the GPIO port in accordance with the voltage, current and load requirements of various communication protocols; on the other hand, the hysteresis comparator in the driving circuit is used to achieve the reception of the signal from the OBD end in accordance with the voltage requirements of the communication protocol. Since the transmitting matrix and the receiving matrix are located between the GPIO port and the driving circuit, there is no need to carry excessive current. Therefore, the size requirements for the components in the transmitting matrix are not high, and there is no need to set too many parasitic components. The final integrated transceiver has a small area and can be widely used in various scenarios.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and in particular to an integrated transceiver circuit. Background Art

[0002] Bus transceivers enable data exchange between interfaces of different types of devices. Traditional bus transceivers are built by integrating transceivers supporting different protocols and using relay switches to control the selection of the transceiver and the external OBD interface. However, this method requires relay switching and cannot be integrated on-chip, resulting in large circuit size and high cost. Even though some integrated circuits can achieve partial OBD pin switching through a combination of transceivers and matrix switches, the switching method is fixed and some pins are shared by multiple transceivers, resulting in excessive pin parasitic capacitance and making it impossible to implement high-speed bus protocols such as CAN FD. This results in a large chip area and limited application scenarios. Summary of the Invention

[0003] The present application provides an integrated transceiver circuit that occupies a small area and is applicable to a wide range of scenarios.

[0004] An integrated transceiver circuit, comprising:

[0005] Send Matrix;

[0006] Receive matrix;

[0007] a buffer for providing a reference voltage;

[0008] A plurality of driving circuits, each of the driving circuits comprising:

[0009] A voltage stabilizing circuit, used for providing a power supply voltage with an adjustable voltage value;

[0010] A driver, comprising a transistor NH and an upper tube load adjustment unit connected between the source and drain of the transistor NH, and a transistor PL and a lower tube load adjustment unit connected between the source and drain of the transistor PL, wherein the gates of the transistor NH and the transistor PL are respectively connected to the transmitting matrix, the source of the transistor NH is connected to the voltage stabilizing circuit, and the source of the transistor PL is connected to the ground terminal. The driver is configured to output an output drive signal with voltage, current, and load controllable when selected by the transmitting matrix;

[0011] a differential impedance control unit, comprising a control switch and a load element connected in series with the control switch, wherein the control switch is configured to selectively conduct a conductive path in which the driver, the load element, and the buffer are located, so as to maintain a reference voltage of the output drive signal at the reference voltage;

[0012] Hysteresis comparator, including:

[0013] a first threshold comparator, configured to receive an input drive signal from an external device and compare a voltage of the input drive signal with a first hysteresis voltage;

[0014] a second threshold comparator, configured to receive the input drive signal and compare a voltage of the input drive signal with a second hysteresis voltage; wherein the first hysteresis voltage is smaller than the second hysteresis voltage;

[0015] an RS trigger, wherein a reset terminal of the RS trigger is connected to the output terminal of the first threshold comparator, and a set terminal of the RS trigger is connected to the output terminal of the second threshold comparator;

[0016] The receiving matrix is ​​selectively connected to the output end of each of the RS triggers.

[0017] In one embodiment, the driving circuit further includes:

[0018] a first DAC circuit, connected to the first threshold comparator, for providing the first hysteresis voltage;

[0019] The second DAC circuit is connected to the second threshold comparator and is used to provide the second hysteresis voltage.

[0020] In one embodiment, the driving circuit further includes:

[0021] The first voltage divider circuit is respectively connected to the bus power supply, the first DAC circuit and the second DAC circuit, and can be configured to divide the power supply voltage of the bus power supply to obtain a first voltage, and use the first voltage as a reference voltage for the first DAC circuit, and to obtain a second voltage, and use the second voltage as a reference voltage for the second DAC circuit.

[0022] In one embodiment, the integrated transceiver circuit further includes:

[0023] A plurality of first differential comparators are provided, each of the first differential comparators corresponding one-to-one to each differential terminal pair of the external device, and two input terminals of the first differential comparator are connected one-to-one to two terminals of the corresponding differential terminal pair; and an output terminal of each first differential comparator is connected to the receiving matrix.

[0024] In one embodiment, the integrated transceiver circuit further includes:

[0025] two first gates;

[0026] a second differential comparator, wherein two input terminals of the second differential comparator are respectively connected to the output terminals of the two first gates in a one-to-one correspondence, and an output terminal of the second differential comparator is connected to the receiving matrix;

[0027] The first selector is used to connect to each communication terminal of the external device and to select one of the communication terminals to be connected to the differential comparator.

[0028] In one embodiment, comparison thresholds and output polarities of the first differential comparator and the second differential comparator are adjustable.

[0029] In one embodiment, the number of the first differential comparators is at least 4; the external device includes but is not limited to 4 groups of differential terminal pairs, wherein the first differential terminal pair includes terminal OBD6 and terminal OBD14; the second differential terminal pair includes terminal OBD3 and terminal OBD11; the third differential terminal pair includes terminal OBD3 and terminal OBD8; and the fourth differential terminal pair includes terminal OBD12 and terminal OBD1.

[0030] In one embodiment, the integrated transceiver circuit further includes:

[0031] a plurality of second voltage divider circuits, each of the second voltage divider circuits corresponding one-to-one to each monitoring terminal group of the external device, and the second voltage divider circuit is connected to each communication terminal in the corresponding monitoring terminal group, for dividing the communication signal from each communication terminal;

[0032] a plurality of second selectors, connected one-to-one with each of the second voltage divider circuits, for selecting at most one of the divided communication signals for output;

[0033] A plurality of buffer amplifiers are connected to the second gates in a one-to-one correspondence, and are used to output the communication signal output by the second gate.

[0034] In one embodiment, the number of the second voltage divider circuits, the number of the second selectors and the number of the buffer amplifiers are at least 4, and the external devices include but are not limited to 4 groups of terminal groups to be monitored, wherein the first terminal group to be monitored includes terminal OBD1, terminal OBD3, terminal OBD7 and terminal OBD9; the second terminal group to be monitored includes terminal OBD2, terminal OBD6, terminal OBD8 and terminal OBD10; the third terminal group to be monitored includes terminal OBD11, terminal OBD13, terminal OBD15 and terminal OBD16; and the fourth terminal group to be monitored includes terminal OBD14.

[0035] In one embodiment, the upper tube load adjustment unit and the lower tube load adjustment unit respectively include a plurality of parallel branches, wherein each branch includes a switch element and a resistance element or a current mirror unit connected in series with the switch element.

[0036] In one embodiment, the driving circuit further includes:

[0037] Two output configuration circuits, each of which includes an inverter and a switching element connected in parallel between the input and output of the inverter; wherein the input of the inverter is connected to the target transistor, and the output of the inverter is connected to the gate of the target transistor; the target transistor is the transistor NH or the transistor PL.

[0038] The aforementioned transmission matrix and receiving matrix are used to establish communication channels between each GPIO port of an external control device and any OBD terminal. Driver circuits are also provided at the output of the transmission matrix and the input of the receiving matrix. The upper and lower tube driver sections of the driver circuits convert signals from the external control device into output drive signals with voltage, current, and load compatibility. A differential impedance control unit controls the buffer access to the driver to maintain a reference voltage for the output drive signal when in differential input, thereby enabling transmission of signals from the GPIO port in accordance with the voltage, current, and load requirements of various communication protocols. Furthermore, a hysteresis comparator in the driver circuit enables reception of signals from the OBD terminal in accordance with the voltage requirements of the protocol. Thus, by gating the transmission matrix and receiving matrix and using the driver circuit for voltage regulation, signal transmission and reception under various protocols are ultimately achieved. Because the transmission matrix and receiving matrix are located between the GPIO port and the driver circuit and operate in a low-voltage domain, they do not need to carry excessive current. Therefore, the component size requirements of the transmission matrix are not high, and there is no need to provide too many parasitic elements. The resulting integrated transceiver is compact and can be widely used in various scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A circuit structure diagram of an integrated transceiver circuit according to an embodiment of the present application;

[0040] Figure 2 A circuit structure diagram of an integrated transceiver circuit according to another embodiment of the present application;

[0041] Figure 3 A circuit structure diagram of an integrated transceiver circuit according to another embodiment of the present application;

[0042] Figure 4 A circuit structure diagram of an integrated transceiver circuit according to another embodiment of the present application;

[0043] Figure 5This is a circuit structure diagram of an integrated transceiver circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0045] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0047] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0048] Figure 1 An integrated transceiver circuit provided by an embodiment of the present invention is as follows: Figure 1As shown, the integrated transceiver circuit includes a transmitting matrix 110, a buffer 120, a receiving matrix 140 and a plurality of driving circuits 130, wherein each driving circuit includes a voltage stabilizing circuit 131, a driver, a differential impedance control unit and a hysteresis comparator; the voltage stabilizing circuit is used to provide a supply voltage with an adjustable voltage value; the driver includes a transistor NH and an upper tube load regulating unit 1321 connected between the source and drain of the transistor NH, and a transistor PL and a lower tube load regulating unit 1322 connected between the source and drain of the transistor PL, the gates of the transistor NH and the transistor PL are respectively connected to the transmitting matrix 110, the source of the transistor NH is connected to the voltage stabilizing circuit 131, and the source of the transistor PL is connected to the ground terminal, and the driver is configured to output an output driving signal with adjustable voltage, current and load when it is selected by the transmitting matrix 110; the differential impedance control unit includes a control switch K1 and a control switch K2 connected to the control switch K3. The control switch K1 is connected in series with a load element 1331, and the control switch is used to selectively turn on the conductive path where the driver, the load element 1331 and the buffer 120 are located, so as to maintain the reference voltage of the output drive signal at the reference voltage; the hysteresis comparator includes a first threshold comparator 1341, a second threshold comparator 1342 and an RS trigger; the first threshold comparator 1341 is used to receive an input drive signal from an external device and compare the voltage of the input drive signal with the first hysteresis voltage; the second threshold comparator 1342 is used to receive an input drive signal and compare the voltage of the input drive signal with the second hysteresis voltage; the first hysteresis voltage is less than the second hysteresis voltage; the reset terminal of the RS trigger is connected to the output terminal of the first threshold comparator 1341, the set terminal of the RS trigger is connected to the output terminal of the second threshold comparator 1342, and the output terminal of the RS trigger is connected to the receiving matrix 140.

[0049] The integrated transceiver circuit of this embodiment can be used for signal transmission and reception between an external control device and an external diagnostic device. Specifically, the transmission matrix 110 can construct multiple signal transmission channels by matching input and output terminals. Each input terminal of the transmission matrix 110 can be used to connect to each GPIO port of the external control circuit in a one-to-one correspondence. The output terminal of the transmission matrix 110 is connected to each transistor in a one-to-one correspondence. Each input terminal of the transmission matrix 110 can be connected to each of its output terminals via a switch. By opening and closing the switch, any input and output terminal in the transmission matrix 110 can be matched, and a connection can be formed between each GPIO port and any transistor. Since the output of each transistor can be connected to each communication terminal of the external device (for example, each OBD terminal of the diagnostic device) in a one-to-one correspondence, any connection can be formed between each GPIO port of the external control circuit and each communication terminal of the external device.

[0050] When the external control circuit is connected to each communication terminal of the external device, in order to satisfy the external control circuit to transmit signals to the external device according to the desired communication protocol, the driver circuit 130 can obtain the desired voltage and current under the communication protocol based on the signal of the external control circuit, and at the same time provide a load that matches the external device, thereby achieving signal transmission to the external device. Specifically, the voltage regulator circuit 131, transistor NH, and upper tube load adjustment unit 1321 in the driver circuit 130 constitute the upper tube driver portion, which can be used to obtain an output drive signal with a high voltage and current value. Since the supply voltage of the voltage regulator circuit 131 and the resistance of the upper tube load adjustment unit 1321 are adjustable, the voltage, current, and load of the output drive signal are configurable. The transistor PL and the lower tube load adjustment unit 1322 constitute the lower tube driver portion, which is used to obtain a 0V output drive signal. The transistors NH and PL adopt a push-pull output mode. Based on the upper tube driver portion and the lower tube driver portion, the driver can achieve configurable voltage, current, and load of the output drive signal, thereby meeting the voltage, current, and load requirements under various communication protocols. In one embodiment, the voltage of the output driving signal can be configured to be 5V, 8V, 12V, or 24V.

[0051] For single-line communication protocols, such as the single-line CAN protocol, K-LINE protocol, and VPW protocol, an output drive signal with a specific voltage, current, and load is obtained through an upper tube drive part or a lower tube drive part in a drive circuit 130 to meet the voltage and current requirements under the protocol.

[0052] To solve the signal transmission problem under differential communication protocols such as two-wire CAN and RS485, each driving circuit 130 may also be provided with a differential impedance control unit, which is connected between the buffer 120 and the driver. When differential signal transmission is performed, the two driving circuits 130 can be used to respectively receive two differential signals that are differential with each other, and the load of the load adjustment unit at both ends of the transistor in the corresponding working state is adjusted to 0, so that two output driving signals are obtained through the driving of the driver. At the same time, the control switch K1 in the differential impedance control unit is used to turn on the conductive path where the driver, load element 1331 and buffer 120 are located, so that both output driving signals are terminated to the buffer 120, so as to maintain the reference voltage of the two output driving signals at the reference voltage provided by the buffer 120, reduce signal interference, and improve the stability and reliability of the two output driving signals. The connection relationship between the driver, control switch K1, load element 1331, and buffer 120 is that one end of the control switch K1 is connected to one end of the load element 1331, and the other end of the control switch K1 and the other end of the load element 1331 are connected to the driver and buffer 120. The connection relationship can be arbitrary. For example, the other end of the control switch K1 can be connected to the output end of the driver, and the load element 1331 is connected to the buffer 120; or the control switch K1 can be connected to the buffer 120, and the load element 1331 is connected to the output end of the driver. In one embodiment, to achieve the output of a 5V differential signal, the reference voltage provided by the buffer 120 can be 2.5V, and the load element 1331 can be a resistor element R1 with a resistance of 60Ω (refer to Figure 5 shown).

[0053] Similar to the structure of the transmitting matrix 110, the receiving matrix 140 can also construct multiple receiving channels by matching the input and output ends, thereby realizing the connection between each hysteresis comparator and any external GPIO port. Each hysteresis comparator is correspondingly connected to the OBD end of the external device. Therefore, by selecting one of the communication channels, a connection between any GPIO port and the OBD end can be established.

[0054] A hysteresis comparator compares the input drive signal with a first hysteresis voltage and a second hysteresis voltage, respectively. An RS flip-flop then outputs a signal with a corresponding voltage based on the comparison result. By appropriately setting the first and second hysteresis voltages, the input drive signal can be transmitted under the corresponding communication protocol. Furthermore, because the input drive signal is compared with the two hysteresis voltages and then the RS flip-flop performs a logical operation on the two comparison results, the output of the RS flip-flop remains unchanged when the voltage of the input drive signal is between the first and second hysteresis voltages, thereby improving the accuracy and reliability of the output signal.

[0055] According to the requirements of the communication protocol, the first hysteresis voltage and the second hysteresis voltage can be configured as desired values; in one embodiment, the first hysteresis voltage and the second hysteresis voltage can be directly provided by an external power supply or generated by an internal circuit.

[0056] The above-mentioned integrated transceiver circuit uses the transmission matrix 110 and the receiving matrix 140 to build a communication channel between each GPIO port of the external control device and any OBD terminal. At the same time, a driving circuit 130 is set at the output end of the transmission matrix 110 and the input end of the receiving matrix. On the one hand, the upper tube driving part and the lower tube driving part in the driving circuit 130 can convert the signal from the external control device into an output driving signal that can be matched with voltage, current and load. In combination with the differential impedance control unit, the buffer 120 is controlled to access the driver to meet the requirement of being able to maintain the reference voltage of the output driving signal when in differential input, thereby achieving electrical matching under various communication protocols. On the other hand, the hysteresis comparator in the driving circuit is used to receive the signal from the OBD end according to the voltage requirement of the protocol. In this way, the transmitting matrix 110 and the receiving matrix are selected, and the driving circuit 130 is used to adjust the voltage, and finally the signal transmission under various protocols is realized. Since the transmitting matrix 110 and the receiving matrix are located between the GPIO port and the driving circuit 130, they work in the low-voltage domain and do not need to carry excessive current. Therefore, the size requirements of the components in the transmitting matrix 110 are not high, and there is no need to set too many parasitic components. The final integrated transceiver circuit has a small area and can be widely used in various scenarios.

[0057] In one embodiment, the number of the driving circuits 130 may be 13, corresponding to the 13 OBD terminals of the diagnostic device.

[0058] In one embodiment, the driving circuit 130 further includes a first DAC circuit and a second DAC circuit (not shown), wherein the first DAC circuit is connected to the first threshold comparator 1341 for providing a first hysteresis voltage; and the second DAC circuit is connected to the second threshold comparator 1342 for providing a second hysteresis voltage.

[0059] The DAC circuit can be a digital-to-analog converter; it can be understood that the first hysteresis voltage and the second hysteresis voltage can be generated by two DAC circuits respectively. Since the voltage output by the DAC circuit has a specific proportional relationship with its reference voltage, the desired hysteresis voltage can be obtained by adjusting the size of the reference voltage provided to the DAC circuit.

[0060] Therefore, the hysteresis voltage is generated by using a DAC circuit, the circuit is simple, and based on the relationship between the output voltage of the DAC circuit and the reference voltage, the size of the hysteresis voltage can be easily adjusted.

[0061] In one embodiment, the driving circuit 130 further includes a first voltage divider circuit (not shown), which is respectively connected to the bus power supply, the first DAC circuit, and the second DAC circuit, and can be configured to divide the power supply voltage of the bus power supply to obtain a first voltage, and use the first voltage as a reference voltage for the first DAC circuit, and to obtain a second voltage, and use the second voltage as a reference voltage for the second DAC circuit.

[0062] It will be appreciated that the reference voltage of the DAC circuit can be obtained by dividing the external bus power supply by a first voltage divider circuit; the voltage division ratio of the first voltage divider circuit is configurable, thereby enabling configurable reference voltage for the DAC circuit. In one embodiment, the first voltage divider circuit can include an adjustable load, and a specific voltage value can be obtained by adjusting the resistance of the load connected to the conductive path. In one embodiment, the first voltage and the second voltage are equal to 0.2 times the power supply voltage. In this way, using the first voltage divider circuit to divide the external bus power supply eliminates the need for a separate internal power supply, saving space and cost.

[0063] In one embodiment, Figure 2 As shown, the integrated transceiver circuit further includes a plurality of first differential comparators 150, each of which corresponds one-to-one to each differential terminal pair of the external device, and the two input ends of the first differential comparator 150 are respectively connected one-to-one to the two terminals of the corresponding differential terminal pair; the output end of each first differential comparator 150 is connected to the receiving matrix 140.

[0064] It can be understood that the above-mentioned hysteresis comparator can be used to implement reception under a single-wire communication protocol, while for reception of differential signals under a two-wire communication protocol, a differential comparator can be used. Specifically, the differential terminal pair of the external device can be two terminals among the terminals of the external device, which are used to output two differential signals that are differential to each other. For multiple groups of differential terminal pairs of the external device, the same number of first differential comparators 150 can be provided and connected to each differential terminal pair in a one-to-one correspondence, wherein the two input terminals of the first differential comparator 150 are respectively connected to the two differential terminals of the corresponding differential terminal pair. By comparing the voltage difference between the two differential signals with the comparison threshold, a comparison result of the corresponding voltage value can be output.

[0065] In one embodiment, Figure 3As shown, the integrated transceiver circuit also includes: two first selectors 170 and a second differential comparator 160, the two input ends of the second differential comparator 160 are respectively connected to the output ends of the two first selectors 170 in a one-to-one correspondence, and the output end of the second differential comparator 160 is connected to the receiving matrix 140; the first selector 170 is used to connect to each communication terminal of the external device, and to select one of the communication terminals to be connected to the differential comparator.

[0066] It is understood that the first differential comparator 150 is connected to the differential terminal pair defined at the factory for the external device. Considering that the external device may use other terminals to output differential signals, this can be achieved by providing two first selectors 170 and a second differential comparator 160. Specifically, the two first selectors 170 can each have multiple connection terminals to connect to the respective communication terminals of the external device. During signal transmission, the first selector 170 can select one of the communication terminals to connect to the second differential comparator 160. In this way, the two first selectors 170 can select two ports to output differential signals and connect them to the second differential comparator 160, thereby achieving reception of differential signals output by any communication terminal.

[0067] In one embodiment, the comparison threshold and output polarity of the first differential comparator 150 are adjustable.

[0068] It can be understood that the comparison threshold of the first differential comparator 150 is adjustable, so that the comparison result output by the first differential comparator 150 can be configured.

[0069] The output end of the first differential comparator 150 may be provided with an inverter and a switch, and the switch is connected in parallel to the input and output ends of the inverter to selectively connect the inverter to the output end of the first differential comparator 150, thereby adjusting the polarity of the output signal.

[0070] In one embodiment, the comparison threshold and output polarity of the second differential comparator 160 are adjustable.

[0071] Similarly, similar to the first differential comparator 150 , by adjusting the comparison threshold, the comparison result output by the second differential comparator 160 can be made adjustable.

[0072] The output end of the second differential comparator 160 may be provided with an inverter and a switch, and the switch is connected in parallel to the input and output ends of the inverter to selectively connect the inverter to the output end of the second differential comparator 160, thereby adjusting the polarity of the output signal.

[0073] In one embodiment, the number of first differential comparators 150 is at least 4; the external device includes but is not limited to 4 groups of differential terminal pairs, wherein the first differential terminal pair includes terminal OBD6 and terminal OBD14; the second differential terminal pair includes terminal OBD3 and terminal OBD11; the third differential terminal pair includes terminal OBD3 and terminal OBD8; and the fourth differential terminal pair includes terminal OBD12 and terminal OBD1.

[0074] It is understood that the external device may be an onboard self-diagnostic system. Terminals OBD6 and OBD14, terminals OBD3 and OBD11, terminals OBD3 and OBD8, and terminals OBD12 and OBD1 are typically defaulted to differential terminal pairs for outputting two differential signals. Therefore, to facilitate data transmission, the number of first differential comparators 150 may be at least four, correspondingly connected to each differential terminal pair. Regarding the signal reception process under the differential communication protocol, taking the differential terminal pair of terminals OBD6 and OBD14 as an example, assume that terminal OBD6 is a high-side driver with an output voltage of 5V. A 60Ω differential impedance is connected via a control switch in the driver circuit, and the device is connected to a buffer, thereby switching terminal OBD6 to the CANH function of the differential pair. Assume that terminal OBD14 is a low-side driver with an output voltage of 5V. A 60Ω differential impedance is connected via a control switch in the driver circuit, and the device is connected to a buffer, thereby switching terminal OBD14 to the CANL function of the differential pair. The process of receiving signals for other differential terminal pairs is similar.

[0075] In one embodiment, Figure 4 As shown, the integrated transceiver circuit also includes a plurality of second voltage-dividing circuits (not shown), a plurality of second selectors 180 and a plurality of buffer amplifiers (not shown), each second voltage-dividing circuit is respectively connected one-to-one with each monitoring terminal group of the external device, wherein the second voltage-dividing circuit is connected to each communication terminal in the corresponding monitoring terminal group, for dividing the communication signal from each communication terminal; each second selector 180 is respectively connected one-to-one with each second voltage-dividing circuit, for selecting at most one of the divided communication signals for output; each buffer amplifier is respectively connected one-to-one with each second selector 180, for outputting the communication signal output by the second selector 180.

[0076] Among them, each monitoring terminal group can be a group of communication terminals of the external diagnostic equipment with a voltage to be monitored. In order to realize the monitoring of the output status of each monitoring terminal group, the corresponding second voltage divider circuit is first used to divide the communication signal output by it to reduce the voltage of the communication signal, and then the divided communication signal is transmitted to the corresponding second selector 180, so as to select one of the communication signals of the OBD end for output according to the monitoring needs, and then output through the buffer amplifier to match the input impedance and reduce signal distortion, and finally transmitted to the AUX pin of the integrated transceiver circuit for output.

[0077] In one embodiment, the voltage division ratio of the second voltage division circuit may be 0.2.

[0078] In one embodiment, the number of second voltage divider circuits, the number of second selectors 180 and the buffer amplifier is at least 4, and the external devices include but are not limited to 4 groups of terminal groups to be monitored, wherein the first terminal group to be monitored includes terminal OBD1, terminal OBD3, terminal OBD7 and terminal OBD9; the second terminal group to be monitored includes terminal OBD2, terminal OBD6, terminal OBD8 and terminal OBD10; the third terminal group to be monitored includes terminal OBD11, terminal OBD13, terminal OBD15 and terminal OBD16; and the fourth terminal group to be monitored includes terminal OBD14.

[0079] It is understood that the external device may be an onboard self-diagnostic system, which typically defines terminals OBD1, OBD3, OBD7, and OBD9 as a group of terminals to be monitored; terminals OBD2, OBD6, OBD8, and OBD10 as a group of terminals to be monitored; terminals OBD11, OBD13, OBD15, and OBD16 as a group of terminals to be monitored; and terminal OBD14 as a group of terminals to be monitored. Therefore, to facilitate monitoring, the number of second voltage divider circuits, the number of second selectors 180, and the number of buffer amplifiers may be at least four, thereby correspondingly monitoring each group of terminals to be monitored. This allows voltage monitoring of any OBD terminal. In one embodiment, this monitoring method can be used to read the pin voltage of any OBD terminal and then determine the pin protocol type based on the pin voltage. For example, if the pin voltage of terminal OBD6 is 2.5V, it can be determined that it is a CAN protocol.

[0080] In one embodiment, Figure 5 As shown, the upper tube load adjustment unit 1321 and the lower tube load adjustment unit 1322 respectively include multiple parallel branches, each of which includes a switch element K2 and a resistor element R2 or a current mirror unit (not shown) connected in series with the switch element K2.

[0081] It can be understood that the upper tube load adjustment unit 1321 is used to clamp the output drive signal at a high level, and the lower tube load adjustment unit 1322 is used to clamp the output drive signal at a low level. The upper tube load adjustment unit 1321 and the lower tube load adjustment unit 1322 may include multiple parallel branches, each branch may include a switching element and a resistance element connected in series, or a switching element and a current mirror unit connected in series, and the switching element is used to control the connection of the resistance element or the current mirror unit, thereby realizing the voltage, current and load configuration of the output drive signal.

[0082] In one embodiment, the resistance values ​​of the resistor elements R2 may be the same or different. In one embodiment, the currents provided by the current mirror units may be the same or different.

[0083] In one embodiment, the driver may further include a diode D1 and a diode D2. Figure 5 As shown, they are respectively set at the output ends of transistor NH and transistor PL to limit the current flow and ensure the normal operation of the transistors.

[0084] In one embodiment, the driving circuit 130 further includes two output configuration circuits, each of which includes an inverter N and a switching element connected in parallel between the input and output ends of the inverter N; wherein the input end of the inverter N is connected to the target transistor, and the output end of the inverter N is connected to the gate of the target transistor; the target transistor is a transistor NH or a transistor PL.

[0085] It can be understood that the signal from the external device may be a high voltage indicating a dominant state or a low voltage indicating a dominant state. To achieve driving of the transistor, an output configuration circuit can be provided at the gate of each transistor to change the polarity of the signal transmitted from the external device to the transistor. Specifically, the output configuration circuit may include an inverter N and a switch element K3 connected in parallel across inverter N. Switch element K3 can selectively connect inverter N between the transmission matrix 110 and the transistor, thereby selectively changing the polarity of the signal output by the transmission matrix 110 to effectively drive the transistor. For example, if the signal output by the transmission matrix 110 is a low level and transistor NH requires a high level drive, the switch can be opened, allowing the signal to be converted to a high level through inverter N and further transmitted to transistor NH.

[0086] The embodiment of the present invention further provides an integrated transceiver circuit, such as Figure 5As shown, it includes a transmitting matrix 110, a receiving matrix 140, a buffer 120, multiple driving circuits 130, multiple first differential comparators 150, two first selectors 170, a second differential comparator 160, multiple second voltage divider circuits, multiple second selectors 180 and multiple buffer amplifiers. Each driving circuit 130 includes a voltage stabilizing circuit 131, a driver, a differential impedance control unit, a hysteresis comparator, a first DAC circuit, a second DAC circuit, a first voltage divider circuit and two output configuration circuits.

[0087] In the signal transmission mode, the driver includes a transistor NH and an upper tube load adjustment unit 1321 connected between the source and drain of transistor NH, a transistor PL and a lower tube load adjustment unit 1322 connected between the source and drain of transistor PL, a diode D1 connected to the drain of transistor NH, and a diode D2 connected to the drain of transistor PL. The voltage regulator circuit 131 is used to output a supply voltage to the source of transistor NH and the upper tube load adjustment unit 1321. The source of transistor PL is connected to ground. In this way, the driver can be configured to output an output drive signal with a configurable voltage when selected by the transmission matrix 110. The gates of transistors NH and PL can also be connected to output configuration circuits, which include an inverter N and a switch element connected in parallel between the input and output of inverter N. This switch element can be used to connect inverter N between the transmission matrix 110 and the transistor, thereby adapting to both dominant and recessive input modes.

[0088] The differential impedance control unit includes a control switch K1 and a load element 1331 connected in series with the control switch K1. The control switch K1 can selectively turn on the conductive path where the driver, the load element 1331 and the buffer 120 are located to maintain the reference voltage of the output drive signal at the reference voltage.

[0089] In the signal receiving mode, the hysteresis comparator includes a first threshold comparator 1341, a second threshold comparator 1342 and an RS trigger. The first voltage divider circuit can be configured to divide the power supply voltage of the bus power supply, and use the first voltage obtained by the voltage division as the reference voltage of the first DAC circuit, and use the second voltage obtained by the voltage division as the reference voltage of the second DAC circuit, so that the first DAC circuit provides a first hysteresis voltage to the first threshold comparator 1341, and the second DAC circuit provides a second hysteresis voltage to the second threshold comparator 1342. The first threshold comparator 1341 and the second threshold comparator 1342 respectively receive A driving signal is output, and the voltage of the output driving signal is compared with the corresponding hysteresis voltage, wherein the first hysteresis voltage is less than the second hysteresis voltage. The comparison result of the first threshold comparator 1341 is output to the reset terminal of the RS trigger, and the comparison result of the second threshold comparator 1342 is output to the set terminal of the RS trigger. The output result of the RS trigger is output to the receiving matrix 140, and then transmitted by the receiving matrix 140 to the corresponding port of the external control device. In this way, when the voltage of the input driving signal is between the first hysteresis voltage and the second hysteresis voltage, the output result of the RS trigger remains unchanged, thereby improving the accuracy and reliability of the output signal.

[0090] Each first differential comparator 150 corresponds one-to-one to each differential terminal pair of the external device, and the two input terminals of the first differential comparator 150 are connected one-to-one to the two terminals of the corresponding differential terminal pair; the output terminal of each first differential comparator 150 is connected to the receiving matrix 140, thereby realizing the reception of differential signals from the defined differential terminal pairs.

[0091] The two input ends of the second differential comparator 160 are respectively connected to the output ends of the two first selectors 170 in a one-to-one correspondence, and the output end of the second differential comparator 160 is connected to the receiving matrix 140; the first selector 170 is used to connect to each communication terminal of the external device, so that the two first selectors 170 can respectively select one of the communication terminals to be connected to the second differential comparator 160, thereby realizing the reception of differential signals from undefined terminal pairs.

[0092] The comparison thresholds and output polarities of the first differential comparator 150 and the second differential comparator 160 are adjustable, so that the voltage of any input drive signal and the drive polarity can be adjusted.

[0093] Furthermore, the coordination of multiple second voltage-dividing circuits, multiple second selectors 180, and multiple buffer amplifiers enables OBD output monitoring. Each second voltage-dividing circuit corresponds one-to-one with each monitoring terminal group of an external device. The second voltage-dividing circuit is connected to each communication terminal in the corresponding monitoring terminal group to divide the voltage of the communication signal from each communication terminal. Each second selector 180 is connected one-to-one with each second voltage-dividing circuit to select at most one of the divided communication signals for output. Finally, the buffer amplifier amplifies the communication signal output by the second selector 180. This allows the external monitoring device to determine the OBD output status based on the amplified signal.

[0094] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An integrated transceiver circuit, characterized in that: include: Send Matrix; Receive matrix; a buffer for providing a reference voltage; A plurality of driving circuits, each of the driving circuits comprising: A voltage stabilizing circuit, used for providing a power supply voltage with an adjustable voltage value; A driver, comprising a transistor NH and an upper tube load adjustment unit connected between the source and drain of the transistor NH, and a transistor PL and a lower tube load adjustment unit connected between the source and drain of the transistor PL, wherein the gates of the transistor NH and the transistor PL are respectively connected to the transmitting matrix, the source of the transistor NH is connected to the voltage stabilizing circuit, and the source of the transistor PL is connected to the ground terminal. The driver is configured to output an output drive signal with voltage, current, and load controllable when selected by the transmitting matrix; a differential impedance control unit, comprising a control switch and a load element connected in series with the control switch, wherein the control switch is configured to selectively conduct a conductive path in which the driver, the load element, and the buffer are located, so as to maintain a reference voltage of the output drive signal at the reference voltage; Hysteresis comparator, including: a first threshold comparator, configured to receive an input drive signal from an external device and compare a voltage of the input drive signal with a first hysteresis voltage; a second threshold comparator, configured to receive the input drive signal and compare a voltage of the input drive signal with a second hysteresis voltage; wherein the first hysteresis voltage is smaller than the second hysteresis voltage; an RS trigger, wherein a reset terminal of the RS trigger is connected to the output terminal of the first threshold comparator, and a set terminal of the RS trigger is connected to the output terminal of the second threshold comparator; The receiving matrix is ​​selectively connected to the output end of each of the RS triggers.

2. The integrated transceiver circuit according to claim 1, wherein: The driving circuit further includes: a first DAC circuit, connected to the first threshold comparator, for providing the first hysteresis voltage; The second DAC circuit is connected to the second threshold comparator and is used to provide the second hysteresis voltage.

3. The integrated transceiver circuit according to claim 2, wherein: The driving circuit further includes: The first voltage divider circuit is respectively connected to the bus power supply, the first DAC circuit and the second DAC circuit, and can be configured to divide the power supply voltage of the bus power supply to obtain a first voltage, and use the first voltage as a reference voltage for the first DAC circuit, and to obtain a second voltage, and use the second voltage as a reference voltage for the second DAC circuit.

4. The integrated transceiver circuit according to claim 1, wherein: The integrated transceiver circuit further includes: A plurality of first differential comparators are provided, each of the first differential comparators corresponding one-to-one to each differential terminal pair of the external device, and two input terminals of the first differential comparator are connected one-to-one to two terminals of the corresponding differential terminal pair; and an output terminal of each first differential comparator is connected to the receiving matrix.

5. The integrated transceiver circuit according to claim 4, wherein: The integrated transceiver circuit further includes: two first gates; a second differential comparator, wherein two input terminals of the second differential comparator are respectively connected to the output terminals of the two first gates in a one-to-one correspondence, and an output terminal of the second differential comparator is connected to the receiving matrix; The first selector is used to connect to each communication terminal of the external device and to select one of the communication terminals to be connected to the differential comparator.

6. The integrated transceiver circuit according to claim 5, characterized in that: The comparison thresholds and output polarities of the first differential comparator and the second differential comparator are adjustable.

7. The integrated transceiver circuit according to claim 4, wherein: The number of the first differential comparators is at least 4; the external device includes but is not limited to 4 groups of differential terminal pairs, wherein the first differential terminal pair includes terminal OBD6 and terminal OBD14; the second differential terminal pair includes terminal OBD3 and terminal OBD11; the third differential terminal pair includes terminal OBD3 and terminal OBD8; and the fourth differential terminal pair includes terminal OBD12 and terminal OBD1.

8. The integrated transceiver circuit according to claim 1, wherein: The integrated transceiver circuit further includes: a plurality of second voltage divider circuits, each of the second voltage divider circuits corresponding one-to-one to each monitoring terminal group of the external device, and the second voltage divider circuit is connected to each communication terminal in the corresponding monitoring terminal group, for dividing the communication signal from each communication terminal; a plurality of second selectors, connected one-to-one with each of the second voltage divider circuits, for selecting at most one of the divided communication signals for output; A plurality of buffer amplifiers are connected to the second gates in a one-to-one correspondence, and are used to output the communication signal output by the second gate.

9. The integrated transceiver circuit according to claim 8, wherein: The number of the second voltage divider circuits, the number of the second selectors and the number of the buffer amplifiers are at least 4, and the external devices include but are not limited to 4 groups of terminal groups to be monitored, wherein the first terminal group to be monitored includes terminal OBD1, terminal OBD3, terminal OBD7 and terminal OBD9; the second terminal group to be monitored includes terminal OBD2, terminal OBD6, terminal OBD8 and terminal OBD10; the third terminal group to be monitored includes terminal OBD11, terminal OBD13, terminal OBD15 and terminal OBD16; and the fourth terminal group to be monitored includes terminal OBD14.

10. The integrated transceiver circuit according to claim 1, wherein: The upper tube load adjustment unit and the lower tube load adjustment unit respectively include a plurality of parallel branches, wherein each branch includes a switch element and a resistance element or a current mirror unit connected in series with the switch element.

11. The integrated transceiver circuit according to claim 1, wherein: The driving circuit further includes: Two output configuration circuits, each of which includes an inverter and a switching element connected in parallel between the input and output of the inverter; wherein the input of the inverter is connected to the target transistor, and the output of the inverter is connected to the gate of the target transistor; the target transistor is the transistor NH or the transistor PL.

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