A modulation method for parallel converter

Abstract

The invention discloses a modulation method for a parallel converter, establishes a parallel converter mathematical model, determines a basic voltage vector and a space voltage vector plane; divides the space voltage vector plane into 6 large sectors, selects a basic voltage vector with a zero-sequence circulating current change rate of ‑1~+1 in each large sector, determines 8 switch timings based on the principle of minimum switching times, divides the large sector into 8 sub-sectors corresponding to 8 switch timings based on the principle of minimum voltage synthesis error, and obtains 48 optimal switch timings covering the entire space voltage vector plane; calculates the three-phase switch duty ratio based on the vector synthesis principle and the switch timing, and normalizes the three-phase switch duty ratios of the 48 sub-sectors; tracks the change of the zero-sequence circulating current of the parallel converter to optimize the three-phase switch duty ratio, synthesizes a modulation wave based on the optimal switch timing, and generates a PWM signal to control the on-off of the switch tube of the parallel converter after comparison with the carrier, and completes the modulation. The invention improves the efficiency of the parallel converter.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a modulation method for a parallel converter. Background Art

[0002] With the growing demand for high power in industrial applications, parallel converters are widely used in various high power applications, such as high power motor drives, grid-connected wind power generation and uninterruptible power supplies. Parallel converters reduce the size and cost while doubling the system capacity by directly connecting two two-level converters in parallel, becoming an excellent current expansion topology.

[0003] Since two two-level parallel converters share the same DC bus, the AC output of the converter is connected to the load through the circulating current suppression inductor. When a common-mode voltage difference occurs between the converters, the common-mode voltage difference will excite the inductance of the parallel branch, thereby generating a zero-sequence circulating current with the DC capacitor, the parallel branch inductance and the power switch device as the conduction loop. The zero-sequence circulating current does not participate in the AC / DC power conversion of the parallel system, but is only a parasitic loss of the parallel system, which reduces the energy conversion efficiency of the system. The zero-sequence circulating current includes high-frequency zero-sequence circulating current and low-frequency zero-sequence circulating current. The high-frequency zero-sequence circulating current is related to the switching order of the system, and the low-frequency zero-sequence circulating current is mostly due to the asymmetry of the operating conditions. In addition, the parallel system is usually used in high-current applications. In order to reduce the switching loss under high-current conditions, it is necessary to reduce the number of actions of the power switch devices of the parallel system within the carrier period as much as possible. Therefore, in order to improve the operating performance and reliability of the two parallel converters, it is necessary to propose a modulation method to suppress the zero-sequence circulating current of the parallel converter and reduce the switching loss. Summary of the invention

[0004] The purpose of the present invention is to provide a modulation method for a parallel converter.

[0005] The technical solution to achieve the purpose of the present invention is: a modulation method of a parallel converter, characterized by comprising the following steps:

[0006] Step 1: Establish a mathematical model of a parallel converter and determine a basic voltage vector and a space voltage vector plane;

[0007] Step 2: Divide the spatial voltage vector plane into 6 large sectors, select a basic voltage vector with a zero-sequence circulating current change rate of -1~+1 in each large sector, and determine 8 switching timings based on the principle of minimum switching times. Based on the principle of minimum voltage synthesis error, divide the large sector into 8 sub-sectors corresponding to 8 switching timings, and obtain 48 optimal switching timings covering the entire spatial voltage vector plane;

[0008] Step 3: Calculate the three-phase switch duty ratio according to the vector synthesis principle and the switch timing, and normalize the three-phase switch duty ratios of the 48 sub-sectors;

[0009] Step 4: Track the change of zero-sequence circulating current of the parallel converter to optimize the duty cycle of the three-phase switch, synthesize the modulation wave based on the optimal switching timing, and generate a PWM signal after comparing it with the carrier to control the on and off of the switch tube of the parallel converter to complete the modulation.

[0010] A control system for a three-phase motor driver in multiple working states implements the modulation method of the parallel converter to achieve modulation of the parallel converter.

[0011] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the modulation method of the parallel converter is implemented to realize the modulation of the parallel converter.

[0012] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the modulation method of the parallel converter is implemented to achieve the modulation of the parallel converter.

[0013] Compared with the prior art, the present invention has the following significant advantages: 1) designing the optimal switching timing to suppress high-frequency zero-sequence circulating current and reduce switching loss; 2) optimizing the three-phase switch duty cycle to suppress low-frequency zero-sequence circulating current; 3) constructing a carrier modulation method to greatly reduce the amount of calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the topology diagram of the parallel converter.

[0015] Figure 2 It is the space voltage vector diagram of parallel converter.

[0016] Figure 3 This is the zero-sequence circulating current path diagram of the parallel converter.

[0017] Figure 4 This is the sub-sector division diagram of the first largest sector.

[0018] Figure 5 This is an action mode diagram.

[0019] Figure 6 It is a flow chart of the present invention.

[0020] Figure 7 It is the AC side output current waveform under the 180° staggered carrier modulation method under low modulation index operating conditions.

[0021] Figure 8 It is the zero-sequence circulating current waveform under the 180° staggered carrier modulation method under low modulation index operating conditions.

[0022] Fig. 9It is the AC side output current waveform of the modulation method of the present invention under low modulation index operating conditions.

[0023] Fig.10 Zero-sequence circulating current waveform under the modulation method of the present invention under low modulation index operating conditions.

[0024] Fig.11 It is the AC side output current waveform under the 180° staggered carrier modulation method under high modulation index operating conditions.

[0025] Fig.12 It is the zero-sequence circulating current waveform under the 180° staggered carrier modulation method under high modulation index operating conditions.

[0026] Fig.13 It is the output current waveform of the AC side under the modulation method of the present invention under high modulation index operating conditions.

[0027] Fig.14 It is the zero-sequence circulating current waveform under the modulation method of the present invention under high modulation index operating conditions.

[0028] Fig.15 It is the zero-sequence circulating current waveform without low-frequency zero-sequence circulating current suppression when the operating conditions are asymmetric.

[0029] Fig.16 It is the zero-sequence circulating current waveform with low-frequency zero-sequence circulating current suppression when the operating conditions are asymmetric. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The parallel converter topology has a three-level characteristic. The existing staggered 180° modulation method reduces the equivalent output current harmonics by staggering the carrier, but ignores the introduction of a larger zero-sequence circulating current. In view of this, the present invention selects a basic voltage vector with a zero-sequence circulating current change rate of -1~+1 in each large sector by analyzing the basic voltage vector of the parallel converter and the relationship between the zero-sequence circulating current and the switching state, and determines 8 optimal switching timings based on the principle of minimum switching times and minimum voltage synthesis error. The three-phase switch duty cycle is optimized to suppress low-frequency zero-sequence circulating current, and a carrier modulation method is constructed for 48 optimal switching timings covering the entire spatial voltage vector plane, which greatly reduces the amount of calculation to be implemented. A modulation method for a parallel converter, comprising the following:

[0032] Step 1: Establish a mathematical model of the parallel converter and determine the basic voltage vector and the space voltage vector plane:

[0033] Figure 1 The topology diagram of the parallel converter is shown in Figure 2. The DC side shares the DC bus, and the AC side is connected in parallel to the AC load through the filter reactor. 11 -S 16 The first converter with a freewheeling diode switch tube (IGBT), S 21 -S 26 The switch tube (IGBT) with freewheeling diode for the second converter. j is the AC load voltage; i j is the three-phase output current on the AC side; i j1 and i j2 are the three-phase output currents of the sub-converters, where j = a, b, c; C is the DC bus capacitance, V DC is the DC bus voltage; L s is the AC side filter inductor, L1 and L2 are the filter inductors of the two sub-converters, R s , R1 and R2 are the corresponding parasitic resistances respectively; the mathematical model of parallel converter is established:

[0034]

[0035] u a 、u b and u c Respectively represent the three-phase equivalent output voltage, satisfying:

[0036]

[0037] Among them, V DC is the DC side voltage of the parallel converter, s a1 、s b1 、s c1 Indicates the switching state of the three-phase bridge arm switch tube of the first converter, s a2 、s b2 、s c2 Indicates the switch state of the three-phase bridge arm switch tube of the second converter. All switch states can only be 1 or 0. When it is 1, it means that the upper switch tube of the corresponding bridge arm is turned on and the lower switch tube is turned off. When it is 0, it means that the upper switch tube of the corresponding bridge arm is turned off and the lower switch tube is turned on.

[0038] There are 2 parallel converters 6 = 64 basic voltage vectors, and further based on the 64 basic voltage vectors, the space voltage vector plane of the parallel converter is obtained, and the 64 basic voltage vectors are classified into 19 vertex vectors, namely, zero vector: V0, including ten basic voltage vectors; small vector: V s1 、Vs2 、V s3 、V s4 、V s5 、V s6 , each small vector contains six basic voltage vectors; medium vector: V m1 、V m2 、V m3 、V m4 、V m5 、V m6 , each medium vector contains two basic voltage vectors; large vector: V l1 、V l2 、V l3 、V l4 、V l5 、V l6 , each large vector contains a basic voltage vector. The basic voltage vectors and switch states corresponding to each vertex vector are as follows, where the upper part in the brackets is the switch state of the three-phase bridge arm switch tube of the first converter, and the lower part is the switch state of the three-phase bridge arm switch tube of the second converter;

[0039] The zero vector is:

[0040] ;

[0041] The small vectors are:

[0042] ;

[0043] The vectors are:

[0044] ;

[0045] The large vectors are:

[0046] .

[0047] Step 2: Divide the spatial voltage vector plane into 6 large sectors, select a basic voltage vector with a zero-sequence circulating current change rate of -1~+1 in each large sector, and determine 8 switching timings based on the principle of zero-sequence circulating current balance and minimum number of switching times. Based on the principle of minimum voltage synthesis error, divide the large sector into 8 sub-sectors corresponding to 8 switching timings, and obtain 48 optimal switching timings covering the entire spatial voltage vector plane:

[0048] Divide the spatial voltage vector plane into 6 large sectors;

[0049] According to the angle between the basic voltage vector position and the a-axis position, the six large sectors are: 0°-60° is sector I, 60°-120° is sector II, 120°-180° is sector III, 180°-240° is sector IV, 240°-300° is sector V, and 300°-360° is sector VI;

[0050] In each large sector, a basic voltage vector with a zero-sequence circulating current change rate of -1 to +1 is selected and eight switching sequences are determined based on the principle of zero-sequence circulating current balance and minimum switching times;

[0051] Calculate the zero-sequence circulating current change rate of 64 basic voltage vectors, expressed as V DC / (2L1) is used as the base value for normalization, and the basic voltage vector with a zero-sequence circulating current change rate of -1 to +1 is selected as follows:

[0052] The zero vector is:

[0053] ;

[0054] The small vectors are:

[0055] ;

[0056] The vectors are:

[0057] ;

[0058] The large vectors are:

[0059] ;

[0060] Each large sector contains a zero vector, two small vectors, a medium vector and two large vectors. Based on the principle of zero-sequence circulating current balance and minimum switching times, the 8 switching sequences of sector I are:

[0061] Table 1 8 switch timings of sector I

[0062]

[0063] The 8 switch timings of sector II are:

[0064] Table 2 8 switch timings of sector II

[0065]

[0066] The 8 switch timings of sector III are:

[0067] Table 3 Timing of 8 switches in sector III

[0068]

[0069] The 8 switch timings of sector IV are:

[0070] Table 4 8 switch timings of sector IV

[0071]

[0072] The 8 switch timings of sector V are:

[0073] Table 5 The 8 switch timings of sector V

[0074]

[0075] The 8 switch timings of sector VI are:

[0076] Table 6 8 switch timings of sector VI

[0077]

[0078] Based on the principle of minimum voltage synthesis error, the large sector is divided into 8 sub-sectors corresponding to 8 switching timings, and 48 optimal switching timings covering the entire spatial voltage vector plane are obtained;

[0079] Ignoring the influence of parasitic resistance on the inductor, the current ripple expression satisfies: ;

[0080] Where U e represents the basic voltage vector of the parallel converter, U ref represents the reference voltage vector of the parallel converter; ∆t represents the duration of a certain vector in the switching cycle; U rip represents the voltage error vector;

[0081] Based on the principle of minimum voltage synthesis error, it is necessary to use the basic voltage vector synthesis of the adjacent reference voltage vector as much as possible. For the switching timing with overlapping linear modulation area, the boundary line of the overlapping area is obtained by calculating the effective value of the current ripple switching period; each large sector is divided into 8 sub-sectors ①~⑧, and sub-sectors ①~⑧ correspond to the switching timing Sqx1~Sqx8 one by one, x is Ⅰ~Ⅵ, sector ① adopts the switching timing Sqx1, sector ② adopts the switching timing Sqx2, sector ③ adopts the switching timing Sqx3, and so on, so as to obtain 48 optimal switching timings covering the entire spatial voltage vector plane.

[0082] Step 3: Calculate the three-phase switch duty ratio according to the vector synthesis principle and the switch timing, and normalize the three-phase switch duty ratios of the 48 sub-sectors:

[0083] According to the vector synthesis principle, the three basic voltage vectors of each optimal switching timing are used to synthesize the reference voltage vector, and the duty cycle of the basic voltage vector is calculated:

[0084] Among them, u a 、u b and u c Respectively represent the A, B and C phase voltages of the reference voltage vector; u α and u β Represents the component of the reference voltage vector in the two-phase stationary coordinate system; V Xα and V Xβ Represents the basic voltage vector V X Component in the two-phase stationary coordinate system; V Yα and V Yβ Represents the basic voltage vector V Y Component in the two-phase stationary coordinate system; V Zα and V Zβ Represents the basic voltage vector V Z The component in the two-phase stationary coordinate system; d X ,d Y and d Z Represents the basic voltage vector V X 、V Y and V Z The corresponding duty cycle;

[0085] According to the duty cycle of the basic voltage vector and each optimal switch timing, the three-phase switch duty cycle of the first converter and the three-phase switch duty cycle of the second converter in 48 neutron sectors are obtained;

[0086] The duty ratio of the three-phase switches in each sub-sector of sector I is:

[0087] Table 7 Duty ratio of three-phase switches in each sub-sector of sector I

[0088]

[0089] The duty ratio of the three-phase switches in each sub-sector of sector II is:

[0090] Table 8 Duty ratio of three-phase switches in each sub-sector of sector II

[0091]

[0092] The duty ratio of the three-phase switches in each sub-sector of sector III is:

[0093] Table 9 Duty ratio of three-phase switches in each sub-sector of sector III

[0094]

[0095] The duty ratio of the three-phase switches in each sub-sector of sector IV is:

[0096] Table 10 Duty ratio of three-phase switches in each sub-sector of sector IV

[0097]

[0098] The duty ratio of the three-phase switches in each sub-sector of sector V is:

[0099] Table 11 Duty ratio of three-phase switches in each sub-sector of sector V

[0100]

[0101] The duty ratio of the three-phase switches in each sub-sector of sector VI is:

[0102] Table 12 Duty ratio of three-phase switches in each sub-sector of sector VI

[0103]

[0104] u a * 、u b * and u c * Indicated by DC bus voltage V DC The three-phase voltage per unit value is the reference;

[0105] Normalize the three-phase switch duty ratios of the sub-sectors in each major sector of the above two converters:

[0106] ;

[0107] Where, d a1 ,d b1 ,d c1 ,d a2 ,d b2 ,d c2 is the normalized three-phase switch duty cycle, where d a1 ,d b1 ,d c1 Corresponding to the first converter, d a2 ,d b2 ,d c2 For the second converter, u max 、u mid and u min for u a * 、u b * and u c * The maximum, middle, and minimum values ​​of .

[0108] Step 4: Track the change of zero-sequence circulating current of the parallel converter to optimize the duty cycle of the three-phase switch, synthesize the modulation wave based on the optimal switch timing, and generate a PWM signal to control the switch on and off to complete the modulation after comparing with the carrier:

[0109] Track the change of zero-sequence circulating current of parallel converter to optimize the duty cycle of three-phase switch;

[0110] Optimize the three-phase switch duty cycle of the first converter and keep the three-phase switch duty cycle of the second converter unchanged. z >0, for d max The duty cycle of the phase switch is reduced by ∆d, and the other two phases remain unchanged; when the zero-sequence circulating current i z <0, for d min The duty cycle of the phase switch is increased by ∆d, and the other two phases remain unchanged, where d max and d min is the maximum and minimum value of the duty cycle of the three-phase switch of the first converter. In order not to destroy the reference voltage vector synthesis, ∆d≤d max , where ∆d=abs(i z ) / (T s *V DC *2L1), abs is the absolute value function, T s is the switching period; by reasonably inserting ∆d, the optimized three-phase switch duty cycle d of the first converter is obtained. a1opt ,d b1opt and d c1opt , the second converter three-phase switch duty cycle d a2 ,d b2 and d c2 remain unchanged;

[0111] The modulation wave is synthesized based on the optimal switching timing, and after comparison with the carrier, a PWM signal is generated to control the switch on and off to complete the modulation;

[0112] According to the optimal switching sequence and the optimized three-phase switch duty cycle, the modulation wave m of the first converter of the six large sectors is determined. a1 、m b1 、m c1 and the second converter modulates the wave m a2 、m b2 、m c2 And action mode:

[0113] Table 13 Modulation waves and operation modes of six large sectors

[0114]

[0115] The two action modes are specifically: action 1: when the modulation wave is ≥ carrier, the switch state is 1, otherwise the switch state is 0; action 2: when each phase modulation wave is ≤ carrier, the switch state is 1, otherwise the switch state is 0;

[0116] The modulation wave of the first converter is compared with carrier wave 1 to generate a PWM signal, and the modulation wave of the second converter is compared with carrier wave 2 to generate a PWM signal. Carrier wave 1 is in a downward-upward counting mode, and carrier wave 2 is in an upward-downward counting mode, that is, carrier wave 1 and carrier wave 2 have a phase difference of 180°;

[0117] According to the relationship between the sector position and the three-phase reference voltage, the modulation waves and action modes of the above six large sectors are normalized, m a1 、m b1 、m c1 、m a2 、m b2 、m c2 is the normalized modulation wave:

[0118] ;

[0119] Only when When k a =1, otherwise k a =0; only when When k b =1, otherwise k b =0; only when When k c =1, otherwise k c = 0, when k j =0, the j-phase modulation wave is action mode 1; when k j =1, the j-phase modulation wave is action mode action2, j=a,b,c;

[0120] According to the above modulation wave expression and action mode, carrier modulation is realized, and the PWM signal is output to control the on and off of the switch tube of the parallel converter to complete the modulation of the parallel converter.

[0121] The present invention also proposes a control system for a three-phase motor driver in multiple working states, which implements the modulation method of the parallel converter to achieve modulation of the parallel converter.

[0122] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the modulation method of the parallel converter is implemented to realize the modulation of the parallel converter.

[0123] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the modulation method of the parallel converter is implemented to achieve the modulation of the parallel converter. In summary, the present invention achieves the suppression of high-frequency and low-frequency zero-sequence circulating currents, the reduction of switching losses, and the reduction of current ripple of the parallel converter by optimizing the duty cycle and switching timing of the three-phase switch, thereby effectively improving the efficiency of the parallel converter system.

[0124] In order to verify the effectiveness of the scheme of the present invention, the following experiment was carried out.

[0125] Example 1

[0126] In this embodiment, the 180° staggered carrier modulation method is compared with the modulation method of the present invention under the low modulation index operating condition. The 180° staggered carrier modulation method reduces the output current harmonics on the AC side and introduces a larger zero-sequence circulating current. Figure 7 is the AC side output current under the 180° staggered carrier modulation method under low modulation index operating conditions, Figure 8 It is the zero-sequence circulating current under the 180° staggered carrier modulation method under low modulation index operating conditions. The modulation method of the present invention reduces the zero-sequence circulating current of the system while optimizing the current harmonics and switching losses. Fig. 9 is the AC side output current under the modulation method of the present invention under low modulation index operating conditions, Fig.10 It is the zero-sequence circulating current under the modulation method of the present invention under low modulation index operating conditions.

[0127] Example 2

[0128] In this embodiment, the modulation method of the present invention is compared with the staggered 180° carrier modulation method under the high modulation index operating condition. The staggered 180° carrier modulation method introduces a larger zero-sequence circulating current while reducing the harmonics of the AC side output current, but the peak value of the circulating current is lower than that under the low modulation index operating condition. Fig.11 is the AC side output current under the 180° staggered carrier modulation method under high modulation index operating conditions, Fig.12 It is the zero-sequence circulating current under the staggered 180° carrier modulation method under high modulation index operating conditions. The modulation method of the present invention reduces the zero-sequence circulating current of the system while optimizing the current harmonics and switching losses. However, compared with the peak value of the circulating current under low modulation index conditions, it is still smaller than the staggered 180° carrier modulation method. Fig.13 is the AC side output current under the modulation method of the present invention under high modulation index operating conditions, Fig.14 It is the zero-sequence circulating current under the modulation method of the present invention under high modulation index operating conditions.

[0129] Example 3

[0130] This embodiment operates at a high modulation index and has an asymmetric operating condition. Taking the first converter with different three-phase filter inductance values ​​as an example, the zero-sequence circulating current waveform without low-frequency zero-sequence circulating current suppression is as follows: Fig.15 As shown, the zero-sequence circulating current waveform with low-frequency zero-sequence circulating current suppression is as follows Fig.16 As shown, the low-frequency zero-sequence circulating current suppression can effectively suppress the low-frequency zero-sequence circulating current caused by asymmetric operating conditions.

[0131] The above three embodiments show that the modulation method proposed in the present invention can achieve zero-sequence circulating current suppression and switching loss reduction under the full modulation index of the system.

[0132] The above embodiments can prove the effectiveness of the present invention. To make the description concise, not all possible working conditions in the above embodiments are described. However, as long as there is no contradiction in the working conditions of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A modulation method for a parallel converter, characterized in that: The following steps are involved: Step 1: Establish a mathematical model of a parallel converter and determine a basic voltage vector and a space voltage vector plane; Step 2: Divide the spatial voltage vector plane into 6 large sectors, select a basic voltage vector with a zero-sequence circulating current change rate of -1~+1 in each large sector, and determine 8 switching timings based on the principle of minimum switching times. Based on the principle of minimum voltage synthesis error, divide the large sector into 8 sub-sectors corresponding to 8 switching timings, and obtain 48 optimal switching timings covering the entire spatial voltage vector plane; Step 3: Calculate the three-phase switch duty ratio according to the vector synthesis principle and the switch timing, and normalize the three-phase switch duty ratios of the 48 sub-sectors; Step 4: Track the change of zero-sequence circulating current of the parallel converter to optimize the duty cycle of the three-phase switch, synthesize the modulation wave based on the optimal switch timing, and generate a PWM signal after comparing it with the carrier to control the switching tube of the parallel converter to complete the modulation. The specific method is as follows: (1) Track the changes in zero-sequence circulating current of parallel converters to optimize the duty cycle of three-phase switches; Optimize the three-phase switch duty cycle of the first converter and keep the three-phase switch duty cycle of the second converter unchanged. z >0, for d max The duty cycle of the phase switch is reduced by ∆d, and the other two phases remain unchanged; when the zero-sequence circulating current i z <0, for d min The duty cycle of the phase switch is increased by ∆d, and the other two phases remain unchanged, where d max and d min is the maximum and minimum value of the three-phase switch duty cycle of the first converter. In order not to destroy the reference voltage vector synthesis, ∆d≤d max , where ∆d=abs(i z ) / (T s *V DC *2L1), abs is the absolute value function, T s is the switching period; by reasonably inserting ∆d, the optimized three-phase switch duty cycle d of the first converter is obtained. a1opt ,d b1opt and d c1opt , the three-phase switch duty cycle d of the second converter a2 ,d b2 and d c2 Remain unchanged; where L1 represents the output inductance of the converter bridge side, V DC is the DC side voltage of the parallel converter; (2) Based on the optimal switching timing, the modulation wave is synthesized and compared with the carrier to generate a PWM signal to control the switching tube of the parallel converter to complete the modulation; According to the optimal switching sequence and the optimized three-phase switch duty cycle, the modulation wave m of the first converter of the six large sectors is determined. a1 、m b1 、m c1 and the modulation wave m of the second converter a2 、m b2 、m c2 And action mode: Sector I: ， Sector II: ， Sector III: ， Sector IV: ， Sector V: ， Sector VI: ； The two action modes are as follows: action1: when the modulation wave is ≥ carrier, the switch state is 1, otherwise the switch state is 0; action2: when each phase modulation wave is ≤ carrier, the switch state is 1, otherwise the switch state is 0; The modulation wave of the first converter is compared with carrier 1 to generate a PWM signal, and the modulation wave of the second converter is compared with carrier 2 to generate a PWM signal. Carrier 1 is in a downward-upward counting mode, and carrier 2 is in an upward-downward counting mode, that is, carrier 1 and carrier 2 have a phase difference of 180°; According to the relationship between the sector position and the three-phase reference voltage, the modulation waves and action modes of the six large sectors of the two converters are normalized. a1 、m b1 、m c1 、m a2 、m b2 、m c2 is the normalized modulation wave: ； Only when When k a =1, otherwise k a =0; only if When k b =1, otherwise k b =0; only when When k c =1, otherwise k c = 0, when k j =0, the j-phase modulation wave is action mode 1; when k j =1, the j-phase modulation wave is action mode action2, j=a,b,c.

2. The modulation method of a parallel converter according to claim 1, characterized in that: Step 1: Establish a mathematical model of the parallel converter and determine the basic voltage vector and the space voltage vector plane. The specific method is as follows: (1) Establish a mathematical model of parallel converter; ； Among them, e a 、e b 、e c are the AC load voltages of phase a, phase b, and phase c respectively, i a 、i b and i c Respectively represent the three-phase parallel current; L e and R e Respectively represent the equivalent inductance and equivalent parasitic resistance, satisfying L e =L s +L1 / 2 and R e =R s +R1 / 2, where L s and R s They represent the inductance and parasitic resistance of the AC side, L1 and R1 represent the output inductance and parasitic resistance of the converter bridge side; u a 、u b and u c Respectively represent the three-phase equivalent output voltage, satisfying: ； Among them, V DC is the DC side voltage of the parallel converter, s a1 、s b1 、s c1 Indicates the switching state of the three-phase bridge arm switch tube of the first converter, s a2 、s b2 、s c2 Indicates the switch state of the three-phase bridge arm switch tube of the second converter. All switch states are 1 or 0. When 1 is taken, it means that the upper switch tube of the corresponding bridge arm is turned on and the lower switch tube is turned off. When 0 is taken, it means that the upper switch tube of the corresponding bridge arm is turned off and the lower switch tube is turned on. (2) Determine the basic voltage vector and the spatial voltage vector plane; There are 2 parallel converters 6 = 64 basic voltage vectors, and further based on the 64 basic voltage vectors, the space voltage vector plane of the parallel converter is obtained, and the 64 basic voltage vectors are classified into 19 vertex vectors, namely, zero vector: V0, including ten basic voltage vectors; small vector: V s1 、V s2 、V s3 、V s4 、V s5 、V s6 , each small vector contains six basic voltage vectors; medium vector: V m1 、V m2 、V m3 、V m4 、V m5 、V m6 , each medium vector contains two basic voltage vectors; large vector: V l1 、V l2 、V l3 、V l4 、V l5 、V l6 , each large vector contains a basic voltage vector. The basic voltage vectors and switch states corresponding to each vertex vector are as follows, where the upper part in the brackets is the switch state of the three-phase bridge arm switch tube of the first converter, and the lower part is the switch state of the three-phase bridge arm switch tube of the second converter; The zero vector is: ； The small vectors are: ； The vectors are: ； The large vectors are: 。 3. The modulation method of a parallel converter according to claim 2, characterized in that: In step 2, the spatial voltage vector plane is divided into 6 large sectors. In each large sector, a basic voltage vector with a zero-sequence circulating current change rate of -1~+1 is selected, and 8 switching timings are determined based on the principle of zero-sequence circulating current balance and minimum number of switching times. Based on the principle of minimum voltage synthesis error, the large sector is divided into 8 sub-sectors corresponding to 8 switching timings, and 48 optimal switching timings covering the entire spatial voltage vector plane are obtained. The specific method is: (1) Divide the spatial voltage vector plane into six large sectors; Based on the angle between the basic voltage vector position and the a-axis position, the six large sectors are: 0°~60° is sector I, 60°~120° is sector II, 120°~180° is sector III, 180°~240° is sector IV, 240°~300° is sector V, and 300°~360° is sector VI; (2) In each large sector, a basic voltage vector with a zero-sequence circulating current change rate of -1 to +1 is selected, and eight switching sequences are determined based on the principle of zero-sequence circulating current balance and minimum switching times; Calculate the zero-sequence circulating current change rate of 64 basic voltage vectors, expressed as V DC / (2L1) is used as the base value for normalization, and the basic voltage vector with a zero-sequence circulating current change rate of -1 to +1 is selected as follows: The zero vector is: ； The small vectors are: ； The vectors are: ； The large vectors are: ； Each large sector contains a zero vector, two small vectors, a medium vector and two large vectors. Based on the principle of zero-sequence circulating current balance and minimum switching times, the 8 switching sequences of sector I are: SqⅠ1: , SqⅠ2: , SqⅠ3: , SqⅠ4: , SqⅠ5: , SqⅠ6: , SqⅠ7: , SqⅠ8: ; The 8 switch timings of sector II are: SqⅡ1: , SqⅡ2: , SqⅡ3: , SqⅡ4: , SqⅡ5: , SqⅡ6: , SqⅡ7: , SqⅡ8: ; The 8 switch timings of sector III are: SqⅢ1: , SqⅢ2: , SqⅢ3: , SqⅢ4: , SqⅢ5: , SqⅢ6: , SqⅢ7: , SqⅢ8: ; The 8 switch timings of sector IV are: SqⅣ1: , SqⅣ2: , SqⅣ3: , SqⅣ4: , SqⅣ5: , SqⅣ6: , SqⅣ7: , SqⅣ8: ; The 8 switch timings of sector V are: SqⅤ1: , SqⅤ2: , SqⅤ3: , SqⅤ4: , SqⅤ5: , SqⅤ6: , SqⅤ7: , SqⅤ8: ; The 8 switch timings of sector VI are: SqVI1: , SqVI2: , SqVI3: , SqVI4: , SqVI5: , SqVI6: , SqVI7: , SqVI8: ; (3) Based on the principle of minimum voltage synthesis error, the large sector is divided into 8 sub-sectors corresponding to 8 switching timings, and 48 optimal switching timings covering the entire spatial voltage vector plane are obtained; Ignoring the effect of parasitic resistance on the inductor, the current ripple expression satisfies , where U e represents the basic voltage vector of the parallel converter, U ref represents the reference voltage vector of the parallel converter; ∆t represents the duration of a certain vector in the switching cycle; U rip represents the voltage error vector; Based on the principle of minimum voltage synthesis error, it is necessary to use the basic voltage vector synthesis of the adjacent reference voltage vector as much as possible. For the switching timing with overlapping linear modulation area, the boundary line of the overlapping area is obtained by calculating the effective value of the current ripple switching period; each large sector is divided into 8 sub-sectors ①~⑧, and sub-sectors ①~⑧ correspond to the switching timing Sqx1~Sqx8 one by one, x is Ⅰ~Ⅵ, sector ① adopts the switching timing Sqx1, sector ② adopts the switching timing Sqx2, sector ③ adopts the switching timing Sqx3, and so on, so as to obtain 48 optimal switching timings covering the entire spatial voltage vector plane.

4. The modulation method of a parallel converter according to claim 3, characterized in that: In step 3, the three-phase switch duty ratio is calculated according to the vector synthesis principle and the switch timing, and the three-phase switch duty ratios of the 48 sub-sectors are normalized. The specific method is: (1) According to the vector synthesis principle, the three basic voltage vectors of each optimal switching timing are used to synthesize the reference voltage vector, and the duty cycle of the basic voltage vector is calculated: ； Among them, u a 、u b and u c Respectively represent the A, B and C phase voltages of the reference voltage vector; u α and u β Represents the component of the reference voltage vector in the two-phase stationary coordinate system; V Xα and V Xβ Represents the basic voltage vector V X Component in the two-phase stationary coordinate system; V Yα and V Yβ Represents the basic voltage vector V Y Component in the two-phase stationary coordinate system; V Zα and V Zβ Represents the basic voltage vector V Z The component in the two-phase stationary coordinate system; d X ,d Y and d Z Represents the basic voltage vector V X 、V Y and V Z The corresponding duty cycle; (2) Obtaining the three-phase switch duty ratio of the first converter and the three-phase switch duty ratio of the second converter in the 48 sub-sectors according to the duty ratio of the basic voltage vector and each optimal switch timing; The duty ratio of the three-phase switches in each sub-sector of sector I is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; The duty ratio of the three-phase switches in each sub-sector of sector II is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; The duty ratio of the three-phase switches in each sub-sector of sector III is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; The duty ratio of the three-phase switches in each sub-sector of sector IV is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; The duty ratio of the three-phase switches in each sub-sector of sector V is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; The duty ratio of the three-phase switches in each sub-sector of sector VI is: ① / ③ / ⑤ / ⑦: ,② / ④ / ⑥ / ⑧: ; u a * 、u b * and u c * Indicated by DC bus voltage V DC The three-phase voltage per unit value is the reference; (3) Normalize the three-phase switch duty ratios of the sub-sectors in each sector of the two converters: ， ； Where, d a1 d b1 d c1 d a2 d b2 d c2 is the normalized three-phase switch duty cycle, where d a1 d b1 d c1 Corresponding to the first converter, d a2 d b2 d c2 For the second converter, u max 、u mid and u min for u a * 、u b * and u c * The maximum, middle, and minimum values ​​of .

5. A control system for a three-phase motor driver in multiple working states, implementing the modulation method of a parallel converter as described in any one of claims 1 to 4 to achieve modulation of the parallel converter.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the modulation method of the parallel converter according to any one of claims 1 to 4 is implemented to realize the modulation of the parallel converter.

7. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the modulation method of the parallel converter according to any one of claims 1 to 4 is implemented to achieve modulation of the parallel converter.

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