Memory system and operating method thereof, memory controller, and readable storage medium

Abstract

The present disclosure provides a memory system and an operating method thereof, a memory controller and a readable storage medium. The memory system comprises at least one non-volatile storage device and a memory controller coupled to the non-volatile storage device; the memory controller is configured to check whether a logical address corresponding to a host read command is saved in a write buffer; determine a level of a drift corresponding to the logical address not saved in the write buffer; the read voltage corresponding to the drift of different levels is different; send a read command to the non-volatile storage device according to the level of the drift corresponding to the logical address; wherein at least two of the processes of checking whether the logical address is saved, determining the level of the drift and sending the read command are executed in parallel.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to memory systems and methods of operating them, memory controllers, and readable storage media. Background Technology

[0002] The threshold voltage of a memory cell drifts over time. That is, after writing data to a memory cell, the threshold voltage drift varies with the time elapsed, resulting in different read voltages. Performing read commands directly on the memory without considering this threshold voltage drift may lead to read command failures, thus reducing the reliability of the stored data. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a memory system and a method of operating the same, a memory controller, and a readable storage medium.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a memory system, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller being configured to:

[0006] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0007] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0008] A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0009] In some embodiments, the processes of checking whether the logical address is saved, determining the level of drift, and sending a read command are all executed in parallel; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; wherein,

[0010] The first processor is configured to: check whether the logical address corresponding to the host read command is stored in the write buffer, and submit the logical address not stored in the write buffer to the first submission queue;

[0011] The first on-chip memory is configured to store the first submission queue;

[0012] The second processor is configured to: determine the level of drift corresponding to each logical address in the first submission queue, and submit the level of drift corresponding to each logical address to the second submission queue;

[0013] The second on-chip memory is configured to store the second submission queue;

[0014] The third processor is configured to send a read command to the non-volatile memory device according to the level of drift corresponding to each logical address in the second submission queue;

[0015] At any given time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0016] In some embodiments, the second processor is specifically configured as follows:

[0017] Based on the heat of the data corresponding to each logical address in the first submission queue, the level of drift corresponding to each logical address is determined; the heat of the data characterizes the length of the average time difference between data writing and reading.

[0018] In some embodiments, the heat of the data includes hot data, warm data, and cold data; the average time difference between writing and reading the hot data, the warm data, and the cold data increases sequentially.

[0019] The second processor is specifically configured as follows:

[0020] When the data corresponding to the logical address is hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount; when the data corresponding to the logical address is warm data, the drift amount corresponding to the logical address is determined to be the second-level drift amount; when the data corresponding to the logical address is cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0021] In some embodiments, the second processor is specifically configured as follows:

[0022] The order of the logical addresses in the second submission queue is determined based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address in the second submission queue.

[0023] In some embodiments, the second processor is specifically configured as follows:

[0024] By querying the mapping table, the popularity of the data corresponding to each logical address in the first submission queue is determined.

[0025] In some embodiments, the third processor is specifically configured as follows:

[0026] Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device;

[0027] A read command is sent to the non-volatile memory device based on the read voltage used to perform the read command operation.

[0028] In some embodiments, the third processor is specifically configured to: submit the logical address of the read command to the read completion queue when the read of the non-volatile memory device is successful; and submit the logical address of the read command to the write completion queue when the read of the non-volatile memory device fails.

[0029] The second on-chip memory is further configured to store the read completion queue and the write completion queue;

[0030] The second processor is also configured to: redetermine the level of drift corresponding to each logical address in the write completion queue.

[0031] In some embodiments, during the nth time interval, the first processor is configured to: check in the (n+1)th round whether the logical address is stored in the write buffer; the second processor is configured to: determine in the nth round the level of the drift corresponding to the logical address in the first commit queue; and the third processor is configured to: send a read command corresponding to the level of the drift of the logical address in the second commit queue in the (n-1)th round; where n is a positive integer.

[0032] In some embodiments, the first processor is specifically configured to: return the data corresponding to the logical address when the logical address corresponding to the read command is stored in the write buffer;

[0033] The first on-chip memory is also configured to store the returned data.

[0034] In some embodiments, both the first on-chip memory and the second on-chip memory include dynamic random access memory or static random access memory.

[0035] In some embodiments, the memory system includes storage-class memory; the non-volatile memory device includes phase-change memory.

[0036] In a second aspect, embodiments of this disclosure provide a memory controller coupled to at least one non-volatile memory device; the memory controller is configured to:

[0037] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0038] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0039] A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0040] Thirdly, embodiments of this disclosure provide an operation method for a memory system, the memory system comprising: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the operation method comprising:

[0041] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0042] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0043] A read command is sent to the non-volatile memory device according to the level of drift corresponding to the logical address; wherein at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0044] In some embodiments, the processes of checking whether the logical address is saved, determining the level of drift, and sending a read command are all executed in parallel; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; the operation method includes:

[0045] The first processor checks whether the logical address corresponding to the host read command is stored in the write buffer, and submits the logical address that is not stored in the write buffer to the first submission queue.

[0046] The first on-chip memory stores the first submission queue;

[0047] The second processor determines the level of the drift amount corresponding to each logical address in the first submission queue, and submits the level of the drift amount corresponding to each logical address to the second submission queue;

[0048] The second on-chip memory stores the second submission queue;

[0049] The third processor sends a read command to the non-volatile memory device according to the level of drift corresponding to each logical address in the second submission queue;

[0050] At any given time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0051] In some embodiments, before the second processor determines the level of the drift amount corresponding to each logical address in the first submission queue and submits the level of the drift amount corresponding to each logical address to the second submission queue, the operation method further includes:

[0052] The second processor determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue; the heat of the data characterizes the length of the average time difference between writing and reading the data.

[0053] In some embodiments, the heat of the data includes hot data, warm data, and cold data; the average time difference between writing and reading the hot data, the warm data, and the cold data increases sequentially.

[0054] The second processor determines the drift level corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, including:

[0055] When the data corresponding to the logical address is hot data, the second processor determines the drift amount corresponding to the logical address as a first-level drift amount; when the data corresponding to the logical address is warm data, the second processor determines the drift amount corresponding to the logical address as a second-level drift amount; when the data corresponding to the logical address is cold data, the second processor determines the drift amount corresponding to the logical address as a third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0056] In some embodiments, the operating method further includes:

[0057] The second processor determines the order of the logical addresses in the second submission queue based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address in the second submission queue.

[0058] In some embodiments, before the second processor determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, the operation method further includes:

[0059] The second processor determines the popularity of the data corresponding to each logical address in the first submission queue by querying the mapping table.

[0060] In some embodiments, the third processor sends a read command to the non-volatile memory device according to the drift level corresponding to each logical address in the second submission queue, including:

[0061] The third processor determines the read voltage for performing read command operations on the non-volatile memory device based on the level of drift corresponding to each logical address in the second submission queue.

[0062] The third processor sends a read command to the non-volatile memory device based on the read voltage used to perform the read command operation on the non-volatile memory device.

[0063] In some embodiments, after the third processor sends a read command to the non-volatile memory device according to the drift level corresponding to each logical address in the second submission queue, the operation method further includes:

[0064] When the third processor successfully reads the non-volatile memory device, it submits the logical address of the read command to the read completion queue; and when the read of the non-volatile memory device fails, it submits the logical address of the read command to the write completion queue.

[0065] The second on-chip memory stores the read completion queue and the write completion queue;

[0066] The second processor re-determines the level of drift corresponding to each logical address in the write completion queue.

[0067] Fourthly, embodiments of this disclosure provide a readable storage medium storing a computer program, which, when executed, can implement the operation method of the memory system as described in the above technical solutions.

[0068] This disclosure provides a memory system and its operation method, a memory controller, and a readable storage medium. In this disclosure, the memory system includes at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device. The memory controller is configured to send a read command to the non-volatile memory device based on the level of drift corresponding to a logical address. Thus, the read voltage for performing the read command operation on the non-volatile memory device can be determined based on the level of drift corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system.

[0069] Furthermore, in this embodiment of the present disclosure, at least two processes are executed in parallel during the process of checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address that is not stored in the write buffer, and sending the read command according to the level of the drift amount corresponding to the logical address. This can optimize the read latency and improve the read efficiency. Attached Figure Description

[0070] Figure 1 A block diagram of a memory system provided in an embodiment of this disclosure;

[0071] Figure 2 A flowchart illustrating the operation method of the memory system provided in this embodiment of the disclosure;

[0072] Figure 3 A flowchart illustrating an operation method for a memory system provided in an embodiment of this disclosure;

[0073] Figure 4 A schematic diagram showing the logical addresses corresponding to the first processor, the second processor, and the third processor during the nth time interval of the operation method of the memory system provided in this embodiment of the present disclosure;

[0074] Figure 5 A block diagram of a readable storage medium provided in embodiments of this disclosure;

[0075] Figure 6 A block diagram of a memory controller provided in an embodiment of this disclosure;

[0076] Figure 7 A block diagram of a system provided in an embodiment of this disclosure. Detailed Implementation

[0077] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0078] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0079] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0080] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0081] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0082] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0083] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0084] As mentioned earlier, threshold voltage drift can lead to read margin loss and uncorrectable error correction code (UECC).

[0085] In view of the above, embodiments of the present disclosure provide a memory system and a method of operating the same, a memory controller, and a readable storage medium.

[0086] refer to Figure 1 and Figure 2 , Figure 1 This is a block diagram of a memory system provided in an embodiment of the present disclosure. Figure 2 This is a flowchart illustrating the operation method of a memory system provided in an embodiment of this disclosure. Figure 1 and Figure 2As shown, this disclosure provides an operation method for a memory system 100, which includes: at least one non-volatile memory device 110 and a memory controller 120 coupled to the non-volatile memory device 110; the operation method includes:

[0087] Step S201: Check whether the logical address corresponding to the host read command is stored in the write buffer;

[0088] Step S202: Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0089] Step S203: Send a read command to the non-volatile memory device according to the level of the drift amount corresponding to the logical address; wherein, at least two processes are executed in parallel during the process of checking whether the logical address is saved, determining the level of the drift amount and sending the read command.

[0090] In this embodiment of the present disclosure, in step S201, the host sends a read command to the memory controller 120. After receiving the read command sent by the host, the memory controller 120 checks whether the logical address (Logical Block Address, LBA) corresponding to the read command is stored in the write buffer, that is, checks whether the logical address corresponding to the read command is available in the write buffer.

[0091] In some embodiments, if the logical address corresponding to the read command is stored in a write buffer, the data corresponding to that logical address can be retrieved from the write buffer. Here, the write buffer can be located within the host. When the logical address corresponding to the read command is stored in the write buffer, the data corresponding to that logical address can be retrieved from the write buffer, and the access distance to retrieve the data corresponding to that logical address is relatively short.

[0092] In some embodiments, if the logical address corresponding to the read command is not stored in the write buffer, the data corresponding to the logical address can be obtained from the non-volatile memory device 110. Here, when the logical address corresponding to the read command is not stored in the write buffer, the data corresponding to the logical address can be obtained from the non-volatile memory device 110 through the memory controller 120, but the access distance to obtain the data corresponding to the logical address is relatively long.

[0093] In this embodiment of the present disclosure, in step S202, for logical addresses not stored in the write buffer, considering the different drift amounts of the threshold voltages of different memory cells, the level of the drift amount corresponding to the logical address not stored in the write buffer is determined. Different levels of drift amount correspond to different read voltages, and in subsequent steps, the read voltage for performing read command operations on the non-volatile memory device 110 can be determined based on the drift amount level.

[0094] In this embodiment of the present disclosure, in step S203, a read command is sent to the non-volatile memory device 110 according to the level of drift corresponding to the logical address. Thus, the read voltage for performing the read command operation on the non-volatile memory device 110 can be determined based on the level of drift corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system 100.

[0095] In this embodiment, steps S201, S202, and S203 can be executed in a pipeline manner. Specifically, in step S201, it is checked whether the logical address corresponding to the host read command is stored in the write buffer. Depending on whether the logical address is stored in the write buffer, different steps are executed subsequently. For logical addresses not stored in the write buffer, step S202 continues. In other words, for a fixed logical address, if step S201 is executed and the logical address is not stored in the write buffer, step S202 can be executed for that logical address. In step S202, the drift level corresponding to the logical address not stored in the write buffer is determined, and step S203 continues. That is, for a fixed logical address, if step S202 is executed and the drift level corresponding to the logical address is determined, step S203 can be executed for that logical address. In step S203, a read command is sent to the non-volatile memory device 110 according to the drift level corresponding to the logical address. In other words, for a fixed logical address, step S203 is executed, and a read command is sent to the non-volatile memory device 110 according to the level of drift corresponding to the logical address.

[0096] It should be noted that for a fixed logical address, steps S201, S202, and S203 are executed in a pipelined manner, that is, sequentially. However, for multiple logical addresses, steps S201, S202, and S203 can be executed in parallel. This is because the time spent executing steps S201, S202, and S203 is different. For example, for two logical addresses, namely a first logical address and a second logical address, steps S201, S202, and S203 can be executed sequentially for the first logical address, while step S201 can be executed for the second logical address simultaneously with step S202. In other words, there is no need to wait for the first logical address to complete steps S201, S202 and S203 before executing step S201 on the second logical address; at the same time, the logical addresses corresponding to the execution of steps S201, S202 and S203 are different.

[0097] In this embodiment of the disclosure, at least two processes are executed in parallel during the process of checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address not stored in the write buffer, and sending the read command. This can optimize the read latency and improve the read efficiency.

[0098] It should be noted that at least two processes in the steps of checking whether the logical address is saved, determining the level of drift, and sending the read command are executed in parallel, including three cases. In the first case, steps S201 and S202 are combined; that is, one processor executes steps S201 and S202 sequentially in a serial manner, while another processor executes step S203. In this case, the processing of steps S201 and S202 is executed in parallel with the processing of step S203. This can save reading time to a certain extent, optimize reading latency, and improve reading efficiency.

[0099] In the second case, step S201 is executed using one processor; steps S202 and S203 are combined, that is, steps S202 and S203 are executed sequentially using another processor. In this case, the processing of step S201 is executed in parallel with the processing of steps S202 and S203. This can save reading time to some extent, optimize reading latency, and improve reading efficiency.

[0100] In the third case, steps S201, S202, and S203 are executed using three processors respectively. In this case, the processing of steps S201, S202, and S203 is performed in parallel. This further saves reading time, optimizes reading latency, and improves reading efficiency.

[0101] The following is for reference. Figure 3 , Figure 3 A flowchart illustrating an operation method of a memory system provided in an embodiment of this disclosure. (In conjunction with...) Figure 1 and Figure 3 As shown, this paper explains in detail how the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command are all executed in parallel.

[0102] like Figure 1 and Figure 3 As shown, in some embodiments, the processes of checking whether the logical address is saved, determining the level of drift, and sending a read command are all executed in parallel; the memory controller 120 includes: a first processor 121, a second processor 122, a third processor 123, a first on-chip memory 124, and a second on-chip memory 125; the above operation method includes:

[0103] The first processor 121 checks whether the logical address corresponding to the host read command is stored in the write buffer, and submits the logical address that is not stored in the write buffer to the first submission queue.

[0104] The first on-chip memory 124 stores the first submission queue;

[0105] The second processor 122 determines the level of the drift amount corresponding to each logical address in the first submission queue, and submits the level of the drift amount corresponding to each logical address to the second submission queue.

[0106] The second on-chip memory 125 stores the second submission queue;

[0107] The third processor 123 sends a read command to the non-volatile memory device 110 according to the level of drift corresponding to each logical address in the second submission queue;

[0108] At the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0109] like Figure 3 As shown, in step S301, the host dispatch task is performed, that is, the host sends a read command. The execution entity of step S301 is the host.

[0110] In step S302, it is checked whether the logical address corresponding to the host read command is stored in the write buffer. If the result of step S302 is "no", that is, the logical address corresponding to the host read command is not stored in the write buffer, then step S303 is executed; if the result of step S302 is "yes", that is, the logical address corresponding to the host read command is stored in the write buffer, then step S304 is executed.

[0111] In other words, in step S302, it is checked whether the logical address corresponding to the host read command and the logical address in the write buffer overlap (Read LBA overlap check). If the logical address corresponding to the host read command and the logical address in the write buffer do not overlap (Writer Buffer Miss), that is, the logical address corresponding to the host read command is not stored in the write buffer, then step S303 is executed; if the logical address corresponding to the host read command and the logical address in the write buffer overlap (Writer Buffer Hit), that is, the logical address corresponding to the host read command is stored in the write buffer, then step S304 is executed.

[0112] In this embodiment of the disclosure, the main body executing step S302 is the first processor 121 (i.e., Core 1), which is located within the memory controller 120.

[0113] In step S303, logical addresses not stored in the write buffer are submitted to the first submission queue. The first submission queue is stored in the first on-chip memory (OCM) 124, which is located within the memory controller 120. In other words, the first submission queue can also be called a filtered submission queue, that is, logical addresses not stored in the write buffer are filtered out to form a filtered submission queue.

[0114] In this embodiment of the present disclosure, the first processor 121 returns the data corresponding to the logical address when the logical address corresponding to the read command is stored in the write buffer; the first on-chip memory 124 stores the returned data.

[0115] In step S304, for a logical address stored in the write buffer, the data corresponding to the logical address can be returned, completing the data reading process for the logical address. The data corresponding to the logical address stored in the write buffer is stored in the first on-chip memory 124.

[0116] In step S305, the drift level corresponding to each logical address in the first submission queue is determined, that is, the drift level (Predicate DriftLevel) corresponding to each logical address in the first submission queue is predicted (or calculated), and the drift level corresponding to each logical address is submitted to the second submission queue.

[0117] In this embodiment of the disclosure, the main body executing step S305 is the second processor 122 (i.e., Core 2), which is located within the memory controller 120.

[0118] The following section will explain in detail how to determine the drift level corresponding to each logical address in the first commit queue.

[0119] In some embodiments, before the second processor 122 determines the level of the drift amount corresponding to each logical address in the first submission queue and submits the level of the drift amount corresponding to each logical address to the second submission queue, the above operation method further includes:

[0120] The second processor 122 determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue; the heat of the data represents the length of the average time difference between data writing and reading.

[0121] Here, the drift level for each logical address is determined based on the "heat" of the data corresponding to each logical address in the first commit queue, specifically the length of the time difference between writing and reading the data at each logical address. A shorter time difference between writing and reading the data at a logical address indicates higher "heat" of the data; correspondingly, the threshold voltage drift of the storage unit used to store this high-heat data is smaller. Conversely, a longer time difference between writing and reading the data at a logical address indicates lower "heat" of the data; correspondingly, the threshold voltage drift of the storage unit used to store this low-heat data is larger.

[0122] In this embodiment of the disclosure, based on the heat of the data corresponding to each logical address in the first submission queue, and considering the different drift amounts of the threshold voltage of the storage cell used to store this data, different read voltages are applied when performing read command operations on the non-volatile storage device, thereby ensuring the correctness of the read command operations and improving the reliability of the memory system.

[0123] In some embodiments, before the second processor 122 determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, the above operation method further includes:

[0124] The second processor 122 determines the heat of the data corresponding to each logical address in the first submission queue by querying the mapping table.

[0125] In this embodiment of the disclosure, the mapping table includes at least one of the following: a Bloom filter, a Cuckoo filter, an XOR filter, a vacuum filter, and a hash table. This embodiment of the disclosure does not impose any special limitation on the type of mapping table; any mapping table that can be used to query the popularity of data corresponding to a logical address can be applied to the operation method of the memory system provided in this embodiment of the disclosure.

[0126] Specifically, data can be categorized into hot data, warm data, and cold data based on the length of the time difference between writing and reading. Hot data has the shortest time difference between writing and reading, followed by warm data, and cold data has the longest time difference between writing and reading; the time difference between writing and reading increases sequentially from hot data to warm data to cold data.

[0127] For example, the time difference between writing and reading for hot data ranges from 1 microsecond to 2 milliseconds; the time difference between writing and reading for warm data ranges from 1 millisecond to 2 seconds; and the time difference between writing and reading for cold data ranges from 1 second to several hours.

[0128] It should be noted that the write and read time differences for hot, warm, and cold data can overlap. For data whose write and read time differences are not overlapping, the determination of its "hotness" is unique. For example, data with a write and read time difference between 1 microsecond and 1 millisecond can be identified as hot data; data with a write and read time difference between 2 milliseconds and 1 second can be identified as warm data; and data with a write and read time difference exceeding 2 seconds can be identified as cold data. However, for data with overlapping write and read time differences, the determination of its "hotness" is not unique. For example, data with a write and read time difference between 1 millisecond and 2 milliseconds can be identified as either hot or warm data. Data with a write and read time difference between 1 second and 2 seconds can be identified as either warm or cold data. Therefore, the "hotness" of data characterizes the length of the average write and read time difference.

[0129] It is understandable that when there is an overlapping area between the write and read times of hot data, warm data, and cold data, these overlapping areas are all located at the boundary between the two types of data. The read voltage actually has a certain window; for data in the overlapping area, both drift levels corresponding to the two types of data can be applied, and the read voltage corresponding to both drift levels can also be applied.

[0130] In some embodiments, the second processor 122 determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, including:

[0131] When the data corresponding to the logical address is hot data, the second processor 122 determines the drift amount corresponding to the logical address as the first-level drift amount; when the data corresponding to the logical address is warm data, the second processor 122 determines the drift amount corresponding to the logical address as the second-level drift amount; when the data corresponding to the logical address is cold data, the second processor 122 determines the drift amount corresponding to the logical address as the third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0132] As mentioned earlier, the threshold voltage drift of storage cells used to store hot data is the smallest, followed by those used to store warm data, and the threshold voltage drift of storage cells used to store cold data is the largest. Thus, based on the different temperatures of the data stored in the storage cells, the threshold voltage drift of each storage cell can be determined to be different. Subsequently, based on these different threshold voltage drifts, different read voltages can be applied when performing read command operations on these storage cells.

[0133] In some embodiments, the above-described operation method further includes:

[0134] The second processor 122 determines the order of logical addresses in the second submission queue based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address order in the second submission queue.

[0135] Here, the logical addresses in the first commit queue are in an unordered state; that is, the order of hot, warm, and cold data corresponding to logical addresses in the first commit queue is random. In other words, a logical address can be committed to the first commit queue as long as it is determined that it is not stored in the write buffer. Therefore, the order of the logical addresses in the first commit queue corresponds to the moment when it is determined that a logical address is not stored in the write buffer. The "hotness" of the data corresponding to the logical addresses not stored in the write buffer is randomly distributed. Without considering the order of hot, warm, and cold data corresponding to logical addresses in the first commit queue, the drift level corresponding to each logical address in the first commit queue is determined sequentially to obtain the second commit queue; read command operations are then performed on each logical address in the second commit queue sequentially.

[0136] It's important to note that the write and read time difference for hot data is extremely short (i.e., 1 microsecond to 2 milliseconds). If the hot data corresponding to a logical address in the first commit queue is ranked low (i.e., operations on the hot data corresponding to that logical address have a lower priority), then the process waits until the drift level of the hot data corresponding to that logical address in the first commit queue is determined, and further waits before a read command operation can be performed on that hot data. In other words, the time to operate on the hot data corresponding to that logical address may exceed the timeliness requirement of the hot data. Therefore, the ranking of logical addresses in the second commit queue can be determined based on the popularity of the data corresponding to each logical address in the first commit queue; the higher the popularity of the data corresponding to a logical address in the first commit queue, the higher the ranking of the logical address in the second commit queue, and the higher the priority of read command operations on that logical address. In this way, the process of performing read command operations on hot data can be accelerated, meeting the timeliness requirements of hot data.

[0137] In step S306, the level of drift corresponding to each logical address is submitted to the second submission queue. The second submission queue is stored in the second on-chip memory 125, which is located within the memory controller 120. In other words, the second submission queue can also be called the Preficted Submission Queue, which predicts the level of drift corresponding to each logical address to form the predictive submission queue.

[0138] In step S307, a read command is sent to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue. If the read is successful, step S308 is executed; if the read fails, step S309 is executed.

[0139] Specifically, the third processor 123 sends a read command to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue, including:

[0140] The third processor 123 determines the read voltage for performing a read command operation on the non-volatile memory device 110 based on the level of drift corresponding to each logical address in the second submission queue.

[0141] The third processor 123 sends a read command to the non-volatile memory device 110 based on the read voltage for performing a read command operation on the non-volatile memory device 110.

[0142] In this embodiment of the disclosure, the main body executing step S307 is the third processor 123, which is located within the memory controller 120. In other words, the third processor 123 can also be called a storage media controller (Media Controller). The storage media controller is located within the memory controller 120, coupled to the non-volatile storage device 110, and is used to control the non-volatile storage device 110.

[0143] In some embodiments, after the third processor 123 sends a read command to the non-volatile memory device 110 according to the drift level corresponding to each logical address in the second submission queue, the above operation method further includes:

[0144] When the third processor 123 successfully reads from the non-volatile memory device 110, it submits the logical address of the read command to the read completion queue; and when the read from the non-volatile memory device 110 fails, it submits the logical address of the read command to the write completion queue.

[0145] The second on-chip memory 125 stores the Complete Queue of Read and the Complete Queue of Write;

[0146] The second processor 122 redetermines the level of drift corresponding to each logical address in the write completion queue.

[0147] In step S308, when the non-volatile memory device 110 is successfully read, the logical address corresponding to the read command is submitted to the read completion queue. The read completion queue is stored in the second on-chip memory 125, which is located within the memory controller 120.

[0148] In step S309, when a read operation on the non-volatile memory device 110 fails, the logical address corresponding to the read command is submitted to the write completion queue. For each logical address in the write completion queue, step S305 is executed again to redetermine the drift level corresponding to each logical address in the write completion queue. The write completion queue is stored in the second on-chip memory 125, which is located within the memory controller 120.

[0149] For example, the second processor 122 can determine whether the data corresponding to each logical address in the first submission queue is warm or cold data by querying a Bloom filter. However, the accuracy of querying the Bloom filter is not 100%, meaning there may be a false positive rate. In other words, the second processor 122 determines that the data corresponding to a logical address in the first submission queue is warm (or cold) data by querying the Bloom filter, but in reality, the data corresponding to that logical address is cold (or warm). Further, based on the "warmth" of the data corresponding to the logical address, the level of the drift amount corresponding to the logical address is determined, and subsequently, the read voltage is determined based on the level of the drift amount corresponding to the logical address. Since the result of determining the "warmth" of the data corresponding to the logical address in the first submission queue is incorrect, the result of determining the level of the drift amount corresponding to the logical address based on the "warmth" of the data corresponding to the logical address is also incorrect, and the result of determining the read voltage based on the level of the drift amount corresponding to the logical address is also incorrect. Using an incorrect read voltage to perform read command operations may lead to read failure. Therefore, it is necessary to re-determine the level of the drift amount corresponding to the logical address of these read command operations that failed.

[0150] In this embodiment, the algorithm design of the memory controller 120 can be optimized without increasing costs, i.e., without adding hardware. The read voltage for performing read command operations on the non-volatile memory device 110 can be determined based on the drift amount corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system. Furthermore, by performing the processes of checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address not stored in the write buffer, and sending the read command in parallel, the read latency can be optimized and the read efficiency can be improved.

[0151] refer to Figure 4 , Figure 4 This is a schematic diagram showing the logical addresses of the first processor, the second processor, and the third processor during the nth time interval of the operation method of the memory system provided in the embodiments of this disclosure.

[0152] Figure 4Steps S201, S202, and S203 are illustrated, separated by dashed lines. The first processor executes step S201, the second processor executes step S202, and the third processor executes step S203.

[0153] Specifically, the first processor executes step S201, checking whether the logical address corresponding to the host read command is stored in the write buffer, and submitting the logical addresses not stored in the write buffer to the first commit queue. That is, if each logical address in the first commit queue is not stored in the write buffer, the first processor filters out the logical addresses corresponding to the host read command that are not stored in the write buffer. For example, the first processor can check a total of 20 logical addresses in each time interval and submit the logical addresses not stored in the write buffer to the first commit queue.

[0154] It should be noted that multiple logical addresses in the first submission queue are in an unordered state; that is, the order of hot data, warm data, and cold data corresponding to logical addresses in the first submission queue is irregular.

[0155] Specifically, the second processor executes step S202, determining the level of the drift amount corresponding to each logical address in the first submission queue, and submitting the level of the drift amount corresponding to each logical address to the second submission queue. For example, the second processor can determine (or calculate) the drift amount levels corresponding to a total of 5 logical addresses within each time interval. That is, the number of logical addresses processed by the first processor and the second processor can be different within the same time interval.

[0156] Specifically, the third processor is used to execute step S203, which sends a read command to the non-volatile memory device 110 according to the level of drift corresponding to each logical address in the second submission queue.

[0157] In this embodiment of the disclosure, for a fixed logical address, steps S201, S202, and S203 are executed sequentially in a pipelined manner. However, for multiple logical addresses, within the nth time interval, the first processor performs the (n+1)th round to check whether the logical address is stored in the write buffer; the second processor performs the nth round to determine the drift level corresponding to the logical address in the first commit queue; and the third processor performs the (n-1)th round to send the read command corresponding to the drift level of the logical address in the second commit queue; where n is a positive integer. That is, steps S201, S202, and S203 are executed in parallel, and at the same time, the logical addresses processed by steps S201, S202, and S203 are different.

[0158] It should be noted that each step in steps S201, S202, and S203 has consecutive time intervals, such as the (n-1)th round, the nth round, and the (n+1)th round, with each round's processing time corresponding to a time interval. The specific duration of this time interval can be selected based on actual conditions, taking into account factors such as the time period corresponding to the heat level and the parameters of each processor in the memory controller. For example, the duration of the time interval can be K*160ns, where K can be obtained empirically.

[0159] It should be noted that the number of rounds processed by two adjacent steps in the same time interval must differ by at least one round. For example, such as Figure 4 As shown, in the nth time interval, step S201 processes the (n+1)th round, step S202 processes the nth round, and step S203 processes the (n-1)th round. Of course, the number of rounds processed by two adjacent steps in the same time interval can differ by several rounds. For example, in the nth time interval, step S201 processes the (n+3)th round, step S202 processes the nth round, and step S203 processes the (n-3)th round. That is, the processing results obtained by step S201 for the (n+1)th and (n+2)th rounds can be stored in the first on-chip memory. It should be noted that when the number of rounds processed by two adjacent steps in the same time interval differs by one round, the intermediate results stored in the first and second on-chip memories are fewer. After step S201 completes the nth round, it provides the processing result to step S202. This makes the transitions between steps more compact, saving time and improving efficiency. It is understandable that for a fixed logical address, the execution steps S201, S202 and S203 are executed serially, but for multiple logical addresses, the execution steps S201, S202 and S203 are executed in parallel.

[0160] In this embodiment of the disclosure, the memory system 100 may include storage class memory (SCM); the non-volatile storage device 110 may include phase change memory (PCM).

[0161] In the existing storage hierarchy, there is a gap in storage speed and capacity between Dynamic Random Access Memory (DRAM) and non-volatile storage devices (e.g., NAND flash memory), limiting further improvements in computing power. To address this, a storage-level memory is proposed that places storage speed and capacity between DRAM and non-volatile memory. For example, the storage densities of DRAM, PCM, and NAND can be 1X, 1X to 4X, and 4X, respectively; the read latency of DRAM, PCM, and NAND can be 50 nanoseconds, 50 to 100 nanoseconds, and 10 to 25 microseconds, respectively; and the write latency of DRAM, PCM, and NAND can be 20 to 50 nanoseconds, 1 microsecond, and 100 microseconds, respectively. It can be seen that the storage speed (read latency and write latency) and storage capacity (storage density) of PCM allow it to occupy a good position between DRAM and non-volatile memory, serving as an intermediate memory.

[0162] Currently, there are many types of storage media for storage-class memory, with the most mainstream including phase-change memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), and carbon nanotube random access memory (Nantero's CNT Random Access Memory (NRAM).

[0163] The basic principle of phase-change memory (PCM) is as follows: A short-duration electrical pulse with a large signal value is applied to the PCM cell. Under Joule heating, a portion of the initially crystalline PCM layer melts because its temperature exceeds the melting point. After the pulse is interrupted, the molten portion cools rapidly and remains in an amorphous state with low atomic order, thus completing the transition from low resistance to high resistance—this is the reset process. The molten portion in this process is called the programming volume. If a short-duration electrical pulse with a small signal value is applied, causing the temperature within the programming volume to reach above the crystallization temperature but below the melting point, and this is sustained for a sufficient time for the amorphous structure within the programming volume to crystallize, a low-resistance state is obtained—this is the set process. The read process of PCM involves applying a short-duration electrical pulse to the PCM cell, keeping the PCM layer below the crystallization temperature, and measuring the resistance of the PCM cell.

[0164] As the storage medium of phase change memory (PDM), the performance of phase change memory materials directly affects the characteristics of the device. Typically, the characteristics of PDM are mainly measured by indicators such as write operation speed, data retention capability, and on / off ratio. Therefore, research on the performance of PDM materials includes studies on parameters such as crystallization rate, crystallization temperature, amorphous structure stability, thermal stability, and resistivity window (i.e., the ratio of resistivity of the amorphous state to that of the crystalline state).

[0165] For phase-change memory (PCM), the write operation generally takes the longest time among the write, erase, and read operations, becoming a key factor limiting the high-speed operation of PCM. The write operation time is related to the crystallization rate of the PCM material. The faster the crystallization rate, the shorter the write operation time, and the faster the PCM operation speed.

[0166] The data retention capability of phase change memory (PCM) depends on the amorphous structure stability and thermal stability of the PCM material. Better amorphous structure stability and thermal stability result in longer data retention. To achieve better amorphous structure stability and thermal stability, the PCM material needs to have a higher crystallization temperature.

[0167] The on / off ratio of a phase-change memory (PCM) is determined by the resistance window of the PCM material. The resistance window refers to the resistivity difference between the amorphous and crystalline states. A larger resistivity difference between the amorphous and crystalline states results in a larger resistance window, ensuring a higher on / off ratio and enabling accurate and rapid data reading during operations.

[0168] In this embodiment of the disclosure, both the first on-chip memory 124 and the second on-chip memory 125 include dynamic random access memory or static random access memory (SRAM).

[0169] In this embodiment, the first on-chip memory 124 is used to store the intermediate results of step S201, including a first submission queue and data corresponding to logical addresses stored in a write buffer; the second on-chip memory 125 is used to store the intermediate results of step S202, including a second submission queue, a write completion queue, and a read completion queue. By executing steps S201, S202, and S203 in parallel, the efficiency of reading from the non-volatile storage device 110 can be accelerated, thereby minimizing the storage capacity of the first on-chip memory 124 and the second on-chip memory 125 used to store these intermediate results.

[0170] refer to Figure 5 , Figure 5 A block diagram of a readable storage medium provided in embodiments of this disclosure. (See diagram below.) Figure 5As shown, this disclosure provides a readable storage medium 200 storing a computer program 210. When executed, the computer program 210 can implement the memory system operation method described in the above technical solution. The operation method includes: checking whether the logical address corresponding to a host read command is stored in a write buffer; determining the level of the drift amount corresponding to the logical address not stored in the write buffer; different levels of drift amount correspond to different read voltages; and sending a read command to the non-volatile memory device according to the level of the drift amount corresponding to the logical address. At least two of the processes—checking whether the logical address is stored, determining the level of the drift amount, and sending the read command—are executed in parallel.

[0171] This disclosure provides an operation method for a memory controller 120, which is coupled to at least one non-volatile memory device 110; the operation method includes:

[0172] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0173] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0174] Based on the level of drift corresponding to the logical address, a read command is sent to the non-volatile storage device 110; wherein, at least two processes, namely checking whether the logical address is saved, determining the level of drift, and sending the read command, are executed in parallel.

[0175] refer to Figure 6 , Figure 6 This is a block diagram of a memory controller provided in an embodiment of this disclosure. Figure 6 As shown, an embodiment of this disclosure provides a memory controller 120, which is connected to at least one non-volatile memory device ( Figure 6 (Not shown in the diagram) Coupling; the memory controller 120 is configured to:

[0176] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0177] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0178] Based on the level of drift corresponding to the logical address, a read command is sent to the non-volatile memory device; among these processes, at least two are executed in parallel: checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0179] Figure 6The memory controller 120 is illustrated to include a first processor 121, a second processor 122, a third processor 123, a first on-chip memory 124, and a second on-chip memory 125. Specifically, the first processor 121 checks whether the logical address corresponding to the host read command is stored in the write buffer, and submits logical addresses not stored in the write buffer to a first commit queue; the first on-chip memory 124 stores the first commit queue; the second processor 122 determines the drift level corresponding to each logical address in the first commit queue and submits the drift level corresponding to each logical address to a second commit queue; the second on-chip memory 125 stores the second commit queue; the third processor 123 sends a read command to the non-volatile memory device according to the drift level corresponding to each logical address in the second commit queue; wherein, at any given time, the logical addresses corresponding to the first commit queue, the second commit queue, and the read command are different.

[0180] In this embodiment of the disclosure, the memory controller can be coupled to both the host and the non-volatile memory device, and is configured to control the non-volatile memory device. The memory controller may include a communication interface, through which it can communicate with the host; the memory controller can also communicate with the non-volatile memory device through another part of the communication interface, for managing data stored in the non-volatile memory device.

[0181] Still referencing Figure 1 As shown, this disclosure provides a memory system 100, which includes at least one non-volatile memory device 110 and a memory controller 120 coupled to the non-volatile memory device 110; the memory controller 120 is configured to:

[0182] Check if the logical address corresponding to the host read command is stored in the write buffer;

[0183] Determine the level of drift corresponding to the logical address not stored in the write buffer; different levels of drift correspond to different read voltages;

[0184] Based on the level of drift corresponding to the logical address, a read command is sent to the non-volatile storage device 110; wherein, at least two processes are executed in parallel during the processes of checking whether the logical address is saved, determining the level of drift, and sending the read command.

[0185] In some embodiments, the processes of checking whether the logical address is saved, determining the level of drift, and sending a read command are all executed in parallel; the memory controller 120 includes: a first processor 121, a second processor 122, a third processor 123, a first on-chip memory 124, and a second on-chip memory 125; wherein,

[0186] The first processor 121 is configured to: check whether the logical address corresponding to the host read command is stored in the write buffer, and submit the logical address that is not stored in the write buffer to the first submission queue;

[0187] The first on-chip memory 124 is configured to store the first submission queue;

[0188] The second processor 122 is configured to: determine the level of the drift amount corresponding to each logical address in the first submission queue, and submit the level of the drift amount corresponding to each logical address to the second submission queue;

[0189] The second on-chip memory 125 is configured to store the second submission queue;

[0190] The third processor 123 is configured to send a read command to the non-volatile memory device 110 according to the level of drift corresponding to each logical address in the second submission queue;

[0191] At the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

[0192] In some embodiments, the second processor 122 is specifically configured as follows:

[0193] Based on the heat of the data corresponding to each logical address in the first submission queue, the level of drift corresponding to each logical address is determined; the heat of the data characterizes the length of the average time difference between data writing and reading.

[0194] In some embodiments, the data heat includes hot data, warm data, and cold data; the average time difference for writing and reading corresponding to hot data, warm data, and cold data increases sequentially.

[0195] The second processor 122 is specifically configured as follows:

[0196] When the data corresponding to the logical address is hot data, the drift amount corresponding to the logical address is determined as the first-level drift amount; when the data corresponding to the logical address is warm data, the drift amount corresponding to the logical address is determined as the second-level drift amount; when the data corresponding to the logical address is cold data, the drift amount corresponding to the logical address is determined as the third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

[0197] In some embodiments, the second processor 122 is specifically configured as follows:

[0198] The order of logical addresses in the second submission queue is determined based on the popularity of the data corresponding to each logical address in the first submission queue; the higher the popularity of the data corresponding to a logical address, the higher the priority of the logical addresses in the second submission queue.

[0199] In some embodiments, the second processor 122 is specifically configured as follows:

[0200] By querying the mapping table, the popularity of the data corresponding to each logical address in the first submission queue is determined.

[0201] In some embodiments, the third processor 123 is specifically configured as follows:

[0202] Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device 110;

[0203] A read command is sent to the non-volatile memory device 110 based on the read voltage used to perform the read command operation on the non-volatile memory device 110.

[0204] In some embodiments, the third processor 123 is specifically configured to: submit the logical address of the read command to the read completion queue when the read of the non-volatile memory device 110 is successful; and submit the logical address of the read command to the write completion queue when the read of the non-volatile memory device 110 fails.

[0205] The second on-chip memory 125 is also configured to store a read completion queue and a write completion queue;

[0206] The second processor 122 is also configured to: redetermine the level of drift corresponding to each logical address in the write completion queue.

[0207] In some embodiments, during the nth time interval, the first processor 121 is configured to: check in the (n+1)th round whether the logical address is stored in the write buffer; the second processor 122 is configured to: determine in the nth round the level of the drift corresponding to the logical address in the first commit queue; and the third processor 123 is configured to: send a read command corresponding to the level of the drift of the logical address in the second commit queue in the (n-1)th round; where n is a positive integer.

[0208] In some embodiments, the first processor 121 is specifically configured to: return the data corresponding to the logical address when the logical address corresponding to the read command is stored in the write buffer;

[0209] The first on-chip memory 124 is also configured to store the returned data.

[0210] In some embodiments, the first on-chip memory 124 and the second on-chip memory 125 both include dynamic random access memory or static random access memory.

[0211] In some embodiments, the memory system 100 includes storage-class memory; the non-volatile storage device 110 includes phase-change memory.

[0212] refer to Figure 7 , Figure 7 A block diagram of a system provided in an embodiment of this disclosure. (See diagram below.) Figure 7 As shown, system 300 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, or any other suitable electronic device having a non-volatile storage device 310 (e.g., PCM).

[0213] like Figure 7 As shown, system 300 may include a host 330 and a memory system, the memory system including a memory controller 320 and at least one non-volatile storage device 310. The host 330 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 330 may be configured to send data to or receive data from the non-volatile storage device 310. Figure 7 The illustration shows the memory controller 320 connected to four non-volatile memory devices 310. In fact, this embodiment of the present disclosure does not impose a special limitation on the number of non-volatile memory devices 310 connected to the memory controller 320. The number of non-volatile memory devices 310 connected to the memory controller 320 may be less than four (e.g., one); or the number of non-volatile memory devices 310 connected to the memory controller 320 may be greater than four (e.g., five).

[0214] In some embodiments, the memory controller 320 may be coupled to the host 330 and the non-volatile storage device 310, respectively, and is configured to control the non-volatile storage device 310. The memory controller 320 may manage the data stored in the non-volatile storage device 310 and communicate with the host 330.

[0215] In one specific example, the memory system may include at least one non-volatile memory device 310 and a memory controller 320 coupled to the non-volatile memory device 310; wherein, the memory system may include storage-class memory; and the non-volatile memory device 310 may include phase-change memory.

[0216] Still referencing Figure 7 As shown, the memory controller 320 includes a first communication interface 321, a second communication interface 322, a processing unit 323, a read-only memory (ROM) 324, a static random access memory (SRAM) 325, and a storage medium controller 326. The processing unit 323 and the host 330 communicate via the first communication interface 321 and the second communication interface 322. The processing unit 323 can also be connected to the storage medium controller 326 to control the storage medium controller 326. The storage medium controller 326 is connected to the non-volatile storage device 310 to control the non-volatile storage device 310. The processing unit 323 can also be connected to the ROM 324 and the SRAM 325. The processing unit 323 can retrieve data from the ROM 324 and can store some temporary data in the SRAM 325.

[0217] In some embodiments, the first communication interface 321 can be a Peripheral Component Interconnect Express (PCIE), that is, the first communication interface can be an interface set according to the high-speed serial computer expansion bus standard; the second communication interface 322 can be a Compute Express Link (CXL).

[0218] In a specific example, a non-volatile memory device may include phase-change memory (PCM). System-level read latency affects the actual throughput of the memory-class system. The threshold voltage of the phase-change material in the PCM within the memory-class system varies over time. Only by predicting the drift corresponding to the logical address of the data based on its frequency of occurrence, and adjusting the read voltage accordingly, can the initial raw bit error rate (RBER) be guaranteed.

[0219] When the read latency of the storage medium is very small (~160 nanoseconds), the drift amount corresponding to each logical address read is predicted, and the read voltage is adjusted according to the drift amount corresponding to the logical address. On the one hand, the drift time range of the threshold voltage is large, making it difficult to track all written logical addresses. Different drift rates can lead to read margin loss and uncorrectable errors. On the other hand, the time difference between writing and reading hot data is short. By prioritizing the reading of logical addresses corresponding to hot data, the timeliness of hot data can be avoided. Therefore, predicting the drift amount of the storage medium (i.e., phase change material) in the storage-class memory and ensuring the reliability and correctness of the data stored in the storage medium are very important.

[0220] In a specific example, a pipelined approach is used to execute querying the Bloom filter and reading data from the storage medium in parallel, thereby avoiding read latency. This scheme focuses on the read flow efficiency between the core processors (i.e., the first and second processors), the storage medium controller (i.e., the third processor), and the storage medium (i.e., the non-volatile storage device). In this way, the promised initial bit error rate can be guaranteed without affecting the overall read latency.

[0221] In a specific example, the read operation includes the following three steps:

[0222] Step 1: Use the core processor (i.e., Core1) to check whether the logical address to be read overlaps with the logical address in the write buffer; pack the logical addresses not stored in the write buffer to obtain the first submission queue; the core processor here can correspond to the first processor as described above.

[0223] Step 2: Use the core processor (i.e., Core2) to predict the drift amount of logical addresses that are not stored in the write buffer; the drift amount corresponding to the logical address can be predicted based on the popularity of the data corresponding to the logical address; the core processor here can correspond to the second processor as described above.

[0224] Step 3: Use the storage medium controller to send a read command to the non-volatile storage device. The logical address corresponding to the read command has already had its drift amount predicted in step 2. The storage medium controller here can correspond to the third processor as described above.

[0225] The above three steps can be executed in a pipelined manner to improve read efficiency. The three steps run in parallel, and the intermediate results obtained from each step can be stored in on-chip memory.

[0226] This disclosure provides a memory system and its operation method, a memory controller, and a readable storage medium. In this disclosure, the memory system includes at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device. The memory controller is configured to send a read command to the non-volatile memory device based on the level of drift corresponding to a logical address. Thus, the read voltage for performing the read command operation on the non-volatile memory device can be determined based on the level of drift corresponding to the logical address, thereby ensuring the correctness of the read command operation and improving the reliability of the memory system.

[0227] Furthermore, in this embodiment of the present disclosure, at least two processes are executed in parallel during the process of checking whether the logical address is stored in the write buffer, determining the level of the drift amount corresponding to the logical address that is not stored in the write buffer, and sending the read command according to the level of the drift amount corresponding to the logical address. This can optimize the read latency and improve the read efficiency.

[0228] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0229] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory system, characterized in that, The memory system includes: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; the memory controller is configured to: The first processor is configured to: check whether the logical address corresponding to the host read command is stored in the write buffer, and submit the logical address not stored in the write buffer to the first submission queue; The first on-chip memory is configured to store the first submission queue; The second processor is configured to: determine the level of drift corresponding to a logical address not stored in the write buffer, including: determining the level of drift corresponding to each logical address in the first commit queue, and submitting the level of drift corresponding to each logical address to the second commit queue; different levels of drift correspond to different read voltages; The second on-chip memory is configured to store the second submission queue; The third processor is configured to: determine the read voltage corresponding to the logical address based on the level of the drift amount corresponding to the logical address, and send a read command to the non-volatile memory device, including: determining the read voltage corresponding to the logical address based on the level of the drift amount corresponding to each logical address in the second submission queue, and sending a read command to the non-volatile memory device; wherein the processes of checking whether the logical address is saved, determining the level of the drift amount, and sending the read command are all executed in parallel; at the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

2. The memory system according to claim 1, characterized in that, The second processor is specifically configured as follows: Based on the heat of the data corresponding to each logical address in the first submission queue, the level of drift corresponding to each logical address is determined; the heat of the data characterizes the length of the average time difference between data writing and reading.

3. The memory system according to claim 2, characterized in that, The data's popularity includes hot data, warm data, and cold data; the average time difference for writing and reading corresponding to hot data, warm data, and cold data increases sequentially. The second processor is specifically configured as follows: When the data corresponding to the logical address is hot data, the drift amount corresponding to the logical address is determined to be the first-level drift amount; when the data corresponding to the logical address is warm data, the drift amount corresponding to the logical address is determined to be the second-level drift amount; when the data corresponding to the logical address is cold data, the drift amount corresponding to the logical address is determined to be the third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

4. The memory system according to claim 3, characterized in that, The second processor is specifically configured as follows: The order of the logical addresses in the second submission queue is determined based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address in the second submission queue.

5. The memory system according to claim 2, characterized in that, The second processor is specifically configured as follows: By querying the mapping table, the popularity of the data corresponding to each logical address in the first submission queue is determined.

6. The memory system according to claim 1, characterized in that, The third processor is specifically configured as follows: Based on the level of drift corresponding to each logical address in the second submission queue, determine the read voltage for performing a read command operation on the non-volatile memory device; A read command is sent to the non-volatile memory device based on the read voltage used to perform the read command operation.

7. The memory system according to claim 1, characterized in that, The third processor is specifically configured to: when a read operation on the non-volatile memory device is successful, submit the logical address of the read command to the read completion queue; and when a read operation on the non-volatile memory device fails, submit the logical address of the read command to the write completion queue. The second on-chip memory is further configured to store the read completion queue and the write completion queue; The second processor is also configured to: redetermine the level of drift corresponding to each logical address in the write completion queue.

8. The memory system according to claim 1, characterized in that, During the nth time interval, the first processor is configured to: check in the (n+1)th round whether the logical address is stored in the write buffer; the second processor is configured to: determine in the nth round the level of drift corresponding to the logical address in the first commit queue; the third processor is configured to: In round 1, a read command corresponding to the level of the drift amount of the logical address in the second commit queue is sent; where n is a positive integer.

9. The memory system according to claim 1, characterized in that, The first processor is specifically configured to: when the logical address corresponding to the read command is stored in the write buffer, return the data corresponding to the logical address; The first on-chip memory is also configured to store the returned data.

10. The memory system according to claim 1, characterized in that, Both the first on-chip memory and the second on-chip memory include dynamic random access memory or static random access memory.

11. The memory system according to claim 1, characterized in that, The memory system includes storage-level memory; the non-volatile memory device includes phase-change memory.

12. A memory controller, characterized in that, The memory controller is coupled to at least one non-volatile memory device; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; the memory controller is configured to: The first processor is configured to: check whether the logical address corresponding to the host read command is stored in the write buffer, and submit the logical address not stored in the write buffer to the first submission queue; The first on-chip memory is configured to store the first submission queue; The second processor is configured to: determine the level of drift corresponding to a logical address not stored in the write buffer, including: determining the level of drift corresponding to each logical address in the first commit queue, and submitting the level of drift corresponding to each logical address to the second commit queue; different levels of drift correspond to different read voltages; The second on-chip memory is configured to store the second submission queue; The third processor is configured to: determine the read voltage corresponding to the logical address based on the level of the drift amount corresponding to the logical address, and send a read command to the non-volatile memory device, including: determining the read voltage corresponding to the logical address based on the level of the drift amount corresponding to each logical address in the second submission queue, and sending a read command to the non-volatile memory device; wherein the processes of checking whether the logical address is saved, determining the level of the drift amount, and sending the read command are all executed in parallel; at the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

13. A method for operating a memory system, characterized in that, The memory system includes: at least one non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller includes: a first processor, a second processor, a third processor, a first on-chip memory, and a second on-chip memory; the operation method includes: The first processor checks whether the logical address corresponding to the host read command is stored in the write buffer, and submits the logical address that is not stored in the write buffer to the first submission queue. The first on-chip memory stores the first submission queue; The second processor determines the level of drift corresponding to a logical address that is not stored in the write buffer, including: determining the level of drift corresponding to each logical address in the first submission queue, and submitting the level of drift corresponding to each logical address to the second submission queue; different levels of drift correspond to different read voltages; The second on-chip memory stores the second submission queue; The third processor determines the read voltage corresponding to the logical address based on the level of the drift amount corresponding to the logical address, and sends a read command to the non-volatile memory device. This includes: determining the read voltage corresponding to the logical address based on the level of the drift amount corresponding to each logical address in the second submission queue, and sending a read command to the non-volatile memory device; wherein the processes of checking whether the logical address is saved, determining the level of the drift amount, and sending the read command are all executed in parallel; at the same time, the logical addresses corresponding to the first submission queue, the second submission queue, and the read command are different.

14. The method of operating the memory system according to claim 13, characterized in that, Before the second processor determines the drift level corresponding to each logical address in the first submission queue and submits the drift level corresponding to each logical address to the second submission queue, the operation method further includes: The second processor determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue; the heat of the data characterizes the length of the average time difference between writing and reading the data.

15. The method of operating the memory system according to claim 14, characterized in that, The data's popularity includes hot data, warm data, and cold data; the average time difference for writing and reading corresponding to hot data, warm data, and cold data increases sequentially. The second processor determines the drift level corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, including: When the data corresponding to the logical address is hot data, the second processor determines the drift amount corresponding to the logical address as a first-level drift amount; when the data corresponding to the logical address is warm data, the second processor determines the drift amount corresponding to the logical address as a second-level drift amount; when the data corresponding to the logical address is cold data, the second processor determines the drift amount corresponding to the logical address as a third-level drift amount; wherein, the first-level drift amount is less than the second-level drift amount, and the second-level drift amount is less than the third-level drift amount.

16. The method of operating the memory system according to claim 15, characterized in that, The operation method further includes: The second processor determines the order of the logical addresses in the second submission queue based on the popularity of the data corresponding to each logical address in the first submission queue; wherein, the higher the popularity of the data corresponding to the logical address, the higher the priority of the logical address in the second submission queue.

17. The method of operating the memory system according to claim 14, characterized in that, Before the second processor determines the level of drift corresponding to each logical address based on the heat of the data corresponding to each logical address in the first submission queue, the operation method further includes: The second processor determines the popularity of the data corresponding to each logical address in the first submission queue by querying the mapping table.

18. The method of operating the memory system according to claim 13, characterized in that, The third processor sends a read command to the non-volatile memory device according to the drift level corresponding to each logical address in the second submission queue, including: The third processor determines the read voltage for performing read command operations on the non-volatile memory device based on the level of drift corresponding to each logical address in the second submission queue. The third processor sends a read command to the non-volatile memory device based on the read voltage used to perform the read command operation on the non-volatile memory device.

19. The method of operating the memory system according to claim 13, characterized in that, After the third processor sends a read command to the non-volatile memory device according to the drift level corresponding to each logical address in the second submission queue, the operation method further includes: When the third processor successfully reads the non-volatile memory device, it submits the logical address of the read command to the read completion queue; and when the read of the non-volatile memory device fails, it submits the logical address of the read command to the write completion queue. The second on-chip memory stores the read completion queue and the write completion queue; The second processor re-determines the level of drift corresponding to each logical address in the write completion queue.

20. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed, can implement the method of operating the memory system as described in any one of claims 13 to 19.

Images