Processor, instruction processing method, and electronic device including processor

Abstract

Embodiments of the present disclosure provide a processor, an instruction processing method, and an electronic device including the processor. The processor includes a plurality of processor cores and an accelerator module, wherein each of the plurality of processor cores is configured to execute a first type of instruction; the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; the accelerator module is coupled with and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module. The processor can have higher accelerator module usage efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to integrated circuits, and in particular to a processor, an instruction processing method, and an electronic device including the processor. BACKGROUND

[0002] The accelerator unit (or simply "accelerator") of a central processing unit (CPU) generally refers to a technology capable of improving the computing capability of the CPU in a specific application field, for example, a technology capable of improving the processing speed and efficiency of the CPU in a specific application field. The accelerator unit integrated in the CPU is generally divided into two types, i.e., an internal accelerator of a CPU core and an external accelerator of the CPU core, according to the connection relationship with the CPU core.

[0003] However, the CPU accelerator can have problems of low utilization of the accelerator unit or large load offloading overhead. SUMMARY

[0004] According to at least one embodiment of the present disclosure, a processor is provided, including: a plurality of processor cores, wherein each of the plurality of processor cores is configured to execute a first type of instruction; an accelerator module, wherein the accelerator module includes at least one accelerator engine configured to execute a second type of instruction different from the first type of instruction; wherein the accelerator module is coupled to and shared by the plurality of processor cores, and each of the plurality of processor cores dispatches an object instruction belonging to the second type of instruction in an instruction stream processed by itself to the accelerator module for execution and receives an execution result message of the object instruction from the accelerator module.

[0005] For example, a processor according to an embodiment of the present disclosure, wherein: the accelerator module is dynamically coupled to the plurality of processor cores, and receives the same or different object instructions belonging to the second type of instruction from the plurality of processor cores.

[0006] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: identify whether a current instruction in the instruction stream is the first type of instruction or the second type of instruction, dispatch the current instruction to a pipeline of itself in response to the current instruction being the first type of instruction, and dispatch the current instruction to the accelerator module as the object instruction in response to the current instruction being the second type of instruction.

[0007] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: enter the object instruction into a dispatch queue to wait for dispatch, allocate an entry in a reorder buffer (ROB) for the object instruction, and in response to the object instruction becoming the oldest instruction in the ROB, dispatch the object instruction to the accelerator module.

[0008] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores is further configured to: enter the object instruction into a dispatch queue to wait for dispatch, wait for a reorder buffer (ROB) to empty, and in response to the ROB emptying, dispatch the instruction to the accelerator module.

[0009] For example, a processor according to an embodiment of the present disclosure, wherein: the accelerator module is further configured to return a processing result of the object instruction to a corresponding processor core, and the execution result message of the object instruction comprises the execution result of the object instruction; or the accelerator module is further configured to store a processing result of the object instruction into a memory coupled to the plurality of processor cores, and the execution result message of the object instruction comprises a storage address of the execution result of the object instruction in the memory.

[0010] For example, a processor according to an embodiment of the present disclosure, wherein each of the plurality of processor cores comprises: an instruction fetch module configured to fetch instructions; a decode module configured to decode fetched instructions into one or more micro-operations (MOPs); and a dispatch module configured to dispatch the one or more MOPs to a processor core pipeline or the accelerator module.

[0011] For example, a processor according to an embodiment of the present disclosure, wherein the one or more MOPs comprise: a read and fill MOP to read an instruction argument and fill an operand, a load offload MOP to issue a workload to an accelerator engine performing the one or more MOPs.

[0012] For example, a processor according to an embodiment of the present disclosure, wherein in response to the accelerator engine being in a synchronous mode of operation with a corresponding processor core, the accelerator module is configured to return an execution status to the corresponding processor core in response to the object instruction completing execution in the accelerator module.

[0013] For example, a processor according to an embodiment of the present disclosure, wherein the one or more MOPs further comprise: a read response MOP to cause the at least one accelerator engine to return an execution status to a corresponding processor core.

[0014] For example, in a processor according to an embodiment of the present disclosure, the accelerator module further includes: an arbitrator coupled between the multiple processor cores and at least one accelerator engine, and configured to arbitrate the object instructions received from the multiple processor cores to allocate them to a target accelerator engine among the at least one accelerator engine.

[0015] For example, in a processor according to an embodiment of the present disclosure, the accelerator module further includes: a memory interface coupled to the at least one accelerator engine and including a translation lookaside buffer (TLB), wherein the at least one accelerator engine shares the TLB.

[0016] For example, in a processor according to an embodiment of the present disclosure, the TLB includes one or more TLB entries, each of the one or more TLB entries includes a processor core ID, and the processor core identity (ID) identifies to which processor core among the multiple processor cores the current TLB entry belongs.

[0017] For example, in the processor according to an embodiment of the present disclosure, each of the one or more TLB entries further includes a process ID for identifying a process to which the current TLB entry belongs.

[0018] For example, in a processor according to an embodiment of the present disclosure, each of the multiple processor cores is further configured to send a TLB entry operation instruction to the accelerator module, and when the TLB entry operation instruction is executed, the accelerator module performs one or more of the following operations: invalidate all TLB entries, invalidate TLB entries with a specific process ID, invalidate TLB entries with a specific process ID and a specific virtual page number (VPN), invalidate TLB entries with a specific processor core ID, invalidate TLB entries with a specific processor core ID and a specific process ID, and invalidate TLB entries with a specific processor core ID, a specific process ID, and a specific VPN.

[0019] For example, in a processor according to an embodiment of the present disclosure, the accelerator module further includes a data cache, and each of the multiple processor cores is further configured to send a cache operation instruction to the accelerator module, and the cache operation instruction, when executed, causes the accelerator module to perform one or more of the following operations: invalidate all cache lines in the data cache; invalidate one or more cache lines in the data cache; refresh all cache lines in the data cache; and refresh one or more cache lines in the data cache.

[0020] For example, in the processor according to an embodiment of the present disclosure, the at least one accelerator engine includes a control register configured to store the TLB entry operation instruction and the cache operation instruction.

[0021] For example, in a processor according to an embodiment of the present disclosure, the accelerator module further includes a page table walker (PTW) independent of the multiple processor cores, wherein the accelerator module is further configured to: in response to a miss of the at least one accelerator engine for the TLB, use the independent PTW to complete the page table access.

[0022] For example, in a processor according to an embodiment of the present disclosure, the accelerator module further includes a PTW router connected to at least a portion of the multiple processor cores, and the object instruction further includes a processor core ID, wherein the accelerator module is further configured to: in response to a miss of the at least one accelerator engine for the TLB, use the PTW router to access the PTW in the corresponding processor core based on the processor core ID to complete the page table access.

[0023] For example, in a processor according to an embodiment of the present disclosure, each of the at least one accelerator engine includes: an acquisition front-end module configured to decode the object instruction received from the arbitrator; one or more back-end execution modules configured to execute the object instruction decoded by the acquisition front-end module; a memory interface arbitrator module arbitrating memory access requests of the one or more back-end execution modules; and a completion unit module configured to submit the processing results of the object instruction.

[0024] For example, in a processor according to an embodiment of the present disclosure, the acquisition front-end module includes a load offload buffer configured to store object instruction parameters and operands.

[0025] According to at least one embodiment of the present disclosure, an electronic device is provided, including the above-mentioned processor.

[0026] According to at least one embodiment of the present disclosure, an instruction processing method is provided, comprising: receiving an instruction stream to be executed through multiple processor cores, wherein the instruction stream includes a first category of instructions and a second category of instructions different from the first category of instructions; the multiple processor cores respectively process the first category of instructions in the corresponding instruction stream; the multiple processor cores respectively dispatch object instructions belonging to the second category of instructions in the instruction stream processed by themselves to an accelerator module for execution, and receive execution result messages of the object instructions from the accelerator module, wherein the accelerator module includes at least one accelerator engine, is configured to execute the second category of instructions, and the accelerator module is coupled to the multiple processor cores and shared by the multiple processor cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1A is a schematic diagram of a processor according to at least one embodiment of the present disclosure; Figure 1B is a schematic diagram of an example of a processor core according to at least one embodiment of the present disclosure.

[0029] Figure 2 is a schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0030] Figure 3 is a schematic diagram of data interaction between a processor core and an accelerator module according to at least one embodiment of the present disclosure.

[0031] Figure 4 is a schematic diagram of a MOP according to at least one embodiment of the present disclosure.

[0032] Figure 5 Schematic diagram of how an accelerator engine accesses a TLB and a PTW router according to at least one embodiment of the present disclosure.

[0033] Figure 6 FIG. 4 is a schematic diagram of operations of a processor core on a TLB and an optional data cache in an accelerator module according to at least one embodiment of the present disclosure.

[0034] Figure 7 is a schematic structural diagram of an accelerator module according to at least one embodiment of the present disclosure.

[0035] Figure 8 The present invention relates to an instruction processing method according to at least one embodiment of the present disclosure.

[0036] Figure 9 An electronic device including a processor according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Before undertaking a detailed description of the present disclosure, it can be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and / or. The phrase "associated with," as well as derivatives thereof, means any of the following: includes, includes in, interconnected with, contains, contains in, connected with, coupled with, co-mingled with, in a relationship with, in a connection with, in a coupling with, in communication with, cooperating with, inter-leaved, co-located with, in close proximity to, bound in, has a property, has a relationship, or has a connection.

[0038] Definitions for other certain words and phrases used throughout this patent document are provided below. Those of ordinary skill in the art will understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0039] Embodiments of the principles of the present disclosure in the present disclosure are described herein, by way of example only, with reference to the accompanying drawings. To the extent that the present disclosure does not rely on the contents of the accompanying drawings, the organization, numbering, and / or labeling of the figures are for illustrative purposes only and should not be read as limiting the scope of the present disclosure. One skilled in the art will understand that the principles of the present disclosure can be implemented in any suitably arranged system or device. In some instances, the actions recited in the specification can occur in a different order and still accomplish the desired results. Additionally, the processes depicted in the figures are not necessarily required to be performed in the order depicted. In certain embodiments, multitasking and parallel processing can be advantageous.

[0040] Accelerator units integrated into the CPU are generally divided into two types, depending on their connection to the CPU core: internal accelerators and external accelerators. A key design feature of an internal accelerator is that it uses the same instruction set architecture (ISA) as the CPU. The CPU determines whether to dispatch instructions to the accelerator or use the standard CPU arithmetic and logic unit (ALU) based on the instruction encoding. A key design feature of an external accelerator is that it is external to the CPU core and connected to the CPU core via an IO bus (for example, Peripheral Component Interconnect Express (PCIE)). The CPU operates the accelerator by reading and writing the accelerator's IO address.

[0041] Due to their close integration with the CPU pipeline, the accelerator inside the CPU core generally has a one-to-one relationship with the CPU core (i.e., one CPU core is matched with one accelerator). For multi-core CPU chips, if there are multiple different types of accelerators, then each CPU core is generally required to have the same combination of multiple types of accelerators integrated. However, in reality, most CPU workloads may not require all CPU cores to run the same accelerated computing task, which results in relatively low utilization efficiency of a large number of accelerators. In addition, if each core of a multi-core CPU is integrated with multiple types of accelerators in different combinations according to usage needs (for example, the type of CPU workload), it may cause multi-core heterogeneity problems, bringing challenges to software development / deployment and migration, and leading to increased development / deployment and migration costs.

[0042] While accelerators external to the CPU core can share functionality through drivers using an IO bus connection, this approach can introduce significant load shedding overhead. In particular, in applications with fine-grained workloads, the efficiency of external accelerators can be significantly reduced.

[0043] Modern multi-core CPUs, based on implementation and performance considerations, typically package several (e.g., 4 to 8) CPU cores, along with their associated Level 1 data cache (L1D$), Level 2 cache (L2$), and Level 3 cache (L3$), into a module called a core cluster. The CPU cores within a core cluster typically share either the L2$ or L3$. By connecting multiple identical core clusters using an internal interconnect, they form a comprehensive multi-core CPU system.

[0044] The present disclosure provides a processor comprising: multiple processor cores and an accelerator module, wherein each of the multiple processor cores is configured to execute a first category of instructions; the accelerator module comprises at least one accelerator engine, configured to execute a second category of instructions different from the first category of instructions; the accelerator module is coupled to and shared by the multiple processor cores, and the multiple processor cores respectively dispatch object instructions belonging to the second category of instructions in the instruction streams processed by themselves to the accelerator module for execution and receive execution result messages of the object instructions from the accelerator module.

[0045] The processor disclosed herein can solve or alleviate the difficulty of sharing accelerator engines with the same or different functions between cores in a core cluster. For example, in many application scenarios, different types of CPU cores utilize different accelerators (e.g., the type and number of accelerator engines) for their CPU loads. However, due to the static binding between CPU cores and accelerators, each CPU core must integrate the same type of accelerator engine, resulting in low accelerator engine utilization in most cases.

[0046] In the processor disclosed herein, multiple cores within a core cluster can share accelerator engines with the same or different functions. The type and number of accelerator engines can be configured specifically based on the application domains targeted by the entire CPU, and are not directly tied to the number of CPU cores within the core cluster. This allows accelerator engines to be dynamically assigned and bound to CPU cores, thereby improving accelerator engine utilization in different application scenarios.

[0047] Figure 1A is a schematic diagram of a processor according to at least one embodiment of the present disclosure; Figure 1B is a schematic diagram of an example of a processor core according to at least one embodiment of the present disclosure.

[0048] like Figure 1AAs shown, the processor 100 may include a plurality of processor cores 111 , 112 , . . . , 11 n and an accelerator module 120 .

[0049] Multiple processor cores 111-11n may be components within processor 100 that execute instructions. Each of the multiple processor cores 111-11n may independently execute program code, processing different tasks or threads simultaneously. Multiple processor cores 111-11n may improve the processor's parallel processing capabilities, enabling the computer to more quickly perform multiple tasks or more complex calculations. Each of the multiple processor cores 111-11n may execute first-category instructions, such as instructions executed by the processor core's own pipeline. These instructions include, but are not limited to, arithmetic and logic instructions (e.g., addition, subtraction, multiplication, division, AND, OR, NOT, XOR, etc.), data movement instructions (e.g., load, store, input, output, etc.), control flow instructions (e.g., unconditional jumps, subroutine calls, and returns), string processing instructions (e.g., comparisons, moves, string searches, etc.), floating-point arithmetic instructions (e.g., arithmetic operations on floating-point numbers, such as addition, subtraction, multiplication, division, and square root), and privileged instructions (e.g., for operating system-level tasks such as interrupt control and virtual memory management). Multiple processor cores 111 - 11 n may form a core cluster 110 .

[0050] Figure 1B FIG1 shows a pipeline of an exemplary processor core, where the dashed lines with arrows represent redirected instruction flows. Figure 1BAs shown, the processor core (e.g., CPU core) of a single-core or multi-core processor uses pipelining technology to improve instruction-level parallelism. The processor core internally includes multiple pipeline stages. For example, after the pipeline inputs program counters from various sources and the multiplexer (Mux) selects the next program counter (PC), the instruction corresponding to that PC undergoes branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and instruction retire / complete. Waiting queues are set up between each pipeline stage as needed. These queues are typically first-in, first-out (FIFO) queues. For example, after the branch prediction unit, there's a branch prediction (BP) FIFO queue to store branch prediction results; after the instruction fetch unit, there's an instruction cache (IC) FIFO to cache fetched instructions; after the instruction decode unit, there's a decode (DE) FIFO to cache decoded instructions; and after the instruction dispatch and rename unit, there's a finish (RT) FIFO to cache instructions awaiting completion confirmation after execution. The processor core's pipeline also includes an instruction queue to cache instructions awaiting execution by the instruction execution unit after dispatch and rename. To support high operating frequencies, each pipeline stage may contain multiple pipeline stages (clock cycles). Although each pipeline stage performs a limited number of operations, this minimizes the number of clock cycles per stage, improving CPU core performance by increasing the CPU's operating frequency. Each pipeline stage can also accommodate more instructions (a technique known as superscalar technology), further enhancing processor core performance.

[0051] Within the microarchitecture, the processor core translates each architectural instruction into one or more micro-ops (mops). Each micro-op performs a limited number of operations, keeping each pipeline stage short and increasing the processor core's operating frequency. For example, a memory read instruction (load) can be translated into an address generation micro-op and a memory read micro-op. The second micro-op depends on the result of the first micro-op, so the second micro-op will not execute until the first micro-op completes. Micro-ops contain multiple micro-architecture-related fields that are used to pass relevant information between pipeline stages.

[0052] Speculative execution is another technique for improving processor performance. This technique executes the instructions following an instruction before it has completed execution. The branch prediction unit (branch predictor) at the front end of the processor core predicts the direction of a branch instruction and prefetches and executes instructions in that direction. Another speculative execution technique involves executing a memory read instruction before the addresses of all preceding memory write instructions are known. Speculative execution further increases parallelism between instructions, significantly improving processor core performance. When a speculative execution error occurs, such as a branch prediction error or a write instruction preceding a memory read instruction overwriting the same address, all instructions in the pipeline following the erroneous instruction must be flushed (also known as "cleared"), and the program then jumps to the point of error and re-executes to ensure correct execution. To support speculative execution, the processor core microarchitecture must also support an architectural register recovery mechanism to ensure that architectural registers always have correct values ​​during speculative execution.

[0053] Operating systems usually need to support multiple processes running simultaneously while using the CPU. In order to simplify multi-process management and enhance security, applications use a complete virtual address. For example, a 32-bit addressing application has a maximum of 2 32 =4GB of virtual address space available. When a program runs, these virtual addresses are mapped to multiple memory pages, each with its own physical storage address. When an application accesses instructions or data, it must first translate the virtual address of the instruction or data into a physical address. The application then verifies that the access to the page is legal. The corresponding data is then retrieved from memory or cache and passed to the CPU core. The process of translating from virtual to physical addresses is called address translation. The mapping from virtual to physical addresses is stored in tables in memory, and accessing these tables in memory also requires hundreds of clock cycles. To reduce these memory accesses, the CPU core uses multiple levels of cache to store recently used mappings. These caches are called translation lookaside buffers or page table buffers (TLBs). If a TLB query results in a miss or a "miss," the CPU core uses a page table walker (PTW) to navigate the page table pages to locate the required page table entry (PTE) for address translation.

[0054] The pipeline of the processor core of the embodiment of the present disclosure is not limited to Figure 1AIn the examples shown, some components can be omitted or other components can be added as needed. The embodiments of the present disclosure do not limit the architecture of the processor core (such as x86, ARM, MIPS, RISC-V, etc.) and the instruction set executed.

[0055] The accelerator module 120 can be coupled to and shared by multiple processor cores 111-11n. The accelerator module 120 can improve the performance or energy efficiency of the processor cores 111-11n when executing specific computing tasks or in specific scenarios, thereby improving the overall performance of the processor 100. For example, in some scenarios, not all processes running on the processor cores in a core cluster require access to the accelerator engine. In other words, among the processes running on the processor cores in the core cluster, only processes on individual processor cores may require access to the accelerator engine. In this case, statically binding an accelerator hardware module to each processor core may result in waste.

[0056] The accelerator module 120 may include at least one accelerator engine 121. Figure 1A Only one accelerator engine 121 is shown, but example embodiments may include more accelerator engines. The at least one accelerator engine 121 may include multiple accelerator engines of the same or different types. Accelerator engines may include, but are not limited to, application-specific integrated circuits (ASICs), graphics processing units (GPUs), tensor processing units (TPUs), neural network processing units (NPUs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), and the like. The at least one accelerator engine 121 may be configured to execute a second type of instruction that is different from the first type of instruction. The second type of instruction is an instruction that can be executed by the accelerator module, such as encryption and decryption, hash calculation, compression and decompression, etc., but the present disclosure is not limited thereto.

[0057] The multiple processor cores 111-11n can each dispatch target instructions 131 belonging to the second category of instructions in the instruction streams processed by the processor cores 111-11n to the accelerator module 120 for execution. For example, the multiple processor cores 111-11n can each dispatch target instructions 131 belonging to the second category of instructions to at least one accelerator engine 121 in the accelerator 120 for execution. The multiple processor cores 111-11n can receive execution result messages of the target instructions from the accelerator module 120. For example, the multiple processor cores 111-11n can receive execution result messages of the target instructions from at least one accelerator engine 121 in the accelerator module 120.

[0058] Multiple processor cores 111-11n can share at least one accelerator engine 121 with the same or different functions. The type and number of accelerator engines 121 can be configured specifically based on the application fields targeted by the CPU and are not directly related to the number of processor cores 111-11n.

[0059] In one embodiment, during CPU operation, the accelerator module 120 can dynamically couple to the multiple processor cores 111-11n and receive the same or different target instructions belonging to the second category of instructions from one or more of the processor cores 111-11n. For example, the same or different target instructions can be received from the multiple processor cores in the same operating cycle (clock cycle) or in different operating cycles. For example, at least one accelerator engine 121 in the accelerator module 120 can be dynamically coupled to the multiple processor cores 111-11n.

[0060] For example, in response to the load of the processor 100 being a first-class load, the at least one accelerator engine 121 may receive a target instruction from one of the multiple processor cores 111-11n (e.g., processor core 111) and send an execution result message of the target instruction to the processor core. In response to the load of the processor 100 changing from the first-class load to the second-class load, the at least one accelerator engine 121 may change to receive the target instruction from another processor core (e.g., one of the processor cores 112-11n) among the multiple processor cores 111-11n and send an execution result message of the target instruction to the other processor core.

[0061] In this way, the accelerator engine 121 can be dynamically allocated and bound to the multiple processor cores 111 - 11 n , thereby improving the utilization of the accelerator engine in different application scenarios.

[0062] Figure 2 is a schematic diagram of a processor according to at least one embodiment of the present disclosure.

[0063] like Figure 2 As shown, the processor 2000 may include multiple processor cores 2010, 2020, ..., 20n0 and an accelerator module 2300 and a third-level cache L3$ 2200 shared by the processor cores 2010, 2020, ..., 20n0.

[0064] Multiple processor cores 2010, 2020, ..., 20n0 may form a core cluster. Each core cluster may have 4-8 processor cores, that is, the number of multiple processor cores 2010, 2020, ..., 20n0 may be 4-8, but the embodiments of the present disclosure are not limited thereto, and each core cluster may include more or fewer processor cores.

[0065] although Figure 2 While n processor cores 2010, 2020, ..., 20n0 are shown (n is a natural number greater than 1), this is merely an example. The connection topology of the processor cores and accelerator modules in a core cluster can be flexible. For example, every two processor cores can share one accelerator module. For another example, more or fewer processor cores can share one or more accelerator modules.

[0066] although Figure 2 The structures of the multiple processor cores 2010 , 2020 , . . . , 20n0 are shown to be the same, but those skilled in the art will appreciate that one or more of the multiple processor cores 2010 , 2020 , . . . , 20n0 may have different structures.

[0067] Each processor core can identify whether the current instruction in its corresponding instruction stream is a first-category instruction or a second-category instruction. For example, each processor core can identify whether the current instruction to be processed is a processor core instruction or an accelerator instruction. In response to identifying that the current instruction is a processor core instruction, each processor core can dispatch the current instruction to its own pipeline. In response to identifying that the current instruction is an accelerator instruction, each processor core can dispatch the current instruction to the accelerator module 2300 as the target instruction.

[0068] Multiple processor cores 2010, 2020, ..., 20n0 may include instruction fetch modules 2011, 2021, ..., 20n1, respectively. Each of instruction fetch modules 2011, 2021, ..., 20n1 may be configured to fetch instructions. For example, each instruction fetch module may locate the location of the instruction to be executed by processor 2000 in a memory via an address bus and fetch the instruction from the memory. Each instruction fetch module may transmit the fetched instruction to a corresponding decode module.

[0069] Multiple processor cores 2010, 2020, ..., 20n0 may include decode modules 2012, 2022, ..., 20n2, respectively. Each decode module 2012, 2022, ..., 20n2 may be configured to decode a fetched instruction into one or more MOPs. For example, each decode module may decode an instruction from a corresponding instruction fetch module and identify the instruction type and required operands.

[0070] The plurality of processor cores 2010, 2020, ..., 20n0 may include dispatch modules 2013, 2023, ..., 20n3, respectively. Each of the dispatch modules 2013, 2023, ..., 20n3 may be configured to dispatch one or more MOPs to the processor core pipeline or accelerator module. For details of the one or more MOPs, refer to the following description of the MOPs. Figure 4 Description.

[0071] Each dispatch module may dispatch one or more MOPs to the accelerator module 2300 according to whether the one or more MOPs from the corresponding decoding module are MOPs for the accelerator module.

[0072] In one embodiment, each processor core can be configured to place a target instruction to be dispatched to accelerator module 2300 into a dispatch queue (not shown) of the dispatch module to await dispatch. Each processor core can allocate an entry in the reorder buffer (ROB) for the target instruction. In response to the target instruction becoming the oldest instruction in the ROB, each processor core can dispatch the target instruction to accelerator module 2300. The target instruction becoming the oldest instruction in the ROB means that instructions preceding the target instruction have already been executed and committed, thus preventing execution errors due to instruction or data dependencies for the target instruction.

[0073] Alternatively or additionally, in another embodiment, each processor core may be configured to place the target instruction into a dispatch queue to await dispatch. Each processor core may wait for the reorder buffer (ROB) to be drained. In response to the ROB being drained, each processor core may dispatch the instruction to the accelerator module 2300. The draining of the ROB also means that instructions preceding the target instruction have been executed and committed, and thus, no execution error will be caused for the target instruction due to instruction dependencies or data dependencies.

[0074] Each dispatch module may dispatch one or more MOPs to a corresponding transmit module according to whether the one or more MOPs from the corresponding decode module are MOPs for a pipeline of a processor core.

[0075] The plurality of processor cores 2010, 2020, ..., 20n0 may include a transmitting module 2014, 2024 ( Figure 2 Each of the transmit modules 2014, 2024, ..., 20n4 can retrieve instructions from the dispatch queue of the processor core pipeline and distribute them to subsequent modules for execution. For example, each transmit module can retrieve instructions from the dispatch queue of the processor core pipeline from the corresponding dispatch module and distribute them to the corresponding LSU module and ALU module.

[0076] The plurality of processor cores 2010, 2020, ..., 20n0 may include a load and store unit (LSU) module 2015, 2025 ( Figure 2 Each of the LSU modules 2015, 2025, ..., 20n5 can receive and execute load and store instructions. Load and store instructions allow the processor 2000 to access data stored in memory. When executing load and store operations, each LSU module can generate a virtual address. The virtual address can be converted into a physical address through an address translation process (e.g., by a corresponding TLB or PTW), thereby reading or writing data from or into physical memory. Each LSU module can load data from memory into a register of the processor 2000 or store data in a register of the processor 2000 back into memory. Each LSU module can send its execution results to the corresponding completion module.

[0077] The plurality of processor cores 2010, 2020, ..., 20n0 may each include an independent level 1 data cache (eg, L1D$ 2018, L1D$ 2028 ( Figure 2 Not shown), ..., L1D$ 20n8) and level 2 cache (e.g., L2$ 2029, L2$ 2029 ( Figure 2 Multiple processor cores 2010, 2020, ..., 20n0 can share a level 3 cache (L3$) 2200 via a memory coherent bus 2100. Each level 1 data cache may include a translation lookaside buffer (TLB) (e.g., TLB 20181, TLB 20281, ..., TLB 20n81) and a page table walker (PTW) (e.g., PTW 20182, PTW 20282, ..., PTW 20n82).

[0078] Each TLB stores a copy of the page table entries that are most likely to be accessed by the corresponding processor core. These page table entries contain mapping information from virtual addresses to physical addresses. When a processor core needs to access a virtual address, it first checks whether the mapping information for that address already exists in the TLB. If so (i.e., a hit), the processor core can directly use the physical address in the TLB to access memory, avoiding direct access to the page table in memory, reducing the number of memory accesses, and improving address translation speed.

[0079] When the TLB does not contain a mapping for a virtual address (i.e., a TLB miss), the processor core can access the page table in memory through the corresponding PTW to obtain the physical address corresponding to the virtual address. The PTW can traverse the page table to find a matching virtual address and return the found physical address to the corresponding processor core. The PTW can also find the corresponding entry in the page table and backfill it into the TLB.

[0080] The plurality of processor cores 2010, 2020, ..., 20n0 may include arithmetic and logic unit (ALU) modules 2016, 2026 ( Figure 2 Each of the LSU modules 2016, 2026, ..., 20n6 can perform basic arithmetic and logical operations according to the instructions received from the corresponding transmission module. Each ALU module can send its execution results to the corresponding completion module.

[0081] The plurality of processor cores 2010, 2020, ..., 20n0 may include completion modules 2017, 2027 ( Figure 2 Each of the completion modules 2017, 2027, ..., 20n7 may mark the corresponding instruction in the reorder buffer (ROB) as completed. Each completion module may also write the execution result of the corresponding instruction into the ROB for commit.

[0082] Processor 2000 may include an accelerator module 2300. Multiple processor cores 2010, 2020, ..., 20n0 may share an instruction set architecture (ISA) front-end with accelerator module 2300, including, for example, instruction fetch, decode, and dispatch. Accelerator module 2300 may include an arbiter 2310. Arbiter 2310 may be coupled between the multiple processor cores and the accelerator engine. Since accelerator module 2300 is shared by multiple processor cores, arbiter 2310 of accelerator module 2300 may arbitrate target instructions received from the multiple processor cores and assign them to target accelerator engines within the accelerator engine, thereby improving the allocation and utilization efficiency of computing resources within the accelerator module. After being assigned to a target accelerator engine by arbiter 2310, the target instruction may begin execution in the target accelerator engine. If arbitration for a target instruction fails, the corresponding processor core may wait until the target instruction can be assigned to a suitable accelerator engine by arbiter 2310.

[0083] The accelerator module 2300 can include a plurality of accelerator engines 2321, 2322, …, 232m, where m is a natural number greater than 0. The number and type of accelerator engines included in the accelerator module 2300 can be flexibly configured according to the usage requirement of the processor. The description of the accelerator engines can refer to the description of the accelerator engines in Figure 1A , which is not repeated here.

[0084] The accelerator module 2300 can include a memory interface 2350 independent of the plurality of processor cores to access the memory. The accelerator module 2300 can complete the address translation from a virtual address to a physical address independently of the plurality of processor cores. The memory interface 2350 can be coupled with the accelerator engines 2321, 2322, …, 232m and include a TLB 2351. The TLB 2351 can be shared by the accelerator engines 2321, 2322, …, 232m.

[0085] When a corresponding accelerator engine needs to access a certain virtual address, the accelerator engine can first check whether there is mapping information of the address in the TLB. If there is (i.e., hit), the accelerator engine can directly use the physical address in the TLB to access the memory. The specific details of the page table entry in the TLB 2351 can refer to the description of the page table entry in the TLB in Figure 5 .

[0086] The accelerator module 2300 can include a PTW router 2340. When a TLB miss occurs, the page table access can be completed using the PTW in the processor core to which the accelerator engine is bound. In this case, a separate PTW can not be configured in the accelerator module 2300. For example, the corresponding accelerator engine can access the page table in the memory through the PTW router 2340 to obtain the physical address corresponding to the virtual address. When the processor core dispatches instructions to the accelerator module, the process ID of the current process and the processor core ID of the current processor core in the core cluster can be carried in the dispatched instructions. The corresponding accelerator engine can use the PTW router 2340 when a TLB miss occurs and find the PTW in the corresponding processor core according to the processor core ID, so as to obtain the required page table entry.

[0087] The memory interface 2350 can include an optional PTW 2352. The accelerator module 2300 can use the PTW 2352 to independently complete the access of the page table without accessing the PTW in the processor core. For example, when a TLB miss occurs, the accelerator engine can access the page table in the memory through the PTW 2352 to obtain the physical address corresponding to the virtual address, in the case that the accelerator module 2300 includes the independent PTW 2352. By independently configuring the PTW 2352 for the accelerator module 2300, the wires required for the PTW router 2340 to access the processor core can be omitted. Thus, the volume of the processor 2000 can be reduced.

[0088] In at least one embodiment, the accelerator module 2300 can include an optional data cache 2360. For example, the optional data cache 2360 can be configured for the accelerator module 2300 in the case that the memory access performance needs to be improved. In the case that the independent data cache 2360 is not needed, the accelerator module 2300 can directly interface to the third level cache L3$ shared by the plurality of cores in the core cluster through the memory interface 2350.

[0089] The accelerator module 2300 can include a completion module 2330. The completion module 2330 can mark the corresponding instruction as completed in the reorder buffer ROB. The completion module 2330 can also send the execution result of the corresponding instruction to the corresponding completion module in the completion module 2017, 2027, …, 20n7. The details of the data interaction between the accelerator module 2300 and the processor core can be referred to the description of the data interaction between the accelerator module 3200 and the processor core 3100 in Figure 3 .

[0090] Figure 3 is a schematic diagram of the data interaction between a processor core and an accelerator module according to at least one embodiment of the present disclosure.

[0091] Figure 4 is a schematic diagram of the MOP according to at least one embodiment of the present disclosure.

[0092] As Figure 3 shown, the processor core 3100 can interact with the accelerator module 3200. The accelerator module 3200 can include an arbiter 3210 and accelerator engines 3221, 3222, …, 322m. The specific description of the processor core, the accelerator module, the arbiter, the accelerator engine can be referred to the description in Figure 1A and Figure 2 , which will not be repeated here.

[0093] The processor core 3100 can send handshake and status signals to the accelerator module 3200 and can receive handshake and status signals from the accelerator module 3200. The handshake and status signals can include valid, ready, busy, etc. The handshake and status signals can coordinate and synchronize operations between the processor core 3100 and the accelerator module 3200 to ensure correctness and safety of data transfer, to improve reliability and correctness of data transfer.

[0094] The processor core 3100 can send a load offload instruction to the accelerator module 3200. The load offload instruction can include an instruction code and operands required for execution of the instruction. The processor core 3100 can receive a load offload response from the accelerator module 3200. The load offload response can include an instruction execution status and optionally an instruction execution result. For example, the accelerator module 3200 can return a processing result of an object instruction to the corresponding processor core, and the execution result message of the object instruction can include the execution result of the object instruction. For another example, the accelerator module 3200 can also store the processing result of the object instruction into a memory coupled with the plurality of processor cores, and the execution result message of the object instruction can include a storage address of the execution result of the object instruction in the memory. The instruction execution status can indicate whether the execution of the object instruction is successful or whether there is an exception to be processed.

[0095] From the perspective of ISA, all instructions sent by the processor core 3100 to the accelerator module 3200 can be split into one or more MOPs in the decoding stage. Referring now to Figure 4 A description of one or more MOPs.

[0096] Figure 4 An object instruction in the ISA requires 4 instruction parameters, e.g., param1, param2, param3, param4. The processor core can use 4 general purpose registers (GRP) including R1, R2, R3, and R4 to buffer the 4 instruction parameters param1-param4, respectively. The instructions “mov R1, param1”, “mov R2, param2”, “mov R3, param3”, and “mov R4, param4” can be the first type of instructions dispatched to the processor core pipeline to cause the processor core to buffer the 4 instruction parameters param1-param4 into the 4 general purpose registers R1-R4.

[0097] The object instruction "acc_offload R1" dispatched to the accelerator module can be used to call the acceleration function of the accelerator module. The object instruction "acc_offload R1" can be divided into four MOPs including MOP1, MOP2, MOP3 and optional MOP4. MOP1 and MOP2 can be read and fill MOPs. The read and fill MOP can be used to read the object instruction parameters and fill the operands. For example, the read and fill MOP can move the four instruction parameters in the GPR to the load offload buffer of the accelerator module. MOP3 can be a load offload MOP. The load offload MOP can send a workload to the accelerator engine that executes one or more MOPs to start the accelerator engine. The optional MOP4 can be a read response MOP. The read response MOP enables the corresponding accelerator engine to return the instruction execution status to the processor core. After the instruction execution is completed, the result obtained by the accelerator can be written to the general register R1 for subsequent use, but the present disclosure is not limited to this, and the result can also be written to other general registers.

[0098] return Figure 3 In one embodiment, when the processor core 3100 and the corresponding accelerator engine in the accelerator module 3200 are in a synchronous operation mode, the processor core 3100 may not send a read response MOP to the accelerator module 3200. The accelerator engine may return an execution status to the corresponding processor core 3100 in response to the completion of execution of the target instruction in the accelerator module.

[0099] In another embodiment, when the processor core 3100 and the corresponding accelerator engine in the accelerator module 3200 are in asynchronous operation mode, the processor core 3100 may send a read response MOP to the accelerator module 3200. The read response MOP can synchronize the processor core 3100 with the corresponding accelerator engine and handle the exception status returned by the corresponding accelerator engine. For example, if an exception occurs during the execution of the target instruction in the accelerator module 3200, the accelerator module 3200 may internally save the exception status. When the read response MOP is executed, the exception status can be reported to the processor core 3100. In response to receiving the exception status sent by the accelerator module 3200, the processor core 3100 may jump to the exception handler. After the exception is handled, the entire accelerator instruction (including all split MOPs) can be re-executed. When the read response MOP is re-executed, the instruction execution result can be correctly executed and submitted.

[0100] Figure 5 Schematic diagram of how an accelerator engine accesses a TLB and a PTW router according to at least one embodiment of the present disclosure.

[0101] In order to improve the utilization efficiency of the TLB in the accelerator module, the entire accelerator module adopts a centralized TLB 520. That is, all TLB entries in the TLB 520 can be dynamically shared and allocated among multiple accelerator engines 511-51m. Each TLB entry may include

[0102] Each TLB entry in TLB 520 may include a processor core ID, a process ID, and a virtual page number VPN. The processor core ID may identify the processor core to which the current TLB entry belongs among multiple processor cores. The process ID may identify the process to which the current TLB entry belongs. In one embodiment, the process ID may be an address space identifier (ASID) in the TLB entry that identifies the virtual address space to which the TLB entry belongs. VPN may refer to the virtual address page table index number in the processor's TLB entry.

[0103] When a processor core dispatches an instruction to an accelerator engine 511-51m in the accelerator module, the dispatched instruction can carry the process ID of the current process and the processor core ID of the current processor core in the core cluster. When the corresponding accelerator engine needs to access a certain virtual address, it first checks the TLB entry in the TLB 520 based on the process ID and processor core ID to see if there is a mapping for the address. If so (i.e., a match), the accelerator engine can directly use the physical address in the TLB 520 to access the memory.

[0104] When a TLB miss occurs, the corresponding accelerator engine can use the PTW router 530 to search for the PTW in the corresponding processor core (eg, the PTWs of the processor cores 541 - 54 n ) according to the processor core ID, thereby obtaining the required page table entry.

[0105] There's no fixed correspondence between the accelerator engines 511-51m in the accelerator module and the processor cores 541-54n in the core cluster. An accelerator module may include m accelerator engines 511-51m. Because these accelerator engines are independent and require concurrent memory access, the TLB 520 also needs to provide m read and write ports. Because each of the m accelerator engines 511-51m may receive target instructions from each of the n processor cores 541-54n, a PTW router 530 is needed to locate the PTW connection path for the corresponding processor core when a TLB miss occurs.

[0106] Figure 6is a schematic diagram of the operation of a TLB in an accelerator module and optionally a data cache by a processor core according to at least one embodiment of the present disclosure. Details regarding the processor core 611-61n, the at least one accelerator engine 620, the memory interface 630, the TLB 631, the PTW 632, the optional data cache 640, and the L3$ can be found in the detailed description of Figure 2 , which is not repeated here.

[0107] In the case where the accelerator module and the processor core are in a synchronized execution relationship, the control of the TLB 631 and the optional data cache 640 in the accelerator module needs to be kept in sync with the corresponding processor core. The TLB 631 and the optional data cache 640 in the accelerator module need to be managed and controlled by the corresponding processor core.

[0108] Each of the plurality of processor cores 611-61n can send a TLB entry operation instruction to the accelerator module. The TLB entry operation instruction, when executed, can cause the accelerator module to perform one or more of the following operations: invalidate all TLB entries, invalidate TLB entries with a particular process ID, invalidate TLB entries with a particular process ID and a particular VPN, invalidate TLB entries with a particular processor core ID, invalidate TLB entries with a particular processor core ID and a particular process ID, and invalidate TLB entries with a particular processor core ID, a particular process ID, and a particular VPN.

[0109] In the case where the accelerator module includes the optional data cache 640, each of the plurality of processor cores 611-61n can also send a cache operation instruction to the accelerator module. The cache operation instruction, when executed, can cause the accelerator module to perform one or more of the following operations: invalidate all cache lines in the data cache; invalidate one or more cache lines in the data cache; flush all cache lines in the data cache; and flush one or more cache lines in the data cache.

[0110] Figure 7 is a structural schematic diagram of an accelerator module according to at least one embodiment of the present disclosure. Figure 7 The same components in the accelerator module 7000 in Figure 2 are not repeated here.

[0111] Figure 7The accelerator module 7000 may also include accelerator engines 7200 and 7300, but the present disclosure is not limited thereto. The accelerator module 7000 may include more accelerator engines. The structure of the accelerator engine may be similar. For example, the accelerator engine 7200 may include a control register 7210, an acquisition front end 7220, back-end execution modules 7230 and 7240, a completion module 7250, and a memory interface arbitrator 7260.

[0112] The control register 7210 can store reference Figure 6 For example, the memory core can configure the parameters of the behavior of the accelerator engines 7200, 7300, etc. by reading and writing the control register 7210. These parameters are configured using the reference Figure 4 The MOP1 and MOP2 split by the "acc_offload R1" instruction are sent to the accelerator engine.

[0113] The acquisition front-end module 7220 can decode the object instruction received from the arbiter 7100 and dispatch it to one or more back-end execution modules for execution. In the accelerator engine, since multiple back-end execution modules may have concurrent memory access requirements, the accelerator module 7000 includes a memory interface arbiter 7260 to arbitrate the memory access requests of multiple back-end execution modules. Figure 3 As shown, object instructions can carry variable-length instruction parameters and can be split into multiple MOPs by the processor core's decoding module. This design enables a single object instruction to describe multiple parallel operations. For example, a single object instruction can describe two parallel matrix multiply-accumulate operations. These two matrix multiply-accumulate operations are split into two MOPs during the decoding phase to achieve parallel execution.

[0114] The acquisition front-end module 7220 may include a load offload buffer 7221. The load offload buffer 7221 may store object instruction parameters and operands.

[0115] One or more back-end execution modules 7230, 7240 may execute the object instructions decoded by the fetch front-end module 7220. Figure 7 , two backend execution modules 7230 and 7240 are shown, but the accelerator engine 7200 may include more backend execution modules. The backend execution module 7230 may include a control unit 7231 , a loading unit 7232 , an execution unit 7233 , a storage unit 7234 , and an on-chip scratchpad 7235 .

[0116] The control unit 7231 can execute the control flow of instructions and data. The load unit 7232 can read data from memory or other storage devices and prepare the data for use by other functional units (e.g., the execution unit 7233). The execution unit 7233 can perform various arithmetic and logical operations. The storage unit 7234 can write data processed by the execution unit 7233 back to memory or other storage devices. The on-chip buffer 7235 can be a high-speed cache area located on the processor for storing temporary data.

[0117] Figure 8 The method for processing an instruction according to at least one embodiment of the present disclosure includes steps S802, S804, and S806.

[0118] In step S802 , an instruction stream to be executed may be received by multiple processor cores, where the instruction stream includes a first category of instructions and a second category of instructions different from the first category of instructions.

[0119] In step S804 , the first type of instructions in the corresponding instruction stream may be processed by multiple processor cores respectively.

[0120] In step S806, multiple processor cores can respectively dispatch object instructions belonging to the second category of instructions in the instruction stream processed by themselves to the accelerator module for execution, and receive execution result messages of the object instructions from the accelerator module, wherein the accelerator module includes at least one accelerator engine, is configured to execute the second category of instructions, and the accelerator module is coupled to the multiple processor cores and shared by the multiple processor cores.

[0121] The instruction processing method according to at least one embodiment of the present disclosure may further include dynamically coupling the accelerator module to the multiple processor cores, and receiving the same or different target instructions belonging to the second category of instructions from the multiple processor cores.

[0122] The instruction processing method according to at least one embodiment of the present disclosure may further include, by each of the plurality of processor cores, identifying whether a current instruction in an instruction stream is a first-category instruction or a second-category instruction. In response to the current instruction being a first-category instruction, the current instruction is dispatched to the pipeline of the processor core itself. In response to the current instruction being a second-category instruction, the current instruction is dispatched, by the processor core, to an accelerator module as a target instruction.

[0123] The instruction processing method according to at least one embodiment of the present disclosure may further include, by each of the plurality of processor cores, placing the target instruction into a dispatch queue to wait for dispatch, allocating an entry in a ROB for the target instruction, and, in response to the target instruction becoming the oldest instruction in the ROB, dispatching the target instruction to the accelerator module by the processor core.

[0124] The instruction processing method according to at least one embodiment of the present disclosure can further include entering, by each of the plurality of processor cores, the object instruction into a dispatch queue to wait for dispatch, waiting for ROB to be emptied. In response to the ROB being emptied, dispatching, by the processor core, the instruction to the accelerator module.

[0125] The instruction processing method according to at least one embodiment of the present disclosure can further include returning, by the accelerator module, a processing result of the object instruction to the corresponding processor core, and the execution result message of the object instruction includes the execution result of the object instruction. Alternatively or additionally, the processing result of the object instruction can be stored, by the accelerator module, into a memory coupled with the plurality of processor cores, and the execution result message of the object instruction includes a storage address of the execution result of the object instruction in the memory.

[0126] The instruction processing method according to at least one embodiment of the present disclosure can further include obtaining, by an instruction fetch module of each of the plurality of processor cores, the instruction; decoding, by a decode module of the processor core, the obtained instruction into one or more micro-operations (MOPs); and dispatching, by a dispatch module of the processor core, the one or more MOPs to a processor core pipeline or an accelerator module.

[0127] The instruction processing method according to at least one embodiment of the present disclosure can further include reading, by the accelerator module and using a read and fill MOP of the one or more MOPs, an instruction parameter and filling an operand, and offloading, by the accelerator module and using a load offload MOP of the one or more MOPs, a workload to an accelerator engine executing the one or more MOPs.

[0128] The instruction processing method according to at least one embodiment of the present disclosure can further include, in response to the accelerator engine being in a synchronous operation mode with the corresponding processor core, returning, by the accelerator module, an execution status to the corresponding processor core in response to the execution of the object instruction ending in the accelerator module.

[0129] The instruction processing method according to at least one embodiment of the present disclosure can further include, by the accelerator module, using a read response MOP of the one or more MOPs to cause at least one accelerator engine to return an execution status to the corresponding processor core.

[0130] The instruction processing method according to at least one embodiment of the present disclosure can further include arbitrating, by an arbiter of the accelerator module coupled between the plurality of processor cores and the at least one accelerator engine, object instructions received from the plurality of processor cores to be assigned to a target accelerator engine of the at least one accelerator engine.

[0131] The instruction processing method according to at least one embodiment of the present disclosure can further include causing the at least one accelerator engine to share a TLB included in a memory interface of the accelerator module.

[0132] The instruction processing method according to at least one embodiment of the present disclosure may further include sending a TLB entry operation instruction to an accelerator module through each of a plurality of processor cores, so that the accelerator module executes the TLB entry operation instruction to perform one or more of the following operations: invalidate all TLB entries, invalidate TLB entries with a specific process ID, invalidate TLB entries with a specific process ID and a specific virtual page number (VPN), invalidate TLB entries with a specific processor core ID, invalidate TLB entries with a specific processor core ID and a specific process ID, and invalidate TLB entries with a specific processor core ID, a specific process ID, and a specific VPN.

[0133] According to at least one embodiment of the present disclosure, the instruction processing method may further include sending a cache operation instruction to an accelerator module through each of the multiple processor cores, and executing the cache operation instruction through the accelerator module to perform one or more of the following operations: invalidating all cache lines in the data cache; invalidating one or more cache lines in the data cache; refreshing all cache lines in the data cache; and refreshing one or more cache lines in the data cache.

[0134] The instruction processing method according to at least one embodiment of the present disclosure may further include storing the TLB entry operation instruction and the cache operation instruction through a control register of at least one accelerator engine.

[0135] The instruction processing method according to at least one embodiment of the present disclosure may further include completing, by the accelerator module, a page table access using an independent PTW included in the accelerator module in response to a TLB miss occurring in the at least one accelerator engine.

[0136] According to at least one embodiment of the present disclosure, the instruction processing method may further include, in response to a TLB miss occurring in at least one accelerator engine, accessing the PTW in the corresponding processor core based on the processor core ID included in the object instruction through the accelerator module using a PTW router included in the accelerator module to complete the page table access.

[0137] According to at least one embodiment of the present disclosure, the instruction processing method may further include decoding an object instruction received from an arbitrator through an acquisition front-end module included in each of at least one accelerator engines; executing the object instruction decoded by the acquisition front-end module through one or more back-end execution modules included in the accelerator engine; arbitrating memory access requests of one or more back-end execution modules through a memory interface arbitrator module included in the accelerator engine; and submitting the processing results of the object instruction through a completion unit module included in the accelerator engine.

[0138] The instruction processing method according to at least one embodiment of the present disclosure may further include storing object instruction parameters and operands by acquiring a load offload buffer included in the front-end module.

[0139] Figure 9 An electronic device including a processor according to at least one embodiment of the present disclosure.

[0140] like Figure 9 As shown, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and can be configured to be read and executed by the processor 910.

[0141] The memory 920 and the processor 910 may be interconnected via a bus system and / or other connection mechanisms (not shown). For example, the bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc.

[0142] The processor 910 may include the Figure 1A-Figure 7 The processor described herein. For example, the electronic device may include a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA). Processor 910 may be a general-purpose processor or a dedicated processor, and may control other components in electronic device 900 to perform desired functions.

[0143] By way of example, the memory 920 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, and the like. One or more computer program modules 921 may be stored on the computer-readable storage medium, and the processor 910 may execute the one or more computer program modules 921 to implement various functions of the electronic device 900. The computer-readable storage medium may also store various applications and data, as well as data used and / or generated by the applications.

[0144] For example, the electronic device 900 may also include input devices such as a camera, touchscreen, touchpad, keyboard, mouse, webcam, microphone, accelerometer, gyroscope, etc.; output devices such as a liquid crystal display, speaker, vibrator, etc.; storage devices such as a magnetic tape, hard disk (HDD or SDD), etc.; and communication devices such as a network interface card such as a LAN card or modem. The communication device may allow the electronic device 900 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive is connected to the I / O interface as needed. Removable storage media such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc. are installed in the drive as needed, so that computer programs read from the drive can be installed into the storage device as needed.

[0145] For example, the electronic device 900 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device may communicate with a network and other devices via wireless communication, such as the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communications may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0146] The electronic device 900 may be, for example, a system on a chip (SOC) or a device including such a SOC, and may be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigation system, home appliance, communication base station, industrial controller, server, or the like. It may also be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited thereto. The specific functions and technical effects of the electronic device 900 may be referred to above in the description of the processor and its additional aspects according to at least one embodiment of the present disclosure, and will not be further elaborated here.

[0147] The processor according to the present disclosure can implement an accelerator module without targeting specific accelerator functions. This accelerator module is characterized by independent memory access capabilities, which can automatically load, process, and write back data. Workloads that meet these characteristics can be accelerated by implementing a corresponding accelerator engine to accelerate the computational load of the processor core. The processor according to the present disclosure can increase the configuration flexibility of the accelerator engine within a processor core cluster and between processor cores, while also improving the efficiency of the processor accelerator engine.

[0148] The text and drawings in this disclosure are provided as examples only to help understand the present disclosure. They should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, it will be clear to those skilled in the art based on what is disclosed herein that the embodiments and examples shown may be modified without departing from the scope of the present disclosure.

[0149] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0150] Nothing in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is defined solely by the claims.

Claims

1. A processor, comprising: a plurality of processor cores, wherein each of the plurality of processor cores is configured to execute a first class of instructions; an accelerator module, wherein the accelerator module comprises at least one accelerator engine configured to execute a second type of instructions different from the first type of instructions; The accelerator module is coupled to and shared by the multiple processor cores, and the multiple processor cores respectively dispatch object instructions belonging to the second category of instructions in the instruction streams processed by themselves to the accelerator module for execution and receive execution result messages of the object instructions from the accelerator module. Each of the plurality of processor cores is further configured to: identifying whether a current instruction in the instruction stream is an instruction of the first category or an instruction of the second category, and In response to the current instruction being an instruction of the first category, the current instruction is dispatched to the own pipeline.

2. The processor of claim 1 , wherein: The accelerator module is dynamically coupled to the plurality of processor cores and receives the same or different target instructions belonging to the second category of instructions from the plurality of processor cores.

3. The processor according to claim 1, wherein: Each of the plurality of processor cores is further configured to: In response to the current instruction being the second-category instruction, the current instruction is dispatched to the accelerator module as the target instruction.

4. The processor according to claim 1, wherein: Each of the plurality of processor cores is further configured to: Put the object instruction into a dispatch queue to wait for dispatch, allocating an entry in a reorder buffer for the target instruction, and In response to the target instruction becoming the oldest instruction in the re-order buffer, dispatching the target instruction to the accelerator module.

5. The processor according to claim 1, wherein: Each of the plurality of processor cores is further configured to: Put the object instruction into a dispatch queue to wait for dispatch, Wait for the reorder buffer to drain, and In response to the reorder buffer being drained, the target instruction is dispatched to the accelerator module.

6. The processor of claim 1 , wherein: The accelerator module is further configured to return a processing result of the object instruction to the corresponding processor core, and the execution result message of the object instruction includes the execution result of the object instruction; or The accelerator module is further configured to store the processing result of the target instruction in a memory coupled to the multiple processor cores, and the execution result message of the target instruction includes a storage address of the execution result of the target instruction in the memory.

7. The processor according to claim 1, wherein: Each processor core of the plurality of processor cores comprises: an instruction fetch module configured to fetch instructions; a decode module configured to decode the fetched instruction into one or more micro-operations; and The dispatch module is configured to dispatch the one or more micro-operations to the processor core pipeline or the accelerator module.

8. The processor according to claim 7, wherein: The one or more micro-operations include: Read and fill micro-operations, used to read instruction parameters and fill operands, A load offloading micro-operation is used to send a workload to an accelerator engine that executes the one or more micro-operations.

9. The processor according to claim 1, wherein: In response to the accelerator engine and the corresponding processor core being in a synchronous operation mode, the accelerator module is configured to return an execution status to the corresponding processor core in response to completion of execution of the target instruction in the accelerator module.

10. The processor according to claim 8, wherein: The one or more micro-operations further include: The read response micro-operation is used to cause the at least one accelerator engine to return an execution status to the corresponding processor core.

11. The processor according to claim 1 , wherein: The accelerator module further includes: An arbiter is coupled between the plurality of processor cores and the at least one accelerator engine and is configured to arbitrate the target instructions received from the plurality of processor cores to allocate the target instructions to a target accelerator engine among the at least one accelerator engine.

12. The processor of claim 1, wherein: The accelerator module further includes: A memory interface is coupled to the at least one accelerator engine and includes a translation lookaside buffer, wherein the at least one accelerator engine shares the translation lookaside buffer.

13. The processor according to claim 12, wherein: The translation lookaside buffer includes one or more translation lookaside buffer entries, Each of the one or more translation lookaside buffer entries includes a processor core identity, where the processor core identity is used to identify a processor core to which the current translation lookaside buffer entry belongs among the plurality of processor cores.

14. The processor of claim 13, wherein: Each of the one or more translation lookaside buffer entries further comprises: Process ID, used to identify the process to which the current translation lookaside buffer entry belongs.

15. The processor of claim 14, wherein: Each of the plurality of processor cores is further configured to send a translation lookaside buffer entry operation instruction to the accelerator module, the translation lookaside buffer entry operation instruction, when executed, causing the accelerator module to perform one or more of the following operations: Invalidate all translation lookaside buffer entries; Invalidate the translation lookaside buffer entry with a specific process ID; Invalidate the translation lookaside buffer entry with a specific process ID and a specific virtual page number; Invalidate the translation lookaside buffer entry with a specific processor core identity; invalidating a translation lookaside buffer entry having a specific processor core identity and a specific process identity; and Invalidate a translation lookaside buffer entry with a specific processor core ID, a specific process ID, and a specific virtual page number.

16. The processor of claim 15, wherein: The accelerator module also includes a data cache, and Each of the plurality of processor cores is further configured to send a cache operation instruction to the accelerator module, and when the cache operation instruction is executed, the accelerator module performs one or more of the following operations: invalidate all cache lines in the data cache; invalidating one or more cache lines in the data cache; Refreshing all cache lines in the data cache; and One or more cache lines in the data cache are refreshed.

17. The processor of claim 16, wherein: The at least one accelerator engine includes a control register, The control register is configured to store the translation lookaside buffer entry operation instruction and the cache operation instruction.

18. The processor of claim 12, wherein: The accelerator module further includes a page table walker independent of the plurality of processor cores. The accelerator module is further configured to: in response to a miss in the translation lookaside buffer by the at least one accelerator engine, use the independent page table walker to complete a page table access.

19. The processor of claim 12, wherein: The accelerator module further includes a page table walker router connected to at least a portion of the plurality of processor cores, the object instruction further includes a processor core identification, The accelerator module is further configured to: in response to a miss of the at least one accelerator engine on the translation lookaside buffer, use the page table walker router to access the page table walker in the corresponding processor core based on the processor core identity to complete the page table access.

20. The processor of claim 11, wherein: Each of the at least one accelerator engine comprises: an acquisition front-end module configured to decode the object instruction received from the arbitrator; One or more backend execution modules, configured to execute the object instructions decoded by the acquisition front-end module; a memory interface arbitrator module, configured to arbitrate memory access requests from the one or more backend execution modules; The completion unit module is configured to submit the processing result of the object instruction.

21. The processor of claim 20, wherein: The acquisition front-end module includes a load offload buffer configured to store object instruction parameters and operands.

22. An electronic device comprising the processor according to any one of claims 1 to 21.

23. A method for processing an instruction, comprising: Receiving, through a plurality of processor cores, an instruction stream to be executed, wherein the instruction stream includes a first category of instructions and a second category of instructions different from the first category of instructions; The plurality of processor cores respectively process the first type of instructions in the corresponding instruction stream; The multiple processor cores respectively dispatch object instructions belonging to the second category of instructions in the instruction streams processed by the processor cores to the accelerator module for execution, and receive execution result messages of the object instructions from the accelerator module; identifying, by each of the plurality of processor cores, whether a current instruction in the instruction stream is a first category instruction or a second category instruction; and In response to the current instruction being a first-category instruction, dispatching the current instruction to its own pipeline through each of the plurality of processor cores, The accelerator module includes at least one accelerator engine configured to execute the second type of instructions, and the accelerator module is coupled to the multiple processor cores and shared by the multiple processor cores.

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