Chip verification method and system

Abstract

The invention provides a chip verification method and system, and the method can obtain a test case, and the test case comprises a plurality of operation tasks of a chip operation core. Sub-memory areas and an instruction memory area of the register transfer level module are arranged in the total memory area, in the total memory area, the sub-memory areas are not overlapped, and the sub-memory areas and the instruction memory area are not overlapped. And setting register configuration information of the operation task according to the test case and the sub-memory region, wherein the register configuration information comprises a memory initial address and a memory capacity. And generating a running instruction based on the register configuration information, and writing the running instruction into the instruction memory area. And reading the operation instruction in the instruction memory area through the register transfer level module, and executing the operation task based on the operation instruction to obtain an operation result of the operation task. According to the method, an asynchronous parallel multi-task mode can be realized, and the problem of address overlapping among different operation tasks in the asynchronous parallel multi-task mode is solved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a chip verification method and system. Background Art

[0002] AI chips refer to chips that have an AI computing core (Neural Processing Unit, NPU) integrated into the chip. The AI ​​computing core is a hardware concept. The AI ​​computing core is the core part of the AI ​​chip, which can accelerate the operation of the neural network model (AI model). Using the AI ​​computing core can quickly complete the operation of the AI ​​model.

[0003] AI models can perform various complex computing tasks, such as image recognition, speech recognition, natural language processing, etc. A complete AI model needs to be broken down into multiple computing tasks (jobs) before it can be executed on the corresponding AI chip. In order to ensure that the task can be executed correctly and efficiently in the actual chip hardware environment, it is necessary to verify the operation of the task on the AI ​​chip.

[0004] However, conventional verification systems cannot support asynchronous parallel multi-tasking mode. In the asynchronous parallel multi-tasking mode, the address overlap problem between different computing tasks will lead to data pollution, which in turn causes the verification system to make comparison errors. Summary of the invention

[0005] The present application provides a chip verification method and system to solve the problem of address overlap between different computing tasks in an asynchronous parallel multi-tasking mode.

[0006] In a first aspect, the present application provides a chip verification method, the method comprising:

[0007] Acquire a test case, wherein the test case includes a plurality of computing tasks of a chip computing core, and the chip computing core includes a plurality of register transfer level modules;

[0008] A sub-memory area and an instruction memory area of ​​the register transfer level module are set in the total memory area, wherein the sub-memory area is set based on an upper limit value of memory usage of the register transfer level module; in the total memory area, multiple sub-memory areas do not overlap with each other, and the sub-memory area does not overlap with the instruction memory area;

[0009] The register configuration information of the computing task is set according to the test case and the sub-memory area, wherein the register configuration information is the configuration information required by the register when the register transfer level module executes the computing task; the register configuration information includes a memory start address and a memory capacity;

[0010] Generate an operation instruction based on the register configuration information, and write the operation instruction into the instruction memory area, wherein the operation instruction is used to control the register transfer level module to perform the operation task according to the register configuration information;

[0011] The register transfer level module reads the running instruction in the instruction memory area, and executes the computing task based on the running instruction to obtain the running result of the computing task.

[0012] In a second aspect, the present application provides a chip verification system, including a simulation control component and a chip computing core; wherein:

[0013] The simulation control component is used to obtain a test case, wherein the test case includes a plurality of computing tasks of a chip computing core, and the chip computing core includes a plurality of register transfer level modules;

[0014] A sub-memory area and an instruction memory area of ​​the register transfer level module are set in the total memory area, wherein the sub-memory area is set based on an upper limit value of memory usage of the register transfer level module; in the total memory area, multiple sub-memory areas do not overlap with each other, and the sub-memory area does not overlap with the instruction memory area;

[0015] The register configuration information of the computing task is set according to the test case and the sub-memory area, wherein the register configuration information is the configuration information required by the register when the register transfer level module executes the computing task; the register configuration information includes a memory start address and a memory capacity;

[0016] Generate an operation instruction based on the register configuration information, and write the operation instruction into the instruction memory area, wherein the operation instruction is used to control the register transfer level module to perform the operation task according to the register configuration information;

[0017] The chip operation core is used to read the operation instruction in the instruction memory area through the register transfer level module, and execute the operation task based on the operation instruction to obtain the operation result of the operation task.

[0018] It can be seen from the above technical solutions that the present application provides a chip verification method and system, the method can obtain test cases, and the test cases include multiple computing tasks of the chip computing core. A sub-memory area and an instruction memory area of ​​a register transfer level module are set in the total memory area. In the total memory area, multiple sub-memory areas do not overlap, and the sub-memory area does not overlap with the instruction memory area. Then, the register configuration information of the computing task is set according to the test case and the sub-memory area, and the register configuration information includes the memory start address and the memory capacity. Generate an operation instruction based on the register configuration information, and write the operation instruction into the instruction memory area. Read the operation instruction in the instruction memory area through the register transfer level module, and execute the computing task based on the operation instruction to obtain the operation result of the computing task. The method can realize an asynchronous parallel multi-tasking mode and solve the problem of address overlap between different computing tasks in the asynchronous parallel multi-tasking mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the internal data flow structure of a single AI chip computing core provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of the verification process of the synchronous serial multi-tasking mode provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the operation timeline of the synchronous serial multitasking mode and the asynchronous parallel multitasking mode provided in the embodiment of the present application;

[0023] Figure 4 A schematic diagram of memory area overlap in an asynchronous parallel multi-tasking mode provided by an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the architecture of a chip verification system in an asynchronous parallel multi-tasking mode provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the verification process of the asynchronous parallel multi-tasking mode provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of the architecture of a chip verification system in a synchronous serial multi-tasking mode provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of address overlap between multiple tasks provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0029] AI chips refer to chips that integrate AI computing cores (Neural Processing Unit, NPU) in chips (such as System on a Chip, SOC). AI computing core is a hardware concept. AI computing core is the core part of AI chips, which can accelerate the operation of neural network models (AI models). Using AI computing core can quickly complete the operator operation of AI models and shorten the running time of AI models on chips.

[0030] AI models can perform various complex computing tasks, such as image recognition, speech recognition, natural language processing, etc. A complete AI model needs to be broken down into multiple computing tasks (jobs) before it can be executed on the corresponding AI chip. The computing task can be considered the smallest granularity of AI chip operation. The core structure of the AI ​​chip includes three computing cores: matrix core, vector core and scalar core. These three computing cores are used for matrix operations, vector operations and scalar operations respectively.

[0031] A single AI computing core includes multiple register transfer level (RTL) modules, such as multiple direct memory read access (Rdma) modules, multiple computing core processors (Core), and multiple direct memory write access (Wdma) modules. Figure 1As shown, it is a schematic diagram of the internal data flow structure of a single AI chip computing core provided in an embodiment of the present application. A single AI computing core includes two RDMAs, namely RDMA_a and RDMA_b, one Core, namely Core_a, and one WDMA, namely WDMA_a. When the AI ​​computing core is running, RDMA_a, RDMA_b, Core_a and WDMA_a are started at the same time and then run in parallel. RDMA_a and RDMA_b read data from external or internal storage to the inside of the chip. At the same time, Core_a performs data processing on the data, such as matrix multiplication, convolution operations, etc. WDMA_a outputs the processed data to the verification system. The operation scheme of the above-mentioned AI chip belongs to the synchronous serial multitasking mode. When WDMA_a completes the data writing task, a computing task is deemed to be completed, that is, when WDMA_a ends, it is considered that a computing task is completed.

[0032] In the synchronous serial multitasking mode, each computing task relies on the end mark of WDMA_a. Therefore, in order to verify the operation of the AI ​​chip, the verification system construction of the AI ​​chip can choose to rely on the end signal of WDMA_a as the end mark of a computing task, and start the single task reference model and single task result comparison based on the end mark to verify whether its output meets expectations.

[0033] Based on the above chip operation mode, such as Figure 2 As shown, it is a schematic diagram of the verification process of the synchronous serial multi-tasking mode provided in the embodiment of the present application. The verification process of the simulation control component in the verification system is: after starting the simulation, obtain the preset number of tasks and the test case name, randomly generate a set of register configuration information of the computing tasks according to the test case name, and save the register configuration information to the queue. The register configuration information is used to set the internal state of the chip computing core in order to perform specific computing tasks. Repeat the above steps to set the variable cnt. Each time the register configuration information of a computing task is generated, the variable cnt is incremented by 1, that is, cnt++, until the variable cnt is equal to the preset number of tasks, indicating that the register configuration information of the preset number of tasks has been generated according to the test case name.

[0034] Generate the operation instructions for the control chip computing core to perform the computing task based on the register configuration information and write them into the memory. Initialize the memory data of the first computing task, trigger the computing core to start, and the computing core performs the computing task. The verification system waits for the end signal of WDMA_a, that is, the end mark of a computing task. When the end signal of WDMA_a is detected, run the reference model component, which is used to simulate the processing process inside the chip to generate the expected output result. Compare the actual data of the computing task output by WDMA_a with the expected data output by the reference model to check whether the output meets expectations. After the execution of this computing task is completed, continue to initialize the memory data of the next computing task so that the computing core performs the next computing task. Repeat the above steps, set the variable finish, and increment the variable finish by 1 each time a computing task is completed, that is, finish++, until the variable finish is equal to the preset number of tasks, indicating that all computing tasks with the preset number of tasks have completed verification, and then end the simulation.

[0035] like Figure 3 As shown, it is a schematic diagram of the operation timeline of the synchronous serial multitasking mode and the asynchronous parallel multitasking mode provided in the embodiment of the present application. In the verification process of the above synchronous serial multitasking mode, the use of the synchronous serial multitasking mode by a single computing core will cause the chip to process multiple tasks in a longer running time and reduce the running speed of the chip. Figure 3 As shown, in synchronous serial multitasking mode, a single computing core performs multiple computing tasks ( Figure 3 When there are three computing tasks (job0, job1 and job2), job0 can only finish and then start job1, and job1 can only finish and then start job2. "Asynchronous" means Figure 3 Asynchronous triggering in "parallel multitasking" means Figure 3 RDMA_a, RDMA_b, Core_a, and WDMA_a in the system can perform different computing tasks at the same time. Figure 3 The three computing tasks (job0, job1 and job2) shown in the figure are running in parallel at the same time.

[0036] In the asynchronous parallel multi-tasking mode, the hardware modules RDMA_a, RDMA_b, Core_a, and WDMA_a can be started asynchronously, and multiple computing tasks can run in parallel. Different modules in the computing core at the same time point can be executed in different task stages, and the waiting dependency between modules is weakened. For example, RDMA_a can execute job1 after executing job0 without waiting for WDMA_a to complete 10b0. Therefore, the asynchronous parallel multi-tasking mode can shorten the running time of the chip.

[0037] In order to improve the computing speed of the chip, the synchronous serial multitasking mode used by a single computing core can be changed to the asynchronous parallel multitasking mode in the chip architecture. However, the verification system that originally supports the synchronous serial multitasking mode cannot support the asynchronous parallel multitasking mode. Figure 2 The verification process shown cannot support the asynchronous parallel multi-tasking mode, and it is necessary to rebuild the verification system adapted to the asynchronous parallel multi-tasking mode.

[0038] The core reason why the original verification system cannot support the asynchronous parallel multi-tasking mode is the problem of address overlap between different computing tasks. The original verification system does not allow address overlap within each computing task. For example, for job0, the address ranges used by RDMA_a, RDMA_b, Core_a, and WDMA_a cannot overlap. However, different computing tasks are independent of each other, and the addresses between different computing tasks are allowed to overlap. For example, RDMA_a is allowed to use the same address space when executing job2 (RDMA_a_job2) and WDMA_a executes job0 (WDMA_a_job0). Because in the synchronous serial multi-tasking mode, job0 must be completed before job2 can be performed. When job2 uses this space, job0 has already ended and the data comparison is completed. The time difference allows the addresses of different computing tasks to overlap.

[0039] However, in the asynchronous parallel multitasking mode, multiple computing tasks may be running at the same time, such as Figure 4 As shown, it is a schematic diagram of memory area overlap in the asynchronous parallel multi-tasking mode provided by an embodiment of the present application. Assuming that there is an address overlap area between job0 and job2, at time t0, RDMA_a_job2 and WDMA_a_job0 run in parallel, WDMA_a_job0 writes data to the overlap area, and at the same time, RDMA_a_job2 reads the original data from the overlap area, and WDMA_a_job0 will directly pollute the original data of RDMA_a_job2. The address overlap between different computing tasks will cause data pollution problems, thereby causing verification system comparison errors.

[0040] In some embodiments, in the asynchronous parallel multi-tasking mode, it is possible to prevent address overlap within each computing task and between multiple computing tasks, that is, the addresses used by all computing tasks are one-time use and cannot be reused. In this way, the limited memory space of the system will soon be allocated and exhausted, and the one-time use of addresses will result in too few tasks that the simulation can support. If the system memory space can support the execution of 5 computing tasks in an actual scenario, but an operator may need to execute more than 10 computing tasks in succession to complete, the above solution is difficult to meet the operator requirements of real scenarios.

[0041] In some embodiments, in the asynchronous parallel multi-tasking mode, only three fixed-size memory spaces are initially allocated to RDMA_a, RDMA_b, and WDMA_a, and then each computing task reuses the above space. For example, RDMA_a_job0, RDMA_a_job1, and RDMA_a_job2 use the same memory space, and WDMA_a_job0, WDMA_a_job1, and WDMA_a_job2 use the same memory space. However, the use of the same address for each computing task will lead to the problem of limited address randomness. The same address for each task will damage the randomness of the verification, and it is decoupled from the real operator scenario. It is impossible for each computing task to use the same address in the real scenario.

[0042] In the above embodiment, after the chip architecture is changed to the asynchronous parallel multi-tasking mode, the original verification system cannot support the asynchronous parallel multi-tasking mode, and the address overlap problem between different computing tasks will cause data pollution, which in turn causes the verification system to have a comparison error.

[0043] Therefore, in order to solve the above problems, some embodiments of the present application provide a chip verification system, such as Figure 5 As shown, it is a schematic diagram of the architecture of the chip verification system of the asynchronous parallel multi-tasking mode provided by the embodiment of the present application. The chip verification system includes a test case pool, a memory management component, a simulation control component, a reference model component, a data packet transceiver, a comparison component and a simulation report component. In order to realize chip verification, the chip operation core to be verified is integrated in the chip verification system, and the chip operation core includes multiple register transfer level (Register Transfer Level, RTL) modules, and the RTL module is connected with the electrical signal between the components in the verification system, and an electrical signal level control and data interaction channel are created to enable the RTL module to be correctly and effectively verified in the chip verification system.

[0044] The test case pool is used to store test cases, which are used to verify the execution functions of the RTL modules in the chip computing core. Chip verification engineers can store developed test cases in the test case pool. For ease of management and maintenance, test cases can be stored in different subdirectories of the test case pool according to functions, modules, etc., for subsequent simulation testing.

[0045] The memory management component is used to manage memory space. It can interact with multiple components in the verification system and perform corresponding operations, including setting memory areas, initializing data, reading and writing instructions and data, etc.

[0046] The memory management component may receive a request for setting a memory area sent by the simulation control component, set a specified number of memory areas according to the request, and return a start address and an end address of the memory area to the simulation control component.

[0047] The memory management component may receive a request sent by the simulation control component for writing instructions at a specified address, and write the instructions sent by the simulation control component into the corresponding address according to the request.

[0048] The memory management component may receive a request sent by the simulation control component for performing random data initialization on a specific memory area, and perform random data initialization on the specific memory area.

[0049] The memory management component may receive a control instruction sent by the reference model component for reading data at a specified address, read data at the specified address according to the request, and return the read data to the reference model component.

[0050] The memory management component may receive a request sent by the data packet transceiver for reading or writing data at a specified address, and read or write data at the specified address according to the request.

[0051] The memory management component may receive a request sent by the comparison component for reading data at a specified address, read the data at the specified address according to the request, and return the read data to the comparison component.

[0052] The simulation control component is used to control the verification process. In order to solve the problem of address overlap between multiple computing tasks in asynchronous parallel multi-mode, for multiple RTL modules of the chip computing core, sub-memory areas and instruction memory areas can be set for each RTL module in the total memory area. The sub-memory area is set based on the upper limit of the memory usage of the RTL module. The sub-memory area is a set of memory addresses that the RTL module can use in the total memory area. In the total memory area, multiple sub-memory areas do not overlap, and the sub-memory area does not overlap with the instruction memory area.

[0053] In some embodiments, the simulation control component can obtain the memory usage upper limit of the RTL module, divide the sub-memory area in the total memory area according to the memory usage upper limit, and obtain the starting address and ending address of the sub-memory area returned by the memory management component.

[0054] Similarly, the simulation control component can obtain the module number of the RTL module and divide the instruction memory area corresponding to multiple RTL modules in the total memory area according to the module number, that is, each RTL module corresponds to an instruction memory area.

[0055] After setting the sub-memory area and instruction memory area of ​​each RTL module, the simulation control component can obtain test cases from the test case pool. The test cases include multiple computing tasks of the chip computing core. Set the register configuration information of each computing task according to the test case and sub-memory area. The register configuration information is the configuration information required by the register when the RTL module performs the computing task. The register configuration information includes the memory start address and memory capacity. The memory start address is the start address when the RTL module performs the computing task. The memory capacity is the memory capacity required when the RTL module performs the computing task.

[0056] In some embodiments, the simulation control component can set the memory capacity according to the test case, and set the memory start address according to the memory capacity and the sub-memory area. The memory start address is between the start address and the upper limit address of the sub-memory area, and the upper limit address is the memory address obtained by subtracting the memory capacity from the end address of the sub-memory area.

[0057] After setting the register configuration information, the simulation control component generates an operation instruction based on the register configuration information and writes the operation instruction into the instruction memory area. The operation instruction is used to control the RTL module to perform the operation task according to the register configuration information. In other words, for one operation task, the operation instructions of multiple RTL modules can be generated based on the register configuration information of the operation task, and the operation instructions of each RTL module can be written into the instruction memory area corresponding to the RTL module.

[0058] After setting the sub-memory area of ​​each RTL module, the simulation control component can also control the memory management component to perform random data initialization on the sub-memory area to write random data in the sub-memory area, thereby increasing the diversity and coverage of verification.

[0059] After the sub-memory area and the instruction memory area are set up, the simulation control component can start the RTL module of the chip computing core, so that each RTL module reads the running instructions in the instruction memory area corresponding to the RTL module, reads the input data in the sub-memory area according to the running instructions, and executes the computing task based on the running instructions and the input data to obtain the running results of the computing task, and writes the running results into the sub-memory area.

[0060] In some embodiments, in the asynchronous parallel multi-tasking mode, each RTL module in the chip computing core corresponds to an instruction reader and an instruction decoder. In order to realize the asynchronous triggering and starting of multiple RTL modules, the first simulation delay value can be set for each RTL module, and each RTL module corresponds to a first simulation delay value. When the simulation control component starts the RTL module, the timer can be started. When the timing value of the timer is equal to the first simulation delay value corresponding to the RTL module, the instruction reader of the RTL module is triggered to start, so that the instruction reader of the RTL module reads the running instruction in the instruction memory area corresponding to the RTL module and passes it into the instruction decoder. The instruction decoder can decode the running instruction and configure the RTL module according to the running instruction so that the RTL module performs the computing task.

[0061] The reference model component is a functional module with the execution function of the chip computing core, which is used to simulate the function of the RTL module in the chip computing core. The reference model component can receive the register configuration information of each computing task executed by the simulation control component, and send a request for reading data to the memory management component according to the register configuration information to obtain the data and perform corresponding operations, and finally save the output data after the operation in the memory inside the reference model component.

[0062] It should be noted that the embodiments of the present application do not limit the implementation programming language of the reference model component. Different reference model components based on programming languages ​​can be C model, SV model, SystemC model, Python model, etc.

[0063] In some embodiments, when the chip computing core completes a single computing task, an end signal is generated. The simulation control component can input the register configuration information into the reference model component in response to the end signal generated after the single computing task is completed. The reference model component reads the input data in the sub-memory area according to the register configuration information, and performs the computing task based on the input data to obtain a reference result of the computing task, and stores the reference result in the internal memory.

[0064] The comparison component is used to receive the register configuration information of each executed computing task sent by the simulation control component, and according to the register configuration information, send requests for reading data to the memory management component and the reference model component respectively to obtain the running results of the chip computing core and the reference data of the reference model component, and perform data comparison, and record the comparison results in the simulation log file.

[0065] The simulation report component is used to read and analyze the comparison results in the simulation log file after all calculation tasks are completed, and generate and output a verification simulation report based on the comparison results.

[0066] The data packet transceiver is used to verify the transaction level transmission in the system. The data packet transceiver can capture the electrical signal type request sent by the RTL module for reading data at the specified address, call the memory management component to obtain the data at the specified address, encapsulate the electrical signal type address, memory data and response information (read success or failure) into a data packet format that complies with a specific protocol, convert the data and response information in the data packet into electrical signal type data according to the timing required by the protocol, and drive it to the bus. Similarly, the electrical signal type request sent by the chip RTL module for writing data at the specified address is captured, the memory management component is called to write the data to the specified address, the electrical signal type address, electrical signal type data and response information (write success or failure) are encapsulated into a data packet format that complies with the protocol, the response information in the data packet is converted into an electrical signal type response according to the timing required by the protocol, and driven to the bus.

[0067] like Figure 5 , Figure 6 As shown, Figure 6 A schematic diagram of the verification process of the asynchronous parallel multi-tasking mode provided in an embodiment of the present application. The verification process includes the following steps:

[0068] Step a: The simulation control component can interact with the user based on the simulation interface, and obtain the preset number of tasks to be run (job_num), the test case name and each RTL module ( Figure 5 The upper limit of memory usage of RDMA_a, RDMA_b, WDMA_a).

[0069] Step b: Call the memory management component to set the sub-memory areas of RDMA_a, RDMA_b, and WDMAa according to the upper limit of memory usage. The three sub-memory areas do not overlap.

[0070] Step c: Obtain from the memory management component the memory address range of the sub-memory area of ​​RDMA_a, i.e., (starting address: ending address) = (a, b), the memory address range of the sub-memory area of ​​RDMA_b, i.e., (starting address: ending address) = (c, d), and the memory address range of the sub-memory area of ​​WDMA_a, i.e., (starting address: ending address) = (e, f);

[0071] Step d: Call the memory management component to initialize random data in the sub-memory areas of RDMA_a, RDMA_b, and WDMA_a.

[0072] Step e: According to the acquired test case name, the test case is loaded from the test case pool, and a group of register configuration information of the RTL module under the constraints of the test case is randomly generated. For example, the register configuration information of the RTL module corresponding to the first computing task job0 includes the starting address (RDMA_a_job0_start_addr) and memory capacity (RDMA_a_job0mem_size) of RDMA_a, the starting address (RDMA_b_job0_start_addr) and memory capacity (RDMA_b_job0mem_size) of RDMA_b, and the starting address (WDMA_a_job0_start_addr) and memory capacity (WDMA_a_job0mem_size) of WDMA_a. The register configuration information of the RTL module corresponding to the second computing task job1 can be generated in the next cycle, until the register configuration information of the RTL module corresponding to the three computing tasks job0, job1 and job2 is randomly generated.

[0073] Step f: Randomly generate a new start address RDMA_a_job0_start_addr_new in the range of (a, b-RDMA_a_job0mem_size). Randomly generate a new start address RDMA_b_job0_start_addr_new in the range of (c, d-RDMA_b_iob0mem_size). Randomly generate a new start address WDMA_a_job0_start_addr_new in the range of (e, f-WDMA_a_job0mem_size).

[0074] Step g: Reset the address. Update RDMA_a_job0_start_addr in the register configuration information of the above RTL module to RDMA_a_job0_start_addr_new, RDMA-b-job0_start_addr to RDMA_b_job0_start_addr_new, and WDMA_a_job0_start_addr to WDMA_a_job0_start_addr_new.

[0075] Step h: Store the modified register configuration information into a queue for preservation.

[0076] Step i: Loop through steps e to h, set a variable cnt to represent the number of register configuration information stored in the queue, and increment the variable cnt by 1 each time register configuration information for a computing task is generated, i.e., cnt++, until the number of register configuration information stored in the queue is equal to the preset number of tasks (job_num) that need to be run.

[0077] Step j: Generate running instructions from all register configuration information in the queue, a total of 4 groups of running instructions, namely, the running instructions of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0078] Step k: calling the memory management component to set 4 instruction areas for running instructions that do not overlap with the aforementioned sub-memory areas, namely, instruction memory areas of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0079] Step 1: Write the four sets of running instructions generated above into the corresponding instruction memory areas respectively.

[0080] Step m: In order to meet the requirements of asynchronous triggering, a random start delay is generated, and four simulation delay values ​​are randomly generated, namely delay0, delay1, delay2 and delay3.

[0081] Step n: Start the timer. After the delay of delay0, trigger the command reader of RDMA_a to start ( Figure 5 After the delay of delay1, the instruction reader of RDMA_b is triggered to start ( Figure 5 After the delay of delay2, the instruction reader of CORE_a is triggered to start ( Figure 5 After the delay of delay3, the instruction reader of WDMA_a is triggered to start ( Figure 5 The start trigger 4 shown in the figure) wherein RDMA_a, RDMA_b, CORE_a, and WDMA_a are started in a random order, so that RDMA_a, RDMA_b, CORE_a, and WDMA_a asynchronously and concurrently execute multiple computing tasks.

[0082] Step o: Wait for the electrical signal of WDMA_a, which indicates the completion of a computing task, to be pulled high (task completion mark).

[0083] Step p: When the task end mark is detected, the register configuration information of the RTL module of this operation task is passed to the reference model component, and the reference model component is run once.

[0084] Step q: The register configuration information of the RTL module of this operation task is passed to the comparison component. The comparison component reads the running results output by the RTL module and the reference results output by the reference model component from the memory management component and the reference model component respectively according to the register configuration information, and compares the running results and the reference results. If the comparison is wrong, the error information is recorded in the simulation log file.

[0085] Step r: Loop through steps o to q, set a variable finish to represent the loop count, and increment the variable tinish by 1 each time a computation task is executed, i.e. finish++, until the loop count equals the preset number of tasks to be run (job_num), and the simulation ends.

[0086] Step s: The simulation report component analyzes the simulation log file and generates a verification simulation report, wherein the verification simulation report includes a first simulation result (PASS) representing a pass and a first simulation result (FAIL) representing a fail.

[0087] The chip verification system in asynchronous parallel multi-tasking mode provided by the present application is described below with reference to a specific embodiment.

[0088] Embodiment 1

[0089] One test case repeatedly executes 100 computing tasks, and the storage capacity of the static random access memory (SRAM) is 8M.

[0090] Step a: The simulation control component obtains the preset number of tasks to be run based on the simulation interface, job_num=100, obtains the name of the test case to be executed, job_name=padding, and obtains the upper limit of memory usage of the specified RDMA_a, RDMA_b, and WDMA_a, which are 2M, 2M, and 3M respectively, that is, limit_size=2M-2M-3M

[0091] Step b: The simulation control component calls the memory management component to set the sub-memory areas of RDMA_a, RDMA_b, and WDMA_a by name respectively. The capacities of the sub-memory areas are 2M, 2M, and 3M respectively, and the three sub-memory areas do not overlap.

[0092] Step c: The simulation control component obtains the memory address range of RDMA_a, i.e., (starting address: ending address) = (0.2M, 2.2M), the memory address range of RDMA_b, i.e., (starting address: ending address) = (2.5M, 4.5M), and the memory address range of WDMA_a, i.e., (starting address: ending address) = (4.9M, 7.9M) from the memory management component.

[0093] Step d: The simulation control component calls the memory management component to initialize random data in the memory ranges of (0.2M.2.2M), (2.5M, 4.5M), and (4.9M, 7.9M).

[0094] Step e: The simulation control component loads the test case from the test case pool according to the test case name padding, and randomly generates a set of register configuration information of the RTL module under the constraints of the test case. For example, in the first cycle, the first operation task RDMA_a_job0_start_addr=0.7M, RDMA_a_job0_mem_size=0.9M; RDMA_b_job0_start_addr=3.6M, RDMA_b_job0_mem_size=1.3M; WDMA_a_job0_start_addr=5.6M, WDMA_a_job0_mem_size=2M.

[0095] Step f: The simulation control component randomly generates RDMA_a_job0_start_addrnew=0.5M in the range of (0.2M, 2.2M-0.9M), randomly generates RDMA_b_job0_start_addr_new=3M in the range of (2.5M, 4.5M-1.3M), and randomly generates WDMA_a_job0_start_addr_new=5M in the range of (4.9M, 7.9M-2M).

[0096] Step g: The simulation control component resets the address. The RDMA_a_job0_start_addr value in the register configuration information of the above RTL module is updated to 0.5M, the RDMA_b_job0_start_addr value is updated to 3M, and the WDMA_a_job0_start_addr value is updated to 5M.

[0097] Step h: The simulation control component stores the modified register configuration information in a queue for preservation.

[0098] Step i: The simulation control component executes steps e to h 99 times in a loop until the amount of register configuration information stored in the queue is equal to 100.

[0099] Step j: The simulation control component generates running instructions from all register configuration information in the queue, a total of 4 groups of instructions, namely, the running instructions of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0100] Step k: The simulation control component calls the memory management component to set four instruction memory areas for running instructions that do not overlap with the aforementioned sub-memory areas, namely, the instruction memory areas of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0101] Step 1: Write the four sets of running instructions generated above into the corresponding instruction memory area respectively, and record the starting address and instruction length of the running instructions. For example, it can be expressed in the form of (starting address (instr_addr), instruction length (instr_size)), then RDMA_a = (0M, 1K), RDMA_b = (0.01M, 1K), CORE_a = (0.02M, 3K), WDMA_a = (0.04M, 2K).

[0102] Step m: The simulation control component randomly generates 4 simulation delays, namely delay0=100ns, delay1=20ns, delay2=90ns, delay3=6000ns.

[0103] Step n: Start the timer, and at 20ns, trigger the command reader of RDMA_b to start. At 90ns, trigger the command reader of CORE_a to start. At 100ns, trigger the command reader of RDMA_a to start. At 6000ns, trigger the command reader of WDMA_a to start.

[0104] Step o: Wait for the electrical signal of WDMA_a, which indicates the completion of a computing task, to be pulled high (task completion mark).

[0105] Step p: When the task end mark is detected, the register configuration information of the RTL module of this operation task is passed to the reference model component, and the reference model component is run once.

[0106] Step q: The register configuration information of the RTL module of this operation task is passed to the comparison component. The comparison component reads the running results output by the RTL module and the reference results output by the reference model component from the memory management component and the reference model component respectively according to the register configuration information, and compares the running results and the reference results. If the comparison is wrong, the error information is recorded in the simulation log file.

[0107] Step r: Loop through steps o to q 99 times until the loop count equals the preset number of tasks to be run (job_num), and the simulation ends.

[0108] Step s: The simulation report component analyzes the simulation log file and generates a verification simulation report.

[0109] Embodiment 2

[0110] A certain type of test case is specified, and 50 computing tasks are extracted from it. The storage capacity of the static random access memory (SRAM) is 12M.

[0111] Step a: The simulation control component obtains the preset number of tasks that need to be run job_nm=50 based on the simulation interface, obtains the subdirectory name of the test case pool to be extracted job_list=float_list, and obtains the memory usage upper limits of the specified RDMA_a, RDMA_b, and WDMA_a, which are 2M, 2M, and 3M respectively, that is, limit_size=2M-2M-3M.

[0112] Step b: The simulation control component calls the memory management component to set the sub-memory areas of RDMA_a, RDMA_b, and WDMAa respectively by name. The capacities of the sub-memory areas are 2M, 2M, and 3M respectively, and the three sub-memory areas do not overlap.

[0113] Step c: The simulation control component obtains the memory address range of RDMA_a, i.e., (starting address: ending address) = (0.2M, 2.2M), the memory address range of RDMA_b, i.e., (starting address: ending address) = (2.5M, 4.5M), and the memory address range of WDMA_a, i.e., (starting address: ending address) = (4.9M, 7.9M) from the memory management component.

[0114] Step d: The simulation control component calls the memory management component to initialize random data in the memory ranges of (0.2M.2.2M), (2.5M, 4.5M), and (4.9M, 7.9M).

[0115] Step e: The simulation control component randomly extracts one test case of this type from the float_list subdirectory of the test case pool according to the subdirectory name float_list of the test case pool, and randomly generates a set of register configuration information of the RTL module under the constraints of the test case. For example, in the first cycle, the first operation task RDMA_a_job0_start_addr=0.7M, RDMA_a_job0_mem_size=0.9M; RDMA_b_job0_start_addr=3.6M, RDMA_b_job0_mem_size=1.3M; WDMA_a_job0_start_addr=5.6M, WDMA_a_job0_mem_size=2M.

[0116] Step f: The simulation control component randomly generates RDMA_a_job0_start_addr_new=0.5M in the range of (0.2M, 2.2M-0.9M), randomly generates RDMA_b_job0_start_addr_new=3M in the range of (2.5M, 4.5M-1.3M), and randomly generates WDMA_a_job0_start_addr_new=5M in the range of (4.9M, 7.9M-2M).

[0117] Step g: The simulation control component resets the address. The RDMA_a_job0_start_addr value in the register configuration information of the above RTL module is updated to 0.5M, the RDMA_b_job0_start_addr value is updated to 3M, and the WDMA_a_job0_start_addr value is updated to 5M.

[0118] Step h: The simulation control component stores the modified register configuration information in a queue for preservation.

[0119] Step i: The simulation control component loops through steps e to h 49 times until the amount of register configuration information stored in the queue is equal to 100.

[0120] Step j: The simulation control component generates running instructions from all register configuration information in the queue, a total of 4 groups of instructions, namely, the running instructions of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0121] Step k: The simulation control component calls the memory management component to set four instruction memory areas for running instructions that do not overlap with the aforementioned sub-memory areas, namely, the instruction memory areas of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0122] Step 1: Write the four sets of running instructions generated above into the corresponding instruction memory area respectively, and record the starting address and instruction length of the running instructions. For example, it can be expressed in the form of (starting address (instr_addr), instruction length (ins_tr_size)), then RDMA_a = (0M, 1K), RDMA_b = (0.01M, 1K), CORE_a = (0.02M, 3K), WDMA_a = (0.04M, 2K).

[0123] Step m: The simulation control component randomly generates 4 simulation delays, namely delay0=100ns, delay1=20ns, delay2=90ns, delay3=6000ns.

[0124] Step n: Start the timer, and at 20ns, trigger the command reader of RDMA_b to start. At 90ns, trigger the command reader of CORE_a to start. At 100ns, trigger the command reader of RDMA_a to start. At 6000ns, trigger the command reader of WDMA_a to start.

[0125] Step o: Wait for the electrical signal of WDMA_a, which indicates the completion of a computing task, to be pulled high (task completion mark).

[0126] Step p: When the task end mark is detected, the register configuration information of the RTL module of this operation task is passed to the reference model component, and the reference model component is run once.

[0127] Step q: The register configuration information of the RTL module of this operation task is passed to the comparison component. The comparison component reads the running results output by the RTL module and the reference results output by the reference model component from the memory management component and the reference model component respectively according to the register configuration information, and compares the running results and the reference results. If the comparison is wrong, the error information is recorded in the simulation log file.

[0128] Step r: Loop through steps o to q 49 times until the loop count equals the preset number of tasks to be run (job_num), and the simulation ends.

[0129] Step s: The simulation report component analyzes the simulation log file and generates a verification simulation report.

[0130] Embodiment 3

[0131] Test cases are randomly selected, from which 80 computing tasks are extracted. The storage capacity of the static random access memory (SRAM) is 16M.

[0132] Step a: The simulation control component obtains the preset number of tasks job_num=80 that need to be run based on the simulation interface, obtains the subdirectory name job_list=all of the test case pool to be extracted, and obtains the memory usage upper limits of the specified RDMA_a, RDMA_b, and WDMA_a, which are 2M, 2M, and 3M respectively, that is, limit_size=2M-2M-3M.

[0133] Step b: The simulation control component calls the memory management component to set the sub-memory areas of RDMA_a, RDMA_b, and WDMAa respectively by name. The capacities of the sub-memory areas are 2M, 2M, and 3M respectively, and the three sub-memory areas do not overlap.

[0134] Step c: The simulation control component obtains the memory address range of RDMA_a, i.e., (starting address: ending address) = (0.2M, 2.2M), the memory address range of RDMA_b, i.e., (starting address: ending address) = (2.5M, 4.5M), and the memory address range of WDMA_a, i.e., (starting address: ending address) = (4.9M, 7.9M) from the memory management component.

[0135] Step d: The simulation control component calls the memory management component to initialize random data in the memory ranges of (0.2M.2.2M), (2.5M, 4.5M), and (4.9M, 7.9M).

[0136] Step e: The simulation control component randomly extracts one test case from the entire test case pool according to job_list=all, and randomly generates a set of register configuration information of the RTL module under the constraints of the test case. For example, in the first cycle, the first operation task RDMA_a_job0_start_addr=0.7M, RDMA_a_job0_mem_size=0.9M; RDMA_b_job0_start_addr=3.6M, RDMA_b_job0_mem_size=1.3M; WDMA_a_job0_start_addr=5.6M, WDMA_a_job0_mem_size=2M.

[0137] Step f: The simulation control component randomly generates RDMA_a_job0_start_addr_new=0.5M in the range of (0.2M, 2.2M-0.9M), randomly generates RDMA_b_job0_start_addr_new=3M in the range of (2.5M, 4.5M-1.3M), and randomly generates WDMA_a_job0_start_addr_new=5M in the range of (4.9M, 7.9M-2M).

[0138] Step g: The simulation control component resets the address. The RDMA_a_job0_start_addr value in the register configuration information of the above RTL module is updated to 0.5M, the RDMA_b_job0_start_addr value is updated to 3M, and the WDMA_a_job0_start_addr value is updated to 5M.

[0139] Step h: The simulation control component stores the modified register configuration information in a queue for preservation.

[0140] Step i: The simulation control component executes steps e to h 79 times in a loop until the amount of register configuration information stored in the queue is equal to 100.

[0141] Step j: The simulation control component generates running instructions from all register configuration information in the queue, a total of 4 groups of instructions, namely, the running instructions of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0142] Step k: The simulation control component calls the memory management component to set four instruction memory areas for running instructions that do not overlap with the aforementioned sub-memory areas, namely, the instruction memory areas of RDMA_a, RDMA_b, CORE_a, and WDMA_a.

[0143] Step 1: Write the four sets of running instructions generated above into the corresponding instruction memory area respectively, and record the starting address and instruction length of the running instructions. For example, it can be expressed in the form of (starting address (instr_addr), instruction length (instr_size)), then RDMA_a = (0M, 1K), RDMA_b = (0.01M, 1K), CORE_a = (0.02M, 3K), WDMA_a = (0.04M, 2K).

[0144] Step m: The simulation control component randomly generates 4 simulation delays, namely delay0=100ns, delay1=20ns, delay2=90ns, delay3=6000ns.

[0145] Step n: Start the timer, and at 20ns, trigger the command reader of RDMA_b to start. At 90ns, trigger the command reader of CORE_a to start. At 100ns, trigger the command reader of RDMA_a to start. At 6000ns, trigger the command reader of WDMA_a to start.

[0146] Step o: Wait for the electrical signal of WDMA_a, which indicates the completion of a computing task, to be pulled high (task completion mark).

[0147] Step p: When the task end mark is detected, the register configuration information of the RTL module of this operation task is passed to the reference model component, and the reference model component is run once.

[0148] Step q: The register configuration information of the RTL module of this operation task is passed to the comparison component. The comparison component reads the running results output by the RTL module and the reference results output by the reference model component from the memory management component and the reference model component respectively according to the register configuration information, and compares the running results and the reference results. If the comparison is wrong, the error information is recorded in the simulation log file.

[0149] Step r: Loop through steps o to q 79 times until the loop count equals the preset number of tasks to be run (job_num), and the simulation ends.

[0150] Step s: The simulation report component analyzes the simulation log file and generates a verification simulation report.

[0151] The above embodiment is the verification of asynchronous parallel multi-tasking mode, and the chip verification system provided by the embodiment of the present application can also support the verification of synchronous serial multi-tasking mode. Figure 7 The figure is a schematic diagram of the architecture of the chip verification system in the synchronous serial multi-tasking mode provided by the embodiment of the present application. The difference between the verification of the asynchronous parallel multi-tasking mode and the verification of the synchronous serial multi-tasking mode lies in the setting of the instruction memory area and the triggering and starting of the RTL module.

[0152] In synchronous serial multitasking mode, the simulation control component divides an instruction memory area in the total memory area, that is, multiple RTL modules correspond to one instruction memory area.

[0153] After the running instructions are generated based on the register configuration information, the running instructions of multiple RTL modules are written into the instruction memory area. That is, for one computing task, the running instructions of multiple RTL modules can be generated based on the register configuration information of the computing task, and the running instructions of multiple RTL modules are written into one instruction memory area.

[0154] In the synchronous serial multitasking mode, the chip computing core includes an instruction reader and an instruction decoder. For the trigger start of the RTL module, a second simulation delay value can be set. When the simulation control component starts the RTL module, the timer can be started. When the timing value of the timer is equal to the second simulation delay value, the instruction reader of the chip computing core is triggered to start, so that the instruction reader reads the running instructions in the instruction memory area in sequence according to the execution order and passes them to the instruction decoder. The instruction decoder can decode the running instructions and configure the corresponding RTL module according to the running instructions so that the RTL module performs the computing task.

[0155] The chip verification system in synchronous serial multi-tasking mode provided by the present application is described below with reference to a specific embodiment.

[0156] Embodiment 4

[0157] Test cases are randomly selected, from which 80 computing tasks are extracted. The storage capacity of the static random access memory (SRAM) is 18M.

[0158] Step a: The simulation control component obtains the preset number of tasks job_num=80 that need to be run based on the simulation interface, obtains the subdirectory name job_list=all of the test case pool to be extracted, and obtains the memory usage upper limits of the specified RDMA_a, RDMA_b, and WDMA_a, which are 2M, 2M, and 3M respectively, that is, limit_size=2M-2M-3M.

[0159] Step b: The simulation control component calls the memory management component to set the sub-memory areas of RDMA_a, RDMA_b, and WDMAa respectively by name. The capacities of the sub-memory areas are 2M, 2M, and 3M respectively, and the three sub-memory areas do not overlap.

[0160] Step c: The simulation control component obtains the memory address range of RDMA_a, i.e., (starting address: ending address) = (0.2M, 2.2M), the memory address range of RDMA_b, i.e., (starting address: ending address) = (2.5M, 4.5M), and the memory address range of WDMA_a, i.e., (starting address: ending address) = (4.9M, 7.9M) from the memory management component.

[0161] Step d: The simulation control component calls the memory management component to initialize random data in the memory ranges of (0.2M.2.2M), (2.5M, 4.5M), and (4.9M, 7.9M).

[0162] Step e: The simulation control component randomly extracts one test case from the entire test case pool according to job_list=all, and randomly generates a set of register configuration information of the RTL module under the constraints of the test case. For example, in the first cycle, the first operation task RDMA_a_job0_start_addr=0.7M, RDMA_a_job0mem_size=0.9M; RDMA_b_job0_start_addr=3.6M, RDMA_b_job0_mem_size=1.3M; WDMA_a_job0_start_addr=5.6M, WDMA_a_job0_mem_size=2M.

[0163] Step f: The simulation control component randomly generates RDMA_a_job0_start_addrnew=0.5M in the range of (0.2M, 2.2M-0.9M), randomly generates RDMA_b_job0_start_addr_new=3M in the range of (2.5M, 4.5M-1.3M), and randomly generates WDMA_a_job0_start_addr_new=5M in the range of (4.9M, 7.9M-2M).

[0164] Step g: The simulation control component resets the address. The RDMA_a_job0_start_addr value in the register configuration information of the above RTL module is updated to 0.5M, the RDMA_b_job0_start_addr value is updated to 3M, and the WDMA_a_job0_start_addr value is updated to 5M.

[0165] Step h: The simulation control component stores the modified register configuration information in a queue for preservation.

[0166] Step i: The simulation control component executes steps e to h 79 times in a loop until the amount of register configuration information stored in the queue is equal to 100.

[0167] Step j: The simulation control component generates running instructions from all register configuration information in the queue, and only generates one set of running instructions (one trigger, only one set of instructions) as the running instructions of the chip computing core.

[0168] Step k: The simulation control component calls the memory management component to set up an instruction memory area for the running instruction that does not overlap with the aforementioned sub-memory area.

[0169] Step 1: Write the above-generated set of running instructions into the instruction memory area, and record the starting address and instruction length of the running instructions, for example: (nstr_addr, instr_size) = (0M, 100K).

[0170] Step m: The simulation control component randomly generates a simulation delay, delay0=10ns.

[0171] Step n: Start the timer, and at 10ns, trigger the instruction reader of the chip computing core to start ( Figure 7 The start trigger 1 shown in the figure) enables RDMA_a, RDMA_b, CORE_a, and WDMA_a to synchronously and serially execute multiple computing tasks.

[0172] Step o: Wait for the electrical signal of WDMA_a, which indicates the completion of a computing task, to be pulled high (task completion mark).

[0173] Step p: When the task end mark is detected, the register configuration information of the RTL module of this operation task is passed to the reference model component, and the reference model component is run once.

[0174] Step q: The register configuration information of the RTL module of this operation task is passed to the comparison component. The comparison component reads the running results output by the RTL module and the reference results output by the reference model component from the memory management component and the reference model component respectively according to the register configuration information, and compares the running results and the reference results. If the comparison is wrong, the error information is recorded in the simulation log file.

[0175] Step r: Loop through steps o to q 79 times until the loop count equals the preset number of tasks to be run (job_num), and the simulation ends.

[0176] Step s: The simulation report component analyzes the simulation log file and generates a verification simulation report.

[0177] In this embodiment, in order to realize the reuse of RTL modules in the project, the verification system is compatible with the asynchronous parallel multi-tasking mode and the synchronous serial multi-tasking mode, and supports the operation of both the asynchronous parallel multi-tasking mode and the synchronous serial multi-tasking mode. Figure 8 As shown, the verification system supports the situation where addresses overlap between multiple computing tasks to ensure the randomness of address verification, ensure that the simulation is closer to the real scene, and thus ensure the completeness of address verification.

[0178] The verification system supports running multiple computing tasks continuously to deal with the problem of a large number of disassembly tasks for complex operators, and can cover the needs of complex operators. It can be compatible with both single-task and multi-task modes, which is convenient for early RTL debugging. For a single task, just specify job_num=1, and for multi-task, specify job_num>1. It supports specifying a specific task order to run multiple computing tasks, and supports simulating the real operation scenario of the operator. It supports executing the same computing task multiple times in a row to increase the randomness of verification. It supports extracting a specified type and a specified number of test cases from the test case pool to run multiple computing tasks, which is suitable for scenarios where only a certain type of test case may need to be re-debugged after the specific function of the RTL is modified. It supports randomly extracting a specified number of test cases from the test case pool to run multiple computing tasks, increasing the randomness of verification and the richness of scenarios.

[0179] Based on the above chip verification system. Some embodiments of the present application also provide a chip verification method, which is applied to the chip verification system described in the above embodiment. The method comprises the following steps:

[0180] A test case is obtained. The test case includes multiple computing tasks of a chip computing core, and the chip computing core includes multiple register transfer level modules.

[0181] The sub-memory area and instruction memory area of ​​the register transfer level module are set in the total memory area. The sub-memory area is set based on the upper limit of the memory usage of the register transfer level module. In the total memory area, multiple sub-memory areas do not overlap with each other, and the sub-memory area does not overlap with the instruction memory area.

[0182] The register configuration information of the operation task is set according to the test case and the sub-memory area. The register configuration information is the configuration information required by the register when the register transfer level module performs the operation task. The register configuration information includes the memory start address and memory capacity.

[0183] Generate an operation instruction based on the register configuration information and write the operation instruction into the instruction memory area. The operation instruction is used to control the register transfer level module to perform the operation task according to the register configuration information.

[0184] The register transfer level module reads the running instruction in the instruction memory area, and executes the operation task based on the running instruction to obtain the operation result of the operation task.

[0185] The same and similar parts between the various embodiments in this specification can be referenced to each other and will not be described again here.

[0186] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A chip verification method, characterized in that: The method comprises: Acquire a test case, wherein the test case includes a plurality of computing tasks of a chip computing core, and the chip computing core includes a plurality of register transfer level modules; A sub-memory area and an instruction memory area of ​​the register transfer level module are set in the total memory area, wherein the sub-memory area is set based on an upper limit value of memory usage of the register transfer level module; in the total memory area, multiple sub-memory areas do not overlap with each other, and the sub-memory area does not overlap with the instruction memory area; The register configuration information of the computing task is set according to the test case and the sub-memory area, wherein the register configuration information is the configuration information required by the register when the register transfer level module executes the computing task; the register configuration information includes a memory start address and a memory capacity; Generate an operation instruction based on the register configuration information, and write the operation instruction into the instruction memory area, wherein the operation instruction is used to control the register transfer level module to perform the operation task according to the register configuration information; The register transfer level module reads the running instruction in the instruction memory area, and executes the computing task based on the running instruction to obtain the running result of the computing task.

2. The chip verification method according to claim 1, characterized in that: The step of setting a sub-memory region of a register transfer level module in a total memory region comprises: Obtaining a memory usage upper limit value of the register transfer level module; The total memory area is divided into sub-memory areas according to the memory usage upper limit value, and the sub-memory areas are memory address sets that can be used by the register transfer level module in the total memory area.

3. The chip verification method according to claim 1, characterized in that: The step of setting the instruction memory area of ​​the register transfer level module in the total memory area comprises: Obtaining the module quantity of the register transfer level module; Divide the instruction memory areas corresponding to the multiple register transfer level modules in the total memory area according to the number of modules; The step of writing the running instruction into the instruction memory area comprises: The operation instructions of the multiple register transfer level modules are respectively written into the instruction memory areas corresponding to the register transfer level modules.

4. The chip verification method according to claim 1, characterized in that: The step of setting register configuration information of a computing task according to the test case and the sub-memory area comprises: Setting a memory capacity according to the test case, the memory capacity being the memory capacity required by the register transfer level module when executing the computing task; A memory start address is set according to the memory capacity and the sub-memory area, the memory start address is the start address when the register transfer level module executes the calculation task, the memory start address is between the start address and the upper limit address of the sub-memory area, and the upper limit address is the memory address obtained by subtracting the memory capacity from the end address of the sub-memory area.

5. The chip verification method according to claim 3, characterized in that: The step of reading the execution instruction in the instruction memory area through the register transfer level module comprises: Setting a first simulation delay value for each of the plurality of register transfer level modules; Start the timer; When the timing value of the timer is equal to the first simulation delay value corresponding to the register transfer stage module, the register transfer stage module is controlled to read the running instruction from the instruction memory area corresponding to the register transfer stage module.

6. The chip verification method according to claim 1, characterized in that: The step of setting the instruction memory area of ​​the register transfer level module in the total memory area comprises: dividing the instruction memory area in the total memory area; The step of writing the running instruction into the instruction memory area comprises: Writing the operation instructions of the plurality of register transfer level modules into the memory area.

7. The chip verification method according to claim 6, characterized in that: The step of reading the execution instruction in the instruction memory area through the register transfer level module comprises: Set the second simulation delay; Start the timer; When the timing value of the timer is equal to the second simulation delay value, the plurality of register transfer level modules are controlled to read the execution instructions in the instruction memory area in sequence.

8. The chip verification method according to claim 1, characterized in that: The method further comprises: Writing random data into the sub-memory area; Reading input data in the sub-memory area according to the operation instruction through the register transfer level module, and executing the operation task based on the input data to obtain the operation result of the operation task; The operation result is written into the sub-memory area.

9. The chip verification method according to claim 8, characterized in that: The method further comprises: In response to an end signal generated after a single computing task is completed, inputting the register configuration information into a reference model component, wherein the reference model component is a functional module having an execution function of a chip computing core; Reading input data in the sub-memory area according to the register configuration information through the reference model component, and executing the computing task based on the input data to obtain a reference result of the computing task; Comparing the operation result with the reference result to obtain a comparison result; Generate a verification simulation report according to the comparison result; The verification simulation report is output.

10. A chip verification system, characterized in that: It includes simulation control components and chip computing cores; among which: The simulation control component is used to obtain a test case, wherein the test case includes a plurality of computing tasks of a chip computing core, and the chip computing core includes a plurality of register transfer level modules; A sub-memory area and an instruction memory area of ​​the register transfer level module are set in the total memory area, wherein the sub-memory area is set based on an upper limit value of memory usage of the register transfer level module; in the total memory area, multiple sub-memory areas do not overlap with each other, and the sub-memory area does not overlap with the instruction memory area; The register configuration information of the computing task is set according to the test case and the sub-memory area, wherein the register configuration information is the configuration information required by the register when the register transfer level module executes the computing task; the register configuration information includes a memory start address and a memory capacity; Generate an operation instruction based on the register configuration information, and write the operation instruction into the instruction memory area, wherein the operation instruction is used to control the register transfer level module to perform the operation task according to the register configuration information; The chip operation core is used to read the operation instruction in the instruction memory area through the register transfer level module, and execute the operation task based on the operation instruction to obtain the operation result of the operation task.

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