Broadband delay phase-locked loop circuit and delay method thereof

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a broadband delay phase-locked loop circuit and a delay method thereof, and the circuit comprises a delay line which is used for receiving an input signal and outputting first to Nth output signals based on the input signal; the input end of the phase discriminator is connected with the output end of the delay line, and the phase discriminator is used for detecting the phase difference between the input signal and the Nth output signal and generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals; the input end of the averager is connected with the output end of the phase discriminator, and the averager is used for calculating the average value of the first pulse width signal to the Mth pulse width signal; the input end of the integrator is connected with the output end of the averager, the output end of the integrator is connected with the input end of the delay line, and the integrator is used for receiving the average value and generating target control voltage to the delay line based on the average value, so that the delay line is delayed based on the target control voltage.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a broadband delay phase-locked loop circuit and a delay method thereof. Background Art

[0002] Delay-Locked-Loop (DLL) is widely used in high-speed clock generation, memory interface, high-speed communication and other fields due to its high locking accuracy, PVT stability and good jitter characteristics. Figure 1 As shown, it includes a phase detector (PD), a charge pump (CP), a low-pass filter (LF) and a voltage-controlled delay line (VCDL). The CP and LF can also be replaced by an integrator. The VCDL is usually composed of multiple delay cells. The PD controls the charging and discharging of the CP or the integrator by comparing the phase difference between the input reference clock CLK_IN and the output clock CLK_OUT, thereby controlling the control voltage VC of the VCDL.

[0003] like Figure 2 (a) shows a widely used PD structure, called a phase frequency detector (PFD), which includes a first D flip-flop, a second D flip-flop, and an AND gate. When UP and DN are both 0, the rising edge of CLK_IN and the rising edge of CLK_OUT set UP and DN to 1 respectively. When UP and DN are both 1, the reset terminal RST is valid, and UP and DN are reset to 0. Figure 2(b) shows the PFD output curve. Due to the different initial values ​​of UP and DN when the PFD circuit enters the operating state, a given input phase difference corresponds to two different outputs. When UP is initially 1 and DN is initially 0, the PFD defines CLK_IN as preceding CLK_OUT; when UP is initially 0 and DN is initially 1, the PFD defines CLK_OUT as preceding CLK_IN. When both UP and DN are initially 0, the PFD will interpret the actual sequence of CLK_OUT and CLK_IN. When both UP and DN are initially 1, the reset terminal RST is active, which is equivalent to the case where both UP and DN are initially 0. If the PFD's defined sequence does not match the actual sequence, the PFD is considered to have entered an error state. The main problems with the above structure are: First, when the input phase difference is less than 2π, the PFD in the error state will attempt to lock the phase difference to 0, and after stabilization, the DLL enters the error lock state with the minimum VCDL delay. Second, when the input phase is between 2π and 4π, the PFD in the error state will attempt to lock the phase difference to 4π, and after stabilization, the DLL enters the second harmonic lock state. Furthermore, when the input phase is greater than 4π, the DLL enters the harmonic lock state after stabilization, regardless of whether the PFD is in the error state. Due to these problems of error lock and harmonic lock, the operating frequency range of DLLs with typical structures and using PFDs is significantly limited.

[0004] One current solution involves introducing an external reset or start signal. The simplest implementation uses the reset signal to reset the VC, minimizing the initial VCDL delay. However, this approach doesn't address the false lock issue, and therefore requires additional false lock detection circuitry. Improved implementations utilize the reset signal to quantize the input signal period, selecting the appropriate delay cell type, number of delay cells, or initial VC value based on the period length. However, these approaches not only require additional reset and detection circuitry but also fail to address false lock and harmonic lock issues caused by clock signal noise, signal frequency variations, and other factors during DLL operation.

[0005] To solve this problem, another type of current solution eliminates the external reset or start signal, one of which is a representative structure such as Figure 3As shown in the figure, in addition to the typical DLL architecture's phase detector (PD), charge pump (CP), low-pass filter (LF), and voltage-controlled delay line (VCDL), the structure also includes a duty cycle correction circuit (DCC), a pulse generator (Pulse Generator), a harmonic lock and false lock detector (HFLD), an auxiliary charge pump (AUX CP), and an auxiliary voltage-controlled delay line (AUX VCDL). The PD controls the charge and discharge of CP by comparing the phase difference between the input reference clock CLK_IN and the output clock CLK_OUT, thereby controlling the control voltage VC of the VCDL. For ease of description, it is assumed that a higher VC value increases the VCDL delay. The DCC and pulse generator generate a clock signal CLK_B with a period of nT and a pulse width of 0.5T, where n is a positive integer and T is the period of CLK_IN. The specific structure of the pulse generator depends on the value of n. Both the AUX VCDL and the VCDL contain the same m-stage delay unit, where m is a positive even number, and their control voltage is the same VC. CLK_A and CLK_C are the output clock signals of the (0.5mk)th and (0.5m+k)th delay units in the AUXVCDL, respectively. k is a positive integer less than 0.5m. Due to non-ideal factors such as VCDL and AUXVCDL delays not being exactly the same and the CLK_B pulse width not being strictly 0.5T, the k value should generally not be too small. CLK_A, CLK_C, and CLK_B together serve as the input signals of the Harmonic & False Lock Detector. The output signal EN_A controls the CP to stop operation, while UP_A and DN_A control the charging and discharging of the AUXCP, respectively. When the DLL is in the normal lock state, since CLK_B has a pulse width of 0.5T, the arrival time of the CLK_B falling edge should be later than the CLK_A rising edge and earlier than the CLK_C rising edge. At this time, UP_A, UP_B, and EN_A are all 0, CP works normally, and AUX CP does not work; when the CLK_B falling edge is earlier than the CLK_A rising edge, it indicates that a harmonic lock problem may have occurred. At this time, UP_A is 0, EN_A and DN_A have high-level pulse signals, CP stops working, AUX CP discharges, VC decreases, and VCDL delay decreases; when the CLK_B falling edge is later than the CLK_C rising edge, it indicates that a false lock problem may have occurred. At this time, DN_A is 0, EN_A and UP_A have high-level pulse signals, CP stops working, AUX CP charges, VC increases, and VCDL delay increases.

[0006] However, this design and the existing solutions it represents can solve the problems of false lock and harmonic lock without the need for an external reset or start signal. However, it usually requires additional circuit structures including but not limited to a harmonic lock detector, a false lock detector, an auxiliary delay line, an auxiliary loop, multiple control voltages, etc., which are not only more complex to implement but also require more area and power consumption. Summary of the Invention

[0007] The present application provides a broadband delay phase-locked loop circuit and its delay method to solve the technical solutions in the prior art for solving the problems of false lock and harmonic lock without the need for an external reset or start signal. These solutions usually require additional circuit structures including but not limited to a harmonic lock detector, a false lock detector, an auxiliary delay line, an auxiliary loop, multiple control voltages, etc., which are not only more complex to implement but also require more area and power consumption.

[0008] According to a first aspect of the present application, an embodiment provides a broadband delay-locked loop circuit, comprising: a delay line for receiving an input signal and outputting first to Nth output signals based on the input signal, wherein N is an integer; a phase detector, wherein the input end of the phase detector is connected to the output end of the delay line, the phase detector is used to detect the phase difference between the input signal and the Nth output signal, and generate first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, wherein M is an integer; an averager, wherein the input end of the averager is connected to the output end of the phase detector, and is used to calculate the average value of the first to Mth pulse width signals; an integrator, wherein the input end of the integrator is connected to the output end of the averager, and the output end of the integrator is connected to the input end of the delay line, and is used to receive the average value and generate a target control voltage to the delay line based on the average value, so that the delay line is delayed based on the target control voltage.

[0009] Optionally, when N is 8, the delay line includes: a first delay unit, wherein the first input end of the first delay unit receives the input signal, the first input end and the output end of the first delay unit are connected to the phase detector, and the second input end of the first delay unit is connected to the output end of the integrator for outputting a first output signal; a second delay unit, wherein the first input end of the second delay unit is respectively connected to the output end of the first delay unit and the phase detector, the output end of the second delay unit is connected to the phase detector, and the second input end of the second delay unit is connected to the output end of the integrator. for outputting a second output signal; a third delay unit, wherein the first input end of the third delay unit is respectively connected to the output end of the second delay unit and the phase detector, the output end of the third delay unit is connected to the phase detector, and the second input end of the third delay unit is connected to the output end of the integrator, for outputting a third output signal; a fourth delay unit, wherein the first input end of the fourth delay unit is connected to the output end of the third delay unit and the phase detector, the output end of the fourth delay unit is connected to the phase detector, and the second input end of the fourth delay unit is connected to the output end of the integrator, for outputting a fourth output signal output signal; a fifth delay unit, wherein the first input end of the fifth delay unit is connected to the output end of the fourth delay unit and the phase detector, the second input end of the fifth delay unit is connected to the output end of the integrator, and the output end of the fifth delay unit is connected to the phase detector for outputting a fifth output signal; a sixth delay unit, wherein the first input end of the sixth delay unit is respectively connected to the output end of the fifth delay unit and the phase detector, the second input end of the sixth delay unit is connected to the output end of the integrator, and the output end of the sixth delay unit is connected to the phase detector for outputting a sixth output signal ; A seventh delay unit, wherein the first input end of the seventh delay unit is respectively connected to the output end of the sixth delay unit and the phase detector, the second input end of the seventh delay unit is connected to the output end of the integrator, and the output end of the seventh delay unit is connected to the phase detector for outputting a seventh output signal; an eighth delay unit, wherein the first input end of the eighth delay unit is respectively connected to the output end of the seventh delay unit and the phase detector, the second input end of the eighth delay unit is connected to the output end of the integrator, and the output end of the eighth delay unit is connected to the phase detector for outputting an eighth output signal.

[0010] Optionally, the phase detector includes: a plurality of inhibit gates, the input ends of the plurality of inhibit gates being connected to the delay line, for detecting the phase difference between the input signal and the Nth output signal; a plurality of four-input OR gates, the input ends of the plurality of four-input OR gates being connected to the output ends of the plurality of inhibit gates, the output ends of the plurality of four-input OR gates being connected to the averager, for generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals.

[0011] Optionally, the multiple prohibition gates include: a first prohibition gate, wherein the first input end of the first prohibition gate is connected to the first input end of the first delay unit, the second input end of the first prohibition gate is respectively connected to the output end of the first delay unit and the first input end of the second delay unit, and the output end of the first prohibition gate is connected to the multiple four-input OR gates; a second prohibition gate, wherein the first input end of the second prohibition gate is respectively connected to the second input end of the first prohibition gate, the output end of the first delay unit and the first input end of the second delay unit, and the second input end of the second prohibition gate is connected to the output end of the second delay unit and the first input end of the third delay unit. The output end of the second inhibiting gate is connected to the multiple four-input OR gates; a third inhibiting gate, the first input end of the third inhibiting gate is respectively connected to the second input end of the second inhibiting gate, the output end of the second delay unit and the first input end of the third delay unit, the second input end of the third inhibiting gate is connected to the output end of the third delay unit and the first input end of the fourth delay unit, and the output end of the third inhibiting gate is connected to the multiple four-input OR gates; a fourth inhibiting gate, the first input end of the fourth inhibiting gate is respectively connected to the second input end of the third inhibiting gate, the output end of the third delay unit and the first input end of the fourth delay unit, and the second input end of the fourth inhibiting gate is connected to the output end of the third delay unit and the first input end of the fourth delay unit. The input end is respectively connected to the output end of the fourth delay unit and the first input end of the fifth delay unit, and the output end of the fourth prohibition gate is connected to the multiple four-input OR gates; a fifth prohibition gate, the first input end of the fifth prohibition gate is respectively connected to the second input end of the fourth prohibition gate, the output end of the fourth delay unit and the first input end of the fifth delay unit, the second input end of the fifth prohibition gate is respectively connected to the output end of the fifth delay unit and the first input end of the sixth delay unit, and the output end of the fifth prohibition gate is connected to the multiple four-input OR gates; a sixth prohibition gate, the first input end of the sixth prohibition gate is respectively connected to the second input end of the fifth prohibition gate, the output end of the the output end of the fifth delay unit and the first input end of the sixth delay unit are connected, the second input end of the sixth disable gate is respectively connected to the output end of the sixth delay unit and the first input end of the seventh delay unit, and the output end of the sixth disable gate is connected to the multiple four-input OR gates; a seventh disable gate, the first input end of the seventh disable gate is respectively connected to the second input end of the sixth disable gate, the output end of the sixth delay unit and the first input end of the seventh delay unit, the second input end of the seventh disable gate is respectively connected to the output end of the seventh delay unit and the first input end of the eighth delay unit, and the output end of the seventh disable gate is connected to the multiple four-input OR gates;an eighth inhibit gate, wherein a first input end of the eighth inhibit gate is respectively connected to the second input end of the seventh inhibit gate, the output end of the seventh delay unit, and the first input end of the eighth delay unit; a second input end of the eighth inhibit gate is connected to the output end of the eighth delay unit; and an output end of the eighth inhibit gate is connected to the plurality of four-input OR gates;

[0012] Optionally, the multiple four-input OR gates include: a first four-input OR gate, the input ends of the first four-input OR gate are respectively connected to the output end of the first inhibit gate, the output end of the second inhibit gate, the output end of the third inhibit gate and the output end of the fourth inhibit gate, and the output end of the first four-input OR gate is connected to the input end of the averager; a second four-input OR gate, the input ends of the second four-input OR gate are connected to the output end of the fifth inhibit gate, the output end of the sixth inhibit gate, the output end of the seventh inhibit gate and the output end of the eighth inhibit gate, and the output end of the second four-input OR gate is connected to the input end of the averager.

[0013] Optionally, the averager includes: a first resistor and a second resistor, the first resistor and the second resistor are connected in parallel, and both the first resistor and the second resistor are connected to the integrator.

[0014] Optionally, the integrator includes: an amplifier, the non-inverting terminal of the amplifier is connected to the input voltage, and the inverting terminal of the amplifier is connected to the first resistor and the second resistor; a capacitor, one end of the capacitor is connected to the inverting terminal of the amplifier and the first resistor and the second resistor, and the other end of the capacitor is connected to the output terminal of the amplifier.

[0015] Optionally, the delay of the delay line is positively correlated with the target control voltage.

[0016] A second aspect of the present application provides a delay method for a broadband delay phase-locked loop circuit, using the above-mentioned broadband delay phase-locked loop circuit, wherein the method includes: using a delay line to receive an input signal, and outputting first to Nth output signals based on the input signal, wherein N is an integer; detecting the phase difference between the input signal and the Nth output signal by a phase detector, and generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, wherein M is an integer; using an averager to calculate the average value of the first to Mth pulse width signals, and generating a target control voltage to the delay line based on the average value, so that the delay line is delayed based on the target control voltage.

[0017] Optionally, the delay method of the above-mentioned broadband delay phase-locked loop circuit also includes: determining whether the current phase difference between the input signal and the Nth output signal is less than or equal to a first preset value; if the current phase difference is less than or equal to the first preset value, generating current first to Mth pulse width signals based on the current phase difference, using the averager to calculate the average value of the current first to Mth pulse width signals, and using the integrator to generate a first control voltage to the delay line based on the average value of the current first to Mth pulse width signals, so that the delay line increases the delay based on the first control voltage; if the current phase difference is greater than the first preset value and less than or equal to a second preset value, generating current first to Mth pulse width signals based on the current phase difference, using the averager to calculate the average value of the current first to Mth pulse width signals, and using the integrator to generate a second control voltage to the delay line based on the average value of the current first to Mth pulse width signals, so that the delay line reduces the delay based on the second control voltage.

[0018] In the above embodiment, a delay line receives an input signal and outputs first to Nth output signals based on the input signal. A phase detector detects the phase difference between the input signal and the Nth output signal, and generates first to Mth pulse width signals based on the phase difference, the input signal, and the first to Nth output signals. An averager calculates the average of the first to Mth pulse width signals, and based on the average, generates a target control voltage to the delay line, causing the delay line to delay based on the target control voltage. This solves the problem of prior art solutions for false lock and harmonic lock without requiring an external reset or start signal, which typically require additional circuit structures, including but not limited to harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, and multiple control voltages. This not only complicates implementation but also consumes a lot of area and power. This solution eliminates the need for external reset or start signals, and eliminates the need for additional circuit structures, such as harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, and multiple control voltages. It features broadband, multi-phase output, simple implementation, and reduced area and power.

[0019] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of a typical structure of a DLL in the prior art;

[0022] Figure 2Schematic diagram of a PFD circuit and its output curve in the prior art;

[0023] Figure 3 It is a schematic diagram of the circuit structure in the prior art;

[0024] Figure 4 A schematic diagram of a broadband delay-locked loop circuit provided according to an embodiment of the present application;

[0025] Figure 5 Schematic diagram of a broadband delay-locked loop circuit according to one embodiment of the present application;

[0026] Figure 6 is a schematic diagram of an integrator and an averager structure according to one embodiment of the present application;

[0027] Figure 7 Schematic diagram of output curves of an inhibit gate and an OR gate in a phase detector according to one embodiment of the present application;

[0028] Figure 8 Flowchart of a delay method for a wideband delay-locked loop circuit according to an embodiment of the present application.

[0030] 10- wideband delay-locked loop circuit; 100- delay line; 200- phase detector; 300- integrator; 400- averager. DETAILED DESCRIPTION

[0031] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0032] The following describes a broadband delay-locked loop circuit and its delay method according to an embodiment of the present application with reference to the accompanying drawings. With respect to the prior art solutions mentioned in the above background technology for solving the problems of false lock and harmonic lock without the need for an external reset or start signal, which generally require additional circuit structures including but not limited to a harmonic lock detector, a false lock detector, an auxiliary delay line, an auxiliary loop, and multiple control voltages, not only are the implementation methods relatively complex but also require a large area and power consumption. The present application provides a broadband delay-locked loop circuit, in which a delay line is used to receive an input signal and output first to Nth output signals based on the input signal. A phase detector is used to detect the phase difference between the input signal and the Nth output signal, and first to Mth pulse width signals are generated based on the phase difference, the input signal, and the first to Nth output signals. An averager is used to calculate the average value of the first to Mth pulse width signals, and a target control voltage is generated based on the average value to the delay line, so that the delay line is delayed based on the target control voltage. Thus, the technical solutions in the prior art for solving the problems of false locking and harmonic locking without the need for external reset or start signals are solved. Usually, additional circuit structures including but not limited to harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, multiple control voltages, etc. are required, which not only has a relatively complex implementation method but also takes up a large area and consumes a lot of power. Without the need to introduce external reset or start signals, and without the need to use additional circuit structures such as harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, multiple control voltages, etc., the present invention has the characteristics of broadband, multi-phase output, simple implementation, and saving of area and power consumption.

[0033] Specifically, Figure 4 A schematic diagram of a broadband delay-locked loop circuit provided in an embodiment of the present application.

[0034] like Figure 4 As shown, the broadband delay phase-locked loop circuit includes: a delay line 100, a phase detector 200, an averager 400 and an integrator 300.

[0035] Among them, the delay line 100 is used to receive an input signal and output first to Nth output signals based on the input signal, where N is an integer; the input end of the phase detector 200 is connected to the output end of the delay line 100, the phase detector 200 is used to detect the phase difference between the input signal and the Nth output signal, and generate first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, where M is an integer; the input end of the averager 400 is connected to the output end of the phase detector 200, and is used to calculate the average value of the first to Mth pulse width signals; the input end of the integrator 300 is connected to the output end of the averager 400, and the output end of the integrator 300 is connected to the input end of the delay line 100, and is used to receive the average value and generate a target control voltage to the delay line 100 based on the average value, so that the delay line 100 is delayed based on the target control voltage.

[0036] In some embodiments, the delay of the delay line 100 is positively correlated with the target control voltage.

[0037] In the embodiment of the present application, N is 8 and M is 2. Relevant technicians in this field can increase the number of delay unit levels for expansion.

[0038] Optionally, in some embodiments, when N is 8, the delay line 100 includes: a first delay unit 101, wherein the first input end of the first delay unit 101 receives an input signal, the first input end and the output end of the first delay unit 101 are connected to the phase detector 200, and the second input end of the first delay unit 101 is connected to the output end of the integrator 300 for outputting a first output signal; a second delay unit 102, wherein the first input end of the second delay unit 102 is respectively connected to the output end of the first delay unit 101 and the phase detector 200, the output end of the second delay unit 102 is connected to the phase detector 200, and the second input end of the second delay unit 102 is connected to the output end of the integrator 300. , for outputting a second output signal; a third delay unit 103, a first input end of the third delay unit 103 is connected to the output end of the second delay unit 102 and the phase detector 200, respectively, the output end of the third delay unit 103 is connected to the phase detector 200, and the second input end of the third delay unit 103 is connected to the output end of the integrator 300, for outputting a third output signal; a fourth delay unit 104, a first input end of the fourth delay unit 104 is connected to the output end of the third delay unit 103 and the phase detector 200, the output end of the fourth delay unit 104 is connected to the phase detector 200, and the second input end of the fourth delay unit 104 is connected to the output end of the integrator 300, for outputting a third output signal. a fifth delay unit 105, wherein a first input terminal of the fifth delay unit 105 is connected to the output terminal of the fourth delay unit 104 and the phase detector 200, a second input terminal of the fifth delay unit 105 is connected to the output terminal of the integrator 300, and an output terminal of the fifth delay unit 105 is connected to the phase detector 200 for outputting a fifth output signal; a sixth delay unit 106, wherein a first input terminal of the sixth delay unit 106 is connected to the output terminal of the fifth delay unit 105 and the phase detector 200, respectively, a second input terminal of the sixth delay unit 106 is connected to the output terminal of the integrator 300, and an output terminal of the sixth delay unit 106 is connected to the phase detector 200 for outputting a sixth output signal signal; a seventh delay unit 107, a first input end of the seventh delay unit 107 is connected to the output end of the sixth delay unit 106 and the phase detector 200 respectively, a second input end of the seventh delay unit 107 is connected to the output end of the integrator 300, and the output end of the seventh delay unit 107 is connected to the phase detector 200 for outputting a seventh output signal; an eighth delay unit 108, a first input end of the eighth delay unit 108 is connected to the output end of the seventh delay unit 107 and the phase detector 200 respectively, a second input end of the eighth delay unit 108 is connected to the output end of the integrator 300, and the output end of the eighth delay unit 108 is connected to the phase detector 200 for outputting an eighth output signal.

[0039] Optionally, in some embodiments, the phase detector 200 includes: multiple inhibit gates, the input ends of the multiple inhibit gates are connected to the delay line 100, and are used to detect the phase difference between the input signal and the Nth output signal; multiple four-input OR gates, the input ends of the multiple four-input OR gates are connected to the output ends of the multiple inhibit gates, and the output ends of the multiple four-input OR gates are connected to the averager 400, and are used to generate the first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals.

[0040] Optionally, in some embodiments, a plurality of inhibiting gates include: a first inhibiting gate 201, wherein a first input end of the first inhibiting gate 201 is connected to a first input end of the first delay unit 101, a second input end of the first inhibiting gate 201 is respectively connected to an output end of the first delay unit 101 and a first input end of the second delay unit 101, and an output end of the first inhibiting gate 201 is connected to a plurality of four-input OR gates; a second inhibiting gate 202, wherein a first input end of the second inhibiting gate 202 is respectively connected to a second input end of the first inhibiting gate 201, an output end of the first delay unit 101, and a first input end of the second delay unit 102, and a second input end of the second inhibiting gate 202 is respectively connected to an output end of the second delay unit 102 and a first input end of the third delay unit 103. The first input end of the third prohibition gate 203 is connected to the second input end of the second prohibition gate 202, the output end of the second delay unit 102 and the first input end of the third delay unit 103 respectively, the second input end of the third prohibition gate 203 is connected to the output end of the third delay unit 103 and the first input end of the fourth delay unit 104, and the output end of the third prohibition gate 203 is connected to the plurality of four-input OR gates; the fourth prohibition gate 204, the first input end of the fourth prohibition gate 204 is connected to the second input end of the third prohibition gate 203, the output end of the third delay unit 103 and the first input end of the fourth delay unit 104 respectively, and the fourth prohibition gate 204 is connected to the plurality of four-input OR gates; the fourth prohibition gate 204, the first input end of the fourth prohibition gate 204 is connected to the second input end of the third prohibition gate 203, the output end of the third delay unit 103 and the first input end of the fourth delay unit 104 respectively, The second input end of the fifth inhibit gate 205 is respectively connected to the output end of the fourth delay unit 104 and the first input end of the fifth delay unit 105, and the output end of the fourth inhibit gate 204 is connected to a plurality of four-input OR gates; the fifth inhibit gate 205, the first input end of the fifth inhibit gate 205 is respectively connected to the second input end of the fourth inhibit gate 204, the output end of the fourth delay unit 104 and the first input end of the fifth delay unit 105, the second input end of the fifth inhibit gate 205 is respectively connected to the output end of the fifth delay unit 105 and the first input end of the sixth delay unit 106, and the output end of the fifth inhibit gate 205 is connected to a plurality of four-input OR gates; the sixth inhibit gate 206, the first input end of the sixth inhibit gate 206 is respectively connected to the second input end of the fifth inhibit gate 205 a first input terminal of the sixth disabling gate 207 connected to the output terminal of the sixth delay unit 106 and the first input terminal of the seventh delay unit 107, the second input terminal of the sixth disabling gate 206 being connected to the output terminal of the sixth delay unit 106 and the first input terminal of the seventh delay unit 107, respectively; a second input terminal of the seventh disabling gate 207 being connected to the output terminal of the seventh delay unit 107 and the first input terminal of the seventh delay unit 108, respectively; and the output terminal of the seventh disabling gate 207 being connected to the plurality of four-input OR gates; and a seventh disabling gate 207 being connected to the output terminal of the sixth disabling gate 206, the output terminal of the sixth delay unit 106 and the first input terminal of the seventh delay unit 107, respectively.An eighth inhibit gate 208, wherein a first input terminal of the eighth inhibit gate 208 is respectively connected to the second input terminal of the seventh inhibit gate 207, the output terminal of the seventh delay unit 107, and the first input terminal of the eighth delay unit 108; a second input terminal of the eighth inhibit gate 208 is connected to the output terminal of the eighth delay unit 108; and an output terminal of the eighth inhibit gate 208 is connected to a plurality of four-input OR gates.

[0041] Specific as Figure 5 As shown, the second input terminals of the first delay unit 101, the second delay unit 102, the third delay unit 103, the fourth delay unit 104, the fifth delay unit 105, the sixth delay unit 106, the seventh delay unit 107, and the eighth delay unit 108 are all connected to the output terminal of the integrator 300, the first input terminal of the first delay unit 101 receives the input signal CLK_IN, the first input terminal of the first delay unit 101 is connected to the first input terminal of the first disable gate 201, and the output terminal of the first delay unit 101 is respectively connected to the first input terminal of the second delay unit 102, the second input terminal of the first disable gate 201, and the first input terminal of the second disable gate 202;

[0042] The output end of the second delay unit 102 is connected to the first input end of the third delay unit 103, the second input end of the second disable gate 202 and the first input end of the third disable gate 203 respectively;

[0043] The output end of the third delay unit 103 is connected to the second input end of the third prohibition gate 203, the first input end of the fourth prohibition gate 204 and the first input end of the fourth delay unit 104 respectively;

[0044] The output terminal of the fourth delay unit 104 is connected to the first input terminal of the fifth delay unit 105, the second input terminal of the fourth disable gate 204 and the first input terminal of the fifth disable gate 205 respectively;

[0045] The output terminal of the fifth delay unit 105 is connected to the first input terminal of the sixth delay unit 106, the second input terminal of the fifth disable gate 205, and the first input terminal of the sixth disable gate 206 respectively;

[0046] The output terminal of the sixth delay unit 106 is connected to the first input terminal of the seventh delay unit 107, the second input terminal of the sixth disable gate 206 and the first input terminal of the seventh disable gate 207 respectively;

[0047] The output terminal of the seventh delay unit 107 is connected to the first input terminal of the eighth delay unit 108, the second input terminal of the seventh disable gate 207 and the first input terminal of the eighth disable gate 208 respectively;

[0048] The output terminal of the eighth delay unit 108 is connected to the second input terminal of the eighth disable gate 208 .

[0049] Optionally, in some embodiments, multiple four-input OR gates include: a first four-input OR gate 209, the input end of the first four-input OR gate 209 is respectively connected to the output end of the first inhibit gate 201, the output end of the second inhibit gate 202, the output end of the third inhibit gate 203 and the output end of the fourth inhibit gate 204, and the output end of the first four-input OR gate 209 is connected to the input end of the averager 400; a second four-input OR gate 210, the input end of the second four-input OR gate 210 is connected to the output end of the fifth inhibit gate 205, the output end of the sixth inhibit gate 206, the output end of the seventh inhibit gate 207 and the output end of the eighth inhibit gate 208, and the output end of the second four-input OR gate 210 is connected to the input end of the averager 400.

[0050] Specific as Figure 5 As shown, the output end of the first inhibiting gate 201, the output end of the second inhibiting gate 202, the output end of the third inhibiting gate 203 and the output end of the fourth inhibiting gate 204 are all connected to the first four-input OR gate 209, the output end of the fifth inhibiting gate 205, the output end of the sixth inhibiting gate 206, the output end of the seventh inhibiting gate 207 and the output end of the eighth inhibiting gate 208 are all connected to the second four-input OR gate 210, and the output end of the first four-input OR gate 209 and the output end of the second four-input OR gate 210 are both connected to the input end of the averager 400.

[0051] Optionally, in some embodiments, the averager 400 includes: a first resistor 401 and a second resistor 402 , the first resistor 401 and the second resistor 402 are connected in parallel, and both the first resistor 401 and the second resistor 402 are connected to the integrator 300 .

[0052] Optionally, in some embodiments, the integrator 300 includes: an amplifier 301, the non-inverting terminal of the amplifier 301 is connected to the input voltage, and the inverting terminal of the amplifier 301 is connected to the first resistor 401 and the second resistor 402; a capacitor 302, one end of the capacitor 302 is connected to the inverting terminal of the amplifier 301 and the first resistor 401 and the second resistor 402, and the other end of the capacitor 302 is connected to the output terminal of the amplifier 301.

[0053] Specifically, the embodiment of the present application proposes a broadband delay-locked loop circuit for preventing harmonic lock and false lock. The main idea is to maintain the simple typical structure of the DLL, avoid introducing external reset or start signals, avoid using additional circuit structures such as harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, multiple control voltages, etc., and only prevent harmonic lock and false lock by optimizing the phase detector structure, thereby having the characteristics of broadband, saving area and power consumption, and simple implementation.

[0054] Specific as Figure 5As shown, it includes a voltage-controlled delay line 100 (ie, the delay line 100 mentioned above), a phase detector 200, an integrator 300 (ie, Figure 5 The integrator 300 can also be replaced by a charge pump and a low-pass filter. The voltage-controlled delay line 100 includes eight identical voltage-controlled delay units 101 to 108, namely a first delay unit 101, a second delay unit 102, a third delay unit 103, a fourth delay unit 104, a fifth delay unit 105, a sixth delay unit 106, a seventh delay unit 107, and an eighth delay unit 108. The delays thereof are all controlled by a control voltage VC and are positively correlated with VC. The output signals of the delay units 101 to 108 serve as the multi-phase output signals of the phase-locked loop. The first delay unit 101 outputs a first output signal CLK2, The second delay unit 102 outputs a second output signal CLK3, the third delay unit 103 outputs a third output signal CLK4, the fourth delay unit 104 outputs a fourth output signal CLK5, the fifth delay unit 105 outputs a fifth output signal CLK6, the sixth delay unit 106 outputs a sixth output signal CLK7, the seventh delay unit 107 outputs a seventh output signal CLK8, and the eighth delay unit 108 outputs an eighth output signal CLK9, which are respectively denoted as CLK2 to CLK9, and CLK1 represents the input signal CLK_IN.

[0055] Phase detector 200 includes eight inhibit gates 201-208 and two four-input OR gates 209 and 210, wherein the outputs of inhibit gates 201-204 serve as inputs of four-input OR gate 209, and the outputs of inhibit gates 205-208 serve as inputs of four-input OR gate 210.

[0056] The structures of the integrator 300 and the averager 400 are as follows: Figure 6 As shown, it includes a differential-to-single-phase amplifier 301, an integrating capacitor 302, and two identical resistors (a first resistor 401 and a second resistor 402). The reference voltage of the integrator 300 is 0.5 times VDD. In the phase detector 200, the disable gate 201 detects the phase difference between CLK1 and CLK2, that is, detects one-eighth of the phase difference between CLK1 and CLK9, and outputs a signal with a corresponding pulse width, whose period is the same as the input signal. The same applies to the disable gates 202-208. Figure 7 The output curve in which the horizontal axis is the phase difference between CLK1 and CLK9 and the vertical axis is the output pulse width of the inhibit gates 201 to 208 is shown in FIG. Figure 7As shown in (a), T represents the period of the input signal CLK_IN. The first four-input OR gate 209 and the second four-input OR gate 210 respectively play the role of synthesizing the output signals of the first to fourth inhibit gates 201-204 and the fifth to eighth inhibit gates 205-208. The output curve is shown in Figure 1. The horizontal axis is the phase difference between CLK1 and CLK9, and the vertical axis is the output pulse width of the OR gates 209 and 210. Figure 7 As shown in (b), T represents the period of the input signal CLK_IN.

[0057] When the output pulse width of the first to eighth disable gates 201-208 is less than T / 4, the pulse width of the output signal of the two four-input OR gates 209 and 210 is four times that of the first to eighth disable gates 201-208. When the output pulse width of the first to eighth disable gates 201-208 is greater than T / 4, the output signals of the two four-input OR gates 209 and 210 are constantly high with a pulse width of a full cycle. It should be noted that although OR gates 209 and 210 theoretically have identical outputs, in practice, due to factors such as noise and distortion, they are not completely identical. If only one of the outputs is used, the deviation of the overall delay from the ideal delay will increase. Therefore, the average of the outputs of the two four-input OR gates 209 and 210 is used as the input signal of integrator 300 or charge pump.

[0058] When the phase difference between CLK1 and CLK9 is less than 2π, the pulse width of the input signal to the integrator 300 is less than T / 2, the average current direction of the first resistor 401 and the second resistor 402 is to the left, the right plate of the capacitor 302 is charged, and the control voltage VC increases, thereby increasing the delay of the control delay line 100; when the phase difference between CLK1 and CLK9 is in the range of 2π to 14π, the pulse width of the input signal to the integrator 300 is greater than T / 2, the average current direction of the first resistor 401 and the second resistor 402 is to the right, the right plate of the capacitor 302 is discharged, and the control voltage VC decreases, thereby decreasing the delay of the control delay line 100. The above "left" and "right" are as follows: Figure 6 Therefore, the DLL structure and phase detector thereof proposed in the embodiment of the present application have an operating range of 0 to 14π, can completely avoid false locking and prevent harmonic locking in a large range, and thus have a wide operating frequency range.

[0059] It should be noted that the above working range is proportional to n-1, where n is the number of delay unit stages of the voltage-controlled delay line 100 , and thus can be easily expanded by increasing the number of delay unit stages.

[0060] According to the broadband delay phase-locked loop circuit proposed in the embodiment of the present application, a delay line is used to receive an input signal, and first to Nth output signals are output based on the input signal. The phase difference between the input signal and the Nth output signal is detected by a phase detector, and first to Mth pulse width signals are generated based on the phase difference, the input signal and the first to Nth output signals. The average value of the first to Mth pulse width signals is calculated by an averager, and a target control voltage is generated to the delay line based on the average value, so that the delay line is delayed based on the target control voltage. Thus, the technical solutions in the prior art for solving the problems of false locking and harmonic locking without the need for external reset or start signals are solved. Usually, additional circuit structures including but not limited to harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, multiple control voltages, etc. are required. Not only is the implementation method relatively complicated, but it also takes up a lot of area and power consumption. A phase-locked loop based on phase difference synthesis is adopted. On the basis of maintaining the typical simple structure of DLL, the problems of harmonic locking and false locking are solved, and it has multi-phase output and a wider operating frequency range. At the same time, the delay locked loop does not need to introduce external reset or start signals, and does not need to use additional circuit structures such as harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, multiple control voltages, etc., so it has the characteristics of broadband, multi-phase output, simple implementation, and saving area and power consumption.

[0061] Next, a delay method of a wideband delay-locked loop circuit according to an embodiment of the present application will be described with reference to the accompanying drawings.

[0062] Figure 8 4 is a flow chart of a delay method for a broadband delay phase-locked loop circuit according to an embodiment of the present application.

[0063] like Figure 8 As shown, the delay method of the broadband delay phase-locked loop circuit includes the following steps:

[0064] Step S801 : Receive an input signal using a delay line, and output first to Nth output signals based on the input signal, where N is an integer.

[0065] Step S802 , detecting the phase difference between the input signal and the Nth output signal through a phase detector, and generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, where M is an integer.

[0066] In step S803 , an averager is used to calculate the average value of the first to Mth pulse width signals, and a target control voltage is generated based on the average value to the delay line, so that the delay line is delayed based on the target control voltage.

[0067] Optionally, in some embodiments, the delay method of the above-mentioned broadband delay phase-locked loop circuit further includes: determining whether the current phase difference between the input signal and the Nth output signal is less than or equal to a first preset value; if the current phase difference is less than or equal to the first preset value, generating the current first to Mth pulse width signals based on the current phase difference, calculating the average value of the current first to Mth pulse width signals using an averager, and generating a first control voltage to the delay line based on the average value of the current first to Mth pulse width signals using an integrator, so that the delay line increases the delay based on the first control voltage; if the current phase difference is greater than the first preset value and less than or equal to the second preset value, generating the current first to Mth pulse width signals based on the current phase difference, calculating the average value of the current first to Mth pulse width signals using an averager, and generating a second control voltage to the delay line based on the average value of the current first to Mth pulse width signals using an integrator, so that the delay line reduces the delay based on the second control voltage.

[0068] It should be noted that the above explanation of the embodiment of the wideband delay locked loop circuit is also applicable to the delay method of the wideband delay locked loop circuit of this embodiment, and will not be repeated here.

[0069] According to the delay method of a broadband delay-locked phase-locked loop circuit proposed in an embodiment of the present application, a delay line receives an input signal and outputs first to Nth output signals based on the input signal. A phase detector detects the phase difference between the input signal and the Nth output signal, and generates first to Mth pulse width signals based on the phase difference, the input signal, and the first to Nth output signals. An averager calculates the average value of the first to Mth pulse width signals, and based on the average value, generates a target control voltage to the delay line, causing the delay line to delay based on the target control voltage. Thus, the delay line solves the problem of prior art solutions for false lock and harmonic lock without requiring an external reset or start signal, which typically require additional circuit structures including but not limited to harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, and multiple control voltages. This not only complicates implementation but also consumes a lot of area and power. This method eliminates the need for external reset or start signals, and eliminates the need for additional circuit structures such as harmonic lock detectors, false lock detectors, auxiliary delay lines, auxiliary loops, and multiple control voltages. It features broadband, multi-phase output, simple implementation, and saves area and power.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0071] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this application, "N" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0072] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0073] The logic and / or steps represented in the flowchart or otherwise described herein may be considered, for example, as a sequenced list of executable instructions for implementing logical functions, and may be embodied in any computer program product for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from and execute instructions on an instruction execution system, apparatus, or device), or used in conjunction with such instruction execution systems, apparatuses, or devices.

[0074] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

Claims

1. A broadband delay-locked loop circuit, characterized in that: include: A delay line, configured to receive an input signal and output first to Nth output signals based on the input signal, wherein N is an integer; a phase detector, wherein an input end of the phase detector is connected to an output end of the delay line, the phase detector is used to detect a phase difference between the input signal and the Nth output signal, and to generate first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, wherein M is an integer; an averager, the input end of the averager being connected to the output end of the phase detector, and being used for calculating the average values ​​of the first to Mth pulse width signals; An integrator, wherein the input end of the integrator is connected to the output end of the averager, and the output end of the integrator is connected to the input end of the delay line, for receiving the average value and generating a target control voltage to the delay line based on the average value, so that the delay line is delayed based on the target control voltage.

2. The circuit according to claim 1, characterized in that When N is 8, the delay line includes: A first delay unit, wherein a first input end of the first delay unit receives the input signal, a first input end and an output end of the first delay unit are connected to the phase detector, and a second input end of the first delay unit is connected to the output end of the integrator for outputting a first output signal; a second delay unit, wherein a first input end of the second delay unit is respectively connected to an output end of the first delay unit and to the phase detector, an output end of the second delay unit is connected to the phase detector, and a second input end of the second delay unit is connected to an output end of the integrator, for outputting a second output signal; a third delay unit, wherein a first input end of the third delay unit is connected to the output end of the second delay unit and the phase detector respectively, an output end of the third delay unit is connected to the phase detector, and a second input end of the third delay unit is connected to the output end of the integrator, for outputting a third output signal; a fourth delay unit, wherein a first input end of the fourth delay unit is connected to an output end of the third delay unit and the phase detector, an output end of the fourth delay unit is connected to the phase detector, and a second input end of the fourth delay unit is connected to an output end of the integrator, for outputting a fourth output signal; a fifth delay unit, wherein a first input end of the fifth delay unit is connected to an output end of the fourth delay unit and the phase detector, a second input end of the fifth delay unit is connected to an output end of the integrator, and an output end of the fifth delay unit is connected to the phase detector, for outputting a fifth output signal; a sixth delay unit, wherein a first input end of the sixth delay unit is connected to the output end of the fifth delay unit and the phase detector respectively, a second input end of the sixth delay unit is connected to the output end of the integrator, and an output end of the sixth delay unit is connected to the phase detector, for outputting a sixth output signal; a seventh delay unit, wherein a first input end of the seventh delay unit is connected to the output end of the sixth delay unit and the phase detector respectively, a second input end of the seventh delay unit is connected to the output end of the integrator, and an output end of the seventh delay unit is connected to the phase detector, for outputting a seventh output signal; An eighth delay unit, wherein the first input end of the eighth delay unit is respectively connected to the output end of the seventh delay unit and the phase detector, the second input end of the eighth delay unit is connected to the output end of the integrator, and the output end of the eighth delay unit is connected to the phase detector, for outputting an eighth output signal.

3. The circuit according to claim 2, characterized in that The phase detector comprises: a plurality of inhibit gates, wherein input ends of the plurality of inhibit gates are connected to the delay line and are used to detect a phase difference between the input signal and the Nth output signal; A plurality of four-input OR gates, wherein the input ends of the plurality of four-input OR gates are connected to the output ends of the plurality of inhibit gates, and the output ends of the plurality of four-input OR gates are connected to the averager, for generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals.

4. The circuit according to claim 3, characterized in that The plurality of inhibiting gates include: a first inhibit gate, wherein a first input end of the first inhibit gate is connected to a first input end of the first delay unit, a second input end of the first inhibit gate is connected to an output end of the first delay unit and a first input end of the second delay unit, respectively, and an output end of the first inhibit gate is connected to the plurality of four-input OR gates; a second inhibit gate, wherein a first input end of the second inhibit gate is respectively connected to a second input end of the first inhibit gate, an output end of the first delay unit and a first input end of the second delay unit, a second input end of the second inhibit gate is connected to an output end of the second delay unit and a first input end of the third delay unit, and an output end of the second inhibit gate is connected to the plurality of four-input OR gates; a third disabling gate, wherein a first input end of the third disabling gate is respectively connected to a second input end of the second disabling gate, an output end of the second delay unit and a first input end of the third delay unit, a second input end of the third disabling gate is connected to an output end of the third delay unit and a first input end of the fourth delay unit, and an output end of the third disabling gate is connected to the plurality of four-input OR gates; a fourth inhibit gate, wherein a first input end of the fourth inhibit gate is respectively connected to a second input end of the third inhibit gate, an output end of the third delay unit and a first input end of the fourth delay unit, a second input end of the fourth inhibit gate is respectively connected to an output end of the fourth delay unit and a first input end of the fifth delay unit, and an output end of the fourth inhibit gate is connected to the plurality of four-input OR gates; a fifth inhibit gate, wherein a first input end of the fifth inhibit gate is respectively connected to a second input end of the fourth inhibit gate, an output end of the fourth delay unit and a first input end of the fifth delay unit, a second input end of the fifth inhibit gate is respectively connected to an output end of the fifth delay unit and a first input end of the sixth delay unit, and an output end of the fifth inhibit gate is connected to the plurality of four-input OR gates; a sixth inhibit gate, wherein a first input end of the sixth inhibit gate is respectively connected to a second input end of the fifth inhibit gate, an output end of the fifth delay unit, and a first input end of the sixth delay unit, a second input end of the sixth inhibit gate is respectively connected to an output end of the sixth delay unit and a first input end of the seventh delay unit, and an output end of the sixth inhibit gate is connected to the plurality of four-input OR gates; a seventh inhibit gate, wherein a first input end of the seventh inhibit gate is respectively connected to a second input end of the sixth inhibit gate, an output end of the sixth delay unit and a first input end of the seventh delay unit, a second input end of the seventh inhibit gate is respectively connected to an output end of the seventh delay unit and a first input end of the eighth delay unit, and an output end of the seventh inhibit gate is connected to the plurality of four-input OR gates; An eighth inhibit gate, wherein the first input end of the eighth inhibit gate is respectively connected to the second input end of the seventh inhibit gate, the output end of the seventh delay unit, and the first input end of the eighth delay unit, the second input end of the eighth inhibit gate is connected to the output end of the eighth delay unit, and the output end of the eighth inhibit gate is connected to the multiple four-input OR gates.

5. The circuit according to claim 4, characterized in that The plurality of four-input OR gates include: a first four-input OR gate, wherein input terminals of the first four-input OR gate are respectively connected to the output terminals of the first inhibit gate, the second inhibit gate, the third inhibit gate and the fourth inhibit gate, and the output terminals of the first four-input OR gate are connected to the input terminals of the averager; A second four-input OR gate, the input end of the second four-input OR gate is connected to the output end of the fifth inhibit gate, the output end of the sixth inhibit gate, the output end of the seventh inhibit gate and the output end of the eighth inhibit gate, and the output end of the second four-input OR gate is connected to the input end of the averager.

6. The circuit according to claim 1, characterized in that The averager comprises: A first resistor and a second resistor, the first resistor and the second resistor are connected in parallel, and the first resistor and the second resistor are both connected to the integrator.

7. The circuit according to claim 6, characterized in that The integrator comprises: an amplifier, wherein a non-inverting terminal of the amplifier is connected to an input voltage, and an inverting terminal of the amplifier is connected to the first resistor and the second resistor; A capacitor, one end of the capacitor is connected to the inverting end of the amplifier and the first resistor and the second resistor, and the other end of the capacitor is connected to the output end of the amplifier.

8. The circuit according to claim 1, characterized in that The delay of the delay line is positively correlated with the target control voltage.

9. A delay method for a broadband delay-locked loop circuit, characterized in that: A broadband delay phase-locked loop circuit according to any one of claims 1 to 8, wherein the method comprises: receiving an input signal using a delay line, and outputting first to Nth output signals based on the input signal, wherein N is an integer; Detecting a phase difference between the input signal and the Nth output signal by a phase detector, and generating first to Mth pulse width signals based on the phase difference, the input signal and the first to Nth output signals, wherein M is an integer; An averager is used to calculate the average values ​​of the first to Mth pulse width signals, and a target control voltage is generated to the delay line based on the average value, so that the delay line is delayed based on the target control voltage.

10. The method according to claim 9, characterized in that Also includes: Determining whether a current phase difference between the input signal and the Nth output signal is less than or equal to a first preset value; If the current phase difference is less than or equal to the first preset value, generating current first to Mth pulse width signals based on the current phase difference, calculating the average values ​​of the current first to Mth pulse width signals using the averager, and generating a first control voltage to the delay line based on the average values ​​of the current first to Mth pulse width signals using the integrator, so that the delay line increases the delay based on the first control voltage; If the current phase difference is greater than the first preset value and less than or equal to the second preset value, the current first to Mth pulse width signals are generated based on the current phase difference, the average value of the current first to Mth pulse width signals is calculated using the averager, and the second control voltage is generated to the delay line based on the average value of the current first to Mth pulse width signals using the integrator, so that the delay line reduces the delay based on the second control voltage.

Images