Substrate, rewiring layer or adapter plate reusable packaging structure

Abstract

The invention relates to a reusable packaging structure for a substrate, a rewiring layer or an adapter plate, which comprises a first electric connection surface and a second electric connection surface, electric wiring layers and substrate insulating media are arranged between the first electric connection surface and the second electric connection surface in a laminated and staggered manner, the two electric wiring layers are communicated through an electric interconnection hole, and the substrate insulating media are arranged between the first electric connection surface and the second electric connection surface. The first electric connection surface is connected with a first functional chip and an interconnection dummy chip, the first functional chip is electrically connected with the interconnection dummy chip through a first lead-out wire, and the interconnection dummy chip is connected to a solder ball of the second electric connection surface through a second lead-out wire. When the function of a designed and processed system-in-package chip is changed, a first functional chip passes through a first salient point, a first electric connection surface, a second salient point and an internal lead of an interconnection dummy chip in sequence through the interconnection dummy chip; and the other second bump, the first electric connection surface, the second electric connection surface and the solder ball form an external complete signal link of the first functional chip, so that the redesign of the substrate, the rewiring layer or the adapter plate is avoided.

Description

Technical Field

[0001] The present invention relates to the field of packaging and integration of semiconductor integrated circuits, and in particular to a reusable packaging structure of a substrate, a redistribution layer or an adapter board. Background Art

[0002] Integrated Circuit (IC, also known as chip) is a technology that integrates a large number of microelectronic components on a piece of semiconductor material. It is widely used in modern electronic systems, computer systems, and communication systems. The typical IC product development process includes three main stages: chip design, wafer processing and manufacturing, and chip packaging and testing. Among them, chip packaging is the last stage of IC product development, which directly affects the final performance, reliability, cost and market competitiveness of the product. With the continuous advancement of semiconductor technology, the role of chip packaging technology has become increasingly prominent and has become one of the key forces driving the development of the industry.

[0003] According to packaging technology, chip packaging can be classified into traditional packaging and advanced packaging. In traditional packaging, it can be divided into plastic packaging and ceramic packaging. Plastic packaging is a packaging method that has been verified by time and widely used in the manufacturing of various IC products. It can be further divided into lead frame package (LFP) and substrate package (SP).

[0004] LFP uses a metal frame as a substrate and connects the chip's pads to external circuits through multiple leads. It is suitable for a variety of ICs, including logic, storage, microprocessors, and analog signal processors. SP uses a substrate as a physical and electrical connection medium between the chip and the external circuit. Compared with LFP, SP can provide better electrical characteristics and a smaller package size. It is suitable for IC products with high-speed electrical characteristics, high-density integration, a large number of I / O pins, and high reliability. SP packaging forms include ball grid array (BGA), land grid array (LGA), dual in-line package (DIP), quad flat package (QFP), etc. Ceramic packaging is suitable for high-performance electronic devices such as transistors, high-frequency power amplifiers, high-speed data transmission, and low-noise amplifiers due to its excellent heat resistance, moisture resistance, corrosion resistance, and electromagnetic interference resistance.

[0005] Advanced packaging includes wafer level package (WLP), 2.5D package, 3D package, system in package (SiP), etc. WLP can be divided into wafer level chip package (WLCSP), redistribution layer (RDL), flip chip package (FC), through silicon via (TSV).

[0006] WLCSP is divided into two types: Fan-out Package (FOP) and Fan-in Package (FIP). FIP can achieve the smallest package volume because its package size is the same as the chip size, but this method leads to relatively weak physical and chemical protection performance and relatively poor reliability of solder joints. FOP uses the "fan-out" method to connect the chip pads from the periphery of the chip or the array pads to the substrate or circuit board through the redistribution layer and solder balls, retaining the advantages of FIP and overcoming its shortcomings. Therefore, FOP has a very wide range of applications, including but not limited to high-performance computing, millimeter-wave radar, Internet of Things, and mobile processors.

[0007] RDL provides a way to change the position of the chip pad to adapt to the package design or increase the density of the I / O (input / output) pins to achieve a smaller package size or more complex electrical performance requirements. It is widely used in packaging technologies such as FC, WLP and FOP, and is essential for high-speed and high-density applications such as high-performance processors, graphics processors, network communication chips and memories. FC uses bumps to interconnect components downward to the substrate or circuit board, and is widely used in high-performance packaging, SiP, RF and microwave fields. TSV is a technology that interconnects chips by making vertical conductions between chips and wafers, and is one of the key processes for 2.5D / 3D packaging.

[0008] 2.5D packaging is based on wafer processing technology and is currently divided into two major schools. One is the silicon bridge technology embedded in the resin substrate, such as Intel's Embedded Multi-die Interconnect Bridge (EMIB). The other is the adapter board technology using TSV, such as TSMC's Chip on Wafer on Substrate (CoWoS) and Samsung's I-Cube. 3D packaging is used for large-scale integrated circuit chip and memory chip integration. TSMC's System on Integrated Circuit is the most mature, and its technical path combines heterogeneous bonding (Hybrid Bonding, HB) technology and TSV technology.

[0009] SiP uses existing packaging technology and assembly methods to integrate chips with different functions (such as processors, etc.) and possible passive components (such as resistors, capacitors, etc.) in one package. This integration can be two-dimensional (all components are on the same plane) or three-dimensional (components are stacked) to achieve higher integration and smaller size. SiP is popular for its advantages such as miniaturized design, high integration, short R&D cycle, relatively simple structure, high reliability, design flexibility, sealing and high reliability, but at the same time, SiP also faces technical challenges such as thermal management, signal integrity, electromagnetic interference, as well as complex manufacturing process, difficult testing and verification, difficult function changes and inconsistent industry standards.

[0010] Among them, functional changes are common problems in the actual work of SiP research and development. The demander may propose them after the SiP chip is designed and processed. The reasons include but are not limited to adjusting functions, supply chain changes, cost reduction, functional failure, size adjustment or design compatibility, etc. Functional changes will involve electrical characteristics, power and thermal management, size and layout adjustments, signal power integrity, electromagnetic compatibility, thermal stress, reliability and material selection, etc., which will require redesign of the substrate, redistribution layer or adapter board.

[0011] Significant negative impacts caused by functional changes, including but not limited to: (1) Production costs and processes: Redesign may increase costs and may require the introduction of new production equipment or adjustments to the production process.

[0012] (2) Compatibility and scalability: Redesign needs to consider compatibility with existing systems and future scalability, making the design more complex and challenging.

[0013] (3) Testing and verification: The redesign needs to go through a new testing and verification process to ensure that the new functional requirements are met.

[0014] (4) Supply chain and logistics: Redesign may require updating supply chain and logistics strategies to adapt to the needs of new materials or new processes.

[0015] (5) Market response time: Redesign will delay production time and planning, and will not be able to respond quickly to market demand.

[0016] Therefore, when the function of a SiP chip that has been designed and processed is changed, it is necessary to comprehensively consider multiple factors such as technology, cost, time, and market. How to reduce the negative impact caused by the functional change, that is, how to avoid redesigning the substrate, redistribution layer or adapter board, and improve the reusability of the substrate, redistribution layer or adapter board, thereby improving the design flexibility, performance and cost-effectiveness of the SiP chip, is a key issue that the industry needs to solve urgently. Summary of the invention

[0017] The purpose of implementing the present invention is to provide a reusable packaging structure of a substrate, a redistribution layer or an adapter board. The technical solution provided by the present invention is as follows: A reusable packaging structure of a substrate, a redistribution layer or an adapter board, used for a substrate, a redistribution layer or an adapter board, comprising: a first electrical connection surface and a second electrical connection surface, electrical wiring layers and substrate insulating media are stacked and staggered between the first electrical connection surface and the second electrical connection surface, the two electrical wiring layers are connected through a plurality of electrical interconnection holes, the first electrical connection surface is connected to a first functional chip and an interconnection dummy chip, the first functional chip is electrically connected to the interconnection dummy chip through a first lead wire, and the interconnection dummy chip is connected to the solder ball of the second electrical connection surface through a second lead wire.

[0018] Preferably, the first functional chip is arranged on the first electrical connection surface through at least one first bump, the interconnection dummy chip is arranged on the first electrical connection surface through multiple second bumps, a lead connecting the two second bumps is arranged inside the interconnection dummy chip, the first bump is electrically connected to one of the second bumps through a first lead wire, and the other second bump is connected to the solder ball on the second electrical connection surface through a second lead wire.

[0019] Preferably, the number of second bumps of the interconnected dummy sheet is at least two.

[0020] Preferably, the interconnect dummy sheet is made of one or a combination of silicon, gallium arsenide, and ceramic.

[0021] Preferably, the type of the first functional chip is: a central processing unit, a field programmable gate array, a digital signal processor or a memory chip.

[0022] Preferably, the material of the electrical wiring layer and the electrical interconnection hole includes: copper, tungsten, gold, silver, tin, palladium, or an alloy formed by a combination of several of them.

[0023] Preferably, the substrate insulating medium is at least one layer, and the material of the substrate insulating medium is: one or a combination of organic resin, organic film material, glass cloth, silicon oxide, silicon nitride, low temperature co-fired ceramics, and high temperature co-fired ceramics.

[0024] Preferably, the first bump and the second bump are: eutectic solder bumps, copper pillar bumps, micro bumps or indium bumps.

[0025] Preferably, the material of the first functional chip is: one or a combination of silicon, gallium arsenide, indium gallium arsenide, silicon carbide, and gallium nitride.

[0026] Compared with the prior art, the present invention has the following beneficial effects: The present invention aims at ensuring the integrity of the SiP chip function when the function of a SiP chip that has been designed and processed is changed by arranging an interconnection dummy chip on a packaging substrate, a redistribution layer or an adapter board, that is, the first functional chip forms a complete external signal link of the first functional chip through the first bump, the first electrical connection surface, one of the second bumps, the internal lead of the interconnection dummy chip, the other second bump, the first electrical connection surface, the second electrical connection surface and the solder ball in sequence, thereby avoiding the redesign of the substrate, the redistribution layer or the adapter board and the internal structure.

[0027] While improving the flexibility and compatibility of SiP chip design, the present invention enhances the reusability of substrates, redistribution layers or adapter boards, reduces design and processing costs, shortens product development cycles, and achieves rapid market response, thus having significant cost-effectiveness and broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a cross-sectional schematic diagram of the packaging structure of the present invention; Figure 2a This is a cross-sectional schematic diagram of the packaging structure before the function change of Example 1 of the present invention; Figure 2b This is a top view of the packaging structure before the function change of Embodiment 1 of the present invention; Figure 2c This is a schematic cross-sectional diagram of the packaging structure of Embodiment 1 of the present invention; Figure 2d This is a schematic top view of the packaging structure of Embodiment 1 of the present invention; Figure 2e-Ⅰ This is a circuit design schematic diagram of the second function chip of Embodiment 1 of the present invention; Figure 2e-Ⅱ This is a circuit design principle diagram of the first functional chip of Example 1 of the present invention; Figure 2f This is a schematic diagram of the packaging structure verification of Example 1 of the present invention; Figure 2g The length table of each segment of interconnection line in Example 1 of the present invention; Figure 2h Insertion loss comparison diagram before and after adding the interconnection dummy chip internal lead wire to Embodiment 1 of the present invention; Figure 3a This is a cross-sectional schematic diagram of the packaging structure before the function change of Example 2 of the present invention; Figure 3b This is a top view schematic diagram of the packaging structure before the function change of Example 2 of the present invention; Figure 3c This is a schematic cross-sectional view of the packaging structure of Embodiment 2 of the present invention; Figure 3d This is a schematic top view of the packaging structure of Embodiment 2 of the present invention; Figure 4a This is a cross-sectional schematic diagram of the packaging structure before the function change of Example 3 of the present invention; Figure 4b This is a top view of the packaging structure before the function change of Example 3 of the present invention; Figure 4c This is a schematic cross-sectional diagram of the packaging structure of Embodiment 3 of the present invention; Figure 4d This is a schematic top view of the packaging structure of Embodiment 3 of the present invention; In the figure, 101 is a substrate, a redistribution layer or an adapter board; 102 is a first functional chip; 1031 is an interconnection dummy chip; 104 is a lead; 105 is a solder ball; 106 is a first bump; 107 is a second bump; 1011 is a first electrical connection surface; 1012 is a second electrical connection surface; 1013 is an electrical wiring layer; 1014 is a substrate insulating medium; 1015 is an electrical interconnection hole; 201 is a second functional chip. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] like Figure 1 , Figure 2c , Figure 3c , Figure 4cAs shown, the present invention provides a technical solution: a reusable packaging structure of a substrate, a redistribution layer or an adapter board, used for a substrate, a redistribution layer or an adapter board 101, comprising: a first electrical connection surface 1011 and a second electrical connection surface 1012, electrical wiring layers 1013 and a substrate insulating medium 1014 are stacked and staggered between the first electrical connection surface 1011 and the second electrical connection surface 1012, and the material of the electrical wiring layer 1013 and the electrical interconnection hole 1015 is: an alloy formed by one of copper, tungsten, gold, silver, tin, and palladium or a combination of several of them.

[0031] The substrate insulating medium 1014 is at least one layer, and the material of the substrate insulating medium 1014 is: one or a combination of organic resin, organic film material, glass cloth, silicon oxide, silicon nitride, low temperature co-fired ceramics, and high temperature co-fired ceramics.

[0032] The two electrical wiring layers 1013 are connected through a plurality of electrical interconnection holes 1015. The first electrical connection surface 1011 is connected to the first functional chip 102 and the interconnection dummy chip 1031. The material of the interconnection dummy chip 1031 is one or a combination of silicon, gallium arsenide, and ceramic.

[0033] There is at least one first function chip 102, and the type of the first function chip 102 is: a central processing unit, a field programmable gate array, a digital signal processor or a memory chip.

[0034] The material of the first function chip 102 is one of silicon, gallium arsenide, indium gallium arsenide, silicon carbide, gallium nitride, or a combination of several thereof.

[0035] The first function chip 102 is electrically connected to the interconnection dummy chip 1031 through a first lead wire, and the first function chip 102 is arranged on the first electrical connection surface 1011 through at least one first bump 106 .

[0036] At least one first bump 106 of the first function chip 102 is connected to one of the second bumps 107 of the interconnection dummy chip 1031 through a first lead wire. The interconnection dummy sheet 1031 is on the first electrical connection surface 1011 through a plurality of second bumps 107 (the number of second bumps 107 is at least two).

[0037] The interconnection dummy sheet 1031 is provided with leads 104 inside, wherein a second bump 107 is electrically connected to another second bump 107 via the lead 104 , and another second bump 107 is connected to the solder ball 105 of the second electrical connection surface 1012 via a second lead wire.

[0038] The first bump and the second bump may be eutectic solder bumps, copper pillar bumps, micro bumps or indium bumps, and the solder ball 105 may be made of tin-based lead-free solder.

[0039] One end of the solder ball 105 is electrically interconnected with the substrate, the redistribution layer or the second electrical connection surface 1012 of the adapter board 101, and the other end serves as an electrical interconnection structure for the package to be exposed to the outside.

[0040] When the function of a SiP chip that has been designed and processed is changed, the integrity of the SiP chip function is ensured by setting an interconnection dummy chip 1031 on the packaging substrate, the redistribution layer or the adapter board. That is, the first functional chip 102 forms a complete external signal chain of the first functional chip 102 through the first bump 106, the first electrical connection surface 1011, one of the second bumps 107, the internal lead 104 of the interconnection dummy chip 1031, the other second bump 107, the first electrical connection surface 1011, the second electrical connection surface 1012 and the solder ball 105, thereby avoiding the redesign of the substrate, the redistribution layer or the adapter board 101 and the internal structure. Example

[0041] See also Figure 2a to Figure 2h As shown in Example 1, Figure 2a The figure shows a schematic cross-sectional view of the packaging structure before the function is changed. The substrate, redistribution layer or adapter board 101 adopts a resin substrate, and the resin material can be a combination of epoxy glass cloth and Ajinomoto Build-up Film (ABF) material; the first function chip 102 adopts a programmable system-on-chip (PSoC) and is arranged on the first electrical connection surface 1011 through a first bump 106; the second function chip 201 adopts an analog-to-digital converter (ADC) and is arranged on the first electrical connection surface 1011 through a second bump 107; the solder ball 105 is arranged on the second electrical connection surface 1012.

[0042] The PSoC signal of the first function chip 102 is transmitted to the second function chip 201 ADC through the first bump 106 , substrate, redistribution layer or adapter board 101 substrate, and a second bump 107 ; the second function chip 201 ADC leads the signal to the solder ball 105 through another second bump 107 .

[0043] Combination Figure 2e-Ⅰ to Figure 2e-ⅡAs can be seen from the circuit design schematic diagram, the first group of functional chips 102 PSoC respectively lead out signals AD7177_XCLK, XSPI_DOUT, XSPI_DIN, XSPI_SCLK, XSPI_CS, and XSPI_SYNC to the substrate, the redistribution layer, or the adapter board 101 substrate through the bumps IO_0_10, IO_L1P_T0_10, IO_L1N_T0_10, O_L2P_T0_10, and O_L2N_T0_10 of the plurality of first bumps 106, and lead out to the second functional chip 201 ADC through the electrical interconnection holes 1015 therein, corresponding to the bumps XTAL2 / CLKIO, DOUT / RDY, DIN, SCLK, and CS of the plurality of second bumps 107; the second functional chip 201 Among the second bumps 107 of the ADC, bumps AIN[0-3], REF−, REF+, REFOUT, AVDD[1-2], REGCAPD, and REGCAPA lead out signals to the solder balls 105 .

[0044] For the functional change of the SiP that has been designed and processed and the second functional chip 201 ADC is no longer needed, in order to ensure the functional integrity of the first functional chip 102 PSoC, the substrate, redistribution layer or adapter board reusable packaging structure of the present invention is adopted to replace the second functional chip 201 ADC with the interconnection dummy chip 1031.

[0045] See also Figure 2c For example, the first function chip 102 PSoC forms a complete signal chain to the outside through the first bump 106, the first electrical connection surface 1011, one of the second bumps 107, the internal lead 104 of the interconnected dummy chip 1031, the other second bump 107, the first electrical connection surface 1011, the second electrical connection surface 1012 and the solder ball 105.

[0046] By analogy, the signals transmitted from the first function chip 102 PSoC to the second function chip 201 ADC can be led out to the solder ball 105 through the interconnection dummy chip 1031 to form a complete external signal link of the first function chip 102 PSoC, thereby ensuring the functional integrity of the first function chip 102 PSoC, avoiding the redesign of the substrate, redistribution layer or adapter board 101, and improving the reusability of the substrate, redistribution layer or adapter board 101.

[0047] To verify Example 1, an insertion loss simulation is performed on a complete external signal link formed by the first functional chip 102 through the first bump 106, the first electrical connection surface 1011, one of the second bumps 107, the internal lead 104 of the interconnected dummy piece 1031, the other second bump 107, the first electrical connection surface 1011, the second electrical connection surface 1012 and the solder ball 105 to form the first functional chip 102.

[0048] See also Figure 2f The signal AD7117_YCLK is led out from the first function chip 102 PSoC and connected to the second function chip 201 ADC, and the signal Y_REGCAPD is led out from the second function chip 201 ADC to the solder ball 105 .

[0049] Assuming that after the SiP has been designed and processed, the function of the second function chip 201 ADC is changed, in order to ensure the functional integrity of the first function chip 102 PSoC, the interconnection dummy chip 1031 is used to replace the second function chip 201 ADC, and the first function chip 102 PSoC signal AD7117_YCLK is led out to the solder ball 105 set on the second electrical connection surface 1012 through the internal lead 104 of the interconnection dummy chip 1031.

[0050] For the length table of each signal line, see Figure 2g , the simulation results can be found in Figure 2h The results show that interconnecting the internal leads 104 of the dummy chip 1031 introduces a small additional insertion loss, ensuring the functional integrity of the first functional chip 102 PSoC without redesigning the substrate, the redistribution layer or the adapter board 101. Example

[0051] See also Figures 3a to 3d As shown in Example 2, Figure 3a The figure shows a cross-sectional schematic diagram of the packaging structure before the function is changed. The substrate, redistribution layer or adapter board 101 adopts a high-density FOP redistribution layer. The first function chip 102 adopts a programmable system-on-chip (PSoC) and is arranged on the first electrical connection surface 1011 through a first bump 106; the second function chip 201 adopts a transceiver chip and is arranged on the first electrical connection surface 1011 through a second bump 107; the solder ball 105 is arranged on the second electrical connection surface 1012.

[0052] The PSoC signal of the first function chip 102 is transmitted to the second function chip 201 transceiver chip through the first bump 106, the substrate, the redistribution layer or the redistribution layer of the adapter board 101, and a second bump 107; the second function chip 201 transceiver chip leads the signal to the solder ball 105 through another second bump 107.

[0053] For the SiP function change that has been completed and processed, when the second function chip 201 transceiver chip is no longer needed, in order to ensure the functional integrity of the first function chip 102 PSoC, the reused packaging structure of the present invention is adopted to replace the second function chip 201 transceiver chip with the interconnection dummy chip 1031.

[0054] See also Figure 3c , for example, a complete signal chain for the signal of the first functional chip 102 PSoC is formed: a complete signal chain is formed through the first bump 106, the first electrical connection surface 1011, one of the second bumps 107, the internal lead 104 of the interconnected dummy piece 1031, the other second bump 107, the first electrical connection surface 1011, the second electrical connection surface 1012 and the solder ball 105.

[0055] By analogy, the signals from the first function chip 102 PSoC to the second function chip 201 transceiver chip can be led out to the solder ball 105 through the interconnection dummy chip 1031 to form a complete external signal link of the first function chip 102 PSoC, thereby ensuring the functional integrity of the first function chip 102 PSoC, avoiding the redesign of the substrate, redistribution layer or adapter board 101, and improving the reusability of the substrate, redistribution layer or adapter board 101. Example

[0056] See also Figures 4a to 4d As shown, Figure 4a The figure shows a schematic cross-sectional view of the packaging structure before the function is changed. The substrate, redistribution layer or adapter board 101 adopts a TSV adapter board, the first function chip 102 adopts a field programmable gate array (Field-Programmable Gate Array, FPGA), and is arranged on the first electrical connection surface 1011 through a first bump 106; the second function chip 201 adopts an ADC, which is arranged on the first electrical connection surface 1011 through a second bump 107, and the solder ball 105 is arranged on the second electrical connection surface 1012.

[0057] The FPGA signal of the first function chip 102 is transmitted to the second function chip 201 ADC through the first bump 106 , substrate, redistribution layer or adapter board 101 , and a second bump 107 ; the second function chip 201 ADC leads the signal to the solder ball 105 through another second bump 107 .

[0058] For the functional change of the SiP that has been designed and processed and the second functional chip 201 ADC is no longer needed, in order to ensure the functional integrity of the first functional chip 102 FPGA, the substrate, redistribution layer or adapter board reusable packaging structure of the present invention is adopted to replace the second functional chip 201 ADC with the interconnection dummy chip 1031.

[0059] See also Figure 4c , for example, a complete signal chain of the signal of the first functional chip 102 FPGA is formed: through the first bump 106, the first electrical connection surface 1011, one of the second bumps 107, the internal lead 104 of the interconnected dummy chip 1031, the other second bump 107, the first electrical connection surface 1011, the second electrical connection surface 1012 and the solder ball 105 to form a complete signal chain to the outside.

[0060] By analogy, the signals from the first function chip 102 FPGA to the second function chip 201 ADC can be led out to the solder ball 105 through the interconnection dummy chip 1031 to form a complete signal link of the first function chip 102 FPGA to the outside, thereby ensuring the functional integrity of the first function chip 102 FPGA, avoiding the redesign of the substrate, redistribution layer or adapter board 101, and improving the reusability of the substrate, redistribution layer or adapter board 101.

[0061] The embodiments of the present invention disclose preferred embodiments, but are not limited thereto. A person skilled in the art can easily understand the spirit of the present invention based on the above embodiments and make different extensions and changes. However, as long as they do not deviate from the spirit of the present invention, they are all within the protection scope of the present invention.

Claims

1. A substrate, a redistribution layer or an adapter board reusable packaging structure, used for a substrate, a redistribution layer or an adapter board, include: A first electrical connection surface and a second electrical connection surface, electrical wiring layers and substrate insulating media are stacked and staggered between the first electrical connection surface and the second electrical connection surface, and the two electrical wiring layers are connected through electrical interconnection holes, characterized in that the first electrical connection surface is connected to a first functional chip and an interconnection dummy chip, the first functional chip is electrically connected to the interconnection dummy chip through a first lead wire, and the interconnection dummy chip is connected to a solder ball on the second electrical connection surface through a second lead wire.

2. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that It includes: a first functional chip is arranged on a first electrical connection surface through at least one first bump, the interconnection dummy chip is arranged on the first electrical connection surface through multiple second bumps, a lead connecting two second bumps is arranged inside the interconnection dummy chip, the first bump is electrically connected to one of the second bumps through a first lead, and the other second bump is connected to a solder ball on the second electrical connection surface through a second lead.

3. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The interconnection dummy sheet has at least two second bumps.

4. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The interconnection dummy sheet is made of one or a combination of silicon, gallium arsenide and ceramic.

5. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The type of the first functional chip is: a central processing unit, a field programmable gate array, a digital signal processor or a memory chip.

6. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The material of the electrical wiring layer and the electrical interconnection hole is: one of copper, tungsten, gold, silver, tin, palladium or an alloy formed by a combination of several of them.

7. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The substrate insulating medium is at least one layer, and the material of the substrate insulating medium is: one or a combination of organic resin, organic film material, glass cloth, silicon oxide, silicon nitride, low temperature co-fired ceramics, and high temperature co-fired ceramics.

8. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The first bump and the second bump are: eutectic solder bumps, copper pillar bumps, micro bumps or indium bumps.

9. The substrate, redistribution layer or adapter board reusable packaging structure according to claim 1, It is characterized in that The material of the first functional chip is: one or a combination of silicon, gallium arsenide, indium gallium arsenide, silicon carbide, and gallium nitride.

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