Memory device, semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention discloses a memory device, a semiconductor device and a manufacturing method thereof. A memory device includes a memory cell including a first transistor and a second transistor disposed on a front side of a substrate having a first region and a second region. The memory device includes a first interconnect structure disposed on a backside of a substrate. One S / D terminal of the first transistor is coupled to one S / D terminal of the second transistor, and the other S / D terminal of the second transistor is coupled to the first interconnect structure through a first via structure in the first region. The memory device includes a second via structure and a third via structure, both disposed in the second region and each coupled to the first interconnect structure. The first via structure and the second via structure each have a different cross-sectional area than the third via structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device, a semiconductor device, and a method for manufacturing the same. Background Art

[0002] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) in which data is not lost when the IC is powered off. One type of OTP device includes an anti-fuse memory. The anti-fuse memory includes a plurality of anti-fuse memory cells (or bit cells) whose terminals are disconnected before programming and short-circuited (e.g., connected) after programming. The anti-fuse memory can be based on metal oxide semiconductor (MOS) technology. For example, an anti-fuse memory cell can include a programming MOS transistor (or MOS capacitor) and at least one reading MOS transistor coupled in series. The gate dielectric of the programming MOS transistor can be broken down so that the gate and source or drain of the programming MOS transistor are interconnected. Depending on whether the gate dielectric of the programming MOS transistor is broken down, the anti-fuse memory cell can present different data bits by reading the composite current flowing through the programming MOS transistor and the reading MOS transistor. Since the programming state of the anti-fuse cell cannot be determined by reverse engineering, the anti-fuse memory has the advantageous feature of reverse engineering proof. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell, comprising a first transistor and a second transistor, both of which are arranged on a first side of a substrate; a first interconnect structure, arranged on a second side of the substrate opposite to the first side, wherein a first source / drain terminal of the first transistor is floating, a second source / drain terminal of the first transistor is coupled to a first source / drain terminal of the second transistor, and a second source / drain terminal of the second transistor is coupled to the first interconnect structure; a first via structure, arranged in a first region of the substrate and configured to couple the second source / drain terminal of the second transistor to the first interconnect structure; a plurality of second via structures, arranged in a second region of the substrate and each of which is coupled to the first interconnect structure; and a third via structure, arranged in the second region of the substrate and each of which is coupled to the first interconnect structure, wherein the first via structure and the second via structure each have a first cross-sectional area, and the third via structure has a second cross-sectional area different from the first cross-sectional area.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a substrate, comprising a first region and a second region, the first region and the second region each extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction; a first active region, arranged in the first region and on the front side of the substrate, the first active region extending longitudinally along the first direction; a first transistor and a second transistor, arranged in the first active region and coupled in series; a first interconnect structure, formed on the front side of the substrate and coupled to the first transistor and the second transistor; a second interconnect structure, formed on the back side of the substrate opposite to the front side; a first through-hole structure, coupling a portion of the second transistor to the second interconnect structure; a second active region, arranged in the second region and on the first side of the substrate, the second active region extending longitudinally along the first direction; a plurality of second through-hole structures, each coupling a portion of the second active region to the second interconnect structure; and a third through-hole structure, coupling the first interconnect structure to the second interconnect structure in the second region, wherein: the first through-hole structure and the second through-hole structure each extend a first length along the first direction, and the third through-hole structure extends a second length along the first direction, the second length being longer than the first length.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a memory device is provided, comprising: providing a substrate, the substrate having a first portion and a second portion adjacent to the first portion; forming a first transistor and a second transistor in the first portion and a third transistor in the second portion on a front side of the substrate, wherein the first transistor and the second transistor are coupled in series to form an anti-fuse memory cell, and wherein the first transistor, the second transistor and the third transistor are arranged along a first direction; forming a first interconnect structure coupled to the first transistor, the second transistor and the third transistor on the front side of the substrate; forming a first through-hole structure on a back side of the substrate opposite to the front side, the first through-hole structure being coupled to portions of each of the second transistor and the third transistor, respectively; forming a second through-hole structure extending along the first direction in the second portion on the back side of the substrate, wherein the second through-hole structure is coupled to the first interconnect structure and is formed adjacent to the third transistor along a second direction perpendicular to the first direction; and forming a second interconnect structure on the back side of the substrate, the second interconnect structure extending along the first direction and coupled to the first through-hole structure and the second through-hole structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device according to some embodiments is shown.

[0008] Figure 2 According to some embodiments Figure 1 An example circuit diagram of a portion of a memory device.

[0009] Figure 3 According to some embodiments Figure 1 and Figure 2 An example circuit diagram of a memory cell of a memory device of the present invention.

[0010] Figure 4 , Figure 5 , Fig.11 , Fig.15 , Fig.16 , Fig. 20 , Fig.24 , Fig.28 , Fig.29 and Fig.30 Each shows a front-side layout design of an example memory cell coupled to a back-side interconnect structure (eg, a power rail) in accordance with some embodiments.

[0011] Figure 6 According to some embodiments, Figure 4 Schematic cross-sectional view of line AA′ of an example memory cell.

[0012] Figure 7 According to some embodiments, Figure 4 Schematic cross-sectional view of line BB' of an example memory cell.

[0013] Figure 8 , Fig.12 , Fig.17 , Fig.21 and Fig.25 The following diagrams are respectively shown according to some embodiments. Figure 4 , Fig.11 , Fig.16 and Fig.24 Schematic cross-sectional view of line CC' of an example memory cell.

[0014] Fig. 9 , Fig.13 , Fig.18 , Fig. 22 and Fig.26 The following diagrams are respectively shown according to some embodiments. Figure 4 , Fig.11 , Fig.16 and Fig.24 Schematic cross-sectional view of line DD′ of an example memory cell.

[0015] Fig.10 , Fig.14 , Fig.19 , Fig.23 and Fig. 27 The following diagrams are respectively shown according to some embodiments. Figure 4 , Fig.11 , Fig.16 and Fig.24 Schematic cross-sectional view of line EE' of an example memory cell.

[0016] Fig.31 A schematic top view of an example memory cell is shown in accordance with some embodiments.

[0017] Fig.32 A flow chart of a method of manufacturing a semiconductor device according to some embodiments is shown.

[0018] Fig.33 A block diagram of a system for generating an IC layout design according to some embodiments is shown.

[0019] Fig.34 A block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith are shown according to some embodiments.

[0020] Fig.35 A flow chart of an example method for fabricating one or more memory cells on a front side of a substrate coupled with an interconnect structure on a back side of the substrate is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] Typically, the cells of an anti-fuse memory are formed into an array. The array includes a plurality of rows and a plurality of columns, wherein at least one cell is arranged at the intersection of a row and a column. Each cell can be accessed by a corresponding combination of a first access line (e.g., a word line (WL)) arranged along a corresponding row and a second access line (e.g., a bit line (BL)) arranged along a corresponding column. With such an array configuration, the programming transistors of a plurality of cells can share one of the WLs, while their read transistors are coupled to different BLs, respectively. As technology nodes continue to shrink, it becomes challenging to provide power (e.g., voltage) to a large number of memory cells (e.g., anti-fuse memory cells) in such an array through a front-side power rail due to the increase in device density for a given device footprint. Therefore, there is a need for improvements in routing selection of anti-fuse memory arrays with reduced length scales.

[0024] The present disclosure provides various embodiments of anti-fuse memory devices, including a plurality of anti-fuse memory cells formed on the front side of a substrate. Each anti-fuse memory cell includes at least one or more pairs of programming transistors and read transistors coupled in series, wherein one of the source / drain terminals of the read transistor is coupled to a bit line (BL). In many embodiments, the BL is disposed on the back side of the substrate as part of a backside power rail implemented as a backside interconnect structure. In some embodiments, the backside power rail is coupled to the anti-fuse memory cell through a plurality of through-hole structures, the plurality of through-hole structures including, for example, backside through-holes and feed-through through-holes. In some embodiments, the voltage applied at the BL is transmitted by coupling to a similar through-hole structure of a pseudo-transistor formed in a tap region adjacent to the anti-fuse memory cell. By adjusting the arrangement of the through-hole structure, the resistance in the conduction path between the BL and the anti-fuse memory cell can be adjusted (e.g., optimized) to improve device performance.

[0025] Figure 1 Memory device 100 according to various embodiments is shown. Figure 1 In the illustrated embodiment, memory device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, and control logic circuit 110. Although not shown in FIG. Figure 1 , all components of the memory device 100 are operably coupled to each other and to the control logic circuit 110. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1Some or all of the components shown in the drawings may be integrated together. For example, the memory array 102 may include embedded I / O circuits 108. As used herein, the terms "coupled" and "connected" refer to an electrical connection or otherwise operational connection between two components, with or without any intermediate layers or components formed therebetween. Therefore, unless expressly stated otherwise, the terms "coupled," "connected," "electrically coupled," and "operably coupled" may be used interchangeably in this disclosure.

[0026] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., the Y direction). Each of the rows / columns may include one or more conductive structures, each of which is configured as an access line (e.g., a programming word line (WLP), a reading word line (WLR), a bit line (BL)), which will be discussed below. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to a voltage or current through the corresponding conductive structures of the column and the row.

[0027] In some aspects of the present disclosure, each memory cell 103 is implemented as an anti-fuse memory cell, which includes a first set of transistors and a second set of transistors coupled in series. The first set of transistors can each be used as a programming transistor for the memory cell, and the second set of transistors can each be used as a reading transistor for the memory cell. At least one of the first set of transistors can be gated by WLP; and the second set of transistors can be gated by WLR. Although the present disclosure is intended to implement the memory cell 103 as an anti-fuse memory cell, it should be understood that the memory cell 103 can include any of a variety of other memory cells while remaining within the scope of the present disclosure.

[0028] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a bit line, a source line) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0029] Figure 2 1 shows an example circuit diagram of a portion of a memory device 100 (eg, some memory cells 103) according to some embodiments. Figure 2 In the example shown, anti-fuse memory cells 103A, 103B, 103C, and 103D are shown for memory array 102. Although four anti-fuse memory cells 103A-103D are shown, it should be understood that memory array 102 may have any number of anti-fuse memory cells while remaining within the scope of the present disclosure.

[0030] As described above, the memory cells 103 may be arranged in an array. Figure 2 In the embodiment, memory cells 103A and 103B may be arranged in the same row but in different columns; and memory cells 103C and 103D may be arranged in the same row but in different columns. For example, memory cells 103A and 103B are arranged in row R0 but in columns C0 and C1, respectively; and memory cells 103C and 103D are arranged in row R1 but in columns C0 and C1, respectively. With such a configuration, each memory cell may be operably coupled to access lines in corresponding rows and columns, respectively.

[0031] For example, in Figure 2 , memory cell 103A is operably coupled to a programming word line and a reading word line (hereinafter referred to as WLP0 and WLR0, respectively) in row R0 and a bit line (hereinafter referred to as BL0) in column C0; memory cell 103B is operably coupled to WLP0 and WLR0 in row R0 and a bit line (hereinafter referred to as BL1) in column C1; memory cell 103C is operably coupled to a programming word line and a reading word line (hereinafter referred to as WLP1 and WLR1, respectively) in row R1 and BL0 in column C0; and memory cell 103D is operably coupled to WLP1 and WLR1 in row R1 and BL1 in column C1.

[0032] In some embodiments, each of the memory cells 103A-103D can be operably coupled to the I / O circuit 108 through the corresponding WLR, WLP, and BL for access (e.g., programming, reading). For example, the I / O circuit 108 can cause the row decoder 104 to assert WLP0 and WLR0, and cause the column decoder 106 to assert BL0, so as to access the memory cell 103A through WLP0, WLR0, and BL0. Therefore, each of the memory cells 103A-103D can be individually selected for programming or reading. The details of programming and reading the memory cells will be discussed below.

[0033] Each of the memory cells 103A-103D includes a plurality of programming transistors and a plurality of reading transistors, wherein each programming transistor is coupled in series to a corresponding one of the reading transistors. In addition, according to various embodiments, at least two of the programming transistors are individually gated, while the reading transistors may be commonly gated. In the following discussion, the memory cell 103A is selected as a representative example.

[0034] like Figure 2 As shown, memory cell 103A includes programming transistors (T1) 120 and 122 and read transistors (T2) 124 and 126. Programming transistor 120 is coupled in series to read transistor 124; and programming transistor 122 is coupled in series to read transistor 126. One source / drain terminal of each of programming transistors 120 and 122 is floating (i.e., not connected to any other functional component); and the other source / drain terminal of each of programming transistors 120 and 122 is coupled in series to one source / drain terminal of the corresponding read transistor 124 / 126, wherein the other source / drain terminal of read transistors 124 and 126 is commonly coupled to BL0. In some embodiments, a programming transistor (e.g., programming transistor 120) coupled in series with a read transistor (e.g., read transistor 124) is considered a unit cell (e.g., building block) of an anti-fuse memory device.

[0035] In addition, programming transistor 120 is gated by WLP0 (i.e., the gate terminal of programming transistor 120 is coupled to WLP0), while the gate terminal of programming transistor 122 may not be coupled to WLP0 (or otherwise disconnected). On the other hand, read transistors 124 and 126 are both gated by WLR0 (i.e., the gate terminals of read transistors 124 and 126 are both coupled to WLR0).

[0036] refer to Figure 3 , a further detailed circuit diagram of memory cell 103A according to some embodiments is provided to illustrate the operation of each memory cell 103. As shown, each of programming / reading transistors 120 to 126 may include an n-type metal oxide semiconductor field effect transistor (n-type MOSFET), or sometimes referred to as an NMOS transistor. However, it should be understood that each of programming / reading transistors 120 to 126 may include a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) while remaining within the scope of the present disclosure.

[0037] Specifically, respective drain terminals 120D and 122D of programming transistors 120 and 122 are floating (e.g., coupled to no function), and respective source terminals 120S and 122S thereof are coupled to drain terminals 124D and 126D of read transistors 124 and 126, respectively. Source terminals 124S and 126S of read transistors 124 and 126 are commonly coupled to BL0. Programming transistor 120 has a gate terminal 120G coupled to WLP0, while programming transistor 122 has a gate terminal 122G isolated from WLP0. On the other hand, read transistors 124 and 126 have their respective gate terminals 124G and 126G, which are commonly coupled to WLR0.

[0038] To program memory cell 103A, read transistors 124 and 126 are turned on by providing a sufficiently high voltage (e.g., a positive voltage corresponding to a logic high state) to gate terminals 124G and 126G via WLR0. Before, simultaneously with, or subsequently to turning on read transistors 124 and 126, a sufficiently high voltage (e.g., a breakdown voltage (V ) sometimes referred to as a programming voltage) is applied to gate terminals 124G and 126G. BD )) is applied to WLP0, and a sufficiently low voltage (e.g., a positive voltage corresponding to a logic low state or a ground voltage) is applied to BL0. The low voltage applied to BL0 can be transmitted to the source terminal 120S, so that V BD will exist between the source terminal 120S and the gate terminal 120G, thereby causing breakdown of a portion of the gate dielectric of the programming transistor 120 (eg, the portion between the source terminal 120S and the gate terminal 120G).

[0039] After the gate dielectric of the programming transistor 120 is broken down, the portion of the gate dielectric interconnecting the gate terminal 120G and the source terminal 120S behaves as a resistor. Figure 3 As shown, such a portion can be used as resistor 150. Before programming (before the gate dielectric of programming transistor 120 is broken down), there is no conduction path between BL0 and WLP0 even if read transistors 124 and 126 are turned on. After programming, when read transistors 124 and 126 are turned on, there is a conduction path between BL0 and WLP0 (e.g., via resistor 150).

[0040] To read memory cell 103A, similar to programming, read transistors 124 and 126 are turned on via WLR0, and BL0 is coupled to a voltage corresponding to a logic low state. In response, a positive voltage is applied to the gate terminal of programming transistor 120 via WLP0. As described above, if the gate dielectric of programming transistor 120 is not broken down, there is no conduction path between BL0 and WLP0. Therefore, a relatively low current is conducted from WLP0, through transistor 120 and transistors 124 and 126, and to BL0. If the gate dielectric of programming transistor 120 is broken down, there is a conduction path between BL0 and WLP0. Therefore, a relatively high current is conducted from WLP0, through transistor 120 (now equivalent to resistor 150) and transistors 124 and 126, and reaches BL0. Such low current and high current may sometimes be referred to as the I of memory cell 103A, respectively. off and I on . I / O circuit 108 coupled to BL0 ( Figure 1 ) circuit components (such as sense amplifiers) can distinguish I off and I on (and vice versa), thereby determining whether the memory cell 103A presents a logic high ("1") or a logic low ("0"). For example, when reading I on When 1 is read, the memory cell 103A may present a 1; and when 1 is read off Memory cell 103A may present 0 at this time.

[0041] According to various embodiments of the present disclosure, the programming transistor T1 (e.g., programming transistors 120 and 122) and the reading transistor T2 (e.g., reading transistors 124 and 126) are formed on the same side (e.g., front side) of a semiconductor substrate (or substrate), while the voltage applied to the BL (e.g., BL0) of the anti-fuse memory cell 103 is provided from a power rail disposed on the opposite side (e.g., back side) of the substrate through various types of via structures. Such a back-side power rail including a back-side metallization layer may be interchangeably referred to as a back-side interconnect structure throughout the present disclosure. In other words, the back-side interconnect structure may be operatively used as the BL of the anti-fuse memory cell 103. Thus, when a programming voltage is applied to a gate terminal (e.g., gate terminal 120G) of a programming transistor T1 (e.g., programming transistor 120) via WL (e.g., WLP0), a conduction (e.g., programming) path extends from the gate terminal, through at least a source / drain terminal (e.g., source terminal 120S) of the programming transistor T1, both source / drain terminals (e.g., drain terminal 124D and source terminal 124S) of the read transistor T2, a plurality of via structures (e.g., backside vias and / or feedthrough vias), and to a backside interconnect structure. This configuration differs from existing conventional anti-fuse memory cell designs in which the voltage applied at BL is typically provided from the front side, e.g., via a frontside interconnect structure. In this regard, the anti-fuse memory cell 103 of the present disclosure benefits from at least additional routing options from the back side of the substrate, thereby increasing flexibility in cell design and / or ease of manufacturing associated with a manufacturing process.

[0042] In some embodiments, additional via structures, such as backside vias and / or feedthrough vias, are incorporated via dummy transistors coupled to a conduction path between a terminal of a transistor (e.g., a drain terminal of a read transistor T2 in a unit cell) and a backside power rail (i.e., a backside interconnect structure), which is operable to serve as a BL to the anti-fuse memory cell to reduce conduction path resistance and improve device performance in the anti-fuse memory cell 103. In some embodiments, the gate terminal and source / drain terminals of each dummy transistor are coupled to the BL. In some embodiments, the dummy transistors are formed in a tap region (e.g., a P-tap region of an n-type transistor), which extends at least partially adjacent to a device region including the anti-fuse memory cell.

[0043] For example, the present disclosure provides an anti-fuse memory cell structure that includes a device region adjacent to a tap (e.g., pickup, dummy, guard ring, etc.) region on a front side of a substrate, wherein the device region includes a plurality of anti-fuse memory cells, and wherein the tap region includes a plurality of dummy transistors. Each anti-fuse memory cell may include at least one programming transistor T1, such as programming transistor 120, which is coupled in series to a read transistor T2, such as read transistor 124, wherein programming transistor T1 and read transistor T2 are collectively referred to as functional transistors. The source / drain terminals (e.g., Figure 5 The source / drain region 218B) is further coupled to a BL (i.e., a power rail or interconnect structure) disposed in a metallization layer on the back side of the substrate. The source terminal, drain terminal, and gate terminal of each pseudo-transistor are coupled to the BL disposed in the backside metallization layer through at least one additional via structure. In this regard, the resistance along the conduction path can be tuned (e.g., reduced) for a given applied voltage at the BL. In some embodiments, the programming transistor T1 and the reading transistor T2 are formed as part of a front-end-of-line (FEOL) process on the front side of the substrate, and a plurality of metallization layers (each of which includes a plurality of metal structures (e.g., metal lines)) are formed as part of a front-side interconnect structure of a front-end-of-line (BEOL) process by a front-side FEOL process. In addition, the backside metallization layer is formed as part of the backside interconnect structure.

[0044] In some embodiments, the arrangement of the via structures for connecting the functional transistors and the pseudo-transistors is determined based on, for example, the size of each via structure relative to the size of the cell area in which the via structures can be arranged. For example, the backside via coupled to and overlapping the source / drain terminals of the access transistor has a smaller cross-sectional area than the feed-through via, which generally has an elongated shape extending parallel to the active area (e.g., fin) of the anti-fuse memory cell in a top view. Since the resistance generally varies inversely with the cross-sectional area of ​​the conductor, the resistance of the backside via is higher than the resistance of the feed-through via. In some examples, the resistance of the feed-through via can be as low as 1 / 8 of the resistance of the backside via. Therefore, for a device area with a more limited cell area than the tap area, a more area-efficient backside via can be utilized, and more feed-through vias can be utilized in the tap area. In some embodiments, backside vias and feed-through vias are used in both the device area and the tap area.

[0045] Figure 4 2 shows a front side layout design of a portion of an example semiconductor device 200. The semiconductor device 200 includes a plurality of anti-fuse memory cells 201A (eg, anti-fuse memory cells 103) disposed on a front side 202A of a semiconductor substrate (or substrate) 202 (eg, see Figure 5 ). An embodiment of the anti-fuse memory cell 201A is Figure 4 In some embodiments, substrate 202 includes a plurality of doped wells, such as a p-type well and an n-type well for providing n-type devices (such as NMOS devices) and p-type devices (such as PMOS devices), respectively. Figure 4 and follow-up Figure 5-Figure 35 Various dielectric components, such as the FEOL isolation region of the anti-fuse memory cell 201A, have been omitted in order to make the description of the various components of the anti-fuse memory element 201A clearer.

[0046] In the present embodiment, the substrate 202 includes a first region (e.g., area, portion, etc.) P1, a second region P2, and a third region P3 between the first region P1 and the second region P1 along a first lateral direction (e.g., X-axis). In some embodiments, the first region P1 is configured as a device region for providing an active component of the anti-fuse memory cell 201A, and the second region P2 is configured as a tap region adjacent to or surrounding the first region P1, for separating the first region P1 of adjacent anti-fuse memory cells 201A and other functions in a given layout of the semiconductor device 200. The third region P3 may be configured as a dummy region (e.g., without any device), and may include at least one dummy gate structure 222 and at least one source / drain contact 232, each dummy gate structure extending longitudinally along a second lateral direction (e.g., Y-axis) and interposed between the vertical boundaries of the first region P1 and the second region P2 along the first lateral direction. In some embodiments, as shown herein, the second region P2 extends adjacent to the first region P1 along the second lateral direction.

[0047] The first region P1 has a first cell height H1 and the second region P2 has a second cell height H2, each cell height being defined along a second lateral direction. In some embodiments, the cell heights H1 and H2 are the same. In some embodiments, the cell height H1 is greater than the cell height H2. In some embodiments, the cell height H2 is greater than the cell height H1. In some examples, the cell heights H1 and H2 are each at least about 156 nm. Figure 4 In the embodiment shown, cell heights H1 and H2 are both about 208 nm.

[0048] In the first region P1, the anti-fuse memory cell 201A includes a plurality of active regions (also referred to as oxide diffusion regions or OD regions) 204 on the front side 202A of the substrate 202 and separated by isolation regions (not shown separately). Each active region 204 extends longitudinally along a first lateral direction and is separated from one another along a second lateral direction. Each of the active regions 204 may include a monolithic structure, such as a fin active region, for providing a fin field effect transistor (FinFET). Alternatively, each of the active regions 204 may include a stack of nanostructures (e.g., nanosheets, nanorods, etc.) for providing a gate-all-around (GAA) FET. According to some embodiments of the present disclosure, other configurations of the active region 204 may also be applied to the anti-fuse memory cell 201A. As Figure 4 As shown, each active region 204 has a height H3 defined along the second lateral direction, and adjacent active regions 204 are separated by a distance M, which is also referred to as a height of the dummy region 203 of the substrate 202 .

[0049] refer to Figure 4 , the anti-fuse memory cell 201A includes a plurality of gate structures (e.g., functional gate structures) 220A and 220B, which are perpendicular to the orientation of portions of the active region 204 and on the active region 204 to define a channel region in the active region, wherein each channel region is between a pair of source / drain regions (e.g., source / drain terminals) along a first lateral direction. In some embodiments, portions of the gate structures 220A and 220B (collectively referred to as gate structures 220) are spaced apart along a second lateral direction and separated by a dummy region 203. In some embodiments, the anti-fuse memory cell 201A further includes at least one gate structure 221, which is disposed between the outermost one of the gate structures 220 and the third region P3. The gate structure 221 serves as a dummy gate structure for coupling to the ground (VSS) of the anti-fuse memory cell 201A.

[0050] In this embodiment, reference Figure 5 , which depicts Figure 4Detail A of FIG. 2 shows an enlarged view of each gate structure 220A, each gate structure 220A is joined with each pair of source / drain regions 216A / 216B (collectively referred to as source / drain regions 216) to form a programming transistor T1 (a first functional transistor, e.g., a FinFET, a GAA FET, etc.), and each gate structure 220B is joined with each pair of source / drain regions 218A / 218B (collectively referred to as source / drain regions 218) to form a reading transistor T2 (a second functional transistor, e.g., a FinFET, a GAA FET, etc.). The connection and operation of the programming transistor T1 and the reading transistor T2 applied to an anti-fuse memory cell such as the anti-fuse memory cell 201A have been described in detail above. For example, one of the source / drain regions of the programming transistor T1 (e.g., drain region 216A) is floating, and the other of the source / drain regions of the programming transistor T1 (e.g., source region 216B) is coupled in series to one of the source / drain regions of the reading transistor T2 (e.g., drain region 218A) to form an anti-fuse cell (or cell) 225. The other of the source / drain regions (e.g., source region 218B) is coupled to a power rail, which is operable as a BL, which is disposed in a metallization layer on the back side 202B of the substrate 202, as described in detail below. Therefore, the unit cell 225 is referred to as a two-transistor (2T) unit cell. In the present embodiment, as shown, the source / drain regions 218 of two adjacent cells 225 are coupled together at the BL. In addition, although in Figure 4 Two 2T unit cells 225 are depicted in FIG. 2 , but the present embodiment is not limited to such a number or configuration of the unit cells 225 as long as one of the source / drain terminals (eg, the drain terminal) of the read transistor T2 in the unit cell 225 is coupled to the BL disposed on the back side 202B of the substrate 202 .

[0051] Still reference Figure 4 , the anti-fuse memory cell 201A further includes a plurality of source / drain contacts 230, which extend longitudinally along the second lateral direction and are separated from each other along the first lateral direction, each inserted between adjacent gate structures 220. Each of the source / drain contacts 230 is coupled to each of the source / drain regions 216 / 218 of the programming transistor T1 and the reading transistor T2, respectively. In the depicted embodiment, each source / drain contact 230 protrudes from one of the long edges of the active region 204 toward the horizontal boundary L1 of the first region P1 along the second lateral direction.

[0052] refer to Figure 4 and Figure 5, the semiconductor device 200 also includes a front side interconnect structure 300 coupled to the source / drain contacts 230 and the gate structure 220 of the anti-fuse memory cell 201A. The front side interconnect structure 300 includes, for example, a through hole 260, which is configured to couple at least one of the source / drain contacts 230 to a front side metallization layer 310 (M0), and the front side metallization layer 310 includes, for example, metal lines (e.g., metal tracks) 310A, 310B, 310C, and 310D. The anti-fuse memory cell 201A also includes a gate contact 262, which is configured to couple at least some of the gate structures 220 to the front side metallization layer 310. The front side metallization layer 310 can be the first of many metallization layers (e.g., front side metal layers 330 and 350) disposed above the front side 202A of the substrate in the first region P1. Referring to Figure 8-Figure 10 Details of the front-side interconnect structure 300 are described.

[0053] In some embodiments, reference Figure 4 , the second region P2 is a tap region that electrically couples a specific doped well in the substrate 202 (e.g., an n-type well for forming a PMOS device or a p-type well for forming an NMOS device) to a voltage source (e.g., power / ground). In the depicted embodiment, since the functional transistor is an NMOS device, the second region P2 is a p-type tap (or p-tap) region configured to electrically couple the p-type well in the anti-fuse memory cell 201A to the power / ground. In some embodiments, the tap region physically and electrically separates adjacent anti-fuse memory devices 201A. In some embodiments, multiple tap regions may be formed to surround the device region, i.e., the first region P1. In some embodiments, the second region P2 is implemented in the anti-fuse memory cell 201A to reduce or prevent undesirable short circuits caused by latch-up.

[0054] Still reference Figure 4 In the second region P2, the semiconductor device 200 includes a plurality of active regions 206 on the front side 202A of the substrate 202. The active regions 206 are similar to the active regions 204. For example, each active region 206 extends longitudinally along a first lateral direction and is separated from each other along a second lateral direction. Two adjacent active regions 206 are separated by a dummy region 205 in the substrate 202, similar to the dummy region 203 between two adjacent active regions 204.

[0055] Active areas 206 each have a height H4 defined along the second lateral direction, wherein height H4 may be the same as or different from height H3. In some embodiments, height H3 is greater than or equal to height H4. In some embodiments, height H3 and height H4 are each about 32nm, 42nm, or 58nm. For example, height H3 may be about 42nm, and height H4 may be about 32nm. The separation distance N between two adjacent active areas 206 extending as the height of dummy area 205 may be the same as or different from the distance M of dummy area 203. In some instances, distance (or height) M is at least about 62nm and distance (or height) N is at least about 72nm. As will be discussed in detail below, when height M and height N are respectively greater than the height of the feed-through hole defined along the second lateral direction, it is possible to form a feed-through hole between two adjacent active areas 204 and / or between adjacent active areas 206. As shown herein, the cell height H1 is the sum of the total height of the active region 204 (e.g., 2*H3), the height M of the dummy region 203, and the total separation distance between each active region 204 and the corresponding horizontal boundary L1 of the first region P1, which can be calculated as the sum of x*M and (1-x)*M, where x is a fraction between 0 and 1. In other words, the total separation distance between each active region 204 and the corresponding horizontal boundary L1 is equal to the height M. Similarly, the cell height H2 is the sum of the total height of the active region 206 (e.g., 2*H4), the height N of the dummy region 205, and the total separation distance between each active region 206 and each corresponding horizontal boundary L2 of the second region P2, which can be calculated as the sum of y*N and (1-y)*N, where y is a fraction between 0 and 1.

[0056] Similar to the first region P1, the second region P2 of the semiconductor device 200 includes a plurality of gate structures 224 that are perpendicular to the orientation of a portion of each active region 206 and above a portion of each active region to define a channel region between a pair of source / drain regions 226 / 228 along a first lateral direction. Thus, the gate structure 224 is joined to each pair of source / drain regions 226 / 228 to form a pseudo transistor T3 (e.g., FinFET, GAA FET, etc.). The semiconductor device 200 also includes a plurality of source / drain contacts 234 that extend along a second lateral direction and are between adjacent gate structures 224. Each of the source / drain contacts 234 is electrically coupled to each of the source / drain regions 226 / 228 of the pseudo transistor T3. In the depicted top view, each source / drain contact 234 protrudes from one of the long edges of the active region 204 toward the horizontal boundary L2 of the second region P2 along the second lateral direction.

[0057] In the present embodiment, the source / drain terminals (i.e., both source / drain regions 226 / 228) and the gate terminal between the source / source terminals of each dummy transistor T3 are coupled to a BL disposed on the back side 202B of the substrate 202 as part of the backside interconnect structure 250. Thus, the dummy transistor T3 does not participate in the operation of the anti-fuse memory cell 201A. In some embodiments, reference is made to Figure 4 The backside interconnect structure 250 includes a backside metallization layer (BM0) 252, which also includes, for example, a plurality of metal lines (or metal tracks) 252A, 252B, and 252C. In this embodiment, a plurality of dummy transistors T3 are coupled together in parallel.

[0058] Similar to the first region P1, a portion of the dummy transistor T3 in the second region P2 is coupled to the front side interconnect structure 300. For example, the via 260 is configured to couple each of the source / drain contacts 234 to the front side metallization layer 310, and the gate contact 262 is configured to couple each of the gate structures 224 to the front side metallization layer 310.

[0059] refer to Figure 6 , which shows that along Figure 4 2 , the semiconductor device 200 includes a backside via 240 coupled to a portion of the anti-fuse memory cell 201A in the first region P1. The backside via 240 extends vertically (e.g., along the Z-axis) through at least the substrate 202 and the active region 204 to couple a metal line 252A of a backside metallization layer (BM0) 252 to a source / drain region 218 (218B) of a read transistor T2 in an adjacent cell 225, as shown in FIG. Figure 5 Metal line 252A is considered to be the backside interconnect structure 250 (eg Figure 2 and Figure 3 2) is a portion of the backside interconnect structure 250 that is coupled to the front side components (e.g., programming transistor T1 and reading transistor T2) of the anti-fuse memory cell 201A through the backside via 240. In the present embodiment, the backside via 240 directly contacts the metal line 252A and the source / drain region 218. In this regard, the backside via 240 partially penetrates the active region 204 in the vertical direction (e.g., along the Z-axis). As described above, the backside interconnect structure 250 is configured to provide a voltage from the backside 202B to the source / drain region 218 on the front side 202A of the substrate 202 to establish a conduction (e.g., programming) path of the anti-fuse memory cell 201A.

[0060] The backside via 240 has a width 241 defined along the first lateral direction. Although not shown, the backside via 240 may include a metal filling layer (not shown separately) on a barrier layer (not shown separately). The metal filling layer may include any suitable conductive material, including, for example, tungsten (W), copper (Cu), aluminum (Al), gold (Au), cobalt (Co), ruthenium (Ru), etc., or a combination thereof. In some examples, the metal filling layer may include a seed layer. The barrier layer may include Ti, Ta, TiN, TaN, etc., or a combination thereof. In some embodiments, although not shown, the anti-fuse memory cell 201A also includes a first metal silicide layer disposed between the backside via 240 and the source / drain region 218 and a second metal silicide disposed between the front side (or top surface) of the source / drain region 216 / 218 and the source / drain contact 230.

[0061] Figure 7 Shown along Figure 4 The feed-through via 280 in the cross-sectional view of the anti-fuse memory cell 201A along line BB′ in the second region P2 of FIG. Figure 4 As shown in the layout design of FIG. 2 , the feed-through via 280 extends longitudinally in a first lateral direction in a top view and is separated from the adjacent active regions 206 in a second lateral direction. Specifically, the feed-through via 280 is disposed between two adjacent active regions 206. The feed-through via 280 extends through at least the substrate 202 to couple a metal line 252C similar to the metal line 252A to the contact feature 236 on the front side 202A of the anti-fuse memory cell 201A, and then to the front side interconnect structure 300. Unlike the backside via 240, the feed-through via 280 couples the metal line 252C directly to the contact feature 236 and is therefore not coupled to any portion of the pseudo transistor T3. The feed-through via 280 may include a metal filling layer (not shown separately) on a barrier layer (not shown separately), similar to the backside via 240.

[0062] The feed-through via 280 has a width 281 defined along the first lateral direction, wherein the width 281 is greater than the width 241 of the backside via 240, such as Figure 4 Thus, the cross-sectional area of ​​the feed-through via 280 in the XY plane is larger than the cross-sectional area of ​​the backside via 240, resulting in a lower resistance than the backside via 240. As described above, the compositions of the metal filling layer and the barrier layer may be similar to those of the metal filling layer or the barrier layer of the backside via 240, respectively.

[0063] Figure 8 Shown along Figure 4 A cross-sectional view of a portion of the semiconductor device 200 in the first region P1 along line CC′, the cross-sectional view passing through Figure 5Two adjacent cells 225 are shown. Backside vias 240 couple backside metallization layer (BM0) 252 (e.g., metal line 252A) to source / drain regions 218 of read transistor T2 in each cell 225, establishing a connection that transfers the voltage applied at BL from backside 202B to anti-fuse memory cell 201A on frontside 202A.

[0064] Fig. 9 Shown along Figure 4 FIG. 1 is a cross-sectional view of a portion of the semiconductor device 200 in the second region P2 along line DD′. Figure 8 2 shows a cross-sectional view of the anti-fuse memory cell 201A along a first lateral direction, but Fig. 9 The second region P2 is shown to cross the active region 206 and the adjacent dummy region 205 along the second lateral direction. The semiconductor device 200 in the second region P2 includes a backside through hole 244 (also in Figure 4 ), the backside via extends vertically (e.g., along the Z-axis) through a portion of the substrate 202 and the active region 206 to couple the metal line 252B to one of the source / drain regions 226 / 228 of the dummy transistor T3, wherein the metal line 252B (also shown in the attached Figure 4 The backside through hole 244 extends longitudinally along the second lateral direction, as shown in FIG. Figure 4 As shown in the layout design of . Through the pseudo transistor T3 in the second region P2, the backside via 244 couples the backside interconnect structure 250 to the frontside interconnect structure 300, and then couples to the functional transistors (e.g., programming transistor T1 and reading transistor T2) of the anti-fuse memory cell 201A in the first region P1, thereby establishing a conduction path between the functional transistor, the pseudo transistor T3 and the backside interconnect structure 250, from which a voltage is applied. In some embodiments, the backside via 244 is similar in structure and size to the backside via 240 of the anti-fuse memory cell 201A. In some embodiments, the backside vias 240 and 244 have the same structure and size. For example, the backside vias 240 and 244 both have a width 241 as described above. In the present embodiment, the backside vias 240, 244 and the feedthrough via 280 are coupled in parallel between the front side interconnect structure 300 and the backside interconnect structure 250.

[0065] In addition, still refer to Fig. 9, the semiconductor device 200 in the second region P2 includes a feedthrough via 280 extending vertically through the dummy region 205 (i.e., the substrate 202) to couple the backside metallization layer 252 (e.g., metal line 252C) to the contact feature 236, which is further coupled to the frontside interconnect structure 300. This is in contrast to the backside via 244 that couples the metal line 252B to one of the source / drain regions 226 / 228 of the dummy transistor T3. In the depicted embodiment, the metal lines 252B and 252C are separated from each other along the second lateral direction, as shown in FIG. Figure 4 As depicted. Through contact feature 236, feedthrough via 280 couples backside interconnect structure 250 to frontside interconnect structure 300 and subsequently to the functional transistor, thereby establishing a conduction path between functional transistors T1 and T2, dummy transistor T3, and backside interconnect structure 250, from which voltage is applied. As described above, feedthrough vias generally exhibit lower resistance than backside vias due to a larger cross-sectional area (e.g., width 281 is greater than width 241), so by incorporating feedthrough via 280 in second region P2, the resistance of the conduction path can be further reduced.

[0066] In some embodiments, the feedthrough vias 280 have a height H5 extending along the second lateral direction. In this regard, the arrangement of the feedthrough vias 280 between the active regions 206 indicates that the height N of the dummy region 205 is configured to exceed the height H5 of the feedthrough vias 280. In some embodiments, the height H5 is about 70 nm and the height N is at least about 72 nm. In some embodiments, the height H5 is determined based on the height N or the height H4 of the active region 206 given a constant cell height H2 of the second region P2. In the depicted embodiment, because the height M of the dummy region 203 in the anti-fuse memory cell 201A is less than the height H5 (e.g., due to a predetermined size of the first region P1 according to applicable design rules), the first region P1 does not include any feedthrough vias.

[0067] Fig.10 Shown along Figure 4 2 is a cross-sectional view of a portion of the semiconductor device 200 in the first region P1 along line EE′, wherein line EE′ passes through the source / drain region 218 of the read transistor T2 in the unit cell 225 along the second lateral direction. In this regard, Fig.10 A portion of the first region P1 spanning the active region 204 and the adjacent dummy region 203 is shown, wherein the source / drain regions 218 are coupled to metal lines 252A in the backside interconnect structure 250 through the backside vias 240 .

[0068] Common Reference Figure 8-Figure 10, additional details of the front-side interconnect structure 300 and the back-side interconnect structure 250 are also shown. For example, the front-side interconnect structure 300 also includes a front-side metallization layer 330 disposed above the front-side metallization layer 310 and interconnected to the front-side metallization layer 310 through vias 320A, 320B, 320C, 320D, and 320E (collectively referred to as vias 320 (V0)). Additional front-side metallization layers on the front-side metallization layer 310 (M0) may be designated as M1, M2, ..., and M n , wherein the adjacent front metallization layers are respectively connected through vias V1, V2, ... V n-1 Each front side metallization layer includes one or more metal lines to a corresponding via. In the depicted embodiment, front side metallization layers M1 and M2 correspond to front side metal layers 330 (including metal lines 330A, 330B, 330C, and 330D) and 350 (including metal lines 350A and 350B), respectively, and via V1 corresponds to via 340 (including vias 340A and 340B).

[0069] Similarly, the backside interconnect structure 250 includes a plurality of backside metallization layers, such as BM0, BM1, . . . and BM n , through the through holes (such as BV0, BV1, ... BV n-1 For example, backside metallization layer 252(BM0) including metal lines 252A, 252B, and 252C is interconnected to backside metallization layer 254(BM1) including metal lines 254A, 254B, and 254C through one or more of vias 272A, 272B, 272C, and 272D (collectively referred to as vias 272(BV0)).

[0070] It is worth noting that, for the purpose of simplicity and clarity, various dielectric (e.g., insulating) layers forming the front and back metallization layers (including interconnect structures) are omitted in the description of various embodiments of the anti-fuse memory cell disclosed herein. These dielectric layers may include, for example, an etch stop layer (ESL), an interlayer dielectric (ILD) layer, and an intermetallic dielectric (IMD) layer. In addition, in Figure 8-Figure 10 , Figure 12-14 , Figure 17-Figure 19 , Figure 21-23 and Figure 25-27 The substrate 202 extending below the active regions 204 and 206 and the dummy regions 203 and 205 is also omitted in the cross-sectional views of the various anti-fuse memory cells shown.

[0071] In some embodiments, reference Figure 11-Figure 14, the semiconductor device 200 includes a plurality of anti-fuse memory cells 201B. In some embodiments, the anti-fuse memory cells 201B are similar in some respects to the anti-fuse memory element 201A. For example, the anti-fuse memory cells 201B are respectively connected along Fig.12 and Fig.13 The cross-sectional view of lines CC' and DD' shown in FIG. Figure 8 and Fig. 9 0048] A cross-sectional view of an anti-fuse memory cell 201A is shown in FIG.

[0072] However, with Figure 4 Unlike the anti-fuse memory cell 201A shown in the top view and the corresponding cross-sectional view, the dummy region 203 of the anti-fuse memory cell 201B includes a feedthrough hole 286. Fig.11 and Fig.14 , which respectively depict the front layout design and the Fig.11 In the cross-sectional view of line EE' of FIG. 1 , the dummy region 203 in the first region P1 is configured to have a height M that exceeds the height H5 of the feed-through via 286. In this regard, for a given cell height H1, which is substantially the same as the cell height H2 in the illustrated embodiment, the height H3 of the active region 204 is reduced to expand the area of ​​the dummy region 203, thereby allowing the layout of the first region P1 to accommodate the placement of the feed-through via 286. In some embodiments, the reduced height H3 is similar to or the same as the height H4 of the active region 206 in the second region P2. In some embodiments, the reduced height H3 is greater than the height H4 of the active region 206. In some embodiments, instead of reducing the height H3 of the active region 204, the active region 204 is further spaced apart along the second lateral direction to increase the height M of the dummy region 203. In some embodiments, the feed-through via 286 has a width L along the first lateral direction. FTV As shown, the width L FTV Extends the entire width L of the first region P1 P1 .

[0073] In some embodiments, feedthrough holes 280 and 286 have the same structure and size. For example, feedthrough holes 280 and 286 have the same height H5 and width 281 as described above. Fig.13 and Fig.14By comparison, feedthrough vias 286 couple backside interconnect structure 250 (e.g., metal line 252C) to source / drain contacts 230, which are further coupled to frontside interconnect structure 300 (e.g., to metal line 330C through vias 320F and 320G), while feedthrough vias 280 couple backside interconnect structure 250 (e.g., metal line 252) to contact feature 236. Introducing feedthrough vias 286 in first region P1 further reduces the resistance of the conduction path between functional transistors T1 and T2, dummy transistor T3, and backside interconnect structure 250, which is operable to serve as the BL of anti-fuse memory cell 201A.

[0074] In some embodiments, reference Fig.15 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201C. In some embodiments, the anti-fuse memory cells 201C are similar in some respects to the anti-fuse memory cells 201B. For example, in Fig.15 In the top view of , the source / drain region 218 of each read transistor T2 is coupled to the backside interconnect structure 250 through the backside via 240 in the first region P1, the front side interconnect structure 300 is coupled to the backside interconnect structure 250 in the first region P1 (i.e., the dummy region 203) through the feed-through via 286, the source / drain region 226 / 228 of the dummy transistor T3 is coupled to the backside interconnect structure 250 through the backside via 244 in the second region P2, and the front side interconnect structure 300 is coupled to the backside interconnect structure 250 in the second region P1 (e.g., the dummy region 205) through the feed-through via 280.

[0075] However, unlike the anti-fuse memory cell 201B, the length L of the feedthrough hole 286 disposed in the dummy region 203 of the anti-fuse memory cell 201C is FTV is smaller than the conductive via 286 disposed in the dummy region 203 of the anti-fuse memory cell 201B. In some embodiments, L FTV The range of L is about 1 nm to about 500 μm. In some embodiments, L FTV Extends from width L CPP To width L P1 The distance, where the width L CPP is equal to a gate pitch (ie, the separation distance between two adjacent gate structures 220), and the width L P1 Equal to the entire width of the first region P1 along the first lateral direction.

[0076] In some embodiments, reference Figure 16-Figure 19 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201D, wherein Fig.16 2 shows the front side layout design of the anti-fuse memory cell 201D. Fig.18 Shown along Fig.16 DD' of the anti-fuse memory cell 201D. In some embodiments, the anti-fuse memory cell 201D is similar to the anti-fuse memory element 201B in some aspects. For example, the anti-fuse memory cell 201D is respectively along the line DD' of Fig.17 and Fig.19 The cross-sectional view of lines CC' and EE' shown in FIG. Fig.12 and Fig.14 In this regard, the dummy region 203 in the first region P1 of the anti-fuse memory cell 201D is configured to have a height M exceeding the height H5 of the feedthrough via 286, and the height H3 of the active region 204 does not exceed the height H4 of the active region 206.

[0077] However, with Figure 11-Figure 14 The anti-fuse memory cell 201B shown in FIG. Fig.16 and Fig.18 , the dummy region 205 of the anti-fuse memory cell 201D does not include any feedthrough vias 280. Therefore, the resistance of the conduction path between the functional transistors T1 and T2, the dummy transistor T3, and the backside interconnect structure 250 in the anti-fuse memory cell 201D may be similar to the resistance of the anti-fuse memory cell 201A, but greater than the resistance of the anti-fuse memory cell 201B.

[0078] In some embodiments, reference Figure 20-23 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201E, wherein Fig. 20 2 shows the front side layout design of the anti-fuse memory cell 201E. Fig. 22 Shown along Fig. 20 DD' of the anti-fuse memory cell 201E. In some embodiments, the anti-fuse memory cell 201E is similar to the anti-fuse memory element 201A in some aspects. For example, the anti-fuse memory cell 201E is respectively along the line DD' of Fig.21 and Fig.23 The cross-sectional view of lines CC' and EE' in FIG. Figure 8 and Fig.10 0048] A cross-sectional view of an anti-fuse memory cell 201A is shown in FIG.

[0079] and Figure 4Unlike the anti-fuse memory cell 201A shown in the corresponding cross-sectional view, the dummy region 205 of the anti-fuse memory cell 201E does not include any feedthrough vias 280. Therefore, the resistance of the conduction path between the functional transistors T1 and T2, the dummy transistor T3, and the backside interconnect structure 250 in the anti-fuse memory cell 201E can be greater than the resistance of the anti-fuse storage memory cells 201A-201D. However, omitting the feedthrough vias 280 and 286 can have at least the benefit of reducing the complexity and cost of the manufacturing process by using fewer masks (or photomasks) that are intended to perform a photolithography process in forming the feedthrough vias.

[0080] In some embodiments, reference Figure 24-Figure 27 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201F, wherein Fig.24 2 shows the front side layout design of the anti-fuse memory cell 201F. Fig.26 Shown along Fig.24 A cross-sectional view of the anti-fuse memory cell 201F along line DD′, Fig. 27 Shown along Fig.24 2 is a cross-sectional view of the anti-fuse memory cell 201F along line EE′. In some embodiments, the anti-fuse memory cell 201F is similar to the anti-fuse memory cell 201B in some aspects. For example, the dummy regions 203 and 205 of the anti-fuse memory cell 201F include feedthrough vias 280 and 286, respectively.

[0081] However, unlike the anti-fuse memory cell 201B, the first region P1 and the second region P2 of the anti-fuse memory cell 201F do not have any backside vias 240 and 244, respectively, which are present in the anti-fuse memory element 201B. In this regard, although the resistance of the conduction path between the functional transistors T1 and T2, the dummy transistor T3, and the backside interconnect structure 250 in the anti-fuse memory cell 201F may be greater than that of the anti-fuse memory cell 201B, omitting the backside vias 240 and 244 may at least have the benefit of reducing the complexity and cost of the manufacturing process, similar to the benefit of omitting the feedthrough vias 280 and 286 in the structure of the anti-fuse memory cell 201E.

[0082] In some embodiments, reference Fig.28 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201F. The semiconductor device 200 includes two of the first regions P1 arranged along the first lateral direction and separated by the third region P3. For simplicity, the second region P2 is Fig.28 is omitted, although it can be expressed similarly to, for example Figure 4 , Fig.11 , Fig.15 , Fig.16 , Fig. 20 and Fig.24 The manner shown in any one of them is arranged adjacent to the third area P3.

[0083] In some embodiments, as described above with reference to Figure 24-Figure 27 As depicted and described, each anti-fuse memory cell 201F includes two unit cells 225, which are coupled together at the source / drain regions 218 of their respective read transistors T2 by a BL disposed on the back side 202B of the substrate 202 and coupled to the front side 202A of the substrate 202 by at least a feed-through via 286. In the depicted embodiment, the feed-through via 286 extends vertically from the metal line 252C of the backside interconnect structure 250, through the substrate 202, to the contact feature 230 (see, for example, FIG. Fig. 27 Each of the first regions P1 includes a gate structure coupled to a different gate structure (eg, gate structure 220; see, for example, Figure 5 ) and three BLs (e.g., BL0, BL1, and BL2) respectively coupled to the source / drain regions 218 of the read transistors T2 in the unit cells 225 arranged along the first lateral direction. In this regard, Fig.28 The semiconductor device 200 shown in FIG. 2 includes a layout having a three (BL) by four (WL) (3×4) array. In some examples, the semiconductor device 200 can include any one of a plurality of anti-fuse memory cells 201A- 201E arranged in such a 3×4 array within the scope of the present disclosure.

[0084] In some embodiments, reference Fig.29 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201G. The semiconductor device 200 includes a first region P1, the first region P1 being located between two third regions P3 along a first lateral direction. Fig.28 For similar reasons as described above, although the second region P2 can be arranged adjacent to the third region P3 as described above, Fig.29 The second zone is omitted.

[0085] In some embodiments, the anti-fuse memory cell 201G may be similar to the anti-fuse memory elements 201B, 201C, or 201D, as described above with reference to FIG. Figure 11-Figure 19In this regard, each anti-fuse memory cell 201G includes two unit cells 225 coupled together at the source / drain regions 218 of their respective read transistors T2 by a BL disposed on the back side 202B of the substrate 202 and coupled to the front side 202A of the substrate 202 by at least a back side via 240 and a feed-through via 286. In the depicted embodiment, the back side via 240 extends vertically from a metal line 252A of the back side interconnect structure 250, partially through the substrate 202, to contact the source / drain regions 218, and the feed-through via 286 extends vertically from a metal line 252C of the back side interconnect structure 250, through the substrate 202, to the source / drain contact features 230 (see, e.g., FIG. 2 ). Fig.14 ).

[0086] The first region P1 includes a gate structure coupled to a different gate structure (eg, gate structure 220; see, for example, Figure 5 ) and two BLs (eg, BL0 and BL1) coupled to the source / drain regions 218 of the read transistor T2 in the unit cell 225 along the first lateral direction, respectively. In this regard, Fig.29 The semiconductor device 200 shown in FIG. 2 includes a layout having a two (BL) by two (WL) (2x2) array. In some examples, the semiconductor device 200 can include any one of a plurality of anti-fuse memory cells 201A-201F arranged in such a 2x2 array within the scope of the present disclosure.

[0087] In some embodiments, reference Fig.30 , the semiconductor device 200 includes a plurality of anti-fuse memory cells 201H. The semiconductor device 200 includes a first region P1, the first region P1 being located between two third regions P3 along a first lateral direction. Fig.28 The reasons are similar to those mentioned in Fig.30 The second region P2 is omitted in FIG. 1 , although it may be disposed adjacent to the third region P3 as described above.

[0088] In some embodiments, the anti-fuse memory cell 201H differs from the anti-fuse memory cells 201A-201G described above in that each anti-fuse memory cell 201H includes two unit cells 227 coupled together. Each unit cell 227 is configured as a three-transistor (3T) cell, which includes a (first) read transistor T4, a programming transistor T1 (e.g., as described above), and a (second) read transistor T2 (e.g., as described above) coupled in series, where transistors T1, T2, and T4 are collectively referred to as functional transistors. In the depicted embodiment, the cells 227 are coupled together at the source / drain regions 218 of their respective read transistors T2 by a BL, which is disposed on the back side 202B of the substrate 202 and is coupled to the front side 202A of the substrate 202 by at least the back side via 240 and the feed-through via 286. In addition, one of the source / drain regions 219 of the first read transistor T4 that is remote from the programming transistor T1 is also coupled to the BL (e.g., metal layer 252A) through a backside via 245 similar to the backside via 240. In the depicted embodiment, the backside vias 240 and 245 each extend vertically from a metal line 252A of the backside interconnect structure 250, partially through the substrate 202, to contact the source / drain regions 218 and 219, respectively, and a feedthrough via 286 extends vertically from a metal line 252C of the backside interconnect structure 250, through the substrate 202 to the contact feature 230. In this regard, when the anti-fuse memory cell 201H is in an unprogrammed state (i.e., before breaking down the gate dielectric of the programming transistor T1), the read current is increased, resulting in a larger read window.

[0089] The first region P1 includes a gate structure coupled to a different gate structure (eg, gate structure 220; see, for example, Figure 5 ) and two BLs (e.g., BL0 and BL1) coupled to the source / drain region 218 of the read transistor T2 and the source / drain region 219 of the first read transistor T4 in each cell 227, respectively. In this regard, Fig.30 The semiconductor device 200 shown in FIG. 2 includes a layout having a two (BL) by two (WL) (2×2) array.

[0090] Fig.31 A schematic top view of an anti-fuse memory cell 201I is depicted. The anti-fuse memory cell 201I can be similar to any of the anti-fuse memory cells 201A-201H described above, except that the second region P2 surrounds or encloses the first region P1, rather than extending along the first region P1 as depicted in the anti-fuse memory cells 201A-201F. In this regard, the second region P2 is operable to function as a guard ring structure coupled to the first region P1.

[0091] Fig.32is a flow chart of a method 400 of forming or manufacturing a semiconductor device (eg, semiconductor device 200) according to some embodiments. It should be understood that in Fig.32 Additional operations are performed before, during, and / or after the illustrated method 400. In some embodiments, the method 400 may be used to form a semiconductor device according to various layouts (designs) disclosed herein.

[0092] In operation 410 of method 400, a semiconductor device (eg, semiconductor device 200 (see FIG. 1 ) having a layout corresponding to the structure of any one of anti-fuse memory cells 201A-201I) is generated. Figure 4-Figure 31 ) layout design. Operation 410 is performed by a processing device (e.g., Fig.33 In one method, the layout design is generated by placing a layout design of one or more standard cells through a user interface. In one method, the layout design is automatically generated by a processor executing a synthesis tool that converts a logic design (e.g., Verilog) into a corresponding layout design. In some embodiments, the layout design is presented in a Graphical Database System (GDSII) file format.

[0093] In operation 420 of method 400, a semiconductor device is manufactured based on the layout design. In some embodiments, operation 420 of method 400 includes manufacturing at least one mask based on the layout design, and manufacturing the semiconductor device based on the at least one mask. Fig.35 Several example manufacturing operations of operation 420 are discussed with reference to method 700 .

[0094] In some embodiments, method 400 is implemented as a stand-alone software application executed by a processor. In some embodiments, method 400 is implemented as a software application as part of an additional software application. In some embodiments, method 400 is implemented as a plug-in for a software application. In some embodiments, method 400 is implemented as a software application as part of an EDA tool. In some embodiments, method 400 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-temporary computer readable medium. In some embodiments, the layout design is generated based on a netlist created based on a schematic design.

[0095] Fig.33is a schematic diagram of a system 500 for designing and manufacturing IC layout designs according to some embodiments. System 500 generates or places one or more IC layout designs as described herein. In some embodiments, system 500 manufactures one or more semiconductor devices based on one or more IC layout designs as described herein. System 500 includes (e.g., hardware) processor 502 and non-transitory computer-readable storage medium 504 encoded (e.g., stored) with computer program code 506, such as a set of executable instructions. Computer-readable storage medium 504 is configured to interface with a manufacturing machine for producing semiconductor devices. Processor 502 is electrically coupled to computer-readable storage medium 504 via bus 508. Processor 502 is also electrically coupled to I / O interface 510 via bus 508. Network interface 512 is also electrically connected to processor 502 via bus 508. Network interface 512 is connected to network 514 so that processor 502 and computer-readable storage medium 504 can be connected to external elements via network 514. The processor 502 is configured to execute computer program code 506 encoded in the computer-readable storage medium 504 so that the system 500 can be used to perform part or all of the operations as described in the method 400 .

[0096] In some embodiments, processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0097] In some embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 504 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0098] In some embodiments, computer-readable storage medium 504 stores computer program code 506 configured to cause system 500 to perform method 400. In some embodiments, computer-readable storage medium 504 also stores information required to perform method 400 and information generated during the performance of method 400, such as layout design 516, user interface 518, manufacturing unit 520, and / or a set of executable instructions for performing the operations of method 400.

[0099] In some embodiments, computer readable storage medium 504 stores instructions (eg, computer program code 506) for interfacing with a manufacturing machine. The instructions (eg, computer program code 506) enable processor 502 to generate manufacturing instructions readable by a manufacturing machine to effectively implement method 400 in a manufacturing process.

[0100] System 500 includes I / O interface 510. I / O interface 510 is coupled to external circuitry. In some embodiments, I / O interface 510 includes a keyboard, keypad, mouse, trackball, trackpad, and / or cursor direction keys for transmitting information and commands to processor 502.

[0101] The system 500 also includes a network interface 512 coupled to the processor 502. The network interface 512 allows the system 500 to communicate with a network 514 to which one or more other computer systems are connected. The network interface 512 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-13154. In some embodiments, the method 400 is implemented in two or more systems 500, and information such as layout design, user interface, and manufacturing unit is exchanged between different systems 500 via the network 514.

[0102] The system 500 is configured to receive information related to the layout design through the I / O interface 510 or the network interface 512. The information is transmitted to the processor 502 through the bus 508 to determine the layout design for producing the IC. The layout design is then stored in the computer-readable storage medium 504 as the layout design 516. The system 500 is configured to receive information related to the user interface through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as the user interface 518. The system 500 is configured to receive information related to the manufacturing unit through the I / O interface 510 or the network interface 512. The information is stored in the computer-readable storage medium 504 as the manufacturing unit 520. In some embodiments, the manufacturing unit 520 includes manufacturing information used by the system 500.

[0103] In some embodiments, method 400 is implemented by a manufacturing device to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs generated by system 500. In some embodiments, system 500 includes a manufacturing device (e.g., manufacturing tool 522) to manufacture an integrated circuit using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, Fig.26 The system 500 generates a layout design for an IC that is smaller than other methods. In some embodiments, Fig.33The system 500 generates a layout design for a semiconductor device that occupies less area than other methods.

[0104] Fig.34 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 600 and its associated IC manufacturing flow according to at least one embodiment of the present disclosure.

[0105] exist Fig.34 In the embodiment, the IC manufacturing system 600 includes entities that interact in the design, development and manufacturing cycle and / or services related to manufacturing IC devices (semiconductor devices) 660 (e.g., corresponding to semiconductor device 200), such as a design room 620, a mask room 630, and an IC manufacturing plant / manufacturer ("fab") 640. The entities in the IC manufacturing system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some implementation examples, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, two or more of the design room 620, the mask room 630, and the IC manufacturing plant 640 are owned by a single company. In some embodiments, two or more of the design room 620, the mask room 630, and the IC manufacturing plant 640 coexist in a public facility and use public resources.

[0106] The design office (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 660. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 660 to be manufactured. Various layers are combined to form various IC components. For example, parts of the IC design layout 622 include various IC components, such as active areas, gate structures, source / drain areas, interconnect structures and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and in various material layers disposed on the semiconductor substrate. The design office 620 implements appropriate design procedures to form the IC design layout 622. The design process includes one or more of logical design, physical design or placement and routing. The IC design layout 622 is presented in one or more data files with information of the geometric patterns. For example, the IC design layout 622 can be represented in a GDSII file format or a DFII file format.

[0107] The mask room 630 includes mask data preparation 632 and mask manufacturing 634. The mask room 630 uses the IC design layout 622 to manufacture one or more masks that will be used to manufacture various layers of the IC device 660 based on the IC design layout 624. The mask library 630 performs mask data preparation 632, where the IC design layout 622 is translated into a representative data file ("RDF"). The mask data preparation 632 provides the RDF to the mask manufacturing 634. The mask manufacturing 634 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or a semiconductor wafer. The mask data preparation 632 manipulates the design layout to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer 640. In Fig.34 , mask data preparation 632 and mask manufacturing 634 are illustrated as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 634 may be collectively referred to as mask data preparation.

[0108] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 622. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0109] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that checks an IC design layout that has been processed in OPC using a set of mask creation rules that contain certain geometry and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 634, which can undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0110] In some embodiments, mask data preparation 632 includes a lithography process check (LPC), which simulates a process to be performed by IC fabrication plant 640 to fabricate IC device 660. LPC simulates the process based on IC design layout 622 to create a simulated fabricated device, such as IC device 660. Process parameters in the LPC simulation may include parameters associated with various processes of the IC fabrication cycle, parameters associated with tools used to fabricate ICs, and / or other aspects of the fabrication process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated fabricated device is created by LPC, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC may be repeated to further refine the IC design layout 622.

[0111] It should be understood that the above description of mask data preparation 632 has been simplified for clarity. In some embodiments, mask data preparation 632 includes additional features, such as logic operations (LOPs) that modify IC design layouts according to manufacturing rules. In addition, the processing applied to IC design layout 622 during mask data preparation 632 can be performed in a variety of different orders.

[0112] After mask data preparation 632 and during mask manufacturing 634, a mask or mask set is manufactured based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or a plurality of e-beam mechanisms are used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, the mask is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the mask. In another example, a mask is formed using a phase shift technique. In a phase shift mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The masks produced by mask manufacturing 634 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0113] IC fabrication plant 640 is an IC fabrication entity that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fabrication plant 640 is a semiconductor foundry. For example, there may be a first fabrication facility for front-end fabrication of multiple IC products (e.g., source / drain regions, gate structures), while a second fabrication facility may provide mid-end fabrication of interconnects (e.g., contact features, vias, gate contacts, etc.) for IC products, and a third fabrication facility may provide fabrication of front-end metallization layers, such as M0, M1, M2, ..., and M3 for IC products. n , backside metallization layers, such as BM0, BM1, ... and BM n etc., through holes, such as V0, V1, V2, ... and V n-1 , and through holes such as BV0, BV1, ... and BV n-1 etc.), and the fourth manufacturing facility can provide other services to the foundry entity.

[0114] IC manufacturing plant 640 uses the mask manufactured by mask chamber 630 to manufacture IC device 660. Therefore, IC manufacturing plant 640 uses IC design layout 622 at least indirectly to manufacture IC device 660. In some embodiments, semiconductor wafer 642 is manufactured by IC manufacturing plant 640 using mask (one or more masks) to form IC device 660. Semiconductor wafer 642 includes a silicon substrate or other suitable substrate with material layers formed thereon. The semiconductor wafer also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0115] IC manufacturing system 600 is shown with design room 620, mask room 630, and IC fabrication plant 640 as separate components or entities. However, it should be understood that one or more of design room 620, mask room 630, and IC fabrication plant 640 are part of the same component or entity.

[0116] Fig.35 7 is a flow chart illustrating an example method 700 for manufacturing a semiconductor device according to various aspects of the present disclosure, the semiconductor device including the disclosed anti-fuse memory cells (e.g., anti-fuse memory cells 201A-201I) and a backside power rail coupled to the anti-fuse memory cells (e.g., backside interconnect structure 250 for providing a voltage at BL). Method 700 may be method 400 ( Fig.32 ) as part of operation 420. In this way, a semiconductor device can be manufactured based on at least a portion of the layout design disclosed herein.

[0117] At least some operations of method 700 may be used to form a semiconductor device having a non-planar transistor configuration. For example, the semiconductor device may include one or more FinFETs or GAAFETs. However, it should be understood that the transistors of the semiconductor device may each be configured in any of a variety of other types of transistors, such as complementary FETs (CFETs), while still within the scope of the present disclosure. It should be noted that method 700 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and / or after method 700, and some other operations may only be briefly described herein. The following discussion of method 700 may refer to Figure 1-Figure 31 One or more components of a

[0118] In brief overview, method 700 begins with operation 702 of providing a semiconductor substrate, the semiconductor substrate including a first portion and a second portion adjacent to the first portion. Method 700 proceeds to operation 704, on the front side of the semiconductor substrate, forming a first transistor and a second transistor in the first portion, and forming a third transistor in the second portion, wherein the first transistor is coupled in series with the second transistor to form an anti-fuse memory cell. Method 700 proceeds to operation 706, and operation 706 forms a first interconnect structure coupled to the first, second, and third transistors on the front side. Method 700 proceeds to operation 708, and forms a first via structure coupled to a portion of each of the second and third transistors on the back side of the semiconductor substrate. Method 700 proceeds to operation 710, and forms a second via structure on the back side adjacent to the third transistor in the second portion, the second via structure coupled to the first interconnect structure. Method 700 proceeds to operation 712, and forms a second interconnect structure on the back side coupled to the first and second via structures.

[0119] In various embodiments, first and second transistors (e.g., functional transistors T1, T2, and T4) and a first interconnect structure (e.g., front side interconnect structure 300) on a front side (e.g., front side 202A) of a semiconductor substrate (e.g., substrate 202) form a plurality of disclosed anti-fuse memory cells (e.g., anti-fuse memory cells 201A to 201I), and a second interconnect structure (e.g., back side interconnect structure 250) on a back side (e.g., back side 202B) of the semiconductor substrate is operatively used as a power rail for a bit line BL, which is coupled to the anti-fuse memory cells and / or second via structures (e.g., feedthrough vias 280 and 286) on the front side via a plurality of first via structures (e.g., back side vias 240, 244, and 245).

[0120] Corresponding to operation 702, a semiconductor substrate (e.g., substrate 202) may include a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor substrate may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. The semiconductor substrate includes a first portion (e.g., a first region P1) and a second portion (e.g., a second region P2).

[0121] Corresponding to operation 704, on the front side of the semiconductor substrate (e.g., in the first region P1 and the second region P2), a plurality of transistors, including first and second transistors (e.g., functional transistors T1, T2, and T4) and a third transistor (e.g., dummy transistor T3), are formed in the first portion and the second portion, respectively. In the present embodiment, the first, second, and third transistors are arranged along a first direction (e.g., a first lateral direction or an X-axis). The first transistor and the second transistor are formed in series to form an anti-fuse memory cell (e.g., anti-fuse memory cells 201A-201I) on the front side. Using FinFET as an example embodiment of a transistor, the transistor can be formed by at least some of the following process steps: forming a fin structure (e.g., active region 204 or 206) protruding from a semiconductor substrate; forming a dummy gate structure (not shown here) spanning a channel region of the fin structure; forming gate spacers (not shown here) disposed along opposite sidewalls of the dummy gate structure; forming source / drain regions (e.g., source / drain regions 216 / 218 / 219 and 226 / 228) disposed on opposite sides of the dummy gate structure in the fin structure; removing the dummy gate structure; and forming an active (e.g., metal) gate structure (e.g., gate structure 220 or 224) to replace the dummy gate structure.

[0122] Corresponding to operation 706, a first interconnect structure (e.g., front-side interconnect structure 300) is formed on the front side of the semiconductor substrate. As described above, the first interconnect structure may include a plurality of mid-end-of-line (MEOL) interconnect structures (e.g., source / drain contacts 230 and 234, contact features 236 and 238, via 260, gate contact 262, etc.) and a plurality of back-end-of-line (BEOL) interconnect structures (e.g., front-side metallization layers, such as M0, M1, M2, ..., and M3). n, and through holes such as V0, V1, V2, ... and V n-1 etc.). In some embodiments, the MEOL and BEOL interconnect structures can each extend in a single direction. For example, the source / drain contacts 230 and 234 and the contact features 236 and 238 can all extend in a second lateral direction parallel to the gate structures 220, 222, and 224. The first interconnect structure can be formed by at least some of the following steps: forming a dielectric layer over the transistors on the front side; patterning the dielectric layer to form openings corresponding to the locations of various components of the first interconnect structure; and forming a conductive (e.g., metal) structure in the opening to form the first interconnect structure. Each first interconnect structure disposed on the front side may include one or more metal materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof, disposed in a dielectric material (e.g., an ILD layer, an IMD layer, etc.; not shown here).

[0123] Corresponding to operations 708 and 710, on the back side (e.g., back side 202B) of the semiconductor substrate, a plurality of via structures, including first via structures (e.g., back side vias 240, 244, and 245) and second via structures (e.g., feed-through vias 280 and 286), are connected to portions of the components formed on the front side of the semiconductor substrate. In operation 708, the first via structure is coupled to each of the second transistor and the third transistor (e.g., functional transistor T2 and dummy transistor T3, respectively). In operation 710, the second via structure extends in a second portion (e.g., second region P2) along a first direction (e.g., a first lateral direction or an X-axis) and is adjacent to the third transistor (e.g., dummy transistor T3) along a second direction (e.g., a second lateral direction or a Y-axis) perpendicular to the first direction. The second via structure is coupled to the first interconnect structure.

[0124] The first and second via structures can be formed by at least some of the following processing steps: flipping the semiconductor substrate; optionally thinning the semiconductor substrate from the back side until the bottom surface of the source / drain region (e.g., source / drain regions 216 / 218 / 219 and 226 / 228) is exposed; forming a dielectric layer on the back side; patterning the dielectric layer to form openings corresponding to the locations of the backside vias and the feedthrough vias; and forming a conductive (e.g., metal) structure in the opening to form the via structure on the back side. The resulting backside vias (e.g., backside vias 240, 244, and 245) are each coupled to one of the source / drain regions of each transistor, and the resulting feedthrough vias (e.g., feedthrough vias 280 and 286) are each coupled to a contact feature (e.g., contact feature 236). Each feedthrough via has a larger cross-sectional area than the backside via, thereby having a lower resistance.

[0125] Corresponding to operation 712, on the back side of the semiconductor substrate, a second interconnect structure (e.g., backside interconnect structure 250) is formed. In the present embodiment, the second interconnect structure functions as a power rail operable as a BL coupled to the anti-fuse memory cell from the back side. The second interconnect structure extends along a first direction and is coupled to the first via structure (e.g., backside vias 240, 244, and 245) and the second via structure (e.g., feed-through vias 280 and 286). The second interconnect structure is formed in a manner similar to the formation of the first interconnect structure and is connected to each via structure formed in operation 708. Each second interconnect structure disposed on the back side may include one or more metal materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or a combination thereof.

[0126] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell includes a first transistor and a second transistor, the first transistor and the second transistor are both arranged on a first side of a substrate. The memory device includes a first interconnect structure, the first interconnect structure is arranged on a second side of the substrate opposite to the first side. The first source / drain terminal of the first transistor is floating, the second source / drain terminal of the first transistor is coupled to the first source / drain terminal of the second transistor, and the second source / drain terminal of the second transistor is coupled to the first interconnect structure. The memory device includes a first through-hole structure, the first through-hole structure is arranged in a first region of the substrate and is configured to couple the second source / drain terminal of the second transistor to the first interconnect structure. The memory device includes a plurality of second through-hole structures, the plurality of second through-hole structures are arranged in a second region of the substrate and each second through-hole structure is coupled to the first interconnect structure. The memory device includes a third through-hole structure, the third through-hole structure is arranged in a second region of the substrate and each is coupled to the first interconnect structure. The first through-hole structure and the second through-hole structure each have a first cross-sectional area, and the third through-hole structure has a second cross-sectional area different from the first cross-sectional area.

[0127] In some embodiments, the first interconnect structure is operable to function as a bit line of a memory cell.

[0128] In some embodiments, the conduction path is formed by applying a programming voltage on a gate terminal of the first transistor.

[0129] In some embodiments, the conduction path extends from a gate terminal of the first transistor, through at least a second source / drain terminal of the first transistor, a first source / drain terminal and a second source / drain terminal of the second transistor, and to the first interconnect structure.

[0130] In some embodiments, the first via structure, the second via structure, and the third via structure are coupled in parallel to each other.

[0131] In some embodiments, the first cross-sectional area is smaller than the second cross-sectional area.

[0132] In some embodiments, the memory device further includes a second interconnect structure disposed on the first side, wherein the first via structure, the second via structure, and the third via structure are respectively coupled to the second interconnect structure.

[0133] In some embodiments, at least a portion of the second region extends adjacent to the first region.

[0134] In some embodiments, the memory cell is disposed in the first region, and the memory device further includes a plurality of third transistors disposed in the second region, wherein a gate terminal and a source / drain terminal of each third transistor are coupled to the first interconnect structure.

[0135] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a substrate, the substrate includes a first region and a second region, the first region and the second region each extending longitudinally along a first direction and extending laterally along a second direction perpendicular to the first direction. The semiconductor device includes a first active region, the first active region is arranged in the first region and on the front side of the substrate, the first active region extending longitudinally along the first direction. The semiconductor device includes a first transistor and a second transistor, the first transistor and the second transistor are arranged in the first active region and coupled in series. The semiconductor device includes a first interconnect structure, the first interconnect structure is formed on the front side of the substrate and coupled to the first transistor and the second transistor. The semiconductor device includes a second interconnect structure, the second interconnect structure is formed on the back side of the substrate opposite to the front side. The semiconductor device includes a first through-hole structure, coupling a portion of the second transistor to the second interconnect structure. The semiconductor device includes a second active region, arranged in the second region and on the first side of the substrate, the second active region extending longitudinally along the first direction. The semiconductor device includes a plurality of second through-hole structures, each coupling a portion of the second active region to the second interconnect structure. The semiconductor device includes a third through-hole structure, coupling the first interconnect structure to the second interconnect structure in the second region. The first through-hole structure and the second through-hole structure each extend along the first direction by a first length. The third through-hole structure extends along the first direction by a second length, the second length being longer than the first length.

[0136] In some embodiments, the conduction path is formed by applying a programming voltage on a gate terminal of the first transistor.

[0137] In some embodiments, the first active region extends along the second direction to a first height, and the second active region extends along the second direction to a second height, the second height being less than the first height.

[0138] In some embodiments, the first active region extends along the second direction to a first height, and the second active region extends along the second direction to a second height, the second height being the same as the first height.

[0139] In some embodiments, the semiconductor device further includes at least one fourth via structure coupling the first interconnect structure in the first region to the second interconnect structure, wherein the third via structure extends longitudinally along the first direction.

[0140] In some embodiments, the semiconductor device further includes a third transistor disposed in the second active region along the first direction, wherein the second via structure couples a source / drain region of the third transistor to the second interconnect structure.

[0141] In some embodiments, the second interconnect structure is operable to function as a bit line of a memory device.

[0142] In some embodiments, the first source / drain region of the first transistor is floating; the second source / drain region of the first transistor is coupled in series to the first source / drain region of the second transistor; and the first via structure couples the second source / drain region of the second transistor to the second interconnect structure.

[0143] In some embodiments, the semiconductor device also includes: a third transistor disposed in the first region, wherein a first source / drain region of the third transistor is coupled in series with a first source / drain region of the first transistor; and a fourth through-hole structure coupling a second source / drain region of the third transistor to a second interconnect structure.

[0144] In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed. The method includes providing a substrate having a first portion and a second portion adjacent to the first portion. The method includes forming a first transistor and a second transistor in the first portion and a third transistor in the second portion on the front side of the substrate. The first transistor and the second transistor are coupled in series to form an anti-fuse memory cell. The first transistor, the second transistor, and the third transistor are arranged along a first direction. The method includes forming a first interconnect structure coupled to the first transistor, the second transistor, and the third transistor on the front side of the substrate. The method includes forming a first through-hole structure on the back side of the substrate opposite to the front side, the first through-hole structure being coupled to a portion of each of the second transistor and the third transistor, respectively. A second through-hole structure extending in the first direction in the second portion is formed on the back side of the substrate. The second through-hole structure is coupled to the first interconnect structure and is formed adjacent to the third transistor along a second direction perpendicular to the first direction. The method includes forming a second interconnect structure on the back side of the substrate, the second interconnect structure extending along the first direction and coupled to the first through-hole structure and the second through-hole structure.

[0145] In some embodiments, forming the second via structure includes forming a third via structure extending along the first direction in the first portion, and wherein the third via structure is coupled to the first interconnect structure and formed adjacent to the first transistor and the second transistor along the second direction.

[0146] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0147] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A memory cell comprising a first transistor and a second transistor, wherein the first transistor and the second transistor are both disposed on a first side of a substrate; a first interconnect structure disposed on a second side of the substrate opposite the first side, wherein a first source / drain terminal of the first transistor is floating, a second source / drain terminal of the first transistor is coupled to a first source / drain terminal of the second transistor, and a second source / drain terminal of the second transistor is coupled to the first interconnect structure; a first via structure disposed in a first region of the substrate and configured to couple the second source / drain terminal of the second transistor to the first interconnect structure; a plurality of second via structures disposed in a second region of the substrate and each coupled to the first interconnect structure; and third via structures disposed in the second region of the substrate and each coupled to the first interconnect structure, The first through-hole structure and the second through-hole structure each have a first cross-sectional area, and the third through-hole structure has a second cross-sectional area different from the first cross-sectional area.

2. The memory device according to claim 1, wherein: The first interconnect structure is operable to serve as a bit line for the memory cell.

3. The memory device according to claim 1, wherein: A conduction path is formed by applying a programming voltage on the gate terminal of the first transistor.

4. The memory device according to claim 3, wherein: The conduction path extends from the gate terminal of the first transistor, through at least the second source / drain terminal of the first transistor, the first source / drain terminal and the second source / drain terminal of the second transistor, and to the first interconnect structure.

5. The memory device of claim 1 , further comprising a second interconnect structure disposed on the first side, wherein: The first via structure, the second via structure, and the third via structure are respectively coupled to the second interconnect structure.

6. The memory device according to claim 1, wherein: The memory cell is disposed in the first region, and the memory device further includes a plurality of third transistors disposed in the second region, wherein a gate terminal and a source / drain terminal of each of the third transistors are coupled to the first interconnect structure.

7. A semiconductor device comprising: a substrate including a first region and a second region, the first region and the second region each extending longitudinally along a first direction and laterally along a second direction perpendicular to the first direction; a first active region disposed in the first region and on the front side of the substrate, the first active region extending longitudinally along the first direction; A first transistor and a second transistor, disposed in the first active region and coupled in series; a first interconnect structure formed on the front side of the substrate and coupled to the first transistor and the second transistor; a second interconnect structure formed on a back side of the substrate opposite the front side; a first via structure coupling a portion of the second transistor to the second interconnect structure; a second active region disposed in the second region and on the first side of the substrate, the second active region extending longitudinally along the first direction; a plurality of second via structures, each coupling a portion of the second active area to the second interconnect structure; as well as a third via structure coupling the first interconnect structure to the second interconnect structure in the second region, wherein: The first through-hole structure and the second through-hole structure each extend a first length along the first direction, and The third through hole structure extends along the first direction by a second length, and the second length is longer than the first length.

8. The semiconductor device according to claim 7, wherein: The first active region extends along the second direction to a first height, and the second active region extends along the second direction to a second height, the second height being smaller than the first height.

9. The semiconductor device according to claim 7, further comprising a third transistor, the third transistor being arranged in the second active region along the first direction, wherein: The second via structure couples a source / drain region of the third transistor to the second interconnect structure.

10. A method for manufacturing a memory device, comprising: providing a substrate having a first portion and a second portion adjacent to the first portion; forming a first transistor and a second transistor in the first portion and a third transistor in the second portion on a front side of the substrate, wherein the first transistor and the second transistor are coupled in series to form an anti-fuse memory cell, and wherein the first transistor, the second transistor, and the third transistor are arranged along a first direction; forming a first interconnect structure coupled to the first transistor, the second transistor, and the third transistor on the front side of the substrate; forming a first via structure on a back side of the substrate opposite the front side, the first via structure being coupled to a portion of each of the second transistor and the third transistor, respectively; forming a second via structure extending along the first direction in the second portion on the back side of the substrate, wherein the second via structure is coupled to the first interconnect structure and is formed adjacent to the third transistor along a second direction perpendicular to the first direction; and A second interconnect structure is formed on the back side of the substrate, the second interconnect structure extending along the first direction and coupled to the first via structure and the second via structure.

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