A method and apparatus for generating control signals based on a timing interrupt of a second pulse

Abstract

The application belongs to the field of interrupt control, and specifically discloses a control signal generation method and device for timing interrupt based on a second pulse. Through the application, the reception of a second pulse signal, the optimized shaping of a second pulse single-ended signal, the output of a second pulse effective indication signal, and the output of a second pulse absence indication signal are realized, and a precise control signal based on the second pulse for controlling a timing interrupt implementation circuit is generated. In application occasions with more signal defects, the application can eliminate the influence of ringing, noise, jitter, etc. on the second pulse single-ended signal, can meet the requirement of precise control of the external second pulse signal on the timing interrupt implementation circuit, can make the timing interrupt implementation circuit adapt to the mismatch between the local clock precision and the external clock precision, and can avoid the timing problems caused by the mismatch, and has good robustness and stable and reliable operation.

Description

Technical Field

[0001] The present application belongs to the field of interrupt control, and more specifically, relates to a method and device for generating a control signal for a timed interrupt based on a pulse-per-second (PPS) pulse. Background Art

[0002] In complex application environments, circuit stability and accuracy issues caused by local power supply instability, signal glitches caused by high-frequency interference sources in space, and signal ringing caused by impedance changes during signal transmission will all have varying degrees of impact on single-ended pulse-per-second signals.

[0003] Furthermore, after receiving the second pulse, the timer interrupt implementation circuit typically counts the local clock ticks within one second, generating a regular interrupt signal to the CPU. However, the mismatch in accuracy between the external and local clocks makes it difficult for the local clock tick count to perfectly match the external clock's time. Summary of the Invention

[0004] In response to the defects of the existing technology, the purpose of this application is to provide a control signal generation method and device based on second pulse timing interruption, aiming to solve the problems of the influence of ringing, noise, jitter, etc. on the second pulse single-ended signal, and the mismatch between the local clock accuracy and the time accuracy of the external second pulse signal.

[0005] To achieve the above objectives, in a first aspect, the present application provides a method for generating a control signal based on a timed interrupt of a second pulse, comprising:

[0006] Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to a first threshold, the second pulse valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is low;

[0007] Under the beat of the local clock, the number of clock cycles is counted with the pulse-per-second valid indication signal as a count reset signal. If the count value of the number of clock cycles is less than or equal to a third threshold, the pulse-per-second absent indication signal is at a low level; otherwise, the pulse-per-second absent indication signal is at a high level until the count value of the number of clock cycles is reset by the next pulse-per-second valid indication signal, at which point the pulse-per-second absent indication signal returns to a low level again.

[0008] The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interruption implementation circuit to realize control of the timing interruption implementation circuit;

[0009] Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0010] Preferably, the pulse-per-second differential signal is converted to obtain a pulse-per-second single-ended signal.

[0011] Preferably, the pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

[0012] To achieve the above objectives, in a second aspect, the present application provides a control signal generating device based on a timed interrupt of a second pulse, comprising:

[0013] A second pulse valid indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock. If the positive pulse width count value is less than or equal to a first threshold, the second pulse valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is low; the first threshold is the product of the jitter signal width to be eliminated and the local clock frequency; the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency;

[0014] The pulse-per-second absence indication circuit is configured to count clock cycles in a local clock beat using a pulse-per-second validity indication signal as a count reset signal. If the count value of the clock cycles is less than or equal to a third threshold, the pulse-per-second absence indication signal is at a low level. Otherwise, the pulse-per-second absence indication signal is at a high level until the count value of the clock cycles is reset by the next pulse-per-second validity indication signal, at which point the pulse-per-second absence indication signal returns to a low level again. The third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the pulse-per-second validity indication signal.

[0015] Preferably, the second pulse valid indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse valid indication signal output unit;

[0016] The first counter is a binary counter whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock;

[0017] The first counter enabling unit is configured to enable counting of the first counter;

[0018] The second pulse valid indication signal output unit is used to compare the count value of the first counter with the first threshold and the second threshold, and generate a second pulse valid indication signal according to the comparison result.

[0019] Preferably, the first counter enabling unit is configured to compare the count value of the first counter with a second threshold value, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold value.

[0020] Preferably, the second pulse absence indication circuit includes: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit;

[0021] The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock and use the second pulse valid indication signal as the reset signal;

[0022] The second counter enabling unit is configured to enable counting of the second counter;

[0023] The second pulse absence indication signal output unit is used to compare the count value of the second counter with a third threshold value, and generate a second pulse absence indication signal according to the comparison result.

[0024] Preferably, the second counter enabling unit is configured to compare the count value of the second counter with a third threshold value, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold value.

[0025] Preferably, it also includes:

[0026] A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal;

[0027] The second pulse single-ended signal optimization and shaping circuit is used to optimize and shape the second pulse single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the second pulse single-ended signal, and generate an optimized and shaped second pulse access signal.

[0028] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0029] The present application provides a method and device for generating a control signal for a timed interrupt based on a pulse-second signal. By receiving a pulse-second signal, optimizing and shaping a single-ended pulse-second signal, and outputting a pulse-second validity indication signal and a pulse-second absence indication signal, a precise pulse-second-based control signal for controlling a timed interrupt implementation circuit is generated. The method and device are independent of an external pulse-second signal generating device and a timed interrupt implementation circuit, and can eliminate the effects of ringing, noise, jitter, and the like on the single-ended pulse-second signal in applications with a high number of signal defects. Furthermore, the method and device can meet the requirements for precise control of the timed interrupt implementation circuit by an external pulse-second signal, enabling the timed interrupt implementation circuit to adapt to mismatches between local and external clock accuracy and avoid timing issues caused by such mismatches. The method and device can effectively prevent the timed interrupt implementation circuit from performing unnecessary work and incurring additional hardware overhead, meeting the requirements for precise control of the timed interrupt implementation circuit by an external pulse-second signal, and exhibiting good robustness and stable and reliable operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a flow chart of a control signal generation method based on second pulse timing interruption provided in an embodiment of the present application.

[0031] Figure 2 This is a circuit connection diagram of the second pulse receiving circuit, the second pulse access signal optimization shaping circuit, and the second pulse effective indication circuit provided in the embodiment of the present application.

[0032] Figure 3 This is a circuit connection diagram of the second pulse absence indication circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0034] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0035] The terms "first" and "second" in this specification and claims are used to distinguish different objects rather than to describe a specific order of objects. For example, "first response message" and "second response message" are used to distinguish different response messages rather than to describe a specific order of response messages.

[0036] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0037] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.

[0038] First, the technical terms involved in the embodiments of this application are introduced.

[0039] "Pulse per second" refers to the number of pulses generated per second, that is, a pulse signal with a time interval of 1 second, which is used to indicate the whole second.

[0040] An interruption occurs when the CPU pauses execution of the current program due to an emergency situation. The CPU then switches to executing a special program to handle the emergency. After the emergency is complete, the CPU automatically returns to the program where it was originally paused to continue execution. This interruption of execution due to an external factor is called an interruption.

[0041] When this execution process is caused by an interrupt issued to the CPU according to a certain pattern within the whole second time period indicated by the second pulse, this interrupt is called a "timed interrupt based on the second pulse".

[0042] The “local clock” refers to a clock signal of the same frequency and phase provided to the control signal generation method and device for the timer interrupt and the timer interrupt implementation circuit.

[0043] "External clock" refers to the clock signal used by an external device that generates an external second pulse signal.

[0044] Next, the technical solutions provided in the embodiments of this application are introduced.

[0045] like Figure 1 As shown, the present application provides a method for generating a control signal based on a timed interrupt of a second pulse, comprising:

[0046] Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to a first threshold, the second pulse valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is low;

[0047] Under the beat of the local clock, the number of clock cycles is counted with the pulse-per-second valid indication signal as a count reset signal. If the count value of the number of clock cycles is less than or equal to a third threshold, the pulse-per-second absent indication signal is at a low level; otherwise, the pulse-per-second absent indication signal is at a high level until the count value of the number of clock cycles is reset by the next pulse-per-second valid indication signal, at which point the pulse-per-second absent indication signal returns to a low level again.

[0048] The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interruption implementation circuit to realize control of the timing interruption implementation circuit;

[0049] Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

[0050] The first threshold = the jitter signal width that needs to be eliminated * the local clock frequency.

[0051] The second threshold = the first threshold + the pulse width of the valid indication signal * the local clock frequency.

[0052] The third threshold value=the local clock frequency−the number of clock cycles corresponding to the positive pulse width of the pulse-per-second valid indication signal.

[0053] Preferably, the pulse-per-second differential signal is converted to obtain a pulse-per-second single-ended signal.

[0054] Preferably, the pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

[0055] Correspondingly, the present application provides a control signal generating device based on a timed interrupt of a second pulse, comprising:

[0056] A second pulse valid indication circuit is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock. If the positive pulse width count value is less than or equal to a first threshold, the second pulse valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is low; the first threshold is the product of the jitter signal width to be eliminated and the local clock frequency; the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency;

[0057] The pulse-per-second absence indication circuit is configured to count clock cycles in a local clock beat using a pulse-per-second validity indication signal as a count reset signal. If the count value of the clock cycles is less than or equal to a third threshold, the pulse-per-second absence indication signal is at a low level. Otherwise, the pulse-per-second absence indication signal is at a high level until the count value of the clock cycles is reset by the next pulse-per-second validity indication signal, at which point the pulse-per-second absence indication signal returns to a low level again. The third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the pulse-per-second validity indication signal.

[0058] Preferably, the second pulse effective indication circuit is used to further eliminate the influence of jitter on control accuracy that is not eliminated by the second pulse single-ended signal optimization shaping circuit due to the large level fluctuation range, and generate a second pulse effective indication signal according to the second pulse access signal to realize control of the timing interrupt implementation circuit.

[0059] Preferably, the second pulse absence indication circuit is used to generate a second pulse absence indication signal according to the second pulse valid indication signal, so as to realize control of the timing interruption realization circuit.

[0060] Preferably, the second pulse valid indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse valid indication signal output unit;

[0061] The first counter is a binary counter whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock;

[0062] The first counter enabling unit is configured to enable counting of the first counter;

[0063] The second pulse valid indication signal output unit is used to compare the count value of the first counter with the first threshold and the second threshold, and generate a second pulse valid indication signal according to the comparison result.

[0064] Preferably, the first counter enabling unit is configured to compare the count value of the first counter with a second threshold value, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold value.

[0065] The pulse-per-second valid indication circuit includes not only a NOT gate, a first counter, a first counter enabling unit, and a pulse-per-second valid indication signal output unit, but may also include logic gate circuits such as an OR gate according to the needs of reset control.

[0066] The first threshold is determined by the local clock frequency and the width of the jitter signal to be eliminated. By setting the first threshold, the pulse-per-second valid indication circuit ignores positive pulse jitter signals within the pulse-per-second access signal optimized by the Schmitt trigger buffer circuit that are less than or equal to the set positive pulse width, and considers positive pulse signals greater than the set positive pulse width as "valid" positive pulse signals.

[0067] The second threshold is determined by the local clock frequency, the first threshold, and the positive pulse width of the second pulse valid indication signal, wherein the positive pulse width of the second pulse valid indication signal is determined by the input requirements of the timing interrupt implementation circuit.

[0068] The first counter should have at least a clock input port (clk), a count clear port (CLR), a count enable port (EN), and a count value output port (Q). The clock input port (clk) is connected to the local clock. The count clear port (CLR) is controlled by a pulse-per-second access signal output from a pulse-per-second single-ended signal optimization and shaping circuit and a global reset signal. The count enable port (EN) is controlled by the first counter enable unit.

[0069] The pulse-per-second valid indication signal output unit generates a pulse-per-second valid indication signal based on a comparison result of the count value of the first counter with a first threshold and a second threshold. When the count value of the first counter is less than or equal to the first threshold, the pulse-per-second valid indication signal is low. When the count value of the first counter is greater than the first threshold and less than or equal to the second threshold, the pulse-per-second valid indication signal is high. When the count value of the first counter is greater than the second threshold, the positive pulse width of the pulse-per-second valid indication signal has reached the input requirement of the timer interrupt implementation circuit, and the pulse-per-second valid indication signal output unit controls the pulse-per-second valid indication signal to be low.

[0070] Preferably, the second pulse absence indication circuit includes: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit;

[0071] The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock and use the second pulse valid indication signal as the reset signal;

[0072] The second counter enabling unit is configured to enable counting of the second counter;

[0073] The second pulse absence indication signal output unit is used to compare the count value of the second counter with a third threshold value, and generate a second pulse absence indication signal according to the comparison result.

[0074] Preferably, the second counter enabling unit is configured to compare the count value of the second counter with a third threshold value, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold value.

[0075] The third threshold is determined by the local clock frequency and the positive pulse width of the pulse-per-second valid indication signal. The third threshold is equal to the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the pulse-per-second valid indication signal.

[0076] The second counter should include at least a clock input port (clk), a count clear port (CLR), a count enable port (EN), and a count value output port (Q). The clock input port (clk) is connected to a local clock. The count clear port (CLR) is controlled by a pulse-per-second valid indication signal. The count enable port (EN) is controlled by the second counter enable unit.

[0077] The pulse-per-second absence indication signal output unit generates a pulse-per-second absence indication signal based on a comparison result between the count value of the second counter and a third threshold value. When the count value of the second counter is less than or equal to the third threshold value, the pulse-per-second absence indication signal is at a low level. When the count value of the second counter is greater than the third threshold value, the pulse-per-second absence indication signal is at a high level. The pulse-per-second absence indication signal returns to a low level until the count value of the second counter is cleared by the next pulse-per-second valid indication signal.

[0078] A timer interrupt implementation circuit operates in each second cycle under the combined control of a second pulse valid indication signal and a second pulse absent indication signal output by a method and apparatus for generating control signals for a timer interrupt based on a second pulse. The second pulse valid indication signal indicates the arrival of a new external second cycle for the timer interrupt implementation circuit. The second pulse valid indication signal is used to control the clearing of relevant counters, register variables, and the like within the timer interrupt implementation circuit. After clearing, the timer interrupt implementation circuit, operating under the influence of a local clock, can regularly generate interrupts to the CPU by controlling relevant counters, register variables, and the like. When all interrupts that the timer interrupt implementation circuit is supposed to generate within one second have completed, but the next positive pulse of the second pulse valid indication signal has not yet arrived, to prevent the timer interrupt implementation circuit from starting the next second cycle, the present application also uses the second pulse absent indication signal to control the clearing of relevant counters, register variables, and the like within the timer interrupt implementation circuit. This effectively prevents the timer interrupt implementation circuit from performing unnecessary work and incurring additional hardware overhead. The timer interrupt implementation circuit will only begin a new second cycle when the next positive pulse of the second pulse valid indication signal arrives.

[0079] Preferably, it also includes:

[0080] A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal;

[0081] The second pulse single-ended signal optimization and shaping circuit is used to optimize and shape the second pulse single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the second pulse single-ended signal, and generate an optimized and shaped second pulse access signal.

[0082] The pulse-per-second receiving circuit mainly includes an RS485 receiving unit and its peripheral power supply and grounding circuits.

[0083] The RS485 receiving unit receives a pair of differential signals and outputs a CMOS digital signal. The interface level meets the TIA / EIA-485 protocol specifications. The RS485 receiving unit should at least include a receiver in-phase input interface (A), a receiver inverting input interface (B), a receiver output interface (RO), and a receiver output enable (RE#). A and B are a pair of differential signals used to receive external pulse-second signals. The receiver output interface (RO) outputs a single-ended pulse-second signal. When RE# is connected to a low level (zero level), the RO output is valid; when RE# is connected to a high level, RO is in a high-impedance state. When RE# is low (zero level), if the difference between the A and B levels is higher than the input high-level threshold, the RO output is high; if the difference between the A and B levels is lower than the input low-level threshold, the RO output is low (zero level).

[0084] The pulse-per-second single-ended signal optimization shaping circuit mainly includes a Schmitt trigger buffer unit.

[0085] The Schmitt trigger buffer unit converts the level of the CMOS digital signal output by the second pulse receiving circuit into a level signal that matches the input level of the second pulse effective indication circuit, and eliminates ringing, noise, slight jitter, etc. on the second pulse single-ended signal to generate an optimized and shaped second pulse access signal.

[0086] Example

[0087] In this embodiment, if Figure 2 As shown, the pulse-per-second receiving circuit is implemented using an RS-485 transceiver chip (BL1590), powered by a 3.3V supply. The pulse-per-second single-ended signal optimization and shaping circuit in this device is implemented using a Schmitt trigger buffer chip (RS1G17). The pulse-per-second valid indication circuit includes two NOT gates, an OR gate, a first counter, a first counter enable unit, and a pulse-per-second valid indication signal output unit. Both the pulse-per-second valid indication circuit and the pulse-per-second absent indication circuit are implemented using an FPGA. The BL1590 chip receives a pair of differential level signals and outputs a 3.3V CMOS digital pulse signal. This CMOS-level digital pulse signal is a pulse-per-second single-ended signal (RO1). After optimization and shaping by a Schmitt trigger buffer unit (RS1G17), the pulse-per-second single-ended signal (RO1) is generated as a pulse-per-second access signal (RO2). The RS1G17 eliminates ringing, noise, and slight jitter on the pulse-per-second single-ended signal (RO1), completing the optimization of the pulse-per-second single-ended signal. When the pulse-per-second signal (RO1) rises above the upper threshold voltage of 2.1V, the trigger circuit within the RS1G17 switches the pulse-per-second access signal (RO2) to its current state. When the pulse-per-second signal (RO1) falls below the lower threshold voltage of 0.45V, the trigger circuit within the RS1G17 switches RO2 to its current state. As long as disturbances caused by ringing, noise, and slight jitter keep the pulse-per-second signal (RO1) within the hysteresis voltage range formed by two critical voltages (the upper and lower thresholds), the RS1G17 can prevent false circuit triggering caused by these disturbances. The pulse-per-second access signal (RO2) is introduced into the FPGA via an IO pin. The global reset signal (RSTn), which is active low, is also introduced into the FPGA via an IO pin. The local clock (CLK) frequency introduced into the FPGA is 125MHz.

[0088] Under ideal conditions, free from ringing, noise, and jitter, the pulse-per-second single-ended signal (RO1) output by the BL1590 and the pulse-per-second access signal (RO2) output by the RS1G17 are both unipolar rectangular pulse signals, with the positive pulse width of RO2 being 100ms. However, in practical applications, the pulse-per-second access signal (RO2), generated after RS1G17 optimizes and shapes the pulse-per-second single-ended signal (RO1), may still contain jitter signals that are not eliminated by RS1G17, such as positive pulse jitter signals with a width of approximately 20μs. Within the FPGA, the first counter in the pulse-per-second valid indication circuit counts the number of clock cycles corresponding to the positive pulse width of the pulse-per-second access signal (RO2). By setting the first threshold and operating the pulse-per-second valid indication signal output unit, this embodiment can further eliminate the impact on control accuracy caused by jitter in the pulse-per-second access signal (RO2) that significantly perturbs the signal level but is not eliminated by RS1G17. In the pulse-per-second access signal (RO2) output by RS1G17, when the positive pulse width is less than or equal to 20μs, the pulse is considered a jitter signal that needs to be eliminated; when the positive pulse width is greater than 20μs, the positive pulse is considered a "true" positive pulse. A 20μs positive pulse width corresponds to 2500 clk clock cycles. The timer interrupt implementation circuit requires a high-level width of 24ns for the pulse-per-second valid indication signal (Sp_clr). 24ns corresponds to 3 local clock cycles. Therefore, the first threshold is 2500. The second threshold is set to 2503.

[0089] In this embodiment, the inverted signal (RO3) of the pulse-per-second access signal (RO2) and the inverted signal (RST) of the global reset signal (RSTn) serve as inputs to the OR gate. After the global reset completes, the first counter actually counts the number of clock cycles corresponding to the positive pulse width of the pulse-per-second access signal (RO2), that is, the number of clock cycles corresponding to the low-level (zero-level) width of the inverted signal (RO3) of the pulse-per-second access signal (RO2). The first counter receives the local clock clk as input and the output signal (CLR1) of the OR gate as input. The counting bit width of the first counter is set to 12 bits. The output of the first counter is Q1[11:0]. The inputs to the first counter enable unit are the count value Q1[11:0] of the first counter and the second threshold. The output of the first counter enable unit provides input to the enable signal input terminal of the first counter. The inputs to the pulse-per-second valid indication signal output unit are the count value Q1[11:0] of the first counter, the first threshold, and the second threshold. The output of the pulse-per-second valid indication signal output unit is the pulse valid indication signal (Sp_clr).

[0090] The low level of the pulse-per-second access signal (RO2) corresponds to the high level of the RO3 signal. The high level of the RO3 signal, or the high level of the inverted signal (RST) of the global reset signal (RSTn), clears the first counter. After the global reset is completed, when the pulse-per-second access signal (RO2) is low, the RO3 signal is high, and the clear signal of the first counter is valid. When the clear signal of the first counter is valid, even if the enable signal of the first counter is allowed to count by 1 under the beat of the local clock, the count value of the first counter remains 0, and the Sp_clr ​​signal remains low. After the global reset is completed, when the pulse-per-second access signal (RO2) is high, the RO3 signal is low, and the clear signal of the first counter is invalid. When the clear signal of the first counter is invalid and the first counter is allowed to count by 1, the first counter is incremented once at each clk clock beat. The first counter simultaneously outputs its count value to the first counter enable unit and the pulse-per-second valid indication signal output unit. The first counter enable unit compares the first count value with the second threshold value. When the first count value is less than or equal to the second threshold value of 2503, the first counter is allowed to increment; when the first count value is greater than the second threshold value of 2503, the first counter is not allowed to increment. The pulse-per-second valid indication signal output unit compares the count value of the first counter with the first and second threshold values ​​to determine whether a "real" pulse-per-second has arrived. This determines whether the Sp_clr ​​signal is low or high, and the duration of the high level. When the count value of the first counter is less than or equal to 2500, the Sp_clr ​​signal is low. When the count value of the first counter is greater than 2500 and less than or equal to 2503, the Sp_clr ​​signal is high. When the count value of the first counter is greater than 2503, the Sp_clr ​​signal is low. Therefore, the width of the positive pulse in the Sp_clr ​​signal generated by the pulse-per-second valid indication signal output unit in the pulse-per-second valid indication circuit is 24ns.

[0091] In the first application scenario, where ringing, noise, and slight jitter are present, the single-ended pulse-per-second signal (RO1) is optimized and shaped by the Schmitt trigger buffer unit (RS1G17). A 100ms-wide positive pulse appears every second on the pulse-per-second access signal (RO2). However, an 18μs-wide positive pulse jitter signal appears 30ns before this positive pulse. After the global reset completes, and before the positive pulse jitter occurs, the RO3 signal and the CLR1 signal are both high, and the first counter remains at 0. When the positive pulse jitter occurs, the RO3 signal and the CLR1 signal both go low, and the first counter restarts from zero. The first count enable unit allows the first count value to continue as long as it is less than or equal to 2503. When the first counter reaches 2250, a falling edge appears on the pulse-per-second access signal (RO2), and the positive pulse jitter ends. During the positive pulse of the dithering signal, the count value of the first counter is less than 2500, indicating that the "real" second pulse has not arrived, and the Sp_clr ​​signal remains low. Subsequently, the count value of the first counter is cleared to zero due to the low level of the second pulse access signal (RO2). The Sp_clr ​​signal remains low until the second pulse access signal (RO2) has a positive pulse again. After the positive pulse ends, the first counter starts counting from zero again.

[0092] In the second application scenario, free of ringing, noise, and slight jitter, the single-ended pulse-per-second signal (RO1) is optimized and shaped by the Schmitt trigger buffer unit (RS1G17). A positive pulse with a width of 100ms appears every second on the pulse-per-second access signal (RO2). After the global reset completes, before the positive pulse of the pulse-per-second access signal (RO2) arrives, the RO3 signal and the CLR1 signal are both high, and the count value of the first counter remains at 0. When the positive pulse of the single-ended pulse-per-second signal (RO1) arrives, the RO3 signal and the CLR1 signal both go low, and the first counter restarts counting from zero in accordance with the local clock. The first count enable unit allows the first count value to remain as long as it is less than or equal to 2503. When the count value of the first counter is less than 2501, Sp_clr ​​is low. When the count value of the first counter equals 2501, it is determined that a "real" pulse-per-second has arrived, and the Sp_clr ​​signal goes high. When the count value of the first counter is equal to 2501, 2502, or 2503, Sp_clr ​​is at a high level. When the count value of the first counter is greater than 2503, Sp_clr ​​becomes a low level. Therefore, the second pulse valid indication signal output unit in the second pulse valid indication circuit generates an Sp_clr ​​signal with a positive pulse width of 24ns.

[0093] The pulse valid indication signal (Sp_clr) remains high for three local clock cycles, or 24 ns. At a local clock frequency of 125 MHz, starting from the time Sp_clr ​​transitions from low to high, the second counter's count value remains at 0 for the three local clock cycles when Sp_clr ​​is high. After Sp_clr ​​transitions low, the second counter's count value reaches 124999997, which is exactly one second. Therefore, the third threshold is set to 124999997.

[0094] like Figure 3 As shown, the second counter receives the local clock clk input and receives the pulse valid indication signal (Sp_clr) output by the second pulse valid indication circuit as input. The counting bit width of the second counter is set to 27 bits. The output of the second counter is Q2[26:0]. The input of the second counter enable unit is the count value Q2[26:0] of the second counter and the third threshold. The output of the second counter enable unit provides input to the enable signal input terminal of the second counter. The input of the second pulse absence indication signal output unit is the count value Q2[26:0] of the second counter and the third threshold. The output of the second pulse absence indication signal output unit is the pulse absence indication signal (Sp_absent).

[0095] A high level on the pulse valid indication signal (Sp_clr) clears the second counter. When the pulse valid indication signal (Sp_clr) is high, the clear signal for the second counter is valid. When the clear signal for the second counter is valid, the second counter's count value remains at 0, and the Sp_absent signal remains low, even if the second counter's enable signal is enabled to increment by 1, according to the local clock. When the pulse valid indication signal (Sp_clr) is low, the clear signal for the second counter is inactive. When the clear signal for the second counter is inactive and the second counter is enabled to increment by 1, the second counter increments by 1 at every clk clock tick. The second counter outputs its count value simultaneously to the second counter enable unit and the pulse-absent indication signal output unit. The second counter enable unit compares the second count value with a third threshold: when the second count value is less than or equal to the third threshold of 124999997, the second counter is enabled to increment by 1; when the second count value is greater than the third threshold of 124999997, the second counter is disabled from incrementing by 1. The pulse-per-second absence indication signal output unit compares the count value of the second counter with a third threshold to determine whether the time elapsed from counting from 0 to the current value has reached one second. This determines whether the Sp_absent signal is low or high. When the second counter's count value is less than 124999997, the Sp_absent signal is low. When the second counter's count value is equal to 124999997, the time elapsed from counting from 0 to the current value has reached one second, and the Sp_absent signal is low. When the second counter's count value is equal to 124999998, indicating that the count time has reached one second according to the local clock, Sp_clr ​​is low, indicating that the second counter has not been cleared, and Sp_absent is high. If the external clock's one second is exactly equal to the one second counted in the local clock tick, then in the next clock tick after the second counter reaches 124999997, the seconds pulse valid indicator signal (Sp_clr) will go high, clearing the second counter, and Sp_absent will not go high. If the external clock's one second is longer than the local clock's one second, the positive pulse of the seconds pulse valid indicator signal (Sp_clr) will be "delayed," causing the seconds pulse absent indicator signal (Sp_absent) to remain high for a period of time.

[0096] The second pulse absence indication signal (Sp_absent) and the second pulse valid indication signal (Sp_clr) are used to control the relevant counters (third counter, non Figure 2 and Figure 3the local clock frequency is shorter than the 1 second time of the external second pulse, the 1 second time in the local clock beat counting case has arrived, but the positive pulse of the second pulse valid indication signal (Sp_clr) does not come, then the pulse absence indication signal (Sp_absent) changes from low level to high level. When the pulse absence indication signal (Sp_absent) is high level, the related counters, register variables, etc. in the timing interrupt implementation circuit are cleared, at this time the timing interrupt implementation circuit does not generate an interrupt signal to the CPU. When the positive pulse of the second pulse valid indication signal (Sp_clr) comes, the high level of the second pulse valid indication signal (Sp_clr) lasts for 3 clk periods, and the Sp_absent signal also changes from high level to low level. The time when the Sp_absent signal lasts for high level is actually the time when the timing interrupt implementation circuit needs to wait for the positive pulse of the second pulse valid indication signal (Sp_clr) to come. Through this waiting time, the time point when the related counters, register variables, etc. in the timing interrupt implementation circuit end the clearing can be synchronized with the positive pulse signal of the relatively delayed second pulse valid indication signal (Sp_clr). When the second pulse absence indication signal (Sp_absent) and the second pulse valid indication signal (Sp_clr) are both low level, the clearing of the related counters, register variables, etc. in the timing interrupt implementation circuit ends, and the timing interrupt implementation circuit can start to generate an interrupt signal according to a certain rule and provide it to the CPU. Therefore, the introduction of the second pulse valid indication signal (Sp_clr) and the second pulse absence indication signal (Sp_absent) enables the timing interrupt implementation circuit to avoid the timing problem caused by the mismatch between the local clock precision and the external second pulse signal time precision. At the same time, the second pulse absence indication signal (Sp_absent) as one of the clearing signals of the related counters, register variables, etc. in the timing interrupt implementation circuit, can effectively prevent the timing interrupt implementation circuit from performing unnecessary work and causing additional hardware overhead.

[0097] On the contrary, without the waiting time when the pulse absence indication signal (Sp_absent) changes from low level to high level and lasts for high level, when the 1 second time counted according to the local clock frequency is shorter than the 1 second time of the external second pulse, the timing interrupt implementation circuit calculates that the 1 second time has arrived according to the local clock frequency, but the positive pulse of the second pulse valid indication signal (Sp_clr) does not come, the timing interrupt implementation circuit will ignore the difference between the local clock precision and the external second pulse precision, and start to generate an interrupt signal according to a certain rule and provide it to the CPU again according to the local clock beat, which leads to a certain error in the control of the timing interrupt implementation circuit by the external second pulse, and may cause adverse consequences.

[0098] In an application scenario where one second counted according to the local clock frequency is longer than one second counted by the external second pulse, when one second counted according to the local clock frequency has not yet been reached, the positive pulse of the second pulse valid indication signal (Sp_clr) arrives, and the high level of the second pulse valid indication signal (Sp_clr) will last for three clk cycles, and the Sp_absent signal will remain at a low level. After the positive pulse of the Sp_clr ​​signal causes the relevant counters, register variables, etc. in the timing interrupt implementation circuit to be cleared to zero, the timing interrupt implementation circuit begins to generate interrupt signals according to a certain rule and provides them to the CPU, so that the time point when the relevant counters, register variables, etc. in the timing interrupt implementation circuit end clearing to zero can be synchronized with the relatively early positive pulse signal of the second pulse valid indication signal (Sp_clr). Therefore, this embodiment enables the timing interrupt implementation circuit to adapt to application scenarios where the second period of the local clock is longer than the second period of the external second pulse.

[0099] In summary, the control signal for the timing interruption implementation circuit generated by this embodiment enables the timing interruption implementation circuit to adapt to the mismatch between the local clock accuracy and the external clock accuracy, and can avoid the timing problem caused by such mismatch.

[0100] It is understandable that the detailed functional implementation of each of the above units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0101] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0102] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0103] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0104] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0105] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0106] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in or transmitted by a computer readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media sets. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0107] It can be understood that various numerical numbers involved in the embodiments of the present application are only distinguished for convenience of description, and are not used to limit the scope of the embodiments of the present application.

[0108] Those skilled in the art easily understand that the above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A control signal generation method based on timed interruption of second pulse, characterized in that: include: Under the beat of the local clock, the number of clock cycles corresponding to the positive pulse width of the unipolar rectangular pulse signal is counted. If the positive pulse width count value is less than or equal to a first threshold, the second pulse valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the second pulse valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the second pulse valid indication signal is low; Under the beat of the local clock, the number of clock cycles is counted with the pulse-per-second valid indication signal as a count reset signal. If the count value of the number of clock cycles is less than or equal to a third threshold, the pulse-per-second absent indication signal is at a low level; otherwise, the pulse-per-second absent indication signal is at a high level until the count value of the number of clock cycles is reset by the next pulse-per-second valid indication signal, at which point the pulse-per-second absent indication signal returns to a low level again. The generated second pulse valid indication signal and second pulse absent indication signal are sent as control signals to the timing interrupt implementation circuit to realize control of the timing interrupt implementation circuit, wherein when the second pulse absent indication signal is at a high level, the relevant counters and register variables in the timing interrupt implementation circuit are cleared to zero; when the second pulse absent indication signal and the second pulse valid indication signal are both at a low level, the clearing of the relevant counters and register variables in the timing interrupt implementation circuit is completed; Among them, the first threshold is the product of the jitter signal width that needs to be eliminated and the local clock frequency, the second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency, and the third threshold is the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the second pulse valid indication signal.

2. The control signal generating method according to claim 1, wherein: The pulse-per-second differential signal is converted to a pulse-per-second single-ended signal.

3. The control signal generating method according to claim 2, wherein: The pulse-per-second single-ended signal is optimized and shaped to eliminate the influence of ringing, noise and slight jitter on the pulse-per-second single-ended signal, and to generate an optimized and shaped pulse-per-second access signal.

4. A control signal generating device based on timed interruption of second pulse, characterized in that: include: A pulse-per-second valid indication circuit is configured to count the number of clock cycles corresponding to the positive pulse width of an input unipolar rectangular pulse signal under the beat of a local clock. If the positive pulse width count value is less than or equal to a first threshold, the pulse-per-second valid indication signal is low; if the positive pulse width count value is greater than the first threshold and less than or equal to a second threshold, the pulse-per-second valid indication signal is high; if the positive pulse width count value is greater than the second threshold, the pulse-per-second valid indication signal is low. The first threshold is the product of the jitter signal width to be eliminated and the local clock frequency. The second threshold is the sum of the first threshold and the product of the pulse width of the valid indication signal and the local clock frequency; a pulse-per-second absence indication circuit, configured to count clock cycles in a local clock beat using a pulse-per-second validity indication signal as a count reset signal; if the clock cycle count value is less than or equal to a third threshold, the pulse-per-second absence indication signal is at a low level; otherwise, the pulse-per-second absence indication signal is at a high level until the clock cycle count value is reset by the next pulse-per-second validity indication signal, at which point the pulse-per-second absence indication signal returns to a low level again; the third threshold being the difference between the local clock frequency and the number of clock cycles corresponding to the positive pulse width of the pulse-per-second validity indication signal; The generated second pulse valid indication signal and second pulse absent indication signal are sent to the timing interrupt implementation circuit as control signals to realize the control of the timing interrupt implementation circuit. When the second pulse absent indication signal is at a high level, the relevant counters and register variables in the timing interrupt implementation circuit are cleared; when the second pulse absent indication signal and the second pulse valid indication signal are both at a low level, the clearing of the relevant counters and register variables in the timing interrupt implementation circuit is completed.

5. The control signal generating device according to claim 4, wherein: The second pulse valid indication circuit mainly includes: a NOT gate, a first counter, a first counter enabling unit, and a second pulse valid indication signal output unit; The first counter is a binary counter whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the second threshold plus 1, and is used to count the number of clock cycles corresponding to the positive pulse width of the input unipolar rectangular pulse signal under the beat of the local clock; The first counter enabling unit is configured to enable counting of the first counter; The second pulse valid indication signal output unit is used to compare the count value of the first counter with the first threshold and the second threshold, and generate a second pulse valid indication signal according to the comparison result.

6. The control signal generating device according to claim 5, wherein: The first counter enabling unit is configured to compare the count value of the first counter with a second threshold value, and enable the first counter to count only when the count value of the first counter is less than or equal to the second threshold value.

7. The control signal generating device according to claim 4, wherein: The second pulse absence indication circuit includes: a second counter, a second counter enabling unit, and a second pulse absence indication signal output unit; The second counter is a binary counter, whose counting bit width is not less than the counting bit width required for the count value of the counter to reach the third threshold plus 1, and is used to count the number of clock cycles under the beat of the local clock and use the second pulse valid indication signal as the reset signal; The second counter enabling unit is configured to enable counting of the second counter; The second pulse absence indication signal output unit is used to compare the count value of the second counter with a third threshold value, and generate a second pulse absence indication signal according to the comparison result.

8. The control signal generating device according to claim 7, wherein: The second counter enabling unit is configured to compare the count value of the second counter with a third threshold value, and enable the second counter to count only when the count value of the second counter is less than or equal to the third threshold value.

9. The control signal generating device according to claim 4, wherein: Also includes: A pulse-per-second receiving circuit is used to convert the pulse-per-second differential signal to obtain a pulse-per-second single-ended signal; The second pulse single-ended signal optimization and shaping circuit is used to optimize and shape the second pulse single-ended signal to eliminate the influence of ringing, noise, and slight jitter on the second pulse single-ended signal, and generate an optimized and shaped second pulse access signal.

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