Method for analyzing time sequence of logic system design and related equipment

Abstract

The invention provides a method and related equipment for analyzing a time sequence of a logic system design, and the method comprises the steps: converting the delay among a plurality of programmable logic devices into a delay logic circuit among the plurality of programmable logic devices; and a plurality of partial logic and delay logic circuits corresponding to the plurality of programmable logic devices are used as a whole for static time sequence analysis, so that the problem that delay among the programmable logic devices cannot be analyzed is solved, and time sequence analysis of the whole logic system design is realized.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a method and related equipment for analyzing the timing of logic system design. Background Art

[0002] A hardware simulation tool (e.g., a programmable logic device or a hardware simulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, an integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) or a system-on-chip (System-On-Chip, referred to as SOC) for a specific application. Therefore, the logic system design tested in the simulation tool can also be called a design under test (Design Under Test, referred to as DUT). The simulation tool can simulate the design under test through one or more configurable components (e.g., Field Programmable Gate Array (FPGA)), including performing various operations of the design under test, thereby testing and verifying the functions of each module of the design under test before manufacturing. By connecting a variety of peripheral daughter cards to the simulation tool, the effect of the design under test and various peripherals running as a complete system can also be tested.

[0003] When multiple PLDs are used to simulate a design under test, static timing analysis is a necessary design step to accurately estimate the delay within each PLD and the delay between each PLD. However, static timing analysis tools can be used to analyze the delay within a PLD, but cannot analyze the delay between each PLD. Summary of the invention

[0004] A first aspect of the present application provides a method for analyzing the timing of a logic system design, wherein the logic system design is implemented on a hardware simulation tool, wherein the hardware simulation tool includes a plurality of programmable logic devices, and the plurality of programmable logic devices respectively include a plurality of partial logics of the logic system design, and the method includes: determining delays between the plurality of programmable logic devices; converting the delays between the plurality of programmable logic devices into delay logic circuits between the plurality of programmable logic devices; and performing static timing analysis on a plurality of partial logics corresponding to the plurality of programmable logic devices and the delay logic circuit as a whole.

[0005] A second aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method as described in the first aspect.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and when the set of instructions is executed, causes the computer to perform the method as described in the first aspect.

[0007] The present application provides a method and related equipment for analyzing the timing of a logic system design. The method converts the delay between multiple programmable logic devices into a delay logic circuit between the multiple programmable logic devices, and performs static timing analysis on multiple partial logics and delay logic circuits corresponding to the multiple programmable logic devices as a whole, thereby solving the problem of being unable to analyze the delay between each programmable logic device, and further realizing the timing analysis of the entire logic system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A schematic structural diagram of an electronic device according to an embodiment of the present application is shown.

[0010] Figure 2 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of an exemplary hardware simulation tool according to an embodiment of the present application is shown.

[0012] Figure 4 A flow chart of an exemplary method for performing static timing analysis on a logic system design according to an embodiment of the present application is shown.

[0013] Figure 5 A flowchart of an exemplary method for analyzing the timing of a logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0014] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0015] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0016] As described above, when multiple programmable logic devices are used to simulate the design under test, static timing analysis is a necessary design step in order to accurately estimate the delay within each programmable logic device and the delay between each programmable logic device. However, static timing analysis tools can be used to analyze the delay within a programmable logic device, but cannot analyze the delay between each programmable logic device.

[0017] In view of this, the present application provides a method and related equipment for analyzing the timing of a logic system design, by converting the delay between multiple programmable logic devices into a delay logic circuit between the multiple programmable logic devices, and performing static timing analysis on multiple partial logics and delay logic circuits corresponding to the multiple programmable logic devices as a whole, thereby solving the problem of being unable to analyze the delays between each programmable logic device, and further realizing the timing analysis of the entire logic system design.

[0018] Figure 1 FIG. 1 is a schematic diagram showing the structure of an electronic device 100 according to an embodiment of the present application. The electronic device 100 may be an electronic device for running a simulation system. Figure 1 As shown, the electronic device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in the electronic device.

[0019] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0020] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating errors of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0021] The network interface 106 can be configured to provide the electronic device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0022] The peripheral interface 108 can be configured to connect the electronic device 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0023] The bus 110 can be configured to transmit information between various components of the electronic device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0024] It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above electronic device architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0025] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0026] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and an electronic device 100 connected to the simulation tool 202. The simulation tool may also be referred to as a hardware simulation tool.

[0027] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 can be a programmable logic device or a hardware simulator (emulator). A design under test can include multiple modules. The design under test can be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 can include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0028] Simulation tool 202 can include interface unit 2022, is used for coupling with electronic equipment 100 communication ground, to carry out the communication between electronic equipment 100 and simulation tool 202.In certain embodiments, interface unit 2022 can include one or more interfaces with electrical connection capability.For example, interface unit 2022 can include RS232 interface, USB interface, LAN port, optical fiber interface, IEEE1394 (firewire interface) etc.In certain embodiments, interface unit 2022 can be wireless network interface.For example, interface unit 2022 can be WIFI interface, bluetooth interface etc.

[0029] The electronic device 100 may transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data, etc. to the electronic device 100 via the interface unit 2022.

[0030] The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design to be tested during the simulation process. In some embodiments, the signal values ​​generated by the design to be tested during the simulation process may be directly read by the electronic device 100. It is understood that the memory 2024 may also be independent of the simulation tool 202, for example, using an external memory.

[0031] The simulation tool 202 may also include an FPGA 2026 for implementing the logic system design in hardware on the FPGA. It is understandable that the simulation tool 202 may include multiple FPGAs, which are only examples in the figure.

[0032] In addition to being connected to the electronic device 100, the simulation tool 202 can also be connected to one or more daughter cards 204 or one or more FPGAs via the interface unit 2022. When connected to multiple FPGAs, the method of the embodiment of the present application is also applicable to perform timing analysis on the multiple FPGAs.

[0033] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that restores the actual use scenario of the chip as much as possible before the chip is taped out to verify whether the chip function is accurate and complete. The daughter card 204 can include a memory daughter card (for example, providing a DDR memory interface), a communication daughter card (for example, providing a variety of network interfaces or a wireless network card interface), etc.

[0034] The electronic device 100 can be used to configure the simulation tool 202 to simulate a design to be tested. The design to be tested can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the electronic device 100 can be a virtual electronic device in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog).

[0035] The electronic device 100 may receive a request from a user to debug the design to be tested. As described above, the design to be tested may include one or more modules. The description of the design to be tested may be completed with a hardware description language. The electronic device 100 may be synthesized based on the description of the design to be tested to generate, for example, a gate-level circuit netlist (not shown) of the design to be tested. The gate-level circuit netlist of the design to be tested may be loaded into the simulation tool 202 for operation, and then a circuit structure corresponding to the design to be tested may be formed in the simulation tool 202. Therefore, the circuit structure of the design to be tested may be obtained according to the description, and accordingly, the circuit structure of each block in the design to be tested may also be obtained similarly.

[0036] Figure 3 FIG. 3 is a schematic diagram of an exemplary hardware simulation tool 302 according to an embodiment of the present application. The hardware simulation tool 302 may be the simulation tool 202 .

[0037] The hardware simulation tool 302 may include multiple programmable logic devices (e.g., FPGAs). The logic system design 304 may be implemented on one or more programmable logic devices. In some embodiments, the logic system design 304 may be divided into multiple partial logics, and the multiple partial logics may be implemented on multiple programmable logic devices, respectively.

[0038] Take the hardware simulation tool 302 including three programmable logic devices (FPGA 3021, FPGA 3022 and FPGA 3023) as an example. Figure 3 As shown, FPGA 3021, FPGA 3022 and FPGA 3023 may respectively include multiple partial logics corresponding to logic system design 304. When performing timing analysis on logic system design 304, for multiple partial logics corresponding to logic system design 304, timing analysis may be performed using a static timing analysis tool to estimate the internal delay of the programmable logic device. However, the static timing analysis tool may analyze the delay of a single entity (internal delay of the programmable logic device), and for the connection between multiple programmable logic devices, such as connection 306, 308 and 310, the static timing analysis tool cannot perform timing analysis on the logic between multiple programmable logic devices because the connection (e.g., cable) between multiple programmable logic devices is not a pure digital circuit and spans multiple entities (e.g., serial-to-parallel converter, parallel-to-serial converter, etc.).

[0039] For the delay between multiple programmable logic devices, in some embodiments, it can be measured by experiment. The delay of the logic system design 304 can be obtained by summing the measurement results of the delay between multiple programmable logic devices and the internal delay of the programmable logic device. However, the result obtained by summing the calculation results obtained by the two timing measurement methods is not accurate enough. At the same time, when summing the measurement results of the delay between multiple programmable logic devices and the internal delay of the programmable logic device, it is also necessary to manually write a custom script to perform the sum calculation, which cannot be quickly submitted to different static timing analysis tool applications through standard circuit formats and timing constraints. When cross-validation is used with different static timing analysis tools, the efficiency is low.

[0040] Figure 4 A flow chart of an exemplary method 400 for performing static timing analysis on a logic system design according to an embodiment of the present application is shown.

[0041] like Figure 4 As shown, in some embodiments, in order to implement the simulation of the logic system design 304 on the hardware simulation tool 302 including multiple FPGAs, the logic system design 304 can be split into multiple sub-designs and implemented on multiple FPGAs 3021, 3022 and 3023 respectively. Multiple FPGAs 3021, 3022 and 3023 also have interface logic and cables for connecting the multiple FPGAs 3021, 3022 and 3023. It is understandable that due to its own physical properties (closer to analog circuits), the cable cannot use traditional static timing analysis to determine the delay. It should be noted that the cable in the embodiment of the present application, in addition to the cable itself, also includes the supporting logic required for implementing cross-FPGA communication, and the supporting logic may include modules such as parallel-to-serial converters, check code generators, serial-to-parallel converters, data checkers, clock generators, etc. Both the supporting logic and the cable generate delays.

[0042] In order to implement static timing analysis of the entire logic system design 304 , the embodiment of the present application converts the logic system design 304 into equivalent on-chip logic 402 , inter-chip logic 404 , and inter-chip delay 406 .

[0043] The on-chip logic 402 may be a plurality of partial logics in each programmable logic device (that is, a plurality of sub-designs of the logic system design 304), and the plurality of partial logics correspond to specific constraints (e.g., the second constraint). The constraint may be the number of logic gates consumed by the partial logic, the frequency range of operation, etc. Taking the three programmable logic devices included in the hardware simulation tool 302 as an example, the plurality of partial logics of the logic system design 304 may be implemented on FPGA 3021, FPGA 3022, and FPGA 3023, respectively, and the split on-chip logic 402 may include partial logic 4022 implemented on FPGA 3021, partial logic 4024 implemented on FPGA 3022, and partial logic 4026 implemented on FPGA 3023. It can be understood that the partial logics 4022, 4024, and 4026 have corresponding constraints, respectively.

[0044] The inter-chip logic 404 may be an interface logic for connecting multiple programmable logic devices. Figure 4 As shown, the split inter-chip logic 404 may include interface logic of connection 306 , connection 308 , and connection 310 .

[0045] As described above, the delay between the FPGAs caused by the cables used for connecting between the FPGAs cannot be determined using traditional static timing analysis. For the inter-chip delay of the cable that cannot be analyzed using a static timing analysis tool, in some embodiments, the inter-chip delay 406 of the cable can be converted into a logic circuit 408 (e.g., a delay logic circuit) between multiple programmable logic devices. For example, for inter-chip logic with an inter-chip delay of 5, the inter-chip logic can be converted into a corresponding delay logic circuit through 5 logic function units (e.g., buffers). Through the method of this embodiment, the logic between multiple programmable logic devices can be converted into a pure digital logic circuit.

[0046] like Figure 4 As shown, the inter-chip delay 406 may include a delay 4062 corresponding to the connection 306 between FPGA 3021 and 3022, a delay 4064 corresponding to the connection 308 between FPGA 3022 and 3023, and a delay 4066 corresponding to the connection 310 between FPGA 3023 and 3021. Multiple programmable logic devices may be connected through cables. In some embodiments, when determining the inter-chip delay 406, multiple cables connected between the multiple programmable logic devices and multiple cable delays corresponding to the multiple cables may be obtained. The inter-chip delay 406 is determined by finding the cable configuration of the multiple programmable logic devices. Among them, the multiple cable delays corresponding to the multiple cables may be determined by experimental measurement. The cable configuration may include a cable connecting any two programmable logic devices among the multiple programmable logic devices, and specifically, may include information such as the model of the cable, the serial-to-parallel conversion rate of the interface of the two programmable logic devices connected by the cable, and the parallel-to-serial conversion rate.

[0047] When the inter-chip logic 404 is converted into the logic circuit 408 according to the inter-chip delay 406, in some embodiments, the constraint conditions (e.g., the first constraint conditions) corresponding to each delay logic circuit in the logic circuit 408 can also be determined according to the inter-chip logic 404, and the constraint conditions can ensure that each delay logic circuit meets a specific function. Specifically, the logic circuit 408 may include a delay logic circuit 4082 corresponding to the connection 306, a delay logic circuit 4084 corresponding to the connection 308, and a delay logic circuit 4086 corresponding to the connection 310. It can be understood that the delay logic circuits 4082, 4084, and 4086 have corresponding constraints respectively. In some embodiments, multiple partial logics in the on-chip logic 402 and multiple delay logic circuits in the logic circuit 408 can be merged into a top-level circuit to perform static timing analysis on the on-chip logic 402 and the logic circuit 408 as a whole. In this way, compared with the timing calculation result obtained by summing up the results obtained by the two timing measurement methods, performing static timing analysis on multiple programmable logic devices as a whole can obtain more accurate timing analysis results. In addition, since the method provided in the embodiment of the present application adopts a standard circuit format, it can quickly switch to any open source or static timing analysis tool to perform static timing analysis, and has strong portability. The above method that requires manual writing of custom scripts for summing calculations requires superimposed consideration of process conditions, and the script complexity is high, while the method provided in the embodiment of the present application does not require superimposed consideration of various process conditions, and can quickly calculate the timing results under various process conditions.

[0048] It should be noted that the number of programmable logic devices in the embodiments of the present application is exemplary, and a larger number of programmable logic devices may be configured on the hardware simulation tool, which is not limited in the embodiments of the present application.

[0049] Figure 5 FIG. 5 is a flow chart showing an exemplary method 500 for analyzing the timing of a logic system design according to an embodiment of the present application. The method 500 may be performed by Figure 1 The electronic device 100 is executed, more specifically, by a hardware simulation tool (e.g., Figure 3 The hardware simulation tool 302 in the embodiment is executed. The hardware simulation tool may be a simulation tool (for example, Figure 2 202 in the simulation tool). Logical system design (e.g., Figure 3 The logic system design 304 in the embodiment may be implemented on a hardware simulation tool, which may include multiple programmable logic devices (e.g., Figure 3The FPGA 3021, FPGA 3022 and FPGA 3023 in the embodiment of the present invention are shown in FIG.

[0050] At step 502 , a hardware simulation tool may determine delays between the plurality of programmable logic devices.

[0051] In some embodiments, the hardware simulation tool may divide the logic system design into the multiple partial logics, so as to implement the multiple partial logics on multiple programmable logic devices respectively.

[0052] In some embodiments, the hardware simulation tool can obtain multiple cables (e.g., connections 306, 308, 310) and multiple cable delays corresponding to the multiple cables respectively; determine the cable configuration between the multiple programmable logic devices, the cable configuration includes a cable connecting any two of the multiple programmable logic devices; determine the delay between the multiple programmable logic devices based on the multiple cable delays and the cable configuration. Through the information in the cable configuration, the delay between the multiple programmable logic devices can be determined based on the obtained cable delay.

[0053] In some embodiments, the cable delay includes a delay of the cable (e.g., Figure 4 4062, delay 4064 and delay 4066) and the delay of the interface of the two programmable logic devices connected by the cable (for example, Figure 4 delay caused by the inter-chip logic 404).

[0054] The delay between multiple programmed logic devices can be determined by the cable delay.

[0055] At step 504, the hardware simulation tool may convert the delays between the plurality of programmable logic devices into delay logic circuits (eg, Figure 4 Delay logic circuit 4082, delay logic circuit 4084 and delay logic circuit 4086).

[0056] In some embodiments, the hardware simulation tool can determine the logic between the multiple programmable logic devices; based on the logic between the multiple programmable logic devices, the delay between the multiple programmable logic devices is converted into the delay logic circuit. Through the method of this embodiment, the logic between the multiple programmable logic devices can be converted into a pure digital logic circuit.

[0057] In some embodiments, the hardware simulation tool may determine the first constraint condition corresponding to the delay logic circuit according to the logic between the plurality of programmable logic devices. The first constraint condition may ensure that the delay logic circuit meets a specific function.

[0058] In some embodiments, the hardware simulation tool can determine the second constraint corresponding to the plurality of partial logics; and perform static timing analysis on the plurality of partial logics, the second constraint, the delay logic circuit, and the first constraint as a whole. Thus, compared with the timing calculation result obtained by summing up the results obtained by the two timing measurement methods, performing static timing analysis on the plurality of programmable logic devices as a whole can obtain a more accurate timing analysis result.

[0059] In step 506, the hardware simulation tool may simulate multiple partial logics (eg, Figure 4 The partial logic 4022, partial logic 4024 and partial logic 4026) and the delay logic circuit are subjected to static timing analysis as a whole.

[0060] In some embodiments, the hardware simulation tool may merge the multiple partial logics and the delay logic circuit into a top-level circuit (e.g., on-chip logic 402+logic circuit 408). Thus, compared with the timing calculation result obtained by summing up the results obtained by the two timing measurement methods, performing static timing analysis on multiple programmable logic devices as a whole may obtain more accurate timing analysis results.

[0061] The present application provides a method and related equipment for analyzing the timing of a logic system design. The method converts the delay between multiple programmable logic devices into a delay logic circuit between the multiple programmable logic devices, and performs static timing analysis on multiple partial logics and delay logic circuits corresponding to the multiple programmable logic devices as a whole, thereby solving the problem of being unable to analyze the delay between each programmable logic device, and further realizing the timing analysis of the entire logic system design.

[0062] The present application also provides an electronic device. The electronic device may be Figure 1 The electronic device 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device performs the method 500.

[0063] The embodiment of the present application further provides a non-transitory computer-readable storage medium, which stores a set of computer instructions, and the set of instructions is used to make the computer perform the method 500 when executed.

[0064] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0065] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0066] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0067] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for analyzing the timing of a logic system design, wherein the logic system design is implemented on a hardware simulation tool, wherein the hardware simulation tool includes a plurality of programmable logic devices, and wherein the plurality of programmable logic devices respectively include a plurality of partial logics of the logic system design, wherein the method comprises: determining delays between the plurality of programmable logic devices; converting delays between the plurality of programmable logic devices into delay logic circuits between the plurality of programmable logic devices; Static timing analysis is performed on a plurality of partial logics corresponding to the plurality of programmable logic devices and the delay logic circuit as a whole.

2. The method of claim 1, wherein: Determining the delay between the plurality of programmable logic devices further comprises: Acquire a plurality of cables for connecting the plurality of programmable logic devices and a plurality of cable delays respectively corresponding to the plurality of cables; determining a cable configuration between the plurality of programmable logic devices, the cable configuration comprising a cable connecting any two of the plurality of programmable logic devices; Delays between the plurality of programmable logic devices are determined based on the plurality of cable delays and the cable configuration.

3. The method of claim 1, further comprising: The logic system design is divided into the plurality of logic portions.

4. The method of claim 1, wherein: The performing static timing analysis on the plurality of partial logics corresponding to the plurality of programmable logic devices and the delay logic circuit as a whole further comprises: The plurality of partial logics and the delay logic circuit are merged into a top-level circuit.

5. The method of claim 2, wherein: The cable delay includes a delay of the cable and a delay of interfaces of two programmable logic devices connected by the cable.

6. The method of claim 1, wherein: The step of converting the delay between the plurality of programmable logic devices into a delay logic circuit between the plurality of programmable logic devices further comprises: determining logic between the plurality of programmable logic devices; Based on the logic between the plurality of programmable logic devices, the delays between the plurality of programmable logic devices are converted into the delay logic circuit.

7. The method of claim 6, further comprising: A first constraint condition corresponding to the delay logic circuit is determined according to logic between the plurality of programmable logic devices.

8. The method of claim 7, wherein: The performing static timing analysis on the plurality of partial logics corresponding to the plurality of programmable logic devices and the delay logic circuit as a whole further comprises: Determine a second constraint condition to which the plurality of parts are logically corresponding; The plurality of partial logics, the second constraint condition, the delay logic circuit and the first constraint condition are subjected to static timing analysis as a whole.

9. An electronic device, comprising: a memory for storing a set of instructions; as well as At least one processor is configured to execute the set of instructions so that the electronic device performs the method according to any one of claims 1 to 8. 10 . A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method according to claim 1 when executed.

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