Hybrid solid state drive

Abstract

Systems, methods, and devices are described for writing to a solid state drive (SSD) that includes a non-volatile memory device that includes a first memory region and a second memory region, the first memory region storing an address mapping table. A write request including a host logical block address (LBA) and data is received. It is determined whether the received LBA corresponds to a non-volatile memory device or a second memory region. In response to the received LBA corresponding to the non-volatile memory device, a physical address of the non-volatile memory device corresponding to the received LBA is determined based on an address mapping table, and the included data is written to the determined physical address of the non-volatile memory device. In response to the received LBA corresponding to the second memory region, the included data is written to the second memory region based on the received LBA.

Description

Background Art

[0001] A solid state drive (SSD) is a storage device that uses integrated circuits to persistently store data. An SSD may include volatile memory storage and non-volatile memory storage. Typically, the volatile memory storage is used to store an address mapping table that is used to map logical block addresses (LBAs) to physical addresses of the non-volatile memory storage. A controller of the SSD accesses the address mapping table to determine which physical address corresponds to an LBA (in the non-volatile memory storage) referenced in a read request or a write request. A portion of the volatile memory storage is typically unused. Summary of the invention

[0002] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0003] Methods, systems, and apparatus for utilizing a solid-state drive (SSD) including a nonvolatile memory device are described. The volatile memory device includes a first memory area and a second memory area. The first memory area stores an address mapping table. In one aspect, data is written to the SSD. A write request including a host logical block address (LBA) and data is received. A determination is made as to whether the received LBA corresponds to the nonvolatile memory device or the second memory area. In response to the received LBA corresponding to the nonvolatile memory device, a physical address of the nonvolatile memory device corresponding to the received LBA is determined based on the address mapping table, and the included data is written to the determined physical address of the nonvolatile memory device. In response to the received LBA corresponding to the second memory area, the included data is written to the second memory area based on the received LBA.

[0004] In another aspect, data is read from the SSD. A read request including an LBA is received. A determination is made as to whether the received LBA corresponds to a nonvolatile memory device or a second memory region. In response to the received LBA corresponding to the nonvolatile memory device, a physical address of the nonvolatile memory device corresponding to the received LBA is determined based on an address mapping table, and data is read from the determined physical address of the nonvolatile memory device. In response to the received LBA corresponding to the second memory region, data is read from the physical address of the second memory region corresponding to the received LBA.

[0005] Other features and advantages of the embodiments, as well as the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. It should be noted that the claimed subject matter is not limited to the specific examples described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be clear to those skilled in the relevant art. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated herein and constitute a part of the specification, illustrate embodiments and, together with the description, further serve to explain the principles of the embodiments and to enable those skilled in the relevant art to make and use the embodiments.

[0007] Figure 1 is a block diagram of a server configured to store data according to an example embodiment.

[0008] Figure 2 is a block diagram of a hybrid solid-state drive according to an example embodiment.

[0009] Figure 3A is a flow chart of a process for writing data to a hybrid solid-state drive according to one embodiment.

[0010] Figure 3B is a flow chart of a process for determining a physical address of a non-volatile memory device corresponding to a received LBA, according to one embodiment.

[0011] Figure 3C is a flow chart of a process for writing data to a second memory area of ​​a volatile memory device based on a received LBA, according to one embodiment.

[0012] Figure 4 is an example namespace table according to one embodiment.

[0013] Figure 5 is a flow chart of a process for backing up data stored in a second memory area of ​​a volatile memory device and restoring the data to the second memory area of ​​the volatile memory device according to one embodiment.

[0014] Figure 6 is a flow chart of a process for reading data stored in a hybrid solid-state drive according to one embodiment.

[0015] Embodiments will now be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or functionally similar elements. In addition, the leftmost digit of a reference numeral identifies the figure in which the reference numeral first appears. DETAILED DESCRIPTION

[0016] I. Introduction

[0017] The following detailed description discloses many example embodiments. The scope of this patent application is not limited to the disclosed embodiments, but also includes combinations of the disclosed embodiments and modifications to the disclosed embodiments.

[0018] References in the specification to "one embodiment," "an embodiment," and "an example embodiment" indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered to be within the knowledge of those skilled in the art to affect such particular feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.

[0019] If the performance of an operation is described herein as being "based on" one or more factors, it should be understood that the performance of the operation may be based only on (multiple) such factors, or may be based on (multiple) such factors and one or more additional factors. Therefore, as used herein, the term "based on" should be understood to be equivalent to the term "based at least on".

[0020] The example embodiments described herein are provided for illustrative purposes only and are not intended to be limiting. The examples described herein may be applicable to any type of method or system for utilizing unused volatile memory storage space to store non-volatile data. Additional structural and operational embodiments (including modifications / alterations) will become apparent to those skilled in the relevant art based on the teachings herein.

[0021] Note that the variable "N" is appended to various reference numerals in the accompanying drawings / figures identifying the components shown to indicate that the number of such components is variable, e.g., having any value of 2 or greater. Note that for each different component / reference numeral, the variable "N" has a corresponding value that may be different from the "N" values ​​of other components / reference numerals. Depending on the particular implementation, the "N" value for any particular component / reference numeral may be less than 10, tens, hundreds, thousands, or even greater.

[0022] A number of example embodiments are now described. Any section / subsection headings provided herein are not limiting. Embodiments are described throughout the document, and any type of embodiment may be included under any section / subsection. In addition, the embodiments disclosed in any section / subsection may be combined in any manner with any other embodiments described in the same section / subsection and / or in different sections / subsections.

[0023] II. Example Hybrid Solid-State Drive Embodiments

[0024] A solid state drive (SSD) is a storage device that uses an integrated circuit to store data persistently. The SSD may include a controller configured to receive read requests and write requests from a host computing device. The read request and the write request may include an LBA corresponding to a physical address of a memory portion of the SSD. The controller is configured to read data from the physical address or write data to the physical address based on the LBA. The SSD may include multiple types of memory portions. For example, an SSD according to one embodiment includes a volatile memory portion and a non-volatile memory portion. The volatile memory portion may include a volatile memory device, such as a double data rate (DDR) memory device, a synchronous random access memory (SRAM) device, a dynamic random access memory device (DRAM), etc. The non-volatile memory portion may include a non-volatile memory device, including a flash memory device (e.g., NAND flash, NOR flash, etc.), a non-volatile random access memory (NVRAM), etc. For example, according to one embodiment, the SSD includes a DDR memory device and a NAND flash device.

[0025] The volatile memory portion may be configured to store an address mapping table that maps LBAs to physical addresses of the data center SSD. Depending on the particular implementation, a portion of the volatile memory storage space of the volatile memory device may be unused. For example, an SSD according to one embodiment has a non-volatile storage capacity measured as a power of 10, such as 4 TB or 4×10 12 The size of the address mapping table is proportional to the nonvolatile storage capacity, for example, 0.1% of the nonvolatile storage capacity, which in this example is 4GB or 4×10 9 In one embodiment, the volatile memory storage capacity of the SSD is configured according to a power of 2, such as 4 GiB or 4×2 30 In this example, 294967296 bytes of volatile memory storage space are unused.

[0026] Embodiments and techniques of the present disclosure relate to configuring unused volatile memory storage space as additional storage space. The additional storage space can be used as non-volatile memory storage space. For example, the additional storage space can be used to store data, such as data files, host application metadata files, etc. The embodiment can be implemented in a manner that separates the additional storage space from the volatile memory storage space for storing address mapping tables. For example, according to one embodiment, the volatile memory storage space is divided into a first memory area and a second memory area. The first memory area is configured to store an address mapping table, and the second memory area is configured as the additional storage space. According to another embodiment, the first memory area includes a reserved portion of the storage space for storing data such as system variables.

[0027] According to embodiments herein, a hybrid SSD is an SSD configured to store data in one of its non-volatile memory storage space or its available volatile memory storage space (i.e., storage space not used to store address mapping tables). For example, a hybrid SSD according to an embodiment may provide one or more of the following features.

[0028] Improved service quality Embodiments provide storage options with lower latency than non-volatile memory storage space. For example, DDR memory devices typically have lower latency than NAND flash devices.

[0029] Reduced write amplification . Implementations of non-volatile memory devices may have write cycle limits. For example, a physical address of a NAND flash memory device may be written a certain number of times before a cell associated with the physical address is unavailable or unreliable. An embodiment provides a storage option that does not consume write cycles of a non-volatile memory device. Additionally, if a write request is received with a memory address corresponding to additional storage space, write amplification is reduced. In this case, write cycles of the non-volatile memory device are not consumed to write data to the additional storage space. Applications such as key-value data stores or log file systems may use the additional storage space to reduce consumed write cycles.

[0030] Reduced Total Cost of Ownership (TCO) . Embodiments of the present disclosure may be implemented without increasing bill of materials (BOM) costs. For example, more of the non-volatile memory physical storage capacity may be used as logical storage capacity while reducing overall write amplification. In addition, long-term costs are reduced because overall write cycle consumption is reduced.

[0031] An embodiment of a hybrid SSD is configured to receive read requests and write requests. These requests include a memory address corresponding to a physical address of the hybrid SSD. The memory address may be a logical block address (LBA). The hybrid SSD is configured to read data from the physical address or write data to the physical address based on the memory address. The memory address space may be divided into a plurality of partitions. For example, according to one embodiment, the memory address is divided into a first partition corresponding to a second memory area of ​​a volatile memory storage space and a second partition corresponding to a non-volatile memory storage space. A hybrid data storage manager of the hybrid SSD directs data traffic (e.g., read requests and write requests) to the partition corresponding to the memory address. According to one embodiment, the hybrid data storage manager accesses the partition corresponding to the second memory area of ​​the volatile memory storage space without referring to an address mapping table stored in the first memory area of ​​the volatile memory storage space.

[0032] A hybrid SSD can be used in a variety of applications. For example, a hybrid SSD can be implemented as an external hard drive, a hard drive of a computing device, a hard drive within a storage server, and / or a hard drive within a data center, etc. An external hard drive is a hard drive that can be connected to a computing device. A computing device can be any type of fixed or mobile computing device, including a mobile computing device (e.g., devices, personal digital assistants (PDAs), laptops, notebooks, tablet computers (such as the Apple iPad TM ), netbooks, etc.), mobile phones, wearable computing devices or other types of mobile devices, or fixed computing devices (such as desktop computers or servers). The storage server is configured to manage and access files stored in the storage device. The storage server can be a stand-alone storage server, or a server in a server rack (e.g., 8-40 servers per rack, called a node or "blade server"), a server in a server cluster (e.g., 2-64 servers, 4-8 racks or other numbers of servers and / or racks), or a server in a data center (e.g., thousands of servers, hundreds of racks and / or dozens of clusters). A data center is a group of collocated servers (e.g., located in one or more nearby buildings, with associated components such as backup power, redundant data communications, and environmental controls).

[0033] In an embodiment, a hybrid SSD may be implemented in various ways. For example, Figure 1 1 is a block diagram of a storage server 100 (hereinafter "server 100") configured to store data according to an example embodiment. In an embodiment, server 100 may be a stand-alone server, or a server within a server rack, server cluster, or data center. Server 100 may be connected to other computing devices via wired and / or wireless connections (for simplicity and brevity of illustration, the server 100 is not shown in FIG. 1 ). Figure 1 For example, the server 100 may be accessed by a computing device via a network such as a local area network (LAN), a wide area network (WAN), an enterprise network, the Internet, etc. Figure 1 As shown, the server 100 includes a host device 102 and a storage device 104. Figure 1As shown, the storage device 104 includes drive sets 108 and 110. The drive set 108 includes a bus switch 112 and first to third hybrid SSDs 116, 118, and 120. The drive set 110 includes a bus switch 114 and first to third hybrid SSDs 122, 124, and 126. The host device 102 is configured to manage and access data stored in the storage device 104. For example, the host device 102 can provide a computing device with access to data stored in the storage device 104. For example, the host device 102 can send a read request or a write request to the drive set 108 or the drive set 110. The bus switches 112 and 114 are configured to send the read request or the write request received from the host device 102 to its corresponding hybrid SSD. In one embodiment, the host device 102 includes an interface for directly accessing and managing data stored in the storage device 104. The storage device 104 is a storage area of ​​the server 100 that can be accessed via a wired and / or wireless network and managed by the host device 102 .

[0034] Each of the hybrid SSDs 116, 118, 120, 122, 124, and 126 may be configured to store data in both a volatile memory storage space and a non-volatile memory storage space. Figure 1 As shown, each of the hybrid SSDs 116, 118, 120, 122, 124, and 126 includes a corresponding SSD volatile memory storage space in the SSD volatile memory storage spaces 128, 132, 136, 140, 144, and 148, a corresponding non-volatile memory storage space in the non-volatile memory storage spaces 130, 134, 138, 142, 146, and 150, a corresponding SSD controller in the SSD controllers 152, 154, 156, 164, 166, and 168, and a corresponding hybrid data storage manager in the hybrid data storage manager 158, 160, 162, 170, 172, and 174. Figure 1As shown, hybrid data storage managers 158, 160, and 162 are components of the respective hybrid SSDs 116, 118, and 120, and hybrid data storage managers 170, 172, and 174 are integrated into the respective SSD controllers 164, 166, and 168. Volatile memory storage spaces 128, 132, 136, 140, 144, and 148 are configured to store respective address mapping tables in respective first memory regions. Each of the volatile memory storage spaces 128, 132, 136, 140, 144, and 148 may include unused portions of the volatile memory storage space. These unused portions of the volatile memory storage space may be configured as respective second memory regions. The hybrid data storage managers 158, 160, 162, 170, 172 and 174 are each configured to manage requests to read data from and / or write data to a second memory area of ​​a corresponding volatile memory storage space in the volatile memory storage spaces 128, 132, 136, 140, 144, 148 and / or a corresponding physical address in the physical addresses of the non-volatile memory storage spaces 130, 134, 138, 142, 146 and 150.

[0035] The server 100 may include Figure 1 Additional components and / or subcomponents are not shown in order to facilitate simplicity and brevity of illustration. Figure 1 Only two drive sets are shown in the figure, but it is contemplated herein that a host device such as host device 102 can manage and access data stored in any number of drive sets (e.g., less than ten, tens, hundreds, or even more). In addition, although each drive set is shown as a set of three hybrid SSDs, it is contemplated herein that the drive set can include any number of hybrid SSDs (e.g., less than ten, tens, hundreds, or even more). In addition, the drive set can include other storage devices besides hybrid SSDs, including hard disk drives (HDDs), conventional SSDs, etc. Figure 1 As shown, hybrid data storage managers 158, 160, and 162 are independent components of respective hybrid SSDs 116, 118, and 120, however, it is contemplated herein that, depending on a particular implementation, the hybrid data storage manager may be implemented as a subcomponent of an SSD controller (e.g., as shown and described with respect to hybrid SSDs 122, 124, and 126), a subcomponent of a memory device (e.g., a volatile memory device or a non-volatile memory device), and / or another component of a hybrid SSD.

[0036] Hybrid SSD embodiments (such as Figure 1 The hybrid SSDs 116, 118, 120, 122, 124, and 126 of the illustrated server 100 may be configured in a variety of ways. For example, Figure 2 is a block diagram of a hybrid SSD 200 according to an example embodiment. The hybrid SSD 200 may be Figure 1 Another embodiment of one or more of the hybrid SSDs 116, 118, 120, 122, 124, or 126. Figure 1 The hybrid SSD 200 is described with reference to the server 100 of FIG. Additional structural and operational examples will be apparent to those skilled in the relevant art based on the following description.

[0037] like Figure 2 As shown, hybrid SSD 200 includes SSD controller 202, hybrid data storage manager 218, volatile memory storage space 204 and non-volatile memory storage space 206. SSD controller 202 is configured to enable hybrid SSD 200 to communicate with its components within the system and communicate with other devices and / or systems over a network, such as communication between hybrid SSD 200 and other devices, systems and / or hosts, such as for Figure 1 For example, SSD controller 202 may be communicatively coupled to SSD controller 202 via communication link 212. Figure 1 102. The SSD controller 202 may be directly coupled to the host device 102 via a communication link 212 or indirectly coupled (e.g., through a bus switch such as bus switch 112 or 114). The SSD controller 202 may be communicatively coupled to the hybrid data storage manager 218 via a communication link 230. The hybrid data storage manager 218 may be communicatively coupled to the volatile memory storage space 204 via a communication link 214, and to the non-volatile memory storage space 206 via a communication link 216. The communication links 212, 214, 216, and / or 230 may each include one or more physical (e.g., wires, cables, conductive traces, etc.) and / or wireless (e.g., radio frequency, infrared, etc.) communication connections, or any combination thereof. For example, in a circuit board embodiment, communication link 212 can be a cable connected to a communication interface of SSD controller 202, and communication links 214, 216 and 230 can be conductive traces on a circuit board on which SSD controller 202, volatile memory storage space 204, non-volatile memory storage space 206 and hybrid data storage manager 218 are disposed.

[0038] The volatile memory storage space 204 is configured to store volatile data. The volatile memory storage space 204 may include a first memory area and a second memory area. The first memory area is configured to store the address mapping table 232, and the second memory area is configured as an additional storage space. According to one embodiment, the first memory area is also configured to store system data such as system variables. Figure 2 As shown, the volatile memory storage space 204 includes volatile memory devices 208A-208N ("volatile memory devices 208A-208N" herein), wherein volatile memory devices 208A, 208B, 208C, and 208N are shown. The volatile memory devices 208A-208N can be any type of volatile memory device, including DDR devices, SRAM devices, DRAM devices, etc. Each of the volatile memory devices 208A-208N can be a volatile memory device of the same or different types. For example, according to one embodiment, each of the volatile memory devices 208A-208N is a DDR device. The volatile memory devices 208A-208N can represent a separate device in a group of volatile memory devices. For example, in a circuit board embodiment, each of the volatile memory devices 208A-208N can be an integrated circuit chip disposed on a circuit board. In an embodiment, the first memory region and the second memory region may each be distributed across one or more of the volatile memory devices 208A-208N. For example, the second memory region may include a portion of the storage space of one of the volatile memory devices 208A-208N, a portion of the storage space of a subset of the volatile memory devices 208A-208N, and / or a portion of the storage space of each of the volatile memory devices 208A-208N. Each of the volatile memory devices 208A-208N may have equal or different storage capacities. Figure 2 As shown, the address mapping table 232 is distributed across each of the volatile memory devices 208A-208N, however, other implementations contemplated herein may store the address mapping table 232 on a subset of the volatile memory devices.

[0039] The non-volatile memory storage space 206 is configured to store non-volatile data. The physical address of the non-volatile memory storage space 206 can be divided into one or more partitions. For example, the non-volatile memory storage space 206 may include one or more available storage partitions, backup storage partitions, and / or other partitions that will be understood by those skilled in the relevant art having the benefit of the present disclosure. Figure 2As shown, the non-volatile memory storage space 206 includes non-volatile memory devices 210A-210N ("non-volatile memory devices 210A-210N" herein), wherein non-volatile memory devices 210A, 210B, 210C, and 210N are shown. The non-volatile memory devices 210A-210N can be any type of non-volatile memory device, including flash memory storage devices (e.g., NAND flash memory, NOR flash memory, etc.), non-volatile random access memory (NVRAM), etc. Each of the non-volatile memory devices 210A-210N can be the same or different types of non-volatile memory devices. For example, according to one embodiment, each of the non-volatile memory devices 210A-210N is a NAND flash memory device. The non-volatile memory devices 210A-210N can represent independent devices in a group of non-volatile memory devices. For example, in a circuit board embodiment, each of the non-volatile memory devices 210A-210N may be an integrated circuit chip disposed on a circuit board. Each of the non-volatile memory devices 210A-210N may have equal or different storage capacities.

[0040] According to one embodiment, SSD controller 202 is configured to manage communications received and sent via communication link 212 and communications to and from hybrid data storage manager 218 via communication link 230. For example, SSD controller 202 may receive and send data from hybrid data storage manager 218 via communication link 230. Figure 1 Host device 102 receives a read request or a write request and transmits the request to hybrid data storage manager 218 via communication link 230. SSD controller 202 may include subcomponents configured to perform power management functions, fault monitoring, environmental monitoring, and other functions associated with the operation of hybrid SSD 200 (for brevity and illustrative clarity, Figure 2 ), as understood by those skilled in the relevant art having the benefit of this disclosure.

[0041] The hybrid data storage manager 218 is configured to process read requests and write requests, manage data stored in the volatile memory storage space 204 and the non-volatile memory storage space 206, and access data stored in the volatile memory storage space 204 and the non-volatile memory storage space 206. The hybrid data storage manager 218 includes a memory selector 220, a volatile memory controller 222, an address mapping table manager 224, a non-volatile memory controller 226, and a backup data writer 228. The hybrid data storage manager 218 is configured to receive requests from the SSD controller 202 via a communication link 230.

[0042] Memory selector 220 is configured to determine which physical address is associated with the memory address of the request signal received from SSD controller 202. For example, according to one embodiment, if the received memory address corresponds to the physical address of the second memory region of volatile memory storage space 204, memory selector 220 selects volatile memory storage space 204. If the received memory address corresponds to the physical address of non-volatile memory storage space 206, memory selector 220 selects non-volatile memory storage space 206. According to one embodiment, the memory address is an LBA.

[0043] The volatile memory controller 222 is configured to read data from and write data to the volatile memory storage space 204. For example, when the hybrid SSD 200 is turned on or otherwise powered on, the volatile memory controller 222 receives an address mapping table (e.g., a backup address mapping table stored in the non-volatile memory storage space 206) and writes the received address mapping table to a first memory region of the volatile memory storage space 204 as the address mapping table 232. The volatile memory controller 222 is also configured to receive a request to read data from and write data to a second memory region of the volatile memory storage space 204. For example, if the memory selector 220 selects the volatile memory storage space 204 based on a memory address received with a write request, the volatile memory controller 222 writes the data included in the write request to a physical address of the second memory region based on the received memory address. If the memory selector 220 selects the volatile memory storage space 204 based on the memory address received with the read request, the volatile memory controller 222 reads data from the physical address of the second memory area based on the received memory address. According to one embodiment, the volatile memory controller 222 is configured to transmit a confirmation after completing the read request or the write request. For example, if the received request is a read request, the volatile memory controller 222 is configured to transmit the data read from the second memory area of ​​the volatile memory storage space 204 to the SSD controller 202 via the communication link 230 according to one embodiment, and the SSD controller 202 is then configured to transmit the data to the host device 102 via the communication link 212. If the received request is a write request, the volatile memory controller 222 is configured to transmit a write completion confirmation to the SSD controller 202 via the communication link 230 according to one embodiment, and the SSD controller is then configured to transmit a write completion confirmation to the host device 102 via the communication link 212.

[0044] The volatile memory controller 222 may be configured to determine the physical address in a variety of ways. Figure 2As shown, the volatile memory controller 222 includes an LBA converter 234. The LBA converter 234 is configured to convert the memory address of the request signal received by the hybrid data storage manager 218 into the physical address of the volatile memory storage space 204 if the memory selector 220 selects the volatile memory storage space 204. According to one embodiment, the received memory address is an LBA. In this case, the LBA converter 234 converts the received LBA into the corresponding physical address of the second memory area according to the following equation 1:

[0045] PA=S+(yx)*Size LBA (Equation 1)

[0046] In Equation 1, PA is the physical address, S is the starting physical address of the second memory area of ​​the volatile memory storage space 204, y is the received LBA, x is the number of the first LBA stored in the volatile memory storage space 204, and Size LBA is the size of each LBA in bytes. In a non-limiting example, if the first LBA is stored in physical address 0xEE6B_2800, x is 0 (e.g., the first LBA stored in physical address 0xEE6B_2800 is LBA0), y is 10 (e.g., the received LBA is LBA10), and each LBA is 4096 bytes, then the LBA converter 234 converts the received LBA (LBA10) to physical address 0xEE6B_C800.

[0047] The address mapping table manager 224 is configured to determine the physical address of the non-volatile memory storage space 206 corresponding to the received memory address based on the address mapping table 232. For example, if the memory selector 220 selects the non-volatile memory storage space 206 based on the received memory address, the address mapping table manager 224 is configured to access the address mapping table 232 from the volatile memory storage space 204 to determine the physical address of the non-volatile memory storage space 206 corresponding to the received memory address. The address mapping table manager 224 may be configured to access the address mapping table 232 indirectly via the communication link 114 or via the volatile memory controller 222. According to one embodiment, the address mapping table manager 224 is configured to determine whether the received memory address corresponds to a previously mapped physical address based on the address mapping table 232. If the received memory address corresponds to a previously mapped physical address, the address mapping table manager 224 indicates the physical address of the non-volatile memory storage space 206 corresponding to the received memory address. If the received memory address does not correspond to the previously mapped physical address, the address mapping table manager 224 allocates a new physical address from the available physical addresses to correspond to the received memory address. In this case, the address mapping table manager 224 updates the address mapping table 232 to indicate the physical address corresponding to the received memory address.

[0048] The non-volatile memory controller 226 is configured to write data to and read data from the non-volatile memory storage space 206. The non-volatile memory controller 226 is configured to receive an indication from the address mapping table manager 224 indicating a physical address corresponding to the received memory address. In this case, the non-volatile memory controller 226 writes data to the indicated physical address of the non-volatile memory storage space 206 and / or reads data therefrom. According to one embodiment, the non-volatile memory controller 226 is configured to transmit an acknowledgment after completing a read request or a write request. For example, if the received request is a read request, the non-volatile memory controller 226 is configured according to one embodiment to transmit the data read from the non-volatile memory storage space 206 to the SSD controller 202 via the communication link 230, and the SSD controller 202 is then configured to transmit the data to the host device 102 via the communication link 212. If the received request is a write request, non-volatile memory controller 226 is configured, according to one embodiment, to transmit a write completion confirmation to SSD controller 202 via communication link 230 , which in turn is configured to transmit a write completion confirmation to host device 102 via communication link 212 .

[0049] The backup data writer 228 is configured to manage backup operations of the hybrid data storage manager 218. For example, in response to a power-off event, the backup data writer 228 is configured to write data stored in the second memory area of ​​the volatile memory storage space 204 to the non-volatile memory storage space 206. In some embodiments, the backup data writer 228 is configured to restore data previously stored in the second memory area of ​​the volatile memory storage space 204 in response to a power-on event. According to one embodiment, the hybrid SSD 200 or a system implementing the hybrid SSD 200 includes a backup power circuit (for the sake of brevity and illustrative clarity, Figure 2 200). In this case, the backup power circuit is configured to provide sufficient power to the hybrid SSD 200 so that the backup data writer can perform a backup operation in response to a power failure event. For example, if the second memory area utilizes 200MB and the write bandwidth of the hybrid SSD 200 is 1GB / s, the data stored in the second memory area can be refreshed to the non-volatile memory storage space 206 in less than 1 second. In this case, the backup power circuit is configured to supply power to the hybrid SSD 200 for at least 1 second. A server (such as a server) that implements the backup power circuit and the backup data writer 228 may be configured to provide power to the hybrid SSD 200 for at least 1 second. Figure 1 The server 100) may be configured to treat data stored in the second memory area of ​​the volatile memory storage space 204 as non-volatile data.

[0050] Hybrid SSD 200 may be implemented in various ways. For example, hybrid SSD 200 may include a circuit board. In this case, SSD controller 202, hybrid data storage manager 218, volatile memory devices 208A-208N, and non-volatile memory devices 210A-210N may be integrated circuits mounted to the circuit board. One or more of SSD controller 202, hybrid data storage manager 218, volatile memory devices 208A-208N, and / or non-volatile memory devices 210A-210N may be included in the same integrated circuit package. According to one embodiment, SSD controller 202, hybrid data storage manager 218, volatile memory devices 208A-208N, and / or non-volatile memory devices 210A-210N are implemented in a module (e.g., a "system on a chip" (SOC)). In this case, the SSD controller 202, the hybrid data storage manager 218, the volatile memory devices 208A-208N and / or the non-volatile memory devices 210A-210N may be mounted to separate circuit boards and / or packaged in sub-modules. One or more of the SSD controller 202, the hybrid data storage manager 218, the volatile memory devices 208A-208N and / or the non-volatile memory devices 210A-210N may be disposed on the same circuit board and / or packaged in the same sub-module. Figure 2 As shown, hybrid data storage manager 218 is a separate component of hybrid SSD 200, however, it is contemplated herein that hybrid data storage manager 218 may be implemented as a subcomponent of another component of hybrid SSD 200. For example, hybrid data storage manager 218 according to one embodiment is implemented as a subcomponent of SSD controller 202. According to another embodiment, one or more subcomponents of hybrid data storage manager 218 are implemented as a set of programmed instructions executed by a processor of hybrid SSD 200. In this case, the set of programmed instructions may be stored in one or more memories of hybrid SSD 200, SSD controller 202 and / or hybrid data storage manager 218, volatile memory storage space 204, and / or non-volatile memory storage space 206.

[0051] The hybrid SSD 200 may include Figure 2 Additional components and / or subcomponents not shown in the drawings are for ease and simplicity of illustration. For example, hybrid SSD 200 may include one or more communication interfaces, processors, additional memory devices, and / or sub-controllers.

[0052] Note that in the embodiments, Figure 2 The illustrated hybrid data storage manager 218 may operate in a variety of ways. For example, the hybrid data storage manager 218 may be configured to process data from a host device such as Figure 1 For example, Figure 3A 300 is a flowchart of a process for writing data to a hybrid solid-state drive according to one embodiment. In one embodiment, the hybrid data storage manager 218 may be configured to perform one or all of the steps of the flowchart 300. Figure 1 Server 100 and Figure 2 Flowchart 300 is described with reference to hybrid SSD 200. Additional structural and operational embodiments will be apparent to those skilled in the relevant art based on the following description. Note that not all steps of flowchart 300 need to be performed in all embodiments.

[0053] Flowchart 300 begins at step 302. In step 302, a write request including a host LBA and data is received. For example, Figure 2 The SSD controller 202 receives the Figure 1 Host device 102 receives a write request including a host LBA and data. In addition, hybrid data storage manager 218 is configured to receive a write request from SSD controller 202 via communication link 230 .

[0054] In step 304, it is determined whether the received LBA corresponds to a second memory region of a non-volatile memory device or a volatile memory device. Figure 2 The memory selector 220 determines whether the LBA received in step 302 corresponds to a second memory region of one of the nonvolatile memory devices 210A-210N or one of the volatile memory devices 208A-208N. If the received LBA corresponds to one of the nonvolatile memory devices 210A-210N, the flowchart 300 proceeds to step 306. If the received LBA corresponds to one of the volatile memory devices 208A-208N, the flowchart 300 proceeds to step 310.

[0055] In step 306, the physical address of the non-volatile memory device corresponding to the received LBA is determined based on the address mapping table. Figure 2 The address mapping table manager 224 accesses the address mapping table 232 stored in the first memory area of ​​the volatile memory storage space 204. The address mapping table manager 224 can access the address mapping table 232 directly via the communication link 214 or indirectly (e.g., via the volatile memory controller 222). The address mapping table manager 224 determines the physical address of the non-volatile memory storage space 206 corresponding to the received LBA based on the address mapping table 232.

[0056] In step 308, the included data is written to the determined physical address of the non-volatile memory device. For example, Figure 2 The non-volatile memory controller 226 writes the included data received in step 302 to the physical address of the non-volatile memory storage space 206 determined in step 306 .

[0057] In step 310, the included data is written to the second memory area based on the received LBA. Figure 2 The SSD controller 202 writes the included data received in step 302 to the second memory area of ​​the volatile memory storage space 204 based on the LBA received in step 302. According to one embodiment, the SSD controller 202 writes the included data to the second memory area of ​​the volatile memory storage space 204 via a direct write operation. After the write is completed, the flowchart 300 proceeds to step 312.

[0058] At step 312, flowchart 300 ends. In an embodiment, hybrid data storage manager 218 may be configured to transmit a write completion confirmation as part of step 312. For example, according to one embodiment, hybrid data storage manager 218 transmits the write completion confirmation to SSD controller 202 via communication link 230, and SSD controller 202 in turn transmits the write completion confirmation to SSD controller 202 via communication link 212. Figure 1 The host device 102 transmits a write completion confirmation.

[0059] Although flowchart 300 is described as a process for writing data to a hybrid SSD based on a write request that includes a single LBA, it is contemplated herein that a write request may include multiple LBAs. Hybrid SSD 200 may be configured to perform flowchart 300 sequentially or in batches for each of one or more received LBAs. Furthermore, the received LBAs may correspond to a physical address of volatile memory storage space 204, a physical address of non-volatile memory storage space 206, or a combination of physical addresses of volatile memory storage space 204 and non-volatile memory storage space 206. Furthermore, as will be appreciated by those skilled in the relevant art having the benefit of the present disclosure, it is contemplated herein that other addressing schemes other than logical block addressing using LBAs may be used.

[0060] Note that, in an embodiment, step 306 may be performed in various ways. For example, Figure 3B is a flowchart 320 of a process for determining a physical address of a non-volatile memory device corresponding to a received LBA according to one embodiment. In one embodiment, the flowchart 320 is Figure 3AThe example process of step 306 of FIG. 200 is shown in FIG. 201 , and the hybrid SSD 200 may be configured to perform one or all of the steps of the flowchart 320. Figure 2 Flowchart 320 is described with reference to hybrid SSD 200. Additional structural and operational embodiments will be apparent to those skilled in the relevant art based on the following description. Note that not all steps of flowchart 320 need to be performed in all embodiments.

[0061] Flowchart 320 begins at step 322. According to one embodiment, step 322 is Figure 3A In step 304 of flowchart 300, the received LBA is determined to correspond to a non-volatile memory device (e.g., Figure 2 According to another embodiment, step 322 is an intermediate step between steps 304 and 306. According to yet another embodiment, step 322 is a sub-step of step 306 before step 324.

[0062] In step 324, a new physical address is allocated from the available physical addresses to correspond to the received LBA. For example, Figure 2 The address mapping table manager 224 of the non-volatile memory storage space 206 allocates a new physical address to correspond to the received LBA. The new physical address is an unused available physical address or a reserved physical address. For example, if multiple physical addresses of the non-volatile memory storage space 206 become corrupted or otherwise unsuitable for storing data, the SSD controller 202 can convert the reserved physical address to an available physical address.

[0063] In step 326, the address mapping table is updated to indicate the physical address corresponding to the received LBA. Figure 2 The address mapping table manager 224 updates the address mapping table 232 to indicate the physical address of the non-volatile memory storage space allocated in step 324. Depending on the particular implementation, step 326 may be performed before or after step 308 of flowchart 300. After the address mapping table 232 is updated, flowchart 320 proceeds to step 328.

[0064] Flowchart 320 ends with step 328. According to one embodiment, step 328 is Figure 3A According to another embodiment, step 328 is step 312 of flowchart 300. According to another embodiment, step 328 is an intermediate step between step 326 and step 308 or 312.

[0065] It is contemplated herein that SSD controller 202 may reallocate previously allocated physical addresses of non-volatile memory storage space 206 as part of performing step 324. For example, if address mapping table manager 224, or another component or subcomponent of hybrid SSD 200, determines that a previously allocated physical address is corrupt or otherwise no longer suitable for storing data, address mapping table manager 224 may allocate a new physical address from the available physical addresses to correspond to the received LBA.

[0066] Note that, in embodiments, step 310 may be performed in various ways. For example, Figure 3C is a flowchart 340 of a process for writing data to a second memory area of ​​a volatile memory device based on a received LBA according to one embodiment. In one embodiment, the flowchart 340 is Figure 3A The example process of step 310 of FIG. 310 is shown in FIG. 310 , and the hybrid SSD 200 may be configured to perform one or all of the steps of the flowchart 340 . Figure 2 Flowchart 340 is described with reference to hybrid SSD 200. Additional structural and operational embodiments will be apparent to those skilled in the relevant art based on the following description. Note that not all steps of flowchart 340 need to be performed in all embodiments.

[0067] Flowchart 340 begins at step 342. In step 342, the received LBA is converted into a corresponding physical address of the second memory area. For example, Figure 2 The LBA converter 234 converts the received LBA into a corresponding physical address of the second memory area of ​​the volatile memory storage space 204. The received LBA can be converted into a corresponding physical address in various ways. For example, according to one embodiment, Figure 2 The LBA converter 234 is based on the above Figure 2 The equation 1 described above converts the received LBA into a corresponding physical address of the second memory region.

[0068] In step 344, the included data is written to the corresponding physical address of the second memory area. Figure 2 The volatile memory controller 222 writes the included data to a corresponding physical address of the second memory area of ​​the volatile memory storage space 304 .

[0069] Note that in embodiments, memory addresses such as LBAs may be defined in various ways. For example, Figure 4 is an example namespace table 400 according to one embodiment. Namespace table 400 can be used to understand Figure 2The hybrid SSD 200 of FIG. 10 determines a physical address based on a received memory address. Additional structural and operational embodiments will be apparent to those skilled in the art based on the following description. Figure 1 Server 100 and Figure 2 The Hybrid SSD 200 is described Figure 4 .

[0070] like Figure 4 As shown, the namespace table 400 includes namespace "0" and namespace "1". The namespace table 400 is configured to utilize Y LBAs. Namespace 0 corresponds to the second memory area of ​​the volatile memory storage space and includes LBAs 0 to X-1. Namespace 1 corresponds to the non-volatile memory storage space and includes LBA X to LBA Y-1. Namespaces can be used in a variety of ways. For example, the namespaces can be displayed in an interface of a computing device so that a user can configure data services to utilize a specific namespace. For example, a user can select namespace 0 for lower latency storage, or select namespace 1 for higher storage capacity. In some embodiments, the hybrid data storage manager 218 can be configured to direct data services to a specific namespace based on the application. For example, in a key-value data storage application, the hybrid data storage manager 218 is configured to store log files in namespace 0. In a log file system application, the hybrid data storage manager 218 is configured to store logs in namespace 0. In these example applications, the quality of service can be improved and write amplification can be reduced.

[0071] Although namespace table 400 shows separate namespaces for the second memory region of volatile memory storage space and the non-volatile memory storage space, it is contemplated herein that each region of storage space may be a range of LBAs within the same namespace. Furthermore, it is contemplated herein that the second memory region of volatile memory storage space and / or the non-volatile memory storage space may be divided into additional namespaces. Although the LBA range 0 to X-1 is identical to Figure 4 and the LBA range X to Y-1 is associated with the second memory region in Figure 4 , but it is contemplated herein that the LBA ranges may be ordered in other ways, depending on a particular implementation. For example, according to one embodiment, LBA range 0 to X-1 corresponds to non-volatile memory storage space, and LBA range X to Y-1 corresponds to volatile memory storage space.

[0072] As described herein, the second memory region of the volatile memory storage space is a volatile memory. According to one embodiment, the data stored in the second memory region can be treated as non-volatile data by flushing the data stored in the second memory region to the non-volatile memory storage space during a reboot or power-off period.

[0073] Embodiments of the hybrid SSD may be configured to back up and restore data stored in the second memory area of ​​the volatile memory storage space in various ways. For example, Figure 5 5 is a flowchart 500 of a process for backing up data stored in a second memory area of ​​a volatile memory device and restoring the data to the second memory area of ​​the volatile memory device according to one embodiment. Figure 2 The hybrid SSD 200 may be configured to perform one or all of the steps of the flowchart 500. Figure 2 Flowchart 500 is described with reference to hybrid SSD 200. Additional structural and operational embodiments will be apparent to those skilled in the relevant art based on the following description. Note that not all steps of flowchart 500 need to be performed in all embodiments.

[0074] Flowchart 500 begins at step 502. In step 502, in response to a power failure event, data stored in the second memory area is written to a non-volatile memory device as backup data. For example, in response to a power failure event, Figure 2 The backup data writer 228 writes the data stored in the second memory area of ​​the volatile memory storage space 204 to the non-volatile memory storage space 206 as backup data. The backup data writer 228 can access the data stored in the second memory area of ​​the volatile memory storage space 204 directly via the communication link 214 or indirectly (e.g., via the volatile memory controller 222). The backup data can be accessed via a communication link similar to that described with respect to FIG. Figure 3A 300 is written to the non-volatile memory storage space 206. According to one embodiment, a portion of the non-volatile memory storage space 206 is reserved for storing backup data. The power loss event may include a power loss cycle, a system restart, a power failure, and / or any other situation where power is removed from the hybrid SSD 200. According to one embodiment, the SSD controller 202 may queue the backup operation of step 502 as part of a power loss cycle or system restart. In the event of a loss of power unexpectedly, immediately, or otherwise (e.g., due to a forced reset, forced shutdown, or power failure), the hybrid SSD 200, Figure 1The server 100 or the data center implementing the hybrid SSD 200 may include a backup power circuit to allow the backup data writer 228 to flush the data stored in the second memory area of ​​the volatile memory storage space 204 to the non-volatile memory storage space 206. For example, if the second memory area utilizes 200MB and the write bandwidth of the hybrid SSD 200 is 1GB / s, the data stored in the second memory area can be flushed to the non-volatile memory storage space 206 in less than 1 second.

[0075] In step 504, in response to the power-on event, the backup data stored in the non-volatile memory device is written to the second memory area. Figure 2 The backup data writer 228 of the nonvolatile memory storage space 206 writes the backup data stored in the nonvolatile memory storage space 206 to the second memory area of ​​the volatile memory storage space 204 in response to the power-on event. The backup data writer 228 can access the data stored in the nonvolatile memory storage space 206 directly via the communication link 216 or indirectly (e.g., via the nonvolatile memory controller 226). The backup data can be accessed via a communication link similar to that described with respect to FIG. Figure 3A The power-on event may include restoring power to the hybrid SSD 200 after a power outage or power failure, ending a system reboot, powering on the hybrid SSD 200, and / or otherwise providing power to the hybrid SSD 200.

[0076] Hybrid SSD 200 may be configured to process data from a host device such as Figure 1 For example, Figure 6 600 is a flowchart of a process for reading data stored in a hybrid solid-state drive according to one embodiment. In one embodiment, hybrid SSD 200 may be configured to perform one or all of the steps of flowchart 600. Figure 1 Server 100 and Figure 2 Flowchart 600 is described with reference to hybrid SSD 200. Additional structural and operational embodiments will be apparent to those skilled in the relevant art based on the following description. Note that not all steps of flowchart 600 need to be performed in all embodiments.

[0077] Flowchart 600 begins at step 602. In step 602, a read request including a host LBA is received. For example, Figure 2SSD controller 202 receives the read request from host device 102 via communication link 212 . In addition, hybrid data storage manager 218 receives the read request from SSD controller 202 via communication link 230 .

[0078] In step 604, it is determined whether the received LBA corresponds to a second memory region of a non-volatile memory device or a volatile memory device. Figure 2 The memory selector 220 determines whether the LBA received in step 602 corresponds to the non-volatile memory storage space 206 or the second memory region of the volatile memory storage space 204. If the received LBA corresponds to the non-volatile memory storage space 206, the flowchart 600 proceeds to step 606. If the received LBA corresponds to the second memory region of the volatile memory storage space 204, the flowchart 600 proceeds to step 610.

[0079] In step 606, the physical address of the non-volatile memory device corresponding to the received LBA is determined based on the address mapping table. Figure 2 The address mapping table manager 224 accesses the address mapping table 232 stored in the first memory area of ​​the volatile memory storage space 204, and determines the physical address of the non-volatile memory storage space 206 corresponding to the LBA received in step 602 based on the address mapping table 232.

[0080] In step 608, data is read from the determined physical address of the non-volatile memory device. For example, Figure 2 The non-volatile memory controller 226 reads data from the physical address of the non-volatile memory storage space 206 determined in step 606 , and the flowchart 600 proceeds to step 612 .

[0081] In step 610, data is read from a physical address of a second memory area corresponding to the received LBA. Figure 2 The volatile memory controller 222 reads data from the physical address of the second memory area of ​​the volatile memory storage space 204 corresponding to the LBA received in step 602, and the flowchart 600 proceeds to step 612. According to one embodiment, the physical address of the second memory area can be based on the physical address of the second memory area as described above. Figure 2 The above equation 1 determines. According to one embodiment, the volatile memory controller 222 reads data from the physical address of the second memory area of ​​the volatile memory storage space 204 corresponding to the LBA received in step 602 via a direct read operation.

[0082] Flowchart 600 ends in step 612. In step 612, the data read in step 608 or step 610 is transmitted to the requesting device. For example, Figure 2 The hybrid data storage manager 218 transmits the data read in step 608 or step 610 to the SSD controller 202 via the communication link 230, and the SSD controller 202 then transmits the data read in step 608 or step 610 to the SSD controller 202 via the communication link 212. Figure 1 The host device 102 transmits data.

[0083] III. Additional Example Embodiments and Advantages

[0084] As described above, systems and devices (including data centers, servers, and hybrid SSDs) can be configured to store data in a second memory area of ​​a volatile memory storage space. The hybrid SSD has been described for host devices of data centers and servers, however, it is also contemplated herein that the hybrid SSD can be used in other applications such as computing devices. The volatile memory storage space has been described as having a first memory area and a second memory area, however, it is contemplated herein that the volatile memory storage space can have additional memory areas for functions that will be understood by those skilled in the relevant art who benefit from the present disclosure. For example, the additional memory area of ​​the volatile memory storage space can be used to store system variables.

[0085] In addition, according to the described embodiments and techniques, any components of a data center, server, host device, bus switch, hybrid SSD, SSD controller and / or hybrid data storage manager and their functions can be caused to be activated for operation / execution based on other operations, functions, actions, etc. (including the initialization, completion and / or execution of these functions, actions, etc.).

[0086] In some example embodiments, one or more of the operations of the flowcharts described herein may not be performed. In addition, other operations may be performed in addition to or in place of the operations of the flowcharts described herein. In addition, in some example embodiments, one or more of the operations of the flowcharts described herein may be performed out of order, in an alternating order, or partially (or completely) simultaneously with each other or with other operations.

[0087] The additional example embodiments and advantages described in this section may apply to any embodiment disclosed in this section or any other section of the present disclosure.

[0088] The embodiments described herein and / or any other systems, subsystems, devices, and / or components disclosed herein may be implemented with hardware (e.g., hardware logic / circuitry) or any combination of hardware and software (computer program code configured to be executed in one or more processors or processing devices) and / or firmware.

[0089] IV. Exemplary Processor-Based Implementation

[0090] SSD controllers 152, 154, 156, 164, 166 and 168, hybrid data storage managers 158, 160, 162, 170, 172 and 174, SSD controller 202, hybrid data storage manager 218, memory selector 220, volatile memory controller 222, address mapping table manager 224, non-volatile memory controller 226, backup data writer 228, LBA converter 234, flowchart 300, flowchart 320, flowchart 340, flowchart 500 and / or flowchart 600 can be implemented in hardware or hardware with any combination of software and / or firmware, including being implemented as computer program code configured to be executed in one or more processor units and stored in a computer-readable storage medium, or being implemented as a hardware logic / circuitry system, such as in a system on a chip (SoC). A SoC may include an integrated circuit chip that includes one or more of a processor unit (e.g., a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), a memory, one or more communication interfaces, and / or other circuits and / or embedded firmware for performing its functions.

[0091] The processor unit is an electrical and / or optical circuit implemented in one or more physical hardware circuit device elements and / or integrated circuit devices (semiconductor material chips or tube dies) as a central processing unit (CPU), a microcontroller, a microprocessor and / or other physical hardware processor circuits. The processor unit can execute program code stored in a computer-readable medium, such as program code embodiments of SSD controllers 152, 154, 156, 164, 166 and 168, hybrid data storage managers 158, 160, 162, 170, 172 and 174, SSD controller 202, hybrid data storage manager 218, memory selector 220, volatile memory controller 222, address mapping table manager 224, non-volatile memory controller 226, backup data writer 228, LBA converter 234, flowchart 300, flowchart 320, flowchart 340, flowchart 500 and / or flowchart 600. Note that any suitable memory, including memory, may be used to store SSD controllers 152, 154, 156, 164, 166, and 168, hybrid data storage managers 158, 160, 162, 170, 172, and 174, SSD controller 202, hybrid data storage manager 218, memory selector 220, volatile memory controller 222, address mapping table manager 224, non-volatile memory controller 226, backup data writer 228, LBA converter 234. Examples of such memory include read-only memory (ROM), random access memory (RAM), hard disk drives, disk drives, or other physical storage devices.

[0092] As used herein, the terms "computer program medium", "computer-readable medium" and "computer-readable storage medium" refer to physical hardware media, such as hard disks, removable disks, other physical hardware media (such as RAM, ROM, flash memory cards, memory device packages, portable memory sticks, digital video disks, compact disks, MEMs, nanotechnology-based storage devices, and other types of physical / tangible hardware storage media). Such computer-readable storage media are different from (do not include) and do not overlap with communication media. Communication media embody computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves. The term "modulated data signal" refers to a signal that sets or changes one or more of its characteristics in a manner that encodes information in the signal. By way of example and not limitation, communication media include wireless media (such as acoustic, RF, infrared, and other wireless media) and wired media. Embodiments are also directed to such communication media, which are separate from and do not overlap with embodiments directed to computer-readable storage media.

[0093] V. Additional Example Embodiments

[0094] In one embodiment, a solid state drive (SSD) includes a circuit board, a nonvolatile memory device mounted to the circuit board, a volatile memory device mounted to the circuit board, and a controller mounted to the circuit board. The volatile memory device includes a first memory area and a second memory area. The first memory area is configured to store an address mapping table. The controller is communicatively coupled to the nonvolatile memory device and the volatile memory device. The controller is configured to receive a write request including a host logical block address (LBA) and data. The controller is also configured to determine whether the received LBA corresponds to the nonvolatile memory device or the second memory area. In response to the received LBA corresponding to the nonvolatile memory device, the controller is configured to determine the physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table, and write the included data to the physical address of the nonvolatile memory device. In response to the LBA corresponding to the second memory area, the controller is configured to write the included data to the second memory area based on the LBA.

[0095] In one embodiment, the controller is configured to write the included data to the second memory region based on the received LBA by converting the received LBA to a corresponding physical address of the second memory region and writing the included data to the corresponding physical address of the second memory region.

[0096] In one embodiment, the controller is further configured to receive a read request including an LBA. The controller is further configured to determine whether the received LBA corresponds to a nonvolatile memory device or a second memory area. In response to the received LBA corresponding to the nonvolatile memory device, the controller is configured to determine a physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table, and read data from the determined physical address of the nonvolatile memory device. In response to the received LBA corresponding to the second memory area, the controller is configured to read data from the physical address of the second memory area corresponding to the received LBA.

[0097] In one embodiment, the controller is further configured to write the data stored in the second memory area to the non-volatile memory device as backup data in response to a power-off event.

[0098] In one embodiment, the controller is further configured to write the backup data stored in the non-volatile memory device to the second memory area in response to the power-on event.

[0099] In one embodiment, the controller is configured to determine a physical address of a nonvolatile memory device corresponding to a received LBA by allocating a physical address from available physical addresses to correspond to the received LBA and updating an address mapping table to indicate that the physical address corresponds to the received LBA.

[0100] In one embodiment, the non-volatile memory device is a NAND flash memory device.

[0101] In one embodiment, the volatile memory device is a double data rate (DDR) memory device.

[0102] In one embodiment, a method for writing to a solid state drive (SSD) is performed. The SSD includes a non-volatile memory device and a volatile memory device. The volatile memory device includes a first memory area and a second memory area. The first memory area stores an address mapping table. The method includes receiving a write request including a host logical block address LBA and data. Determine whether the received LBA corresponds to the non-volatile memory device or the second memory area. In response to the received LBA corresponding to the non-volatile memory device, determine the physical address of the non-volatile memory device corresponding to the received LBA based on the address mapping table, and write the included data to the determined physical address of the non-volatile memory device. In response to the received LBA corresponding to the second memory area, write the included data to the second memory area based on the received LBA.

[0103] In one embodiment, writing the included data to the second memory region based on the received LBA includes converting the received LBA to a corresponding physical address of the second memory region.Writing the included data to the corresponding physical address of the second memory region.

[0104] In one embodiment, the method further includes writing the data stored in the second memory area to the non-volatile memory device as backup data in response to the power-off event.

[0105] In one embodiment, the method further includes writing the backup data stored in the non-volatile memory device to the second memory area in response to the power-on event.

[0106] In one embodiment, a physical address of a nonvolatile memory device corresponding to the received LBA is determined based on an address mapping table by allocating a physical address from available physical addresses to correspond to the received LBA. The address mapping table is updated to indicate that the physical address corresponds to the received LBA.

[0107] In one embodiment, the non-volatile memory device is a NAND flash memory device.

[0108] In one embodiment, the volatile memory device is a double data rate (DDR) memory device.

[0109] In one embodiment, a solid state drive (SSD) controller is configured to write to a nonvolatile memory device and a volatile memory device. The volatile memory device includes a first memory area and a second memory area. The first memory area is configured to store an address mapping table. The SSD controller is also configured to receive a write request including a host logical block address (LBA) and data. The SSD controller is also configured to determine whether the received LBA corresponds to the nonvolatile memory device or the second memory area. The SSD controller is also configured to: in response to the received LBA corresponding to the nonvolatile memory device, determine the physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table, and write the included data to the determined physical address of the nonvolatile memory device. The SSD controller is also configured to: in response to the received LBA corresponding to the second memory area, write the included data to the second memory area based on the received LBA.

[0110] In one embodiment, the SSD controller is further configured to write the included data to the second memory area based on the received LBA by converting the received LBA to a corresponding physical address of the second memory area and writing the included data to the corresponding physical address of the second memory area.

[0111] In one embodiment, the SSD controller is further configured to receive a read request including an LBA. The SSD controller is further configured to determine whether the received LBA corresponds to a non-volatile memory device or a second memory area. The SSD controller is further configured to: in response to the received LBA corresponding to the non-volatile memory device, determine the physical address of the non-volatile memory device corresponding to the received LBA based on the address mapping table, and read data from the physical address of the non-volatile memory device. The SSD controller is further configured to: in response to the received LBA corresponding to the second memory area, read data from the physical address of the second memory area corresponding to the received LBA.

[0112] In one embodiment, the SSD controller is further configured to: in response to a power-off event, write the data stored in the second memory area into the non-volatile memory device as backup data.

[0113] In one embodiment, the SSD controller is further configured to write the backup data stored in the non-volatile memory device to the second memory area in response to the power-on event.

[0114] VI. Conclusion

[0115] Although various embodiments have been described above, it should be understood that they are presented by way of example only and not limitation. It will be apparent to those skilled in the relevant art that various changes in form and detail may be made without departing from the spirit and scope of the embodiments. Therefore, the breadth and scope of the embodiments should not be limited by any of the above-described example embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A solid state drive (SSD), comprising: Circuit boards; a non-volatile memory device mounted to the circuit board; a volatile memory device mounted to the circuit board, the volatile memory device comprising a first memory area and a second memory area, the first memory area being configured to store an address mapping table; a controller mounted to the circuit board and communicatively coupled to the non-volatile memory device and the volatile memory device, the controller being configured to: receiving a write request including a host logical block address (LBA) and data; determining whether the received LBA corresponds to the non-volatile memory device or the second memory region; In response to receiving the LBA corresponding to the non-volatile memory device: determining a physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table; as well as writing the included data to the physical address of the non-volatile memory device; as well as In response to the LBA corresponding to the second memory area, the included data is written to the second memory area based on the LBA.

2. The SSD according to claim 1, wherein in order to write the included data to the second memory area based on the received LBA, the controller is configured to: Converting the received LBA into a corresponding physical address of the second memory area; and The included data is written to the corresponding physical address of the second memory area.

3. The SSD of claim 1 , wherein the controller is further configured to: Receiving a read request including the LBA; determining whether the received LBA corresponds to the non-volatile memory device or the second memory region; In response to receiving the LBA corresponding to the non-volatile memory device: determining the physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table; as well as reading data from the determined physical address of the non-volatile memory device; as well as In response to the received LBA corresponding to the second memory region, Data is read from a physical address of the second memory area corresponding to the received LBA.

4. The SSD of claim 1 , wherein in response to a power-off event, the controller is further configured to: The data stored in the second memory area is written to the nonvolatile memory device as backup data.

5. The SSD of claim 4, wherein in response to a power-on event, the controller is further configured to: The backup data stored in the nonvolatile memory device is written to the second memory area.

6. The SSD of claim 1 , wherein to determine the physical address of the nonvolatile memory device corresponding to the received LBA, the controller is configured to: allocating the physical address from available physical addresses to correspond to the received LBA; and The address mapping table is updated to indicate that the physical address corresponds to the received LBA.

7. The SSD of claim 1, wherein the non-volatile memory device is a NAND flash memory device.

8. The SSD of claim 1, wherein the volatile memory device is a double data rate (DDR) memory device.

9. A method for writing to a solid state drive (SSD), the SSD comprising a non-volatile memory device and a volatile memory device, the volatile memory device comprising a first memory area and a second memory area, the first memory area storing an address mapping table, the method comprising: receiving a write request including a host logical block address (LBA) and data; determining whether the received LBA corresponds to the non-volatile memory device or the second memory region; In response to receiving the LBA corresponding to the non-volatile memory device: determining a physical address of the nonvolatile memory device corresponding to the received LBA based on the address mapping table; as well as Writing the included data to the determined physical address of the non-volatile memory device; as well as In response to the received LBA corresponding to the second memory region, the included data is written to the second memory region based on the received LBA.

10. The method of claim 9, wherein the writing the included data to the second memory area based on the received LBA comprises: Converting the received LBA into a corresponding physical address of the second memory area; as well as The included data is written to the corresponding physical address of the second memory area.

11. The method according to claim 9, further comprising: In response to a power-off event, the data stored in the second memory area is written to the nonvolatile memory device as backup data.

12. The method according to claim 11, further comprising: In response to a power-on event, the backup data stored in the non-volatile memory device is written to the second memory area.

13. The method of claim 9, wherein the determining, based on the address mapping table, a physical address of the nonvolatile memory device corresponding to the received LBA comprises: allocating the physical address from available physical addresses to correspond to the received LBA; as well as The address mapping table is updated to indicate that the physical address corresponds to the received LBA.

14. The method of claim 9, wherein the non-volatile memory device is a NAND flash memory device.

15. A solid-state drive (SSD) controller configured to write to a non-volatile memory device and a volatile memory device, the volatile memory device comprising a first memory area and a second memory area, the first memory area storing an address mapping table, the solid-state drive controller being further configured to execute the method according to any one of claims 9 to 14.

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