Pulse counter
By designing asynchronous counters and pulse counters for synchronous reading operations, the problem of low pulse counting efficiency in audio file processing in the prior art is solved, efficient pulse counting and audio file processing in low-frequency environments are realized, and audio file processing is improved efficiency and accuracy.
Patent Information
- Application Number
- CN202410801263.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-22
- Filing Date
- 2024-06-20
- Publication Date
- 2024-12-24
AI Technical Summary
The circuit used for pulse counting in existing audio file processing is inefficient, it is difficult to count effectively in a low-frequency environment and operate based on frequency, and it is impossible to effectively identify pulses in an audio signal.
A pulse counter including an asynchronous counter and a synchronous read operation is designed, and the value reading and reset of the asynchronous counter is synchronized by clock signals. Combined with a circuit suitable for low-frequency operation, it can effectively count pulses at frequencies from 30kHz to 40kHz. And combine neural network for audio file processing.
It realizes efficient counting of pulses in low-frequency environments and can identify pulses in audio files, improving the efficiency and accuracy of audio file processing, and is especially suitable for human sound detection.
Smart Images
Figure CN119182396A_ABST
Abstract
Description
Technical Field
[0001] The present specification generally relates to electronic circuits and devices used in the field of audio file processing. The present specification more particularly relates to a circuit for counting pulses of a signal obtained from an audio file. Background Art
[0002] Audio file processing, especially processing of audio files representing the human voice, is an important problem in many scientific fields.
[0003] It would be desirable to be able to improve, at least in part, certain aspects of circuits and devices used in the field of audio file processing, and in particular to improve certain aspects of circuits for counting pulses of a signal obtained from an audio file. Summary of the invention
[0004] There is a need for more efficient circuits and devices for use in audio file processing.
[0005] Low frequency circuits and devices used in audio file processing are required.
[0006] A more powerful circuit is needed to count the pulses of a signal obtained from an audio file.
[0007] A circuit is needed that can count the pulses of a signal obtained from an audio file and operate based on the frequency.
[0008] One embodiment overcomes some or all of the disadvantages of known circuits and devices used in audio file processing.
[0009] One embodiment overcomes some or all of the disadvantages of known circuits for counting pulses in a signal obtained from an audio file.
[0010] One embodiment provides a pulse counter including an asynchronous counter and a circuit configured to trigger a read operation of a value of the asynchronous counter, the circuit being synchronized by a clock signal.
[0011] According to one embodiment, the counter further comprises a flip-flop adapted to receive said value of said asynchronous counter during a reading phase.
[0012] In one embodiment, the read phase is triggered by an edge of the first synchronization signal.
[0013] In one embodiment, the read phase is stopped by an edge of the second synchronization signal.
[0014] According to one embodiment, the edge of the second synchronization signal also triggers a reset of the asynchronous counter value.
[0015] Another embodiment provides a circuit suitable for recognizing words from an audio file, the circuit comprising the aforementioned pulse counter.
[0016] In one embodiment, the clock frequency of the circuit is 30 kHz to 40 kHz.
[0017] In one embodiment, the clock frequency is 32.728 kHz.
[0018] According to one embodiment, the circuit further comprises a first circuit adapted to implement an acoustic feature extraction function.
[0019] In one embodiment, the circuit further comprises a second circuit adapted to integrate the signal provided by the first circuit.
[0020] According to one embodiment, the circuit further comprises a third circuit configured to implement digital processing of the signal provided by the pulse counter.
[0021] Another embodiment provides a device suitable for processing an audio file, the device comprising the aforementioned circuit.
[0022] In one embodiment, the device further comprises a microphone.
[0023] In one embodiment, the device further comprises a neural network.
[0024] In one embodiment, the device is adapted to detect human voice. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] These and other features and advantages will be described in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, which include:
[0026] Figure 1 An example of an apparatus for processing an audio file is shown in block diagram form and very schematically;
[0027] Figure 2 Shows Figure 1 a circuit diagram of a pulse counter of the type indicated; and
[0028] Figure 3 Shown for illustration Figure 2 Timing diagram of the operation. DETAILED DESCRIPTION
[0029] In different drawings, similar features are represented by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, size, and material properties.
[0030] For clarity, only operations and elements that are useful for understanding the embodiments described herein are shown and described in detail.
[0031] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements can be coupled or connected through one or more other elements.
[0032] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers such as terms "above", "below", "higher", "lower", etc., or directional qualifiers such as "horizontal", "vertical", etc., reference is made to the direction shown in the figure.
[0033] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "order of magnitude" mean within 10%, and preferably within 5%.
[0034] Figure 1 A block diagram of an apparatus 100 for processing an audio file is shown.
[0035] According to one embodiment, the device 100 is adapted to obtain an audio file and then process it. To this end, according to an example, the device 100 comprises:
[0036] - Microphone 101 (microphone);
[0037] - a circuit 102 suitable for recognizing certain audio data (aMFCC); and
[0038] -Neural Network 103 (DNN).
[0039] According to a preferred embodiment, the device 100 is adapted to acquire and process audio files containing human voices. More specifically, the device 100 is adapted to detect human voices.
[0040] According to an example, the microphone 101 is an electronic device suitable for acquiring an audio file. The microphone 101 is configured to provide an original audio file.
[0041] According to an example, the circuit 102 is adapted to recognize certain audio data from a raw audio file provided by the microphone 101. In a preferred embodiment, the circuit 102 is adapted to word recognition.
[0042] According to one example, the circuit 102 includes:
[0043] - a circuit 1021 (AFE) suitable for implementing the function for extracting acoustic features;
[0044] - a circuit 1022 suitable for filtering the acoustic features extracted by the circuit 1021 (IAF);
[0045] - a pulse counter 1023 (ripple counter) according to one embodiment; and
[0046] - a circuit 1024 configured to carry out digital processing of the signal provided by said pulse counter 1023 (digital processing).
[0047] According to an example, the circuit 1021 (AFE) is adapted to extract acoustic features from a raw audio file provided by the microphone 101. More specifically, the circuit 1021 is adapted to extract certain properties from a raw audio file it receives from the microphone 101.
[0048] According to an example, circuit 1022 (IAF) is adapted to filter the acoustic features extracted by circuit 1021, and more specifically, to integrate the signal provided by circuit 1021. Circuit 1022 provides a signal containing pulses to counter 1023. According to an example, circuit 1022 is an analog-to-digital converter driven by software events.
[0049] According to one embodiment, the pulse counter 1023 is an asynchronous counter operating in the analog domain of the circuit 102 and is adapted to count the number of pulses of the signal provided by the circuit 1022 for a given duration. The given duration typically corresponds to a calculation window defined by the duration of the original audio file acquired by the microphone 101.
[0050] According to one embodiment, circuits 1021 and 1022 and counter 1023 are part of the analog domain of circuit 102 and are adapted to operate at low frequencies, ie, 30 kHz to 40 kHz, for example in the order of 32.726 kHz.
[0051] According to an example, the circuit 1024 is configured to implement digital processing of the signal provided by the pulse counter 1023. The circuit 1024 is part of the digital domain of the circuit 102.
[0052] According to an example, the neural network 103 is adapted to receive and process data from the circuit 1024. According to an example, the neural network 103 is a deep neural network.
[0053] Figure 2 About Figure 1 A circuit diagram of a pulse counter 200 of the type of pulse counter 1023 is described.
[0054] The pulse counter 200 is a pulse counter suitable for operating at a low frequency. To this end, the pulse counter is suitable for counting pulses asynchronously and for providing its counting result synchronously, ie synchronously with a clock signal.
[0055] According to one embodiment, the pulse counter 200 includes an asynchronous counter circuit 201 (COUNT) including an input terminal, an output terminal providing an AC signal, and an inverting reset terminal receiving a CA_NRST reset signal.
[0056] The pulse counter 200 also includes a flip-flop 202 (Sync), for example, for reading the value of the asynchronous counter 201. The flip-flop 202 includes an input terminal for receiving an AC signal from the asynchronous counter 201, and an output terminal for providing an output signal DI_CA from the pulse counter 200. The DI_CA signal represents the value of the pulse counter during the reading phase. The flip-flop 202 also includes an enable terminal and an inverting reset terminal for receiving a reset signal DO_NRSTA.
[0057] The pulse counter 200 further includes an inverter circuit 203 which receives the synchronization signal DO_CA_SYNC2 as input and whose output is connected (preferably connected) to the reset terminal of the asynchronous counter 201. Therefore, the rising edge of the DO_CA_SYNC2 synchronization signal resets the value of the asynchronous counter 201 to an initial value, such as zero.
[0058] The pulse counter 200 further comprises an AND logic gate 204 comprising a first input terminal receiving the pulse signal to be analyzed and a second inverting input terminal receiving the CA_SCREEN signal. The output terminal of the gate 204 is linked (preferably connected) to the input terminal of the asynchronous counter 201 .
[0059] According to one embodiment, the pulse counter 200 further includes a circuit 205 (pulse screening) configured to trigger a pulse counter read operation. The circuit 205 includes:
[0060] - a power supply terminal receiving a power supply voltage VDDD;
[0061] - Inverting reset terminal;
[0062] - an input terminal for receiving a DO_CA_SYNC1 synchronization signal; and
[0063] -Provides an output terminal for the CA_SCREEN signal.
[0064] The pulse counter 200 further includes an inverter circuit 206 which receives the DO_CA_SYNC1 synchronization signal as an input and whose output is connected (preferably connected) to an input of the flip-flop 202 .
[0065] The pulse counter 200 further includes an inverter circuit 207 which receives the DO_CA_SYNC2 synchronization signal as input and whose output is connected (preferably connected) to the inverting reset terminal of the circuit 205 .
[0066] The pulse counter 200 operates as follows. As long as the CA_SCREEN signal is in a low state, the asynchronous counter 201 counts the pulses present on the signal. The read phase occurs only when the CA_SCREEN signal is in a high state. Figure 3 The implementation of the phase of reading the value of the asynchronous counter 201 is described.
[0067] Figure 3 Four timing diagrams 301, 302, 303 and 304 are shown, showing Figure 2 Operation of the design shown.
[0068] More specifically, Figure 3 include:
[0069] - a timing diagram 301 showing the time evolution of the clock signal MCLK;
[0070] - a timing diagram 302 representing the time evolution of the DO_CA_SYNC1 synchronization signal;
[0071] - a timing diagram 303 representing the time evolution of the DO_CA_SYNC1 synchronization signal;
[0072] - a timing diagram 303 representing the time evolution of the DO_CA_SYNC2 synchronization signal; and
[0073] - A timing diagram 304 showing the time evolution of the CA_SCREEN signal.
[0074] The clock signal MCLK is used to synchronize the reading phase of the asynchronous counter 201 and the signals DO_CA_SYNC1 and DO_CA_SYNC2. According to an example, the clock signal is low frequency, ie a frequency of 30 kHz to 40 kHz, for example in the order of 32.726 kHz.
[0075] As previously mentioned, the read phase is executed when the CA_SCREEN signal is in the high state.
[0076] The rising edge of the CA_SCREEN signal is triggered by the rising edge of the DO_CA_SYNC1 synchronization signal, and the rising edge of the DO_CA_SYNC1 synchronization signal is triggered by the rising edge of the MCLK clock signal.
[0077] In addition, the rising edge of the DO_CA_SYNC1 synchronization signal deactivates the flip-flop 202 and thus fixes the data stored therein. The data corresponds to the value of the asynchronous counter 201. The falling edge of the DO_CA_SYNC1 synchronization signal is triggered by the falling edge of the MCLK clock signal. The falling edge of the synchronization signal triggers the reading of the asynchronous counter 201.
[0078] The falling edge of the CA_SCREEN signal is triggered by the rising edge of the DO_CA_SYNC2 synchronization signal. The rising edge of the DO_CA_SYNC2 synchronization signal also resets the asynchronous counter 201.
[0079] An advantage of this type of pulse counter is that it can be implemented by a circuit operating at a low frequency, even if the frequency of the received pulses is higher than the low frequency. In particular, this type of pulse counter can be integrated into a low-power, always-on part of an electronic device, which is usually called an ALWAYS ON part.
[0080] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments can be combined, and those skilled in the art will readily conceive of other variations.
[0081] Finally, based on the functional description provided above, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art.
Claims
1. A pulse counter (1023, 200), comprising an asynchronous counter (201) and a circuit (205) configured to trigger a read operation of a value of the asynchronous counter, the circuit (205) being synchronized by a clock signal.
2. The pulse counter according to claim 1, further comprising a flip-flop (202) adapted to receive the value from the asynchronous counter (201) during a reading phase.
3. The pulse counter according to claim 1 or 2, wherein: The read phase is triggered by the edge of the first synchronization signal (DO_CA_SYNC1).
4. The pulse counter according to claim 1 or 2, wherein: The read phase is stopped by the edge of the second synchronization signal (DO_CA_SYNC2).
5. The pulse counter according to claim 4, wherein: The edge of the second synchronization signal (DO_CA_SYNC2) also triggers a reset of the value of the asynchronous counter (201).
6. A circuit (102) adapted for recognizing words from an audio file, comprising a pulse counter (1023, 200) according to any one of claims 1 to 5.
7. The circuit according to claim 6, having a clock frequency of 30 kHz to 40 kHz.
8. The circuit according to claim 7, wherein: The clock frequency is equal to 32.728 kHz.
9. The circuit according to any one of claims 6 to 8, further comprising a first circuit (1021) adapted to implement an acoustic feature extraction function.
10. The circuit according to claim 9, further comprising a second circuit (1022) adapted to integrate the signal provided by the first circuit (1021).
11. The circuit according to any one of claims 6 to 8, further comprising a third circuit (1024) configured to implement digital processing of the signal provided by the pulse counter (1023, 200).
12. A device (100) adapted for processing an audio file, comprising a circuit (102) according to any one of claims 6 to 11.
13. The device according to claim 12, further comprising a microphone (101).
14. The device according to claim 12 or 13, further comprising a neural network (103).
15. A device according to claim 12 or 13, adapted to detect human voice.