Ciphertext data processing method and ciphertext calculation accelerator

Abstract

The embodiment of the invention discloses a ciphertext data processing method and a ciphertext calculation accelerator. The method comprises the steps of obtaining a plurality of first-level ciphertext calculation instructions and ciphertext data; performing serial analysis on the plurality of first-level ciphertext calculation instructions to obtain a plurality of second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction; and sending the plurality of second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to a plurality of processing nodes in parallel, so that the plurality of processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions. In this way, the ciphertext calculation instruction is divided into two stages, the first-stage ciphertext calculation instruction is subjected to serial analysis, and the second-stage ciphertext calculation instruction is subjected to parallel analysis.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a ciphertext data processing method and a ciphertext computing accelerator. Background Art

[0002] Ciphertext calculation refers to converting plaintext into ciphertext and then performing calculation in the ciphertext state. The final result of the ciphertext calculation is consistent with the result of the plaintext calculation. The ciphertext calculation instruction is the control source of the ciphertext calculation. Generally, multiple ciphertext calculation instructions are parsed in a serial manner. However, this method has the problem of too long operation path and low parsing efficiency. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present application hope to provide a ciphertext data processing method and a ciphertext computing accelerator, which solve the problems of long operation paths and low parsing efficiency in related technologies.

[0004] The technical solution of this application is implemented as follows: A ciphertext data processing method comprises: obtaining a plurality of first-level ciphertext calculation instructions and ciphertext data; performing serial parsing on the plurality of first-level ciphertext calculation instructions to obtain a plurality of second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction; and sending the plurality of second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to a plurality of processing nodes in parallel, so that the plurality of processing nodes processes the ciphertext data based on the received second-level ciphertext calculation instructions.

[0005] In the above scheme, obtaining multiple first-level ciphertext calculation instructions and ciphertext data includes: receiving multiple first-level ciphertext calculation instructions and ciphertext data sent by a host computer; and storing the multiple first-level ciphertext calculation instructions and ciphertext data in a memory.

[0006] In the above scheme, multiple first-level ciphertext computing instructions are serially parsed to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction, including: based on the instruction number of the first-level ciphertext computing instruction, each first-level ciphertext computing instruction in the multiple first-level ciphertext computing instructions is sent to the corresponding first-level instruction parsing unit; through the corresponding first-level instruction parsing unit, each first-level ciphertext computing instruction is parsed based on the instruction length of each first-level ciphertext computing instruction to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; the instruction time of the multiple first-level ciphertext computing instructions represents the parsing order of the multiple first-level ciphertext computing instructions.

[0007] In the above scheme, based on the instruction number of the first-level ciphertext calculation instruction, each first-level ciphertext calculation instruction in multiple first-level ciphertext calculation instructions is sent to the corresponding first-level instruction parsing unit, including: matching the instruction numbers of multiple first-level ciphertext calculation instructions with the unit numbers of multiple first-level instruction parsing units to obtain a first-level instruction parsing unit that matches each first-level ciphertext calculation instruction; and sending each first-level ciphertext calculation instruction to the matching first-level instruction parsing unit.

[0008] In the above scheme, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, including: determining the length of time that each first-level ciphertext calculation instruction has been parsed; when the parsed length matches the instruction time of each first-level ciphertext calculation instruction, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes.

[0009] In the above scheme, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, including: sending multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to the second-level instruction parsing unit corresponding to each first-level ciphertext calculation instruction; the second-level instruction parsing unit has a one-to-one correspondence with the first-level instruction parsing unit; through the corresponding second-level instruction parsing unit, based on the instruction numbers and instruction types of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes.

[0010] In the above scheme, based on the instruction numbers and instruction types of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, including: based on the instruction types of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, so that each processing node matches the instruction number of the received second-level ciphertext calculation instruction based on the node number of each processing node; when the node number of each processing node successfully matches the instruction number of the received second-level ciphertext calculation instruction, the instruction parameters of the received second-level ciphertext calculation instruction are sent to each processing node.

[0011] In the above scheme, the format of the first-level ciphertext calculation instruction includes at least: the instruction number of the first-level ciphertext calculation instruction, the instruction length, at least one second-level instruction, and the instruction time; the format of the second-level ciphertext calculation instruction includes at least: the instruction number of the second-level ciphertext calculation instruction, the instruction type, and the instruction parameters.

[0012] A ciphertext computing accelerator comprises: a control unit, a plurality of first-level instruction parsing units, and a plurality of second-level instruction parsing units; the plurality of first-level instruction parsing units are connected in series; the plurality of first-level instruction parsing units have a one-to-one correspondence with the plurality of second-level instruction parsing units; the plurality of second-level instruction parsing units comprise: a plurality of processing nodes connected in parallel; a control unit, used for sending a plurality of first-level ciphertext computing instructions and ciphertext data; a plurality of first-level instruction parsing units, used for serially parsing a plurality of first-level ciphertext computing instructions to obtain a plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; a plurality of second-level instruction parsing units, used for sending a plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction in parallel to a plurality of processing nodes, so that the plurality of processing nodes process the ciphertext data based on the received second-level ciphertext computing instructions.

[0013] In the above scheme, the ciphertext computing accelerator also includes: a storage unit; the storage unit is connected to multiple processing units corresponding to the first secondary instruction parsing unit; the storage unit is used to store data in the ciphertext data processing method during the processing process.

[0014] A computer-readable storage medium stores a computer program, which implements part or all of the steps in the above method when executed by a processor.

[0015] A computer program includes computer-readable codes. When the computer-readable codes are executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0016] A computer program product comprises a non-transitory computer-readable storage medium storing a computer program, wherein when the computer program is read and executed by a computer, part or all of the steps in the above method are implemented.

[0017] The ciphertext data processing method and ciphertext computing accelerator provided by the embodiment of the present application obtain multiple first-level ciphertext computing instructions and ciphertext data; perform serial parsing on multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; send multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction to multiple processing nodes in parallel, so that multiple processing nodes process the ciphertext data based on the received second-level ciphertext computing instructions. In this way, the ciphertext computing instructions are divided into two levels, the first-level ciphertext computing instructions are serially parsed, and the second-level ciphertext computing instructions are parallel parsed. Compared with the pure parallel parsing method, this hierarchical parsing method of ciphertext computing instructions is simpler in wiring, and there will be no congestion during processing; compared with the pure serial parsing method, the instruction parsing efficiency is higher and the instruction parsing time is greatly saved. For example: in a ciphertext computing task with 4 groups of first-level ciphertext computing instructions, pure serial instruction parsing requires 13 clock cycles, and the hierarchical parsing method provided by the present application only requires 4 clock cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the overall flow of ciphertext calculation involved in an instruction method provided in an embodiment of the present application; Figure 2 A schematic diagram of a method for processing encrypted data provided in an embodiment of the present application Figure 1 ; Figure 3 A schematic diagram of an instruction format in a ciphertext data processing method provided in an embodiment of the present application; Figure 4 A schematic diagram of a method for processing encrypted data provided in an embodiment of the present application Figure 2 ; Figure 5 A schematic diagram of the structure of a ciphertext computing accelerator provided in an embodiment of the present application; Figure 6 A schematic diagram of a method for processing encrypted data provided in an embodiment of the present application Figure 3 ; Figure 7 A schematic diagram of the effect of a ciphertext data processing method provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a ciphertext data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0020] It should be understood that the "embodiments of the present application" or "the aforementioned embodiments" mentioned throughout the specification mean that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in the embodiments of the present application" or "in the aforementioned embodiments" appearing throughout the specification may not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0021] Unless otherwise specified, the electronic device performs any step in the embodiments of the present application, and the processor of the electronic device may perform the step. It is also worth noting that the embodiments of the present application do not limit the order in which the electronic device performs the following steps. In addition, the methods used to process data in different embodiments may be the same method or different methods. It should also be noted that any step in the embodiments of the present application can be independently executed by the electronic device, that is, when the electronic device executes any step in the following embodiments, it may not rely on the execution of other steps.

[0022] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In order to better understand the ciphertext data processing method provided in the embodiment of the present application, the relevant knowledge involved in the present application is first explained below.

[0024] The main advantage of ciphertext computing is that data always remains in ciphertext during cross-domain processes (such as data storage, data transmission, data extremism, etc.). Even if the data is captured by others, only the ciphertext fragments of the data are captured and cannot be restored to plaintext. At the same time, ciphertext computing can ensure that the ciphertext calculation results are consistent with the plaintext calculation results, thereby ensuring that the business value of the data is not affected.

[0025] Compared with plaintext calculation, the amount of data in ciphertext calculation increases by hundreds of times. In order to increase the speed of ciphertext calculation, a dedicated ciphertext calculation accelerator is used to accelerate the ciphertext calculation. Figure 1 As shown, the plaintext data is encrypted to obtain the ciphertext data; the ciphertext data is transmitted to the ciphertext calculation accelerator for processing to obtain the ciphertext calculation result; the ciphertext calculation result is decrypted to obtain the plaintext calculation result.

[0026] A ciphertext computing accelerator is a complex circuit that accelerates ciphertext algorithms. This circuit usually consists of five parts: a ciphertext computing control unit (Ciphertext Control Unit, CCU), a ciphertext computing routing unit (Ciphertext Routing Unit, CRU), a ciphertext data moving unit (Ciphertext Datamove Unit, CDU), a ciphertext data storage unit (Ciphertext Memory Unit, CMU) and a ciphertext computing operator unit (Ciphertext Operator Unit, COU).

[0027] Among them, the ciphertext calculation control unit is used to match and parse the ciphertext calculation instructions. The ciphertext calculation routing unit is used to match according to the number of the ciphertext calculation instruction. The ciphertext data transport unit is used to transport the ciphertext data from one address to another address. The ciphertext data storage unit is used to store the ciphertext data. The ciphertext calculation operator unit is used to calculate the ciphertext data.

[0028] As the control source of ciphertext computing, ciphertext computing instructions are closely related to the various components of the ciphertext computing accelerator. The parsing of ciphertext computing instructions plays a vital role in the ciphertext computing accelerator.

[0029] The embodiment of the present application provides a method for processing ciphertext data, which can be applied to BFV and CKKS fully homomorphic ciphertext computing accelerators. Among them, the BFV (Brakerski-Fan-Vercauteren) algorithm is a method for implementing fully homomorphic encryption, which allows calculations to be performed directly on encrypted data without first decrypting the data. The CKKS (Cheon-Kim-Kim-Song) algorithm is an approximate computing homomorphic encryption algorithm, and its core is to regard the encryption noise as part of the approximate computing error, and the decrypted result is directly regarded as an approximation of the original message. Figure 2 As shown, the method includes the following steps 201 to 203: Step 201: Obtain multiple first-level ciphertext calculation instructions and ciphertext data.

[0030] Among them, the format of the first-level ciphertext calculation instruction includes at least: the instruction number of the first-level ciphertext calculation instruction, the instruction length, at least one second-level instruction, and the instruction time; the format of the second-level ciphertext calculation instruction includes at least: the instruction number of the second-level ciphertext calculation instruction, the instruction type, and the instruction parameter.

[0031] Level 1 ciphertext calculation instructions refer to a group of instructions that include a complete ciphertext calculation process, which is used to globally control the overall process of ciphertext calculation. For example: Level 1 ciphertext calculation instructions may include but are not limited to: data handling instructions, operator calculation instructions, data storage instructions and other different types of instructions. Level 1 ciphertext calculation instructions can be set according to the specific operation of ciphertext calculation, that is, the instruction length of level 1 ciphertext calculation instructions is variable. The number of level 2 ciphertext calculation instructions contained in the level 1 ciphertext calculation instructions is determined by the hardware performance of the ciphertext calculation accelerator, that is, this application does not limit the upper limit of the number of level 2 ciphertext calculation instructions.

[0032] The first-level ciphertext calculation instruction includes at least one second-level ciphertext calculation instruction. The second-level ciphertext calculation instruction refers to the specific operation instruction in the ciphertext calculation, and the length of the second-level ciphertext calculation instruction is fixed. Figure 3 As shown, the format of the first-level ciphertext computing instruction may include: a first-level instruction number (the instruction number of the first-level ciphertext computing instruction), an instruction length, a second-level instruction 0, a second-level instruction 1, ..., a second-level instruction n, and an instruction time. The format of the second-level ciphertext computing instruction may include: a second-level instruction number (the instruction number of the second-level ciphertext computing instruction), an instruction type, and an instruction parameter.

[0033] As shown in Table 1 below, the operation types of ciphertext computing instructions may include: data transfer, data cache, operator calculation, etc. The first-level instructions may include: D2D representing data transfer from one location in memory to another, D2M representing data transfer from memory to cache, M2D representing data transfer from cache to memory, M2M representing data transfer between different caches, M2O representing data transfer between cache and computing unit, O2M representing data transfer between different computing units, O2O representing data transfer between different computing units, NTT representing number theory change operator, MOD representing modular multiplication and addition operator. The second-level instructions corresponding to the first-level instruction D2D are: CDUr, CRUm, ..., CRUn, CDUw; the second-level instructions corresponding to the first-level instruction D2M are: CDUr, CRUm, ..., CRUn, CMUw; the second-level instructions corresponding to the first-level instruction M2D are: CMUr, CRUm, ..., CRUn, CDUw; the second-level instructions corresponding to the first-level instruction M2M are: CMUr, CRUm, ..., CRUn, CMUw; The second-level instructions corresponding to the first-level instruction M2O are: CMUr, CRUm, ..., CRUn, COUw; the second-level instructions corresponding to the first-level instruction O2M are: COUr, CRUm, ..., CRUn, CMUw; the second-level instructions corresponding to the first-level instruction O2O are: COUr, CRUm, ..., CRUn, COUw; the second-level instructions corresponding to the first-level instruction NTT are: COUm; the second-level instruction corresponding to the first-level instruction MOD is: COUn.

[0034] Table 1

[0035] In some implementations, the specific implementation of step 201 may be: the host computer sends the plaintext data and the first-level ciphertext calculation instruction to the ciphertext calculation accelerator through the peripheral component interconnect express (PCIE) interface, and the ciphertext calculation accelerator performs instruction parsing, data transfer and calculation processes to achieve hardware acceleration of the ciphertext algorithm. The host computer refers to a computer system that can directly issue control commands.

[0036] Step 202: Serially parse the multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction.

[0037] Since there are instruction conflicts between the first-level ciphertext calculation instructions, the first-level ciphertext calculation instructions are serially parsed in CC1U. CC1U is a ciphertext calculation control unit used to match and parse the first-level ciphertext calculation instructions.

[0038] In some implementations, the specific implementation method of step 202 can be: serially parse multiple first-level ciphertext computing instructions based on the instruction number and instruction length of the first-level ciphertext computing instruction to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction.

[0039] Step 203: Send multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel, so that the multiple processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions.

[0040] A processing node refers to a node that performs calculations on ciphertext data. A processing node may be a ciphertext calculation operator unit COU, a ciphertext data storage unit CMU, or a ciphertext data handling unit CDU, etc.

[0041] Since there will be no conflict between the second-level instructions in each processing node, the second-level ciphertext calculation instructions are parsed in parallel in the CRU. The CRU is also called CC2U, which is a ciphertext calculation control unit used to match and parse the second-level ciphertext calculation instructions.

[0042] In some embodiments, the specific implementation method of step 203 can be: based on the instruction type of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, so that the multiple processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions.

[0043] It should be noted that when multiple processing nodes receive the second-level ciphertext calculation instructions, they can process the ciphertext data in parallel based on the received second-level ciphertext calculation instructions, or they can process the ciphertext data based on the received second-level ciphertext calculation instructions according to their own operating states. That is, this application does not limit the time for multiple processing nodes to process ciphertext data.

[0044] The ciphertext data processing method provided in the embodiment of the present application obtains multiple first-level ciphertext calculation instructions and ciphertext data; performs serial parsing on multiple first-level ciphertext calculation instructions to obtain multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction; and sends multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel, so that multiple processing nodes process the ciphertext data in parallel based on the received second-level ciphertext calculation instructions. In this way, the ciphertext calculation instructions are divided into two levels, the first-level ciphertext calculation instructions are serially parsed, and the second-level ciphertext calculation instructions are parallel parsed. Compared with the pure parallel parsing method, this hierarchical parsing method of ciphertext calculation instructions is simpler in wiring, and there will be no congestion during processing; compared with the pure serial parsing method, the instruction parsing is more efficient and greatly saves the instruction parsing time. For example: in a ciphertext calculation task with 4 groups of first-level ciphertext calculation instructions, the pure serial instruction parsing requires 13 clock cycles, and the hierarchical parsing method provided by the present application only requires 4 clock cycles.

[0045] Based on the above embodiments, the present application provides a method for processing ciphertext data, which is applied to a ciphertext computing accelerator. Figure 4 As shown, the method includes the following steps 401 to 406: Step 401: Receive multiple first-level ciphertext calculation instructions and ciphertext data sent by a host computer.

[0046] In some implementations, the specific implementation of step 401 may be: the host computer encrypts the plaintext data to be processed to obtain ciphertext data; and sends the ciphertext data and the first-level ciphertext calculation instruction to the ciphertext calculation accelerator. The plaintext data may refer to text data, passwords, image data, audio data, etc.

[0047] Step 402: Store the multiple first-level ciphertext calculation instructions and the ciphertext data in a memory.

[0048] The memory may refer to Double Data Rate SDRAM (DDR).

[0049] Step 403: Based on the instruction number of the first-level ciphertext calculation instruction, each first-level ciphertext calculation instruction in the multiple first-level ciphertext calculation instructions is sent to a corresponding first-level instruction parsing unit.

[0050] The instruction number of a certain first-level ciphertext computing instruction is used to uniquely identify the first-level ciphertext computing instruction. The first-level instruction parsing unit refers to a ciphertext computing control unit for matching and parsing the first-level ciphertext computing instruction, which can be represented as CC1U.

[0051] In some implementations, step 403 may be implemented by steps 4031 to 4032 as follows: Step 4031: Match the instruction numbers of the multiple first-level ciphertext computing instructions with the unit numbers of the multiple first-level instruction parsing units to obtain a first-level instruction parsing unit that matches each of the first-level ciphertext computing instructions.

[0052] The unit number of a first-level instruction parsing unit is used to uniquely identify the first-level instruction parsing unit. The first-level instruction parsing unit that matches each first-level ciphertext computing instruction refers to the first-level instruction parsing unit that parses each first-level ciphertext computing instruction, also referred to as the first-level instruction parsing unit corresponding to each first-level ciphertext computing instruction.

[0053] The instruction number of the first-level ciphertext computing instruction corresponds to the first-level instruction parsing unit. In some embodiments, the specific implementation of step 4031 may be: the instruction number of the first-level ciphertext computing instruction and the unit number of the first-level instruction parsing unit may adopt the same encoding method; in this way, the first-level instruction parsing unit that matches each first-level ciphertext computing instruction is, that is, the first-level instruction parsing unit whose unit number is the same as the instruction number of each first-level ciphertext computing instruction.

[0054] Alternatively, in some implementations, the specific implementation of step 4031 may also be: the instruction number of the first-level ciphertext calculation instruction and the unit number of the first-level instruction parsing unit may be encoded in different ways, but there is a certain correspondence between the two. For example, the correspondence may be a multiple relationship, in which case the first-level instruction parsing unit that matches each first-level ciphertext calculation instruction is, that is, a first-level instruction parsing unit whose unit number has a multiple relationship with the instruction number of each first-level ciphertext calculation instruction.

[0055] Step 4032: Send each of the first-level ciphertext calculation instructions to the matching first-level instruction parsing unit.

[0056] Step 404: parse each first-level ciphertext computing instruction based on the instruction length of each first-level ciphertext computing instruction through the corresponding first-level instruction parsing unit to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction.

[0057] The instruction time of the plurality of first-level ciphertext computing instructions represents the parsing order of the plurality of first-level ciphertext computing instructions.

[0058] The instruction length of the first-level ciphertext calculation instruction refers to the number of second-level ciphertext calculation instructions included in the first-level ciphertext calculation instruction.

[0059] In some implementations, step 404 may be specifically implemented by: using a corresponding first-level instruction parsing unit, parsing each first-level ciphertext computing instruction according to the instruction length of each first-level ciphertext computing instruction to obtain multiple second-level ciphertext computing instructions contained in each first-level ciphertext computing instruction.

[0060] Step 405: Determine the length of time that each first-level ciphertext computing instruction has been parsed.

[0061] In some implementations, the specific implementation of step 405 may be: using a time counter to record the length of time each first-level ciphertext calculation instruction has been parsed.

[0062] Step 406: When the parsed duration matches the instruction time of each first-level ciphertext calculation instruction, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, so that the multiple processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions.

[0063] The instruction time of a first-level ciphertext calculation instruction may refer to the time that a single first-level ciphertext calculation instruction can be parsed; for example, the instruction time of a first-level ciphertext calculation instruction may be 10 beats. Alternatively, the instruction time of a first-level ciphertext calculation instruction clearly records the time when the parsing starts. In a feasible implementation, when the first-level instruction parsing unit starts to parse the first-level ciphertext calculation instruction, the time timer starts counting from 0. When the time timer reaches 10 beats, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes; at this time, the time timer is cleared to 0.

[0064] In some implementations, the specific implementation method of "sending the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel" in step 406 can be: based on the instruction type and instruction number of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, sending the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel In some implementations, step 406 may be implemented by steps 4061 to 4062 as follows: Step 4061: Send the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to the second-level instruction parsing unit corresponding to each first-level ciphertext calculation instruction.

[0065] Among them, the secondary instruction parsing unit and the primary instruction parsing unit have a one-to-one correspondence.

[0066] The secondary instruction parsing unit refers to a ciphertext computing control unit used to match and parse secondary ciphertext computing instructions, which can be represented as CC2U.

[0067] Step 4062: Through the corresponding secondary instruction parsing unit, based on the instruction numbers and instruction types of the multiple secondary ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes.

[0068] In some embodiments, the specific implementation method of step 4062 may be: through the corresponding secondary instruction parsing unit, based on the instruction numbers and instruction types of the multiple secondary ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, determine the respective processing nodes of the multiple secondary ciphertext calculation instructions, and send the multiple secondary ciphertext calculation instructions to the corresponding processing nodes in parallel.

[0069] In some embodiments, the specific implementation method of step 4062 may be: based on the instruction type of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, so that each processing node matches the instruction number of the received second-level ciphertext calculation instruction based on the node number of each processing node and the instruction number of the received second-level ciphertext calculation instruction; when the node number of each processing node successfully matches the instruction number of the received second-level ciphertext calculation instruction, the instruction parameters of the received second-level ciphertext calculation instruction are sent to each processing node.

[0070] Instruction parameters refer to the parameters required for the execution of the secondary ciphertext calculation instructions. For example, the instruction parameters of the ciphertext data transfer unit CDU may include but are not limited to: the number of transfers, the transfer address, the bus parameters, etc. The instruction parameters of the ciphertext data storage unit CMU may include but are not limited to: the storage address, the storage type, etc. The instruction parameters of the ciphertext calculation operator unit COU may include but are not limited to: modular multiplication, modular addition, etc.

[0071] It should be noted that, for the description of the same steps and the same contents in this embodiment as those in other embodiments, reference can be made to the description in other embodiments and will not be repeated here.

[0072] The ciphertext data processing method provided in the embodiment of the present application divides the ciphertext calculation instructions into two levels, the first-level ciphertext calculation instructions are serially parsed, and the second-level ciphertext calculation instructions are parallelly parsed. Compared with the pure parallel parsing method, this hierarchical parsing method of ciphertext calculation instructions is simpler in wiring, and there will be no congestion during processing; compared with the pure serial parsing method, the instruction parsing efficiency is higher and the instruction parsing time is greatly saved. For example: in a ciphertext calculation task with 4 groups of first-level ciphertext calculation instructions, pure serial instruction parsing requires 13 clock cycles, while the hierarchical parsing method provided by the present application only requires 4 clock cycles.

[0073] like Figure 5 As shown, an embodiment of the present application provides a ciphertext computing accelerator, the ciphertext computing accelerator comprising: a control unit 51, a plurality of first-level instruction parsing units 52, and a plurality of second-level instruction parsing units 53; The plurality of primary instruction parsing units 52 are connected in series; the plurality of primary instruction parsing units 52 and the plurality of secondary instruction parsing units 53 have a one-to-one correspondence; The plurality of secondary instruction parsing units 53 include: a plurality of processing nodes 54 connected in parallel; The control unit 51 is used to send multiple first-level ciphertext calculation instructions and ciphertext data; The multiple first-level instruction parsing units 52 are used to serially parse the multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; The multiple secondary instruction parsing units 53 are used to send multiple secondary ciphertext calculation instructions corresponding to each primary ciphertext calculation instruction to multiple processing nodes in parallel, so that the multiple processing nodes process the ciphertext data based on the received secondary ciphertext calculation instructions.

[0074] The control unit 51 may refer to a central processing unit (CPU). The primary instruction parsing unit 52 may be represented as CC1U, and the secondary instruction parsing unit 53 may be represented as CC2U / CRU. The processing node 54 may include a ciphertext data handling unit CDU, a ciphertext data storage unit CMU, a ciphertext calculation operator unit COU, etc.

[0075] In some embodiments, the ciphertext computing accelerator further includes: a storage unit 55; the storage unit 55 is connected to a plurality of processing nodes 54 corresponding to the first secondary instruction parsing unit; The storage unit 55 is used to store data in the process of the ciphertext data processing method. For example, the storage unit 55 may be a DDR.

[0076] like Figure 5 As shown, the storage unit 55 and the first CRU may include two processing nodes: the ciphertext data handling unit CDU and the ciphertext data storage unit CMU; the first CRU and the second CRU may include two processing nodes: the ciphertext data storage unit CMU and the ciphertext calculation operator unit COU; the second CRU and the third CRU may include two processing nodes: the ciphertext data storage unit CMU and the ciphertext calculation operator unit COU; the third CRU and the fourth CRU may include two processing nodes: the ciphertext data storage unit CMU and the ciphertext calculation operator unit COU; and the fourth CRU may also include one processing node: the ciphertext calculation operator unit COU.

[0077] The following describes the application of the ciphertext data processing method provided in the embodiment of the present application in a practical scenario.

[0078] 1.1 Product side Compared with plaintext calculation, the amount of ciphertext calculation increases by hundreds of times. In order to improve the speed of ciphertext calculation, this application adopts a dedicated ciphertext calculation accelerator to accelerate the ciphertext calculation, which can perform hardware acceleration of ciphertext calculation hundreds of times.

[0079] As above Figure 1As shown, the present application has been applied in BFV and CKKS fully homomorphic ciphertext computing accelerators. The host computer (HOST) sends the fully homomorphic ciphertext data and first-level ciphertext computing instructions to the ciphertext computing accelerator through the PCIE interface, and the ciphertext computing accelerator performs instruction parsing, transporting, and operator calculation to achieve hardware acceleration of ciphertext computing.

[0080] The structure of the ciphertext computing accelerator is as follows: Figure 5 As shown, its working process is as follows: the upper computer generates ciphertext calculation data and instructions and stores them in the storage unit 55 (memory); the control unit 51 sends the first-level ciphertext calculation instructions to the first-level instruction parsing unit CC1U, and CC1U serially parses the first-level ciphertext calculation instructions to generate second-level ciphertext calculation instructions and sends them to each node in parallel through CRU. The CC2U in the CRU can parse in parallel the number of second-level ciphertext calculation instructions specified in advance; the processing nodes such as CDU, CMU, COU, etc. perform corresponding hardware operations based on the received second-level ciphertext calculation instructions.

[0081] 1.2 Technical side The classification method of ciphertext computing instructions is shown in Table 1: the first-level instructions are a group of instructions that include a complete operation process, such as data transfer, operator calculation, data storage and other instructions; the second-level instructions are the operation instructions of each node within the first-level instructions.

[0082] Due to the conflict between the first-level instructions, the first-level instructions are serially parsed in CC1U, and the instruction time is used to control the output time of the parsing results; due to the global control of the first-level instructions, there will be no conflict between the second-level instructions in each node, and the second-level instructions are parsed in parallel in CRU (CC2U). The two-level instruction format is as follows: Figure 3 As shown, the length of the first-level instruction is variable and includes at least one second-level instruction. The maximum number of second-level instructions included is determined by the hardware performance, and the length of the second-level instruction is fixed.

[0083] The two-level instruction parsing process is as follows Figure 6 As shown, it includes the following steps 601 to 610: Step 601: The CPU issues a first-level instruction.

[0084] Step 602: CC1U receives the first-level instruction and performs number matching.

[0085] If the number matching fails, step 603 is executed; if the number matching succeeds, step 604 is executed.

[0086] Step 603: CC1U forwards to the next CC1U.

[0087] Step 604, CC1U parses the instruction length, and parses out all the secondary instructions according to the instruction length. During the parsing, the instruction time counter starts counting from 0.

[0088] Step 605, CC1U analyzes the instruction time, and sends a secondary instruction when the time timer counts to the preset time, and the time counter is cleared to 0.

[0089] The preset time can be the time for parsing a single first-level instruction, such as 10 beats, or it can be the time from the start time point of parsing to the end time point of parsing a first-level instruction.

[0090] Step 606: CC2U receives and parses all the secondary instructions in parallel and sends the secondary instructions to each node according to the instruction type.

[0091] Step 607: Each node performs secondary instruction number matching.

[0092] If the number matching fails, execute step 608; if the number matching succeeds, execute step 609.

[0093] Step 608: This node does not parse the secondary instruction.

[0094] Step 609: Send instruction parameters to this node.

[0095] Step 610: After all nodes are matched, the parsing of the first-level instruction is completed.

[0096] The beneficial effects of the technical solution of the present application include at least: (1) Compared with a pure parallel parsing solution, the wiring of the present application is simpler and the local wiring of the CCU will not be congested. (2) Compared with a pure serial parsing solution, the parsing of the present application is more efficient and saves instruction parsing time. Figure 7 As shown, the ciphertext calculation task includes four groups of first-level instructions. These four groups of first-level instructions are: the first group of first-level instructions: CDU0r, CDU0, CDU0w, the second group of first-level instructions: COU2r, CRU1, CRU2, CDU3w, the third group of first-level instructions: CMU2r, CRU3, CRU4, CRU5, COU1w, and the fourth group of first-level instructions: COU2NT. Figure 7 It can be seen that pure serial instruction parsing requires 13 clock cycles, while the hierarchical parsing method proposed in this application only requires 4 clock cycles.

[0097] Based on the foregoing embodiments, an embodiment of the present application provides a ciphertext data processing device, which includes the units included and the modules included in the units, and can be implemented by a processor in a computer device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA), etc.

[0098] Figure 8 A schematic diagram of the structure of a ciphertext data processing device provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the ciphertext data processing device 800 includes: an acquisition module 810, a parsing module 820 and a sending module 830, wherein: The acquisition module 810 is configured to obtain a plurality of first-level ciphertext calculation instructions and ciphertext data; The parsing module 820 is configured to perform serial parsing on the plurality of first-level ciphertext computing instructions to obtain a plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; The sending module 830 is configured to send multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel, so that the multiple processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions.

[0099] In some embodiments, the acquisition module 810 is further configured to: receive multiple first-level ciphertext calculation instructions and ciphertext data sent by the host computer; and store the multiple first-level ciphertext calculation instructions and ciphertext data in the memory.

[0100] In some embodiments, the parsing module 820 is further configured to: send each of the multiple first-level ciphertext calculation instructions to a corresponding first-level instruction parsing unit based on the instruction number of the first-level ciphertext calculation instruction; parse each first-level ciphertext calculation instruction based on the instruction length of each first-level ciphertext calculation instruction through the corresponding first-level instruction parsing unit to obtain multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction; the instruction time of the multiple first-level ciphertext calculation instructions represents the parsing order of the multiple first-level ciphertext calculation instructions.

[0101] In some embodiments, the parsing module 820 is further configured to: match the instruction numbers of multiple first-level ciphertext computing instructions with the unit numbers of multiple first-level instruction parsing units to obtain a first-level instruction parsing unit that matches each first-level ciphertext computing instruction; and send each first-level ciphertext computing instruction to the matching first-level instruction parsing unit.

[0102] In some embodiments, the sending module 830 is further configured to: determine the length of time each first-level ciphertext calculation instruction has been parsed; and when the parsed length matches the instruction time of each first-level ciphertext calculation instruction, send multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel.

[0103] In some embodiments, the sending module 830 is further configured to: send multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to the second-level instruction parsing unit corresponding to each first-level ciphertext calculation instruction; the second-level instruction parsing unit has a one-to-one correspondence with the first-level instruction parsing unit; through the corresponding second-level instruction parsing unit, based on the instruction number and instruction type of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, send the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction in parallel to multiple processing nodes.

[0104] In some embodiments, the sending module 830 is further configured to: based on the instruction type of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, send the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction in parallel to multiple processing nodes, so that each processing node matches the instruction number of the received second-level ciphertext calculation instruction based on the node number of each processing node and the instruction number of the received second-level ciphertext calculation instruction; when the node number of each processing node successfully matches the instruction number of the received second-level ciphertext calculation instruction, send the instruction parameters of the received second-level ciphertext calculation instruction to each processing node.

[0105] In some embodiments, the sending module 830 is further configured such that: the format of the first-level ciphertext calculation instruction includes at least: the instruction number of the first-level ciphertext calculation instruction, the instruction length, at least one second-level instruction, and the instruction time; the format of the second-level ciphertext calculation instruction includes at least: the instruction number of the second-level ciphertext calculation instruction, the instruction type, and the instruction parameters.

[0106] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. In some embodiments, the functions or modules included in the device provided in the embodiment of the present application can be used to execute the method described in the above method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0107] It should be noted that in the embodiments of the present application, if the above-mentioned ciphertext data processing method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly reflected in the form of a software product that contributes to the relevant technology. The software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific hardware, software or firmware, or any combination of hardware, software, and firmware.

[0108] The embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, some or all of the steps in the above method are implemented. The computer-readable storage medium can be transient or non-transient.

[0109] An embodiment of the present application provides a computer program, including a computer-readable code. When the computer-readable code is run in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0110] The embodiment of the present application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, some or all of the steps in the above method are implemented. The computer program product can be implemented in hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0111] It should be noted here that the description of the various embodiments above tends to emphasize the differences between the various embodiments, and the same or similar aspects can be referenced to each other. The description of the above device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the embodiments of the device, storage medium, computer program and computer program product of this application, please refer to the description of the method embodiment of this application for understanding.

[0112] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. The serial numbers of the embodiments of the present application mentioned above are for description only and do not represent the advantages and disadvantages of the embodiments.

[0113] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0114] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0115] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0116] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0117] A person skilled in the art can understand that: all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, read-only memories (ROM), magnetic disks or optical disks.

[0118] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0119] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for processing ciphertext data, characterized in that: The ciphertext data processing method comprises: Obtain multiple first-level ciphertext computing instructions and ciphertext data; Serially parsing the multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; The multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes, so that the multiple processing nodes process the ciphertext data based on the received second-level ciphertext calculation instructions.

2. The method for processing ciphertext data according to claim 1, characterized in that: The obtaining of a plurality of first-level ciphertext computing instructions and ciphertext data includes: Receive multiple first-level ciphertext calculation instructions and ciphertext data sent by the host computer; The multiple first-level ciphertext calculation instructions and the ciphertext data are stored in a memory.

3. The ciphertext data processing method according to claim 1 or 2, characterized in that: The serially parsing the multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction includes: Based on the instruction number of the first-level ciphertext calculation instruction, sending each first-level ciphertext calculation instruction of the plurality of first-level ciphertext calculation instructions to a corresponding first-level instruction parsing unit; Through the corresponding first-level instruction parsing unit, each first-level ciphertext computing instruction is parsed based on the instruction length of each first-level ciphertext computing instruction to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; the instruction time of the multiple first-level ciphertext computing instructions represents the parsing order of the multiple first-level ciphertext computing instructions.

4. The method for processing ciphertext data according to claim 3, characterized in that: The step of sending each of the plurality of first-level ciphertext computing instructions to a corresponding first-level instruction parsing unit based on the instruction number of the first-level ciphertext computing instruction comprises: Matching the instruction numbers of the plurality of first-level ciphertext computing instructions with the unit numbers of the plurality of first-level instruction parsing units to obtain a first-level instruction parsing unit matching each of the first-level ciphertext computing instructions; Each of the first-level ciphertext calculation instructions is sent to the matching first-level instruction parsing unit.

5. The ciphertext data processing method according to claim 1, 2, or 4, characterized in that: The sending the plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction to the plurality of processing nodes in parallel includes: Determining the length of time each of the first-level ciphertext computing instructions has been parsed; In a case where the parsed duration matches the instruction time of each first-level ciphertext calculation instruction, multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction are sent in parallel to multiple processing nodes.

6. The method for processing ciphertext data according to claim 5, characterized in that: The sending the plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction to the plurality of processing nodes in parallel includes: Sending the plurality of second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction to the second-level instruction parsing unit corresponding to each first-level ciphertext computing instruction; the second-level instruction parsing unit has a one-to-one correspondence with the first-level instruction parsing unit; Through the corresponding secondary instruction parsing unit, based on the instruction numbers and instruction types of the multiple secondary ciphertext calculation instructions corresponding to each primary ciphertext calculation instruction, the multiple secondary ciphertext calculation instructions corresponding to each primary ciphertext calculation instruction are sent in parallel to multiple processing nodes.

7. The method for processing ciphertext data according to claim 6, characterized in that: The method of sending the multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction in parallel to multiple processing nodes based on the instruction numbers and instruction types of the multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction includes: Based on the instruction types of the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction, sending the multiple second-level ciphertext calculation instructions corresponding to each first-level ciphertext calculation instruction to multiple processing nodes in parallel, so that each processing node performs matching based on the node number of each processing node and the instruction number of the received second-level ciphertext calculation instruction; In the case where the node number of each processing node successfully matches the instruction number of the received second-level ciphertext calculation instruction, the instruction parameters of the received second-level ciphertext calculation instruction are sent to each processing node.

8. The method for processing ciphertext data according to claim 1, characterized in that: The format of the first-level ciphertext computing instruction at least includes: the instruction number of the first-level ciphertext computing instruction, the instruction length, at least one second-level instruction, and the instruction time; The format of the secondary ciphertext calculation instruction at least includes: an instruction number, an instruction type, and instruction parameters of the secondary ciphertext calculation instruction.

9. A ciphertext computing accelerator, characterized in that: The ciphertext computing accelerator comprises: a control unit, a plurality of first-level instruction parsing units, and a plurality of second-level instruction parsing units; The plurality of first-level instruction parsing units are connected in series; the plurality of first-level instruction parsing units have a one-to-one correspondence with the plurality of second-level instruction parsing units; The plurality of secondary instruction parsing units include: a plurality of processing nodes connected in parallel; The control unit is used to send multiple first-level ciphertext calculation instructions and ciphertext data; The multiple first-level instruction parsing units are used to serially parse the multiple first-level ciphertext computing instructions to obtain multiple second-level ciphertext computing instructions corresponding to each first-level ciphertext computing instruction; The multiple secondary instruction parsing units are used to send multiple secondary ciphertext calculation instructions corresponding to each primary ciphertext calculation instruction to multiple processing nodes in parallel, so that the multiple processing nodes process the ciphertext data based on the received secondary ciphertext calculation instructions.

10. The ciphertext computing accelerator according to claim 9, further comprising: Storage unit; The storage unit is connected to a plurality of processing units corresponding to the first secondary instruction parsing unit; The storage unit is used to store data during the processing of the ciphertext data processing method.

Images