A control circuit that realizes four different logic combinations with a single input terminal

Abstract

A control circuit for realizing four different logic combinations with a single input terminal relates to the technical field of logic control circuits, comprising PMOS tubes PM0, PM1, PM2, PM3, PM4 and PM5; NMOS tubes NM1, NM2, NM3, NM4 and NM5; a resistor R1; a first guide inv1 and a second guide inv2; a NAND gate and; a first NOR gate nor1, a second NOR gate nor2, a third NOR gate nor3 and a fourth NOR gate nor4; a PMOS device PM5, an NMOS device NM5, two inverters, a NAND gate and four NOR gates are added, and the width-to-length ratio of the PMOS device and the NMOS device is designed, so that the circuit of the invention can realize the control of four different logic combinations through a single input terminal in, thereby expanding the application of the circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of logic control circuits, and in particular to a control circuit that realizes four different logic combinations with a single input terminal. Background Art

[0002] Logic state control circuits are widely used in the design of integrated circuit chips used in liquid crystal displays, computer motherboards, notebook computers and general consumer electronic products. As such products develop towards lightness, thinness and low power consumption, higher requirements are placed on the structure and power consumption of logic state control circuits. In the design of integrated circuits, usually, one input terminal can be connected to ground (vss) and power supply (vdd), that is, two logic states 0 and 1 can be realized. If 3 to 4 logic combinations are to be realized, two input control terminals are required. Since fewer chip pins can reduce packaging costs and reduce the application PCB board area, when designing integrated circuit chips, designers will try to reduce chip pins as much as possible. If one input terminal is used to realize more than 3 logic combinations, the traditional design needs to use a voltage divider resistor to set the input terminal to different potentials between the power supply vdd and the ground vss, and design multiple comparators to judge the potential of the comparison input terminal. For example, two comparators are required to realize three different logic combinations with one input terminal. Among them, the reference potential of one comparator is greater than half of vdd, and the reference potential of the other comparator is less than half of vdd. When the input terminal is connected to VDD, the outputs of the two comparators are both logic 0; when the input terminal is connected to VSS, the outputs of the two comparators are both logic 1; and when the input terminal is left floating and the input terminal is set to half of VDD with an equal-value voltage-dividing resistor, the output of one of the comparators is logic 0 and the output of the other comparator is logic 1. Therefore, three logic combinations, namely 00, 11 and 01, are realized with one input terminal. However, the two comparators and the voltage-dividing resistors at the input terminal not only increase the chip area, but also increase the power consumption. In view of the above shortcomings, CN114221649B discloses a control circuit that realizes three different logic combinations with one input terminal, which can significantly reduce the chip area and help reduce power consumption. However, the circuit can only realize three logic combinations, and cannot meet the situation of four logic combinations in specific applications. The expansibility of the circuit has great limitations. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a control circuit that realizes four different logic combinations with a single input terminal, and also provides a method for realizing four different logic combinations through the circuit.

[0004] The technical solution adopted by the present invention is:

[0005] A control circuit for realizing four different logic combinations at a single input terminal, characterized in that: it comprises PMOS tubes PM0, PM1, PM2, PM3, PM4, PM5; NMOS tubes NM1, NM2, NM3, NM4, NM5; resistor R1; first inverter inv1, second inverter inv2; NAND gate and; first NOR gate nor1, second NOR gate nor2, third NOR gate nor3, fourth NOR gate nor4; wherein the sources of PM0, PM2, PM3, PM4, PM5 are connected to VDD, The gates of PM0, PM2, PM3, PM4, and PM5 and the drain of PM0 are connected to ibias, the drain of PM2 is connected to the source of PM1, the drain of PM1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the drain of NM1; the drain of PM3 is connected to the gates of NM1, NM2, and NM5 and the drain of NM2, the source of NM2 is connected to the drain of NM3; the drain of PM4 is connected to the gates of NM3 and NM4 and the drain of NM4; the drain of PM5 is connected to the drain of NM5; PM1, NM1, The common connection point of the gates of NM2 and NM5 and the drains of PM3 and NM2 is connected to the input terminal in; the sources of NM1, NM3, NM4 and NM5 are connected to VSS; the common connection point of the drain of PM1 and the resistor R1 is connected to the input terminal of the first inverter inv1 and the input terminal a of the first NOR gate nor1, the common connection point of the drain of NM1 and the resistor R1 is connected to the input terminal of the second inverter inv2 and the input terminal b of the first NOR gate nor1, and the common connection point of the drain of PM5 and the drain of NM5 is connected to the NAND gate an The input terminal b of d is connected to the input terminal b of the fourth NOR gate nor4, the input terminal a of the NAND gate and is connected to the output terminal of the second inverter inv2 and the input terminal b of the second NOR gate nor2, the output terminal of the first inverter inv1 is connected to the input terminal a of the second NOR gate nor2, the input terminal a of the third NOR gate nor3, and the input terminal a of the fourth NOR gate nor4; the first NOR gate nor1, the second NOR gate nor2, the third NOR gate nor3 and the fourth NOR gate nor4 are respectively provided with output terminals Q1, Q2, Q3 and Q4.

[0006] Further, in the present invention, PM3 and PM4 have the same width-to-length ratio. NM2, NM3 and NM4 have the same width-to-length ratio. The width-to-length ratio of PM5 is twice the width-to-length ratio of PM3. The width-to-length ratio of NM5 is 0.25 times the width-to-length ratio of NM3 and NM2.

[0007] The present invention provides a method for the above control circuit to realize four different logic combinations, including:

[0008] When the input terminal IN is connected to VDD, points A, B, and C are all logic low 0, so the outputs of the four NOR gates are only Q1=1, Q2=Q3=Q4=0;

[0009] When the input terminal in is connected to vss, points A, B, and C are all logic high 1, so the outputs of the four NOR gates are only Q2=1, Q1=Q3=Q4=0;

[0010] When the input terminal in is left floating, point B is logic low 0, while points A and C are both logic high 1. Therefore, the outputs of the four NOR gates are only Q3=1, Q1=Q2=Q4=0.

[0011] When the input terminal in is connected to two equal voltage-dividing points from vdd to vss, points B and C are both logic low 0, while point A is still logic high 1. Therefore, the outputs of the four NOR gates are only Q4=1, Q1=Q2=Q3=0.

[0012] Among them, vdd is logic high 1 and vss is logic low 0.

[0013] The technical effects of the present invention are:

[0014] The present invention adds a PMOS device PM5, an NMOS device NM5, two inverters, a NAND gate and four NOR gates, and designs the width-to-length ratio of the provided PMOS device and NMOS device, so that the circuit of the present invention can realize the control of four different logic combinations through a single input terminal in, thereby expanding the application of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0017] See attached Figure 1 The circuit of the present invention includes PMOS tubes PM0, PM1, PM2, PM3, PM4, PM5; NMOS tubes NM1, NM2, NM3, NM4, NM5; resistor R1; first inverter inv1, second inverter inv2; NAND gate and; first NOR gate nor1, second NOR gate nor2, third NOR gate nor3, fourth NOR gate nor4;

[0018] Among them, the sources of PM0, PM2, PM3, PM4, and PM5 are connected to VDD, the gates of PM0, PM2, PM3, PM4, and PM5 and the drain of PM0 are connected to ibias, the drain of PM2 is connected to the source of PM1, the drain of PM1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the drain of NM1; the drain of PM3 is connected to the gates of NM1, NM2, and NM5 and the drain of NM2, the source of NM2 is connected to the drain of NM3; the drain of PM4 is connected to the gates of NM3 and NM4 and the drain of NM4; the drain of PM5 is connected to the drain of NM5; the common connection point where the gates of PM1, NM1, NM2, and NM5 are connected to the drains of PM3 and NM2 is connected to the input terminal in; the sources of NM1, NM3, NM4, and NM5 are connected to VSS; the drain of PM1 is connected to the common The connection point is connected to the input terminal of the first inverter inv1 and the input terminal a of the first NOR gate nor1, the common connection point of the drain of NM1 and the resistor R1 is connected to the input terminal of the second inverter inv2 and the input terminal b of the first NOR gate nor1, the common connection point of the drain of PM5 and the drain of NM5 is connected to the input terminal b of the NAND gate and and the input terminal b of the fourth NOR gate nor4, the input terminal a of the NAND gate and is connected to the output terminal of the second inverter inv2 and the input terminal b of the second NOR gate nor2, the output terminal of the first inverter inv1 is connected to the input terminal a of the second NOR gate nor2, the input terminal a of the third NOR gate nor3, and the input terminal a of the fourth NOR gate nor4; the first NOR gate nor1, the second NOR gate nor2, the third NOR gate nor3 and the fourth NOR gate nor4 are respectively provided with output terminals Q1, Q2, Q3 and Q4.

[0019] Compared with the circuit in the background technology, Figure 1 As shown, the present invention adds a PMOS device PM5, an NMOS device NM5, two inverters, a NAND gate and four NOR gates. In the present invention, PM3 and PM4 have the same width-to-length ratio, NM2, NM3, and NM4 have the same width-to-length ratio, the width-to-length ratio of PM5 is twice that of PM3, and the width-to-length ratio of NM5 is designed to be 0.25 times that of NM3 and NM2. Therefore, when the input terminal in is grounded or suspended, point C is close to vdd (logic high 1).

[0020] In practical applications, when the input terminal in is connected between the power supply vdd and the ground vss by two equal-valued voltage-dividing resistors, the gate voltage of NM5 is high enough to make the current it conducts greater than the current provided by the current mirror PM5. Therefore, the potential of point C becomes a logic low 0.

[0021] When the input terminal in is connected to vdd (logic high 1), Figure 1Points A, B, and C are all logic low 0 (vss), so the outputs of the four NOR gates are only Q1=1 (vdd), Q2=Q3=Q4=0 (vss);

[0022] When the input terminal in is connected to vss (logic low 0), Figure 1 Points A, B, and C are all logic high 1 (vdd), so the outputs of the four NOR gates are only Q2=1 (vdd), Q1=Q3=Q4=0 (vss);

[0023] When the input terminal in is left floating, Figure 1 Point B is logic low 0 (vss), while points A and C are both logic high 1 (vdd). Therefore, the outputs of the four NOR gates are only Q3=1 (vdd), Q1=Q2=Q4=0 (vss);

[0024] When the input terminal IN is connected to two equal voltage-dividing points from VDD to VSS, Figure 1 Points B and C are both logic low 0 (vss), while point A is still logic high 1 (vdd). Therefore, the outputs of the four NOR gates are only Q4=1 (vdd), Q1=Q2=Q3=0 (vss).

[0025] The above analysis clearly shows that in the circuit design of the present invention, a single input terminal in can realize control circuits of four different logic combinations.

[0026] It should be further explained that the above embodiments are only used to understand the technical solution of the present invention, and are not used to limit the protection scope of the present invention. Any obvious adjustments and modifications made to the technical concept of the present invention should also fall within the protection scope of the present invention.

Claims

1. A control circuit that realizes four different logic combinations with a single input terminal, characterized in that: It includes PMOS tubes PM0, PM1, PM2, PM3, PM4, PM5; NMOS tubes NM1, NM2, NM3, NM4, NM5; resistor R1; first inverter inv1, second inverter inv2; NAND gate and; first NOR gate nor1, second NOR gate nor2, third NOR gate nor3, fourth NOR gate nor4; Among them, the sources of PM0, PM2, PM3, PM4, and PM5 are connected to VDD, the gates of PM0, PM2, PM3, PM4, and PM5 and the drain of PM0 are connected to ibias, the drain of PM2 is connected to the source of PM1, the drain of PM1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the drain of NM1; the drain of PM3 is connected to the gates of NM1, NM2, and NM5 and the drain of NM2, the source of NM2 is connected to the drain of NM3; the drain of PM4 is connected to the gates of NM3 and NM4 and the drain of NM4; the drain of PM5 is connected to the drain of NM5; the common connection point where the gates of PM1, NM1, NM2, and NM5 are connected to the drains of PM3 and NM2 is connected to the input terminal in; the sources of NM1, NM3, NM4, and NM5 are connected to VSS; the drain of PM1 is connected to the common The connection point is connected to the input terminal of the first inverter inv1 and the input terminal a of the first NOR gate nor1, the common connection point of the drain of NM1 and the resistor R1 is connected to the input terminal of the second inverter inv2 and the input terminal b of the first NOR gate nor1, the common connection point of the drain of PM5 and the drain of NM5 is connected to the input terminal b of the NAND gate and and the input terminal b of the fourth NOR gate nor4, the input terminal a of the NAND gate and is connected to the output terminal of the second inverter inv2 and the input terminal b of the second NOR gate nor2, the output terminal of the first inverter inv1 is connected to the input terminal a of the second NOR gate nor2, the input terminal a of the third NOR gate nor3, and the input terminal a of the fourth NOR gate nor4; the first NOR gate nor1, the second NOR gate nor2, the third NOR gate nor3 and the fourth NOR gate nor4 are respectively provided with output terminals Q1, Q2, Q3 and Q4.

2. The control circuit for realizing four different logic combinations with a single input terminal according to claim 1, characterized in that: PM3 and PM4 have the same width-to-length ratio.

3. The control circuit for realizing four different logic combinations with a single input terminal according to claim 1, characterized in that: NM2, NM3 and NM4 have the same width-to-length ratio.

4. The control circuit for realizing four different logic combinations with a single input terminal according to claim 1, characterized in that: The aspect ratio of PM5 is twice that of PM3.

5. The control circuit for realizing four different logic combinations with a single input terminal according to claim 1, characterized in that: The width-to-length ratio of NM5 is 0.25 times that of NM3 and NM2.

6. The method for realizing four different logic combinations by a control circuit according to any one of claims 1 to 5, characterized in that: When the input terminal IN is connected to VDD, points A, B, and C are all logic low 0, so the outputs of the four NOR gates are only Q1=1, Q2=Q3=Q4=0; When the input terminal in is connected to vss, points A, B, and C are all logic high 1, so the outputs of the four NOR gates are only Q2=1, Q1=Q3=Q4=0; When the input terminal in is left floating, point B is logic low 0, while points A and C are both logic high 1. Therefore, the outputs of the four NOR gates are only Q3=1, Q1=Q2=Q4=0. When the input terminal in is connected to two equal voltage-dividing points from vdd to vss, points B and C are both logic low 0, while point A is still logic high 1. Therefore, the outputs of the four NOR gates are only Q4=1, Q1=Q2=Q3=0. Among them, vdd is logic high 1 and vss is logic low 0.

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