Solid-state memory and memory management method

Abstract

The embodiment of the invention provides a solid-state memory and a memory management method, and the solid-state memory comprises a computing interconnection interface, a nonvolatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, the dynamic random access memory comprises a controller memory buffer area and a plurality of persistent memory areas, and instructions and data can be separated through the controller memory buffer area and the persistent memory areas to realize effective isolation of the data and the instructions.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state memory, and in particular discloses a solid-state memory and a memory management method. Background Art

[0002] Solid-state storage under the NVMe (Non Volatile Memory Express) over PCIe (peripheral component interconnect express) architecture has occupied a major position in the enterprise storage device market with its advantages such as large-capacity input and output arrays, multi-command management, and high-speed concurrent transmission. However, NVMe over PCIe also faces inherent disadvantages such as cumbersome transaction transmission and long latency due to the X86 instruction set stipulating that PCIe-based memory transactions cannot be directly cached by the host cache architecture. In order to deal with this problem, many interconnect protocols have been proposed, among which the CXL (Compute Express Link) protocol has the potential to solve the above problems due to its own advantages.

[0003] There are three sub-protocols in the CXL protocol. The CXL.io protocol is based on PCIe and is used for device discovery, status reporting, virtual to physical address translation, and direct memory access. CXL.cache is used by devices to cache system memory. CXL.mem enables the CPU and other CXL devices to access device memory and treat it as cacheable memory.

[0004] As an important component of the computer system, the introduction of the CXL protocol also brings new development prospects to storage devices. In addition to using solid-state memory dynamic random access memory as part of the system memory to build a memory pool / memory sharing, the combination of computing interconnect interface, dynamic random access memory and flash memory can also be used as tiered memory and persistent memory, thereby building a new memory / storage product form to deploy in some scenarios where NVMe over PCIe solid-state memory application capabilities are insufficient, such as artificial intelligence and machine learning.

[0005] In the related art, the following memory management method is disclosed: first, device enumeration and address mapping are performed through CXL.io (the capacity used as memory in the flash memory is mapped to memory), and the host writes to the device through the CXL.mem protocol: the data is written to the device dynamic random access memory, and the device side writes the data back to the back-end medium at the appropriate time through the cache controller. The host reads the device through the CXL.mem protocol: the device dynamic random access memory is directly read, and the process is similar to the cache reading the host dynamic random access memory in the CPU structure. If the read misses, the corresponding data will be read back from the flash memory to the device dynamic random access memory, thereby completing the data reading process. Its structure is as follows: Figure 1 shown.

[0006] However, the above memory management methods have the following defects: the solution to the long delay problem still depends on the cache hit rate on the device side, so complex algorithms and hardware designs are needed to reduce the delay; in order to improve the cache hit rate, a large dynamic random access memory capacity is required, which will result in a large cost; the huge dynamic random access memory capacity will bring challenges to the efficient flushing of stored data when the power is off; compared with NVMe over PCIe solid-state storage, this solution has greater changes and potential reliability issues, and the development of the product depends on the deployment and development of the CXL ecosystem.

[0007] In the related art, the following memory management method is also disclosed: The read operation process of NVMe over CXL is compatible with the traditional implementation scheme using the controller memory buffer. The host uses CXL.io to issue NVMe commands to the NVMe over CXL module and performs logical to physical address conversion to access the flash memory. The NVMe over CXL controller also includes a dynamic random access memory controller that copies the contents of the flash media to the dynamic random access memory of the specified controller memory buffer. Once the contents of the flash memory are transferred to the NVMe over CXL dynamic random access memory, the host can use the CXL.mem protocol to directly access the controller memory buffer area. When the host CPU is ready to write the contents of the controller memory buffer area back to the flash memory, it uses CXL.io to issue an NVMe write command to the NVMe over CXL controller and specifies the address of the controller memory buffer area on the NVMe over CXL module. The NVMe over CXL controller writes the contents of the dynamic random access memory to the corresponding flash memory. Its structure is as follows: Figure 2 shown.

[0008] However, the above memory management method has the following defects: since the controller memory buffer area stores CQ (Completion Queue), SQ (Submission Queue) and PRP (Physical Region Page), if it is used as a data cache, it will bring complex management and scheduling problems to the area. When the controller memory buffer area is used as persistent memory, it may also cause reliability problems such as data cannot be efficiently refreshed. Summary of the invention

[0009] In view of the above problems, a method is proposed to overcome the above problems or at least partially solve the above problems, including:

[0010] A solid-state memory and a memory management method:

[0011] A solid-state memory, comprising a computing interconnect interface, a non-volatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, wherein the dynamic random access memory comprises a controller memory buffer area and a plurality of persistent memory areas, wherein:

[0012] The computing interconnect interface is used to perform device enumeration and initialization and receive and send transaction commands, data read instructions and data write instructions;

[0013] The non-volatile memory interface controller is connected to the computing interconnect interface and is used to place the data read instruction and the data write instruction in the controller memory buffer area;

[0014] The cache controller is connected to the computing interconnect interface, and is used to write preset data into a first target persistent memory area according to the data write instruction, and then map the first target persistent memory area to a first target logical block address via the flash memory controller, and map the first target logical block address to a first target physical block address, write the preset data from the first target persistent memory area back to the first target physical block address, receive and parse a second target logical block address from the data read instruction according to the data read instruction, determine a second target physical block address corresponding to the second target logical block address, retrieve the data of the second target physical block address via the flash memory controller, and place it in the second target persistent memory area corresponding to the second target physical block address for the host to retrieve the data.

[0015] Optionally, multiple persistent memory areas in the dynamic random access memory have different priorities. For the third target persistent memory area with the highest priority, data written to the third target persistent memory area is directly written back to the third target physical block address corresponding to the third target persistent memory area without waiting; for the fourth target persistent memory area with the lowest data priority, the data of the fourth target persistent memory area is written back only when persistent memory areas with other priorities do not write back the data; for the fifth target persistent memory area with a priority between the lowest and the highest, the data of the fifth target persistent memory area is written back when the corresponding task is executed in the flash memory medium.

[0016] Optionally, the non-volatile memory interface controller is further used to configure a namespace for the controller memory buffer area and each of the persistent memory areas according to the transaction command, wherein one namespace corresponds to multiple logical block addresses, and one logical block address corresponds to one physical block address.

[0017] Optionally, according to the priority of the persistent memory area, a physical block address configured for the persistent memory area is set in a flash memory medium corresponding to a wear tolerance level.

[0018] Optionally, for the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the fourth target persistent memory area and the fifth target persistent memory area are both configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode and a four-layer unit storage mode.

[0019] Optionally, for the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, for the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory medium corresponding to the fifth target persistent memory area is configured as a multi-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority, the flash memory medium corresponding to the fourth target persistent memory area is configured as a three-layer unit storage mode or a four-layer unit storage mode.

[0020] Optionally, for the third target persistent memory area with the highest priority, the fourth target persistent memory area with the lowest priority, and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the third target persistent memory area, the fourth target persistent memory area, and the fifth target persistent memory area are all configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode, and a four-layer unit storage mode, wherein a cache of a single-layer unit storage mode is configured for the flash memory medium corresponding to the third target persistent memory area.

[0021] Optionally, when the solid-state memory is powered off or receives flush information, the data written to the persistent memory area is written back to the physical block address corresponding to the persistent memory area in order of priority from high to low.

[0022] Optionally, for each of the persistent memory areas, a corresponding memory capacity is configured for the persistent memory areas with different priorities according to a capacity arithmetic decreasing method or a Gaussian algorithm and according to the total capacity of all the persistent memory areas.

[0023] A memory management method is applied to the solid-state memory, and the memory management method comprises:

[0024] Utilizing the computing interconnect interface to perform device enumeration and initialization and to receive and send transaction commands, data read instructions, and data write instructions;

[0025] Using the non-volatile memory interface controller to place the data read instruction and the data write instruction in the controller memory buffer area;

[0026] The cache controller is used to write preset data into a first target persistent memory area according to the data write instruction, and then the first target persistent memory area is mapped to a first target logical block address via the flash memory controller, and the first target logical block address is mapped to a first target physical block address, and the preset data is written back from the first target persistent memory area to the first target physical block address, and a second target logical block address is received and parsed from the data read instruction according to the data read instruction, and a second target physical block address corresponding to the second target logical block address is determined, and the data of the second target physical block address is retrieved via the flash memory controller, and placed in the second target persistent memory area corresponding to the second target physical block address, so that the host can retrieve the data.

[0027] The embodiments of the present invention have the following advantages:

[0028] In an embodiment of the present invention, the solid-state memory includes a computing interconnect interface, a non-volatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, wherein the dynamic random access memory includes a controller memory buffer area and multiple persistent memory areas, and can separate instructions and data through the controller memory buffer area and the persistent memory area to achieve effective isolation of data and instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0030] Figure 1 It is a structural schematic diagram of a solid-state memory provided by the related technology;

[0031] Figure 2 It is a structural schematic diagram of another solid-state memory provided by the related technology;

[0032] Figure 3 is a schematic diagram of the structure of a solid-state memory provided by some embodiments of the present invention;

[0033] Figure 4 is a schematic diagram of address mapping relationships provided by some embodiments of the present invention;

[0034] Figure 5 is a schematic diagram of power-on initialization of a solid-state memory provided by some embodiments of the present invention;

[0035] Figure 6 It is a schematic diagram of a host writing data to a solid-state memory provided by some embodiments of the present invention;

[0036] Figure 7 It is a schematic diagram of a host reading data from a solid-state memory provided by some embodiments of the present invention;

[0037] Figure 8 It is a flowchart of the steps of the memory management method provided by some embodiments of the present invention. DETAILED DESCRIPTION

[0038] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Embodiment 1

[0040] See also Figure 3 , shows a solid-state memory provided by some embodiments of the present invention, the solid-state memory includes a computing interconnect interface, a non-volatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller and a flash memory medium, wherein the dynamic random access memory includes a controller memory buffer area and multiple persistent memory areas, wherein,

[0041] The computing interconnect interface is used to perform device enumeration and initialization and receive and send transaction commands, data read instructions and data write instructions;

[0042] The non-volatile memory interface controller is connected to the computing interconnect interface and is used to place the data read instruction and the data write instruction in the controller memory buffer area;

[0043] The cache controller is connected to the computing interconnect interface, and is used to write preset data into a first target persistent memory area according to the data write instruction, and then map the first target persistent memory area to a first target logical block address via the flash memory controller, and map the first target logical block address to a first target physical block address, write the preset data from the first target persistent memory area back to the first target physical block address, receive and parse a second target logical block address from the data read instruction according to the data read instruction, determine a second target physical block address corresponding to the second target logical block address, retrieve the data of the second target physical block address via the flash memory controller, and place it in the second target persistent memory area corresponding to the second target physical block address for the host to retrieve the data.

[0044] In some embodiments of the present invention, the solid-state memory may be a CXL over PCIe solid-state memory under an ARM (Advanced RISC Machine) architecture, where CXL over PCIe refers to a high-speed interconnection achieved through a PCIe (Peripheral Component Interconnect Express) interface using CXL (Compute Express Link) technology.

[0045] In some embodiments of the present invention, the computing interconnect interface includes a CXL.io interface and a CXL.mem interface. The CXL.io interface is similar to the PCIe interface and is used for block access. The CXL.mem interface is a transaction interface between the CPU and the memory. It uses the physical layer and link layer of CXL for cross-chip communication. Data read and write operations can be performed through the CXL.io interface for block access or through the CXL.mem interface for memory access. The host can read data from the solid-state memory through the CXL.mem interface: when the host needs to read a certain data, it first searches for the flash memory page where the data is located through the CXL.io interface, and puts it into the persistent memory area corresponding to the logical block address according to the logical block address of the flash memory page, and then the host reads the data in the persistent memory area through CXL.mem.

[0046] In some embodiments of the present invention, the dynamic random access memory may be an onboard dynamic random access memory. Figure 3 In the embodiment, the dynamic random access memory includes a flash conversion area, a controller memory buffer area, a persistent memory area 1, a persistent memory area 2... a persistent memory area N, wherein a mapping relationship table between a logical block address and a flash physical block address is stored in the flash conversion area. The controller memory buffer area is used to store a submission queue / completion queue and a physical area page. Persistent memory area 1, persistent memory area 2...persistent memory area N are all persistent memory areas for storing data read and written by the host. The persistent memory area can be mapped to the address space on the external component interconnect bus and can be accessed by the host and other devices. After power failure, controller reset, and persistent memory area enable / disable switching, the data written to the persistent memory area will be retained. The operation of the persistent memory area is similar to that of the controller memory buffer area. The host system can directly read and write this memory area using the basic external component interconnect bus transmission without any command queue overhead.

[0047] When the host writes data to the solid-state storage through the CXL.mem interface, the numbers 1-N can be set to correspond to the data write-back level. The smaller the number, the higher the write-back priority. That is, when the host data is written to the persistent memory area 1, the data does not need to wait to be written back immediately, corresponding to high-priority reliable data. When the host data is written to the persistent memory area 2 to N-1 area, it corresponds to different write-back levels for different tasks inside the flash memory. For example, when garbage collection is performed inside the flash memory, data at level 2 of the persistent memory area is allowed to be written back, while data at other levels is not allowed. When the host data is written to the persistent memory area N area, the corresponding write-back data priority is the lowest. Only when no other levels write data back to the flash memory, data in this area is allowed to be written back. Correspondingly, the flash memory areas corresponding to each persistent memory area should also be different. Data of different levels correspond to different flash memory logical address space areas. By dividing the flash memory space into different logical block address segments and building a mapping relationship, for example, each persistent memory area corresponds to a namespace. In the flash memory controller, the quality of the flash memory media is classified, and data in a high-priority write-back area is preferentially mapped to a non-volatile storage medium with large wear tolerance and high performance, so as to change the mapping relationship between the logical block address and the physical block address.

[0048] In some embodiments of the present invention, the first target persistent memory area is a persistent memory area used when the host writes data, and the second target persistent memory area is a persistent memory area used when the host reads data. The first target persistent memory area and the second target persistent memory area can be any one of persistent memory area 1, persistent memory area 2...persistent memory area N.

[0049] In some embodiments of the present invention, the multiple persistent memory areas in the dynamic random access memory have different priorities. For the third target persistent memory area with the highest priority, data written to the third target persistent memory area is directly written back to the third target physical block address corresponding to the third target persistent memory area without waiting; for the fourth target persistent memory area with the lowest data priority, the data of the fourth target persistent memory area is written back only when the persistent memory areas with other priorities do not write back the data; for the fifth target persistent memory area with a priority between the lowest and the highest, the data of the fifth target persistent memory area is written back when the corresponding task is executed in the flash memory medium.

[0050] In some embodiments of the present invention, the third target persistent memory area may be persistent memory area 1, the fourth target persistent memory area may be persistent memory area N, and the fifth target persistent memory area may be any one of persistent memory area 2…persistent memory area N-1.

[0051] The solid-state storage of the present invention is based on the NVMe over CXL architecture, and utilizes the functions of the CXL interface and the controller memory buffer area and the persistent memory area of ​​NVMe to achieve effective isolation of data and instructions and efficient data flushing by configuring different priorities of the persistent memory area. It has the advantages of high feasibility, simple management, and reliable data, and can not only solve the problems of complex and chaotic data and instruction management in the NVMe over CXL architecture, but also solve the problem that the memory data of the large-capacity dynamic random access memory in the CXL solid-state drive / NVMe over CXL device cannot be efficiently flushed.

[0052] Embodiment 2

[0053] like Figure 4 As shown, the non-volatile memory interface controller is also used to configure a namespace for the controller memory buffer area and each of the persistent memory areas according to the transaction command, one namespace is correspondingly configured with multiple logical block addresses, and one logical block address is correspondingly configured with one physical block address.

[0054] In some embodiments of the present invention, according to the priority of the persistent memory area, the physical block address configured for the persistent memory area is set in the flash memory medium corresponding to the wear tolerance level.

[0055] In some embodiments of the present invention, for the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the fourth target persistent memory area and the fifth target persistent memory area are both configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode and a four-layer unit storage mode.

[0056] In some embodiments of the present invention, for the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, for the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory medium corresponding to the fifth target persistent memory area is configured as a multi-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority, the flash memory medium corresponding to the fourth target persistent memory area is configured as a three-layer unit storage mode or a four-layer unit storage mode.

[0057] In some embodiments of the present invention, for the third target persistent memory area with the highest priority, the fourth target persistent memory area with the lowest priority, and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the third target persistent memory area, the fourth target persistent memory area, and the fifth target persistent memory area are all configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode, and a four-layer unit storage mode, wherein a cache of a single-layer unit storage mode is configured for the flash memory medium corresponding to the third target persistent memory area.

[0058] In some embodiments of the present invention, when the solid-state memory is powered off or receives flush information, the data written to the persistent memory area is written back to the physical block address corresponding to the persistent memory area in order of priority from high to low.

[0059] The solid-state storage of the present invention, when the solid-state storage is powered off or receives flush back information, flushes the data back to the corresponding flash memory in sequence from the fourth target persistent memory area to the third target persistent memory area according to the priority. Since some high-reliability data has been written back to the back-end flash memory medium in real time during the operation of the solid-state drive, even in the case of insufficient capacitance, it can be ensured that high-priority data will be flushed back first.

[0060] In some embodiments of the present invention, data priority levels are divided by the host according to ongoing transactions, and data is placed in different persistent memory areas according to the mapping addresses of the persistent memory areas in the memory space.

[0061] In some embodiments of the present invention, for each of the persistent memory areas, the corresponding memory capacity is configured for the persistent memory areas with different priorities according to the total capacity of all persistent memory areas according to the capacity arithmetic decreasing method or the Gaussian algorithm, and the memory capacity of each area is autonomously configured through the persistent memory area register in the solid-state memory, wherein the high priority accounts for 1δ surround, the secondary level 1.5δ surround, etc., and the 1δ surround means that approximately 68.27% of the data points will fall within the range of the mean plus or minus one standard deviation (μ±1δ). This is a characteristic based on the normal distribution. 1.5δ surround: This may mean that the data points fall within the range of the mean plus or minus 1.5 standard deviations (μ±1.5δ). In this case, according to the normal distribution, approximately 86.6% of the data points will fall within this range.

[0062] Embodiment 3

[0063] The workflow of the solid-state memory of the present invention is:

[0064] First step, see Figure 5During the power-on phase of the solid-state memory, the host enumerates the solid-state memory, divides the address space for the solid-state memory, and maps the memory addresses of the controller memory buffer and the persistent memory area. At the same time, the flash conversion mapping table in the flash memory is loaded into the dynamic random access memory. The host's non-volatile memory driver records the priorities corresponding to the addresses of different persistent memory areas, so that the data is placed in the corresponding persistent memory area during the data reading and writing phase. Among them, the size of the persistent memory area is configured by the device end according to the memory capacity algorithm.

[0065] In the second step, the host's non-volatile memory driver divides the namespace for the solid-state storage and builds a logical block address space.

[0066] Step 3, see Figure 6 , the host performs data writing phase, according to the transaction level: the data is placed in the corresponding persistent memory area through the CXL.mem interface. If it is high-priority data, the data is immediately written back to the non-volatile flash memory medium; at this time, the command is placed in the submission queue of the device controller memory buffer through the CXL.io transaction. The SQ corresponding to the high-level data source has a high weight and is processed by the SSD device side first; the solid-state storage is notified to fetch the command through the doorbell mechanism of CXL.io. After the command is retrieved and parsed, if it is data located on the physical area page of the high-priority persistent memory area, it is placed on a logical block address of the namespace of the corresponding level; the cache controller transmits the data to the flash control module, and the flash controller allocates the corresponding non-volatile physical block address to it according to the received data and the address to be placed. The mapping relationship between the physical block address and the logical block address is recorded and updated to the flash conversion mapping table of the dynamic random access memory located in the solid-state memory to implement a data write operation. However, if the data priority at this time is low, the data is temporarily stored in the corresponding persistent memory area, and the instruction is stored in the submission queue. When waiting for the processing conditions that meet the priority data and there is no other higher priority data to interrupt the queue, the host side sends CXL.io to perform a doorbell, so that the data is placed in the corresponding flash memory. High-priority data can interrupt the writing of low-priority data, giving weight to high-level data.

[0067] Step 4, see Figure 7, the host performs the data reading phase: first, the command is placed in the submission queue of the controller memory buffer through the CXL.io interface; the host side sends CXL.io to perform the doorbell to notify the solid-state storage side to process the instruction. By parsing the instruction, if a logical block address of a certain namespace is retrieved to the physical area page of the corresponding level of persistent memory area; the corresponding flash physical address is found through the flash conversion mapping table, and the flash controller retrieves the data on the corresponding flash physical address and places it in the persistent memory area of ​​the corresponding priority level through the cache controller; the host retrieves the data through the CXL.mem interface to complete the data read operation. In the data read operation, the data is placed in the persistent memory area of ​​the corresponding priority level, but there is no priority level difference in the data read order.

[0068] Embodiment 4

[0069] During the data writing stage of the host, data of different levels are placed in the corresponding persistent memory area. If it is high-priority data, the data is immediately written back to the non-volatile flash memory medium through the controller configured for the persistent memory area. If the data priority at this time is low, the data is temporarily stored in the corresponding persistent memory area. When the processing conditions of the priority data are met and there is no other higher priority data in the queue, the data is placed in the corresponding flash memory through the controller configured for the persistent memory area.

[0070] Embodiment 5

[0071] See also Figure 8 A memory management method of the present invention is applied to the solid-state memory, and the memory management method comprises:

[0072] S1, using the computing interconnect interface to perform device enumeration and initialization and receive and send transaction commands, data read instructions and data write instructions;

[0073] S2, using the non-volatile memory interface controller to place the data read instruction and the data write instruction in the controller memory buffer area;

[0074] S3, using the cache controller to write preset data into the first target persistent memory area according to the data write instruction, and then mapping the first target persistent memory area to the first target logical block address via the flash memory controller, and mapping the first target logical block address to the first target physical block address, writing the preset data from the first target persistent memory area back to the first target physical block address, receiving and according to the data read instruction, parsing the second target logical block address from the data read instruction, determining the second target physical block address corresponding to the second target logical block address, retrieving the data of the second target physical block address via the flash memory controller, and placing it in the second target persistent memory area corresponding to the second target physical block address, so that the host can retrieve the data.

[0075] In some embodiments of the present invention, the method further comprises:

[0076] The non-volatile memory interface controller is used to configure a namespace for the controller memory buffer area and each of the persistent memory areas according to the transaction command, one namespace is correspondingly configured with multiple logical block addresses, and one logical block address is correspondingly configured with one physical block address.

[0077] In some embodiments of the present invention, the method further comprises:

[0078] When the solid-state memory is powered off or receives flush information, the data written to the persistent memory area is written back to the physical block address corresponding to the persistent memory area in descending order of priority of the persistent memory area.

[0079] As for the method embodiment, since it is basically similar to the device embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the device embodiment.

[0080] The above is a detailed introduction to a solid-state storage device and a memory management method. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A solid-state memory, characterized in that: The solid-state memory includes a computing interconnect interface, a non-volatile memory interface controller, a cache controller, a dynamic random access memory, a flash memory controller, and a flash memory medium, wherein the dynamic random access memory includes a controller memory buffer area and multiple persistent memory areas, wherein: The computing interconnect interface is used to perform device enumeration and initialization and receive and send transaction commands, data read instructions and data write instructions; The non-volatile memory interface controller is connected to the computing interconnect interface and is used to place the data read instruction and the data write instruction in the controller memory buffer area; The cache controller is connected to the computing interconnect interface, and is used to write preset data into a first target persistent memory area according to the data write instruction, and then map the first target persistent memory area to a first target logical block address via the flash memory controller, and map the first target logical block address to a first target physical block address, write the preset data from the first target persistent memory area back to the first target physical block address, receive and parse a second target logical block address from the data read instruction according to the data read instruction, determine a second target physical block address corresponding to the second target logical block address, retrieve the data of the second target physical block address via the flash memory controller, and place it in the second target persistent memory area corresponding to the second target physical block address for the host to retrieve the data.

2. The solid-state memory according to claim 1, characterized in that: The multiple persistent memory areas in the dynamic random access memory have different priorities. For the third target persistent memory area with the highest priority, data written to the third target persistent memory area is directly written back to the third target physical block address corresponding to the third target persistent memory area without waiting; for the fourth target persistent memory area with the lowest data priority, the data of the fourth target persistent memory area is written back only when the persistent memory areas with other priorities do not write back the data; for the fifth target persistent memory area with a priority between the lowest and the highest, the data of the fifth target persistent memory area is written back when the corresponding task is executed in the flash memory medium.

3. The solid-state memory according to claim 1, characterized in that: The non-volatile memory interface controller is also used to configure a namespace for the controller memory buffer area and each of the persistent memory areas according to the transaction command, wherein one namespace is correspondingly configured with multiple logical block addresses, and one logical block address is correspondingly configured with one physical block address.

4. The solid-state memory according to claim 1, characterized in that: According to the priority of the persistent memory area, a physical block address configured for the persistent memory area is set in a flash memory medium corresponding to a wear tolerance level.

5. The solid-state memory according to claim 4, characterized in that: For the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the fourth target persistent memory area and the fifth target persistent memory area are both configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode and a four-layer unit storage mode.

6. The solid-state memory according to claim 4, characterized in that: For the third target persistent memory area with the highest priority, the flash memory medium corresponding to the third target persistent memory area is configured as a single-layer unit storage mode, for the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory medium corresponding to the fifth target persistent memory area is configured as a multi-layer unit storage mode, and for the fourth target persistent memory area with the lowest priority, the flash memory medium corresponding to the fourth target persistent memory area is configured as a three-layer unit storage mode or a four-layer unit storage mode.

7. The solid-state memory according to claim 4, characterized in that: For the third target persistent memory area with the highest priority, the fourth target persistent memory area with the lowest priority, and the fifth target persistent memory area with a priority between the lowest and the highest, the flash memory media corresponding to the third target persistent memory area, the fourth target persistent memory area, and the fifth target persistent memory area are all configured as any one of a multi-layer unit storage mode, a three-layer unit storage mode, and a four-layer unit storage mode, wherein a cache of a single-layer unit storage mode is configured for the flash memory medium corresponding to the third target persistent memory area.

8. The solid-state memory according to claim 1, characterized in that: When the solid-state memory is powered off or receives flush information, the data written to the persistent memory area is written back to the physical block address corresponding to the persistent memory area in descending order of priority of the persistent memory area.

9. The solid-state memory according to claim 1, characterized in that: For each of the persistent memory areas, the corresponding memory capacities are respectively configured for the persistent memory areas with different priorities according to the total capacity of all the persistent memory areas in accordance with the capacity arithmetic decreasing method or the Gaussian algorithm.

10. A memory management method, characterized in that: Applied to the solid-state memory according to any one of claims 1 to 9, the memory management method comprises: Utilizing the computing interconnect interface to perform device enumeration and initialization and to receive and send transaction commands, data read instructions, and data write instructions; Using the non-volatile memory interface controller to place the data read instruction and the data write instruction in the controller memory buffer area; The cache controller is used to write preset data into a first target persistent memory area according to the data write instruction, and then the first target persistent memory area is mapped to a first target logical block address via the flash memory controller, and the first target logical block address is mapped to a first target physical block address, and the preset data is written back from the first target persistent memory area to the first target physical block address, and a second target logical block address is received and parsed from the data read instruction according to the data read instruction, and a second target physical block address corresponding to the second target logical block address is determined, and the data of the second target physical block address is retrieved via the flash memory controller, and placed in the second target persistent memory area corresponding to the second target physical block address, so that the host can retrieve the data.

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