Multi-channel high-speed sampling data storage system and control method

Abstract

The invention discloses a multi-channel high-speed sampling data storage system and a control method. The system comprises a disk array, an upper computer, a DDR3 memory particle cache module, a PXIe transport protocol module, an Aurora transport protocol module, a DDR3 memory bank cache module, a data acquisition and signal processing module and an A / D conversion module. The control method comprises the steps that an upper computer issues a control instruction in a PIO mode through a PXIe transmission protocol module and issues reconfiguration data in a DMA reading mode, a first FPGA chip stores the reconfiguration data into a DDR3 memory particle cache module, and reconfiguration of a second FPGA chip is initiated; after configuration is completed, the first FPGA chip transmits a control command and parameters to the second FPGA chip through an Aurora protocol, receives a digital intermediate frequency signal converted by the A / D conversion module according to the command, and carries out corresponding signal processing and logic control in three modes of single point, real time and triggering according to an instruction of an upper computer.

Description

Technical Field

[0001] The present invention relates to the field of high-speed sampling technology, and in particular to a multi-channel high-speed sampling data storage system and a control method. Background Art

[0002] Substations encounter various electromagnetic disturbances during on-site operation. With the increase of transmission voltage level, the electromagnetic disturbance problem will become more serious. Intelligent electrical equipment based on electronic technology is becoming more and more sensitive to electromagnetic disturbances. Therefore, how to ensure the reliability of intelligent electrical equipment in a complex electromagnetic environment within the limited space of the substation has become the focus of research in the power industry. As an important part of the field of information and measurement and control science, data acquisition and transmission technology plays a vital role in the industry.

[0003] Signal streaming and playback systems are new instruments in electromagnetic signal research that meet the needs of most fields for wireless communication analysis and testing. They are mainly used for wireless communication signal testing, electromagnetic environment monitoring, downlink channel monitoring, etc. In engineering testing, it is often necessary to collect, process and store test signals in real time, and it is required to view historical data in time after the test. Therefore, how to quickly, accurately and reliably store these massive data is a current research hotspot.

[0004] FPGA (Field Programmable Gate Array) is the full name of field programmable gate array. With its high performance, high efficiency and low power consumption, FPGA has gradually become the core part of the data acquisition system, and can process more channels and higher-speed signals more quickly and effectively. In terms of high-speed and large-capacity data acquisition, there are many foreign test product manufacturers, and they have successively invested in the research of signal streaming and playback products. In terms of high-speed data transmission and storage technology, companies such as NI and Agilent have conducted research on high-speed serial transmission technology very early. These companies have in-depth research on the PXIe bus and use PXIe to realize board-level communication and communication between the bottom layer and the host computer.

[0005] At present, multi-channel, high-sampling rate data acquisition cards are widely available in the market. Such acquisition cards will instantly generate a large amount of test data. At present, the data storage medium is mainly SATA interface hard disk, and the SATA interface hard disk is limited by the bandwidth of the system bus, such as PCI bus is 133MB / s, PCIe bus is up to 4GB / s, and PXIe bus is up to 6GB / s. Therefore, if you want to build a multi-channel, high-sampling rate, real-time data storage system with reliability, adaptability, flexibility and scalability, then the technical indicators of the system bus, data transmission method, system software architecture, and hardware are very important. Summary of the invention

[0006] In view of the above existing problems, the present invention is proposed.

[0007] Therefore, the present invention provides a multi-channel high-speed sampling data storage system and control method, the purpose of which is to be able to quickly receive and record and store eight-channel analog signals of electromagnetic disturbance, monitor and receive PXIe bus digital quantities, and can realize complete reading back of the data in the memory by recycling the memory, thereby supporting the data preservation, playback and statistical functions of the online monitoring system for electromagnetic disturbance of electronic transformers.

[0008] In order to achieve the above technical objectives, the present invention provides the following technical solutions:

[0009] In a first aspect, the present invention provides a multi-channel high-speed sampling data storage system, comprising: the multi-channel high-speed sampling data storage system comprises a disk array, a host computer, a memory particle cache module, a PXIe transmission protocol module, an Aurora transmission protocol module, a memory bar cache module, a data acquisition and signal processing module, and an A / D conversion module;

[0010] The A / D conversion module, the data acquisition and signal processing module, the Aurora transmission protocol module, the PXIe transmission protocol module, the host computer and the disk array are connected in sequence, the PXIe transmission protocol module is also connected to the memory particle cache module, and the data acquisition and signal processing module is connected to the Aurora transmission protocol module through the memory bar cache module;

[0011] The memory particle cache module and the PXIe transmission protocol module are integrated in the first FPGA chip, and the Aurora transmission protocol module, the memory bar cache module, and the data acquisition and signal processing module are integrated in the second FPGA chip.

[0012] As a preferred solution of the multi-channel high-speed sampling data storage system of the present invention, wherein: the A / D conversion module is composed of a front-end signal conditioning circuit and an A / D converter;

[0013] The front-end conditioning circuit is composed of a high-speed operational amplifier and an analog quantity driving circuit. The analog quantity is amplified by a high-speed operational amplifier whose input impedance is greater than a preset impedance threshold and sent to a high-speed differential operational amplifier to provide a differential input for the A / D converter.

[0014] In a second aspect, the present invention provides a multi-channel high-speed sampling data storage control method, comprising: the host computer sends control instructions in PIO mode through the PXIe transmission protocol module and sends reconfiguration data in DMA read mode, the first FPGA chip stores the received reconfiguration data in the memory particle cache module, and reads out the configuration data according to the corresponding instructions, and initiates reconfiguration of the second FPGA chip; after the reconfiguration of the second FPGA chip is completed, the first FPGA chip transmits the control commands and parameters to the second FPGA chip through the Aurora transmission protocol module, the second FPGA chip receives the digital intermediate frequency signal converted by the A / D conversion module according to the control command and performs corresponding signal processing and logic control in three modes of single point, real-time and trigger according to the control instructions sent by the host computer.

[0015] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it includes:

[0016] In the real-time and trigger mode, the data after signal processing is sent to the memory bar cache module for caching, and the data to be sent by the second FPGA chip is transmitted to the first FPGA chip through the Aurora transmission protocol module. The first FPGA chip receives the processed data, and then sends the processed data to the host computer memory by the PXIe bus in the DMA write mode, for real-time display and decides whether the host computer transfers the data in the memory to the disk array according to user needs;

[0017] When the radio frequency signal is played back, the host computer reads the data in the disk array for real-time display, or sends it to the bottom layer for triggering judgment.

[0018] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it includes:

[0019] When the host computer starts data acquisition, the FPGA chip initializes and configures the A / D converter via the SPI bus;

[0020] The FPGA chip detects whether the internal FIFO storage state is full. When the FIFO storage reaches the full state, the FPGA chip generates a low-level external interrupt request signal. After the host computer responds to the interrupt, it reads the data in the FIFO through the PXI bus.

[0021] The FPGA chip detects whether the internal FIFO storage status is empty. When the FPGA chip receives the FIFO output empty signal, it generates an interrupt request signal to the host computer through the PXI bus again. After responding to the interrupt, the host computer queries the interrupt source. After detecting that the FIFO is an empty signal, the host computer stops reading FIFO data through the bus, and an AD acquisition task is completed at this time.

[0022] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it includes:

[0023] After completing an AD acquisition task, the host computer writes a reset signal to the FPGA chip, so that the FPGA chip stops configuring the A / D converter, the AD conversion process is terminated, and the control process is terminated.

[0024] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it includes:

[0025] When the host computer initiates a DMA transmission operation, the DMA initialization information, control and status information are sent to the intermediate frequency unit terminal through the PIO mode, and the DMA controller of the terminal device receives the data packet, stores the DMA initialization information, control and status information in the register array space of the corresponding address, and then triggers the start of DMA transmission through the register value in the register array;

[0026] The DMA control logic divides and assembles the data load or the requested data length according to the parameter value of the register array space, and finally calculates the source and destination physical addresses, and performs successive calculations to parse the source or destination transaction ID to provide all the required encoding values ​​for the TLP header assembly.

[0027] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it also includes:

[0028] When the system performs a DMA read operation, the bottom PXIe terminal sending module sends multiple memory read request packets, and the host computer returns a memory read completion packet. After receiving the data carried in the completion packet, the entire DMA read operation is completed.

[0029] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it also includes:

[0030] When the system performs a DMA write operation, the terminal writes a request packet through the sending module memory, and carries the payload data of the corresponding request address after the packet header, and sends it to the link through the sending module. After the packet is sent, an interrupt is initiated, and the corresponding interrupt register flag is written to end the DMA process.

[0031] As a preferred solution of the multi-channel high-speed sampling data storage control method of the present invention, it also includes:

[0032] The data read out during DMA read operation is sent to an asynchronous FIFO, and the data source during DMA write operation is another asynchronous FIFO. These two asynchronous FIFOs are connected to the Aurora protocol and storage control logic through an interface module.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention can quickly receive and record and store eight-channel analog signals of electromagnetic disturbance, monitor and receive PXIe bus digital quantities, and can completely read back the data in the memory by recycling the memory, thereby supporting the data preservation, playback and statistical functions of the online monitoring system for electromagnetic disturbance of electronic transformers. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0035] Figure 1 A system structure diagram of a multi-channel high-speed sampling data storage system and a control method according to an embodiment of the present invention;

[0036] Figure 2 This is an operating principle diagram of a multi-channel high-speed sampling data storage system and a control method according to an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of an A / D converter configuration flow of a multi-channel high-speed sampling data storage system and control method according to an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of the structure of an intermediate frequency processing unit of a multi-channel high-speed sampling data storage system and control method according to an embodiment of the present invention;

[0039] Figure 5 A block diagram of a PXIe protocol module implementation of a multi-channel high-speed sampling data storage system and control method according to an embodiment of the present invention;

[0040] Figure 6 A design block diagram of an Aurora protocol implementation module of a multi-channel high-speed sampling data storage system and control method according to an embodiment of the present invention;

[0041] Figure 7This is a structural diagram of the DMA data transmission design of the PXIe protocol of the multi-channel high-speed sampling data storage system and control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary persons in the art without creative work should fall within the scope of protection of the present invention.

[0043] Example 1

[0044] Reference Figure 1 to Figure 7 According to an embodiment of the present invention, a multi-channel high-speed sampling data storage system and control method are provided, which specifically include:

[0045] This embodiment uses the PXIe bus for communication between the bottom layer and the host computer. According to the system requirements, the Xilinx FPGA implementation scheme is adopted. The logic design of PXIe protocol PIO configuration, DMA transmission mode, interrupt control and other functions is carried out. It also provides research on the PCIe transaction layer protocol, understanding of the interrupt control mechanism, familiarity with the PCIe Gen2 hard core interface, and joint debugging of the bottom layer and the host computer. In this embodiment, the Aurora protocol is used to implement Xilinx FPGA inter-chip communication, and the high-speed serial transceiver hardware circuit is tested for transmission and reception, and the FPGA logic design of the Aurora protocol is completed; DDR3 is selected for the high-speed storage part of the streaming system. Considering the system integration, the logic design of PXIe, Aurora, and DDR3 are integrated into two Xilinx FPGA chips. The storage control implementation of DDR3 is mainly combined with the timing of the official soft core for corresponding logic design.

[0046] like Figure 1 As shown, the multi-channel high-speed sampling data storage system provided in this embodiment includes a disk array, a host computer, a DDR3 memory particle cache module, a PXIe transmission protocol module, an Aurora transmission protocol module, a DDR3 memory bar cache module, a data acquisition and signal processing module, and an A / D conversion module;

[0047] In a feasible implementation, the A / D conversion module, the data acquisition and signal processing module, the Aurora transmission protocol module, the PXIe transmission protocol module, the host computer and the disk array are connected in sequence, the PXIe transmission protocol module is also connected to the DDR3 memory particle cache module, and the data acquisition and signal processing module is connected to the Aurora transmission protocol module through the DDR3 memory bar cache module; the DR3 memory particle cache module and the PXIe transmission protocol module are integrated in the first FPGA chip, and the Aurora transmission protocol module, the DDR3 memory bar cache module, and the data acquisition and signal processing module are integrated in the second FPGA chip;

[0048] In a feasible implementation, the A / D conversion module is composed of a front-end signal conditioning circuit and an A / D converter; the front-end conditioning circuit is composed of a high-speed operational amplifier and an analog quantity driving circuit, and the analog quantity is amplified by a high-speed operational amplifier AD825 whose input impedance is greater than a preset impedance threshold and sent to a high-speed differential operational amplifier AD8132 to provide a differential input for the A / D converter.

[0049] It should be noted that the AD825 is selected as the op amp for the front-end analog input because the input impedance of the AD825 is very large, equivalent to an open circuit. After being connected in parallel with the voltage divider resistor, the equivalent resistance is basically the same as the voltage divider resistor, which can ensure accurate analog input. The high-speed differential op amp AD8132 amplifies and drives the single-ended signal to differential and sends it to the A / D converter AD9248.

[0050] It should be noted that FPGA itself does not have AD acquisition function, so there must be an A / D conversion circuit before the FPGA control circuit to convert the analog quantity into a processable digital quantity.

[0051] In the embodiment of the present application, the host computer initially sends control instructions in PIO (programmable input / output) mode through the PXIe protocol and sends reconfiguration data in DMA read mode. The Xilinx XC7K160TFPGA chip stores the received reconfiguration data in the DDR3 SDRAM memory particles, and reads the configuration and data according to the corresponding instructions, initiating the reconfiguration of the XC7K325T FPGA chip. After the configuration is completed, the XC7K160T FPGA transmits the control commands and parameters to the XC7K325T FPGA through the Aurora protocol. The XC7K325T receives the digital intermediate frequency signal that is about to be converted into AD according to the command and performs corresponding signal processing and logic control in the three modes of single point, real-time, and trigger according to the host computer instructions;

[0052] In the embodiment of the present application, in real-time and trigger mode, the data after signal processing is sent to the DDR3 memory cache, and the data to be sent in the XC7K325T is transmitted to the XC7K160T through the Aurora high-speed protocol. The XC7K160T FPGA receives the processed data through the Aurora protocol, and then sends the processed data to the host computer memory through the PXIe bus in the form of DMA write, for real-time display and decides whether the host computer transfers the data in the memory to the disk array according to user needs;

[0053] In the embodiment of the present application, when the RF signal is played back, the host computer reads the data in the disk array for real-time display, and can also send it to the bottom layer for triggering and other judgments.

[0054] Further, such as Figure 2 As shown, according to the design requirements of the signal streaming and playback system, since the disk array streaming technology uses a ready-made solution, the design of the high-speed data transmission and storage part is mainly in the intermediate frequency signal processing unit, wherein the main functions of the high-speed interface part are: first, the host computer can send control and status information to the FPGA through the PXIe bus, and can also read the existing values ​​of the control and status registers in the FPGA, and the intermediate frequency unit and the host computer can communicate command parameters, spectrum data, configuration data, etc. through the PXIe bus in DMA mode; secondly, the two FPGA chips are used to transmit high-speed data through the Aurora protocol, ensuring that the baseband signal is sent to the host computer at high speed after processing, without the bottleneck of transmission bandwidth; finally, the intermediate frequency unit adds DDR3 SDRAM particles and memory bars to the two FPGAs to facilitate the cache of reconfiguration data and signal processing data, optimize the reconfiguration operation, and provide a storage solution for the real-time mode of the system.

[0055] It should be noted that the focus of this embodiment is to realize the logic design of high-speed interfaces such as PXIe, Aurora, and DDR3, which is realized by using Xilinx XC7K325T and XC7K160T FPGAs. The 7 series chips come with PCIe hard core, official free open source Aurora soft core, and official MIG soft core, which can be used to realize the PXIe protocol physical layer and processing layer logic, Aurora high-speed serial protocol, and DDR3 SDRAM controller respectively.

[0056] In the embodiments of the present application, Figure 3 As shown, FPGA uses a top-down approach. When the host computer starts data acquisition, FPGA initializes and configures the A / D converter through the SPI bus:

[0057] The FPGA chip detects whether the internal FIFO storage status is full. When the FIFO storage reaches the full (wrfull) state, the FPGA generates a low-level external interrupt request signal. After the host computer responds to the interrupt, it reads the data in the FIFO through the PXI bus. The FPGA chip detects whether the internal FIFO storage status is empty. When the FPGA receives the FIFO output empty (rdempty) signal, it generates an interrupt request signal to the host computer through the PXI bus again. After responding to the interrupt, the host computer queries the interrupt source. After detecting the FIFO empty signal, the host computer stops reading the FIFO data through the bus, completing an AD acquisition task.

[0058] After completing one acquisition, the host computer writes a reset signal to the FPGA, so that the FPGA stops configuring the A / D converter AD9248, thus terminating the AD conversion process and the control process.

[0059] It should be explained that according to the design requirements of the signal streaming and playback system, since the disk array's streaming technology uses a ready-made solution, the design of the high-speed data transmission and storage part is mainly based on the intermediate frequency signal processing unit, of which the main functions of the high-speed interface part are: first, the host computer can send control and status information to the FPGA through the PXIe bus, and can also read the existing values ​​of the control and status registers in the FPGA, and the intermediate frequency unit and the host computer can communicate command parameters, spectrum data, configuration data, etc. through the PXIe bus in DMA mode; secondly, the two FPGA chips use the Aurora protocol for high-speed data transmission, ensuring that the baseband signal is sent to the host computer at high speed after processing, without the bottleneck of transmission bandwidth; finally, the intermediate frequency unit adds DDR3 SDRAM particles and memory bars to the two FPGAs to facilitate the cache of reconfiguration data and signal processing data, optimize the reconfiguration operation, and provide a storage solution for the real-time mode of the system. The focus of this embodiment is to realize the logic design of high-speed interfaces such as PXIe, Aurora, and DDR3, which is realized by using Xilinx XC7K325T and XC7K160T FPGA. The 7 series chip comes with PCIe hard core, official free open source Aurora soft core, and official MIG soft core, which can be used to realize the PXIe protocol physical layer and processing layer logic, Aurora high-speed serial protocol, and DDR3 SDRAM controller respectively.

[0060] Further, such as Figure 4 As shown, the key modules of the intermediate frequency unit high-speed data transmission and storage technology are composed of PXIe protocol implementation module, Aurora protocol implementation module and DDR3 storage control logic;

[0061] It should be noted that, considering that the system streaming speed of this embodiment is 500MB / s in a single channel, if the best streaming performance is to be achieved, the speed at which the underlying data is sent to the host computer is greater than the speed at which the host computer receives the streaming data. At the same time, considering the user operation and protocol overhead when the underlying unit initiates the DMA write operation, the theoretical transmission speed of the protocol for communication between the underlying and the host computer must be at least greater than 800MB / s. The Xilinx 7 series FPGA chip integrates the PCIe protocol Gen2 hard core inside. The transmission speed of a single link of the second-generation PCIe hard core is 5Gb / s. If the PCIe protocol of 4 links is configured, and because the PCIe protocol adopts the 8B / 10B encoding mechanism, the simplex peak transmission bandwidth of the PXIe bus is R = 5Gb / s*4*8 / 10 / 8 = 2GB / s, which meets the required theoretical transmission speed. Therefore, this embodiment finally selected the Xilinx 7 series FPGA solution to implement the PXIe high-speed transmission protocol.

[0062] It should be noted that the PXIe protocol logic module implements the host computer's control of the intermediate frequency unit, the reading and writing of the status register, and the DMA data communication. PXIe only expands some functions on the basis of the PCIe protocol, and finally realizes the solution using the Xilinx 7 series FPGA chip. The Xilinx 7 series FPGA chip has its own PCIe hard core, which implements the data link layer and physical layer functions of the PCIe protocol, and what the user needs to complete is the most programmable processing layer protocol specification. The user implements two functions through the application of the processing layer specification: one is that the host computer completes the reading and writing of the command register of the high-speed and large-capacity data acquisition unit through the PIO method, and the other is that the host computer and the high-speed and large-capacity data acquisition unit transmit data through the DMA method. Ultimately, for the designer, it is to implement the design of the PIO function logic and DMA controller based on the processing layer protocol specification. Specifically, to complete the PIO and DMA functions, the corresponding packet packaging and unpacking are performed according to the different transaction layer data packet protocols. The block diagram of the PXIe protocol module implementation can be seen in Figure 5 .

[0063] It should be explained that the key technologies involved in the implementation of the PXIe protocol are mainly: 1. Understanding and application of PCIe transaction layer protocol specifications such as data packet format, transaction type, packet encapsulation and unpacking, etc.; 2. Application of regulations such as maximum data payload and computer memory 4KB paging mechanism in the PXIe transaction layer logic design process; 3. Understanding the PXIe interrupt control mechanism and performing corresponding logic implementation.

[0064] It should be noted that in the signal streaming and playback system, sending data from the host computer to the XC7K325T is not the key to determining the system performance, but uploading the baseband signal and spectrum data to the host computer at the bottom layer determines the real-time display and data streaming speed of the entire system. Since the front-end AD sampling rate is 102.4M and the AD bit width is 14bit, only 1.4Gb / s of transmission bandwidth is required to meet the baseband signal upload requirements, and since the spectrum signal has been logarithmically processed, the data transmission speed requirement will be even lower. The minimum single link rate of the Aurora protocol is 3.125Gb / s. If 4 channels are selected, the simplex peak theoretical transmission bandwidth can reach 12.5Gb / s. Considering the user logic design overhead, it can also meet the system requirements well. The Aurora protocol has a soft core for users only in some Xilinx chips, and the PXIe protocol is implemented using Xilinx 7 series FPGA chips. In order to improve the integration of the system, this embodiment also uses a 4-channel Aurora protocol to implement communication between Xilinx FPGA chips, using two Xilinx 7 series FPGA chips, one of which integrates both the Aurora protocol and the PXIe protocol.

[0065] It should be noted that the Aurora high-speed serial communication protocol realizes the transmission between the intermediate frequency unit FPGA chips. First, the commands and parameters issued by the host computer are transmitted from XC7K325T to XC7K160T through the Aurora bus. Secondly, the output data of the signal processing module is transmitted from XC7K325T to XC7K160T through the Aurora protocol, and the flow control function is added to improve the effectiveness of the transmission. The block diagram of the Aurora protocol implementation module design is shown in the figure. Figure 6 As shown in the figure, the transmitted data is transmitted by the asynchronous interface module, directly sent to the Aurora user interface and receives the corresponding flow control signal; the received data is directly led out by the Aurora module user interface and received by the receiving module to the asynchronous interface module; the physical layer is encapsulated by the GTX hard core to complete the high-speed serial communication of the data. Xilinx 7 series FPGA provides Aurora soft core and comes with GTX hard core. To implement the Aurora protocol on the processing board, users need to first customize and generate the Aurora soft core according to user needs, and then appropriately adjust the Aurora protocol physical layer GTX hard core parameters according to the hardware test results, such as pre-emphasis, equalization, etc., and finally complete the data transmission, reception, flow control and other functions through the user interface.

[0066] It should be noted that PXI Express bus PIO (Programmable Input / Output) transactions are generally initiated by the host computer CPU, and the target is a peripheral device. The usual operation sequence is that the software controls the CPU to initiate a memory or IO read / write bus cycle on the host bus, and uses the address of the intermediate frequency unit PXIe device mapped in the PCIe bus domain as the target, and writes or reads the register array in the PXIe endpoint device through memory or IO read and write request transactions, that is, the PIO function can complete the host computer's reading and writing of the intermediate frequency unit control, status registers and parameters. It should be noted that whether the host computer sends instructions and parameters to the intermediate frequency unit or the intermediate frequency unit PXIe endpoint sends register status to the host computer, the request TLP is initiated by the host computer.

[0067] Furthermore, when the host computer reads the underlying instructions and parameter values, the CPU issues a memory read request transaction packet, in which the Fmt[2:0] and Type[4:0] of the TLP header jointly confirm that the TLP is a memory read request transaction packet, the Length field is the total data length of the register values ​​to be read, the address part is the IF unit register array address, and the Requester ID is the host computer's transaction ID. The Requester ID is very important in the memory read request transaction packet, because the memory read request transaction is a non-reporting transaction, and the return of the completion packet adopts the ID routing method. The requirements for other fields are relatively simple and can be written according to the requirements. The memory read request TLP has no load. When the IF unit PXIe endpoint receives this transaction packet, it parses it and parses the register array address. According to the parsed register array address, it is controlled by the trigger instruction sent by the control module to read the instructions and parameter values ​​in the register array according to the specified length. After reading the instructions and parameter values ​​of the corresponding addresses, the sending module initiates a memory read completion packet. The completion packet is used to respond to the memory read request initiated by the host computer. The load data it carries is the read instructions and parameter values. After the host computer successfully receives the completion packet, the instruction and parameter reading operation is completed.

[0068] It should be noted that in the signal streaming and playback system, the host computer and the bottom layer perform high-speed data transmission based on the PXIe protocol DMA method. DMA transmission is a method of directly accessing data from the host computer main memory without passing through the CPU. The entire data transmission process is operated by the DMA controller, which is an efficient data exchange mode. There are two ways of DMA data transmission: read and write. In this article, DMA read and write are both from the perspective of the bottom layer. The effect of DMA read is that the bottom layer directly reads the data in the host computer main memory in DMA mode, and DMA write is that the bottom unit directly writes data to the host computer main memory in DMA mode. It should be noted that whether it is DMA read or DMA write, the instruction setting is performed through the user interface of the signal streaming and playback system, and then the host computer sends the instruction to the intermediate frequency unit in PIO mode through the PXIe protocol. That is to say, although it is DMA read, the DMA read status and control instructions are first initiated by the host computer, and then the bottom PXIe endpoint initiates the memory read transaction to realize the DMA read function. The DMA data transmission of the PXIe protocol is an important part of this embodiment, and plays an important role in the streaming and playback speed of signal data. Its main applications include the sending of host computer reconfiguration data, frequency trigger templates, and test data, and uploading of spectrum data, baseband signals, frequency trigger templates and other data to the host computer main memory.

[0069] It should be noted that in the process of implementing DMA data transmission, the intermediate frequency unit designs the TLP receiving module, TLP sending module, DMA control logic, interrupt control and other modules of the endpoint device according to the PXIe protocol transaction layer specification. The design structure of the DMA data transmission of the PXIe protocol is as follows: Figure 7 As shown in the figure, the implementation of DMA transmission is based on the instruction and parameter transfer module based on the PIO function. It can be seen that the receiving module and sending module in the DMA transmission design are the same units as those in the PIO design, except that the types of data packets received and sent by these two modules in the DMA transmission design have increased. DMA transmission first uses PIO technology to implement the sending of host computer instructions and parameters, and then the bottom layer initiates memory write request TLP and memory read request TLP according to the information sent by the host computer to implement DMA write and DMA read operations respectively.

[0070] In the embodiment of the present application, when the host computer initiates a DMA transmission operation, the DMA initialization information, control and status information are first sent to the intermediate frequency unit terminal through the PIO method, and the DMA controller of the terminal device receives the data packet, stores the DMA initialization information, control and status information in the register array space of the corresponding address, and then triggers the start of DMA transmission through the register value in the register array. The DMA control logic performs segmentation and assembly of the data load or the requested data length according to the parameter value of the register array space. It should be noted that the 4KB boundary cannot be crossed during segmentation; the source and destination physical addresses are calculated and calculated one by one; and the source or destination transaction ID is parsed, etc., to provide all the required coding values ​​for the TLP header assembly.

[0071] In an embodiment of the present application, when the system performs a DMA read operation, the underlying PXIe terminal sending module sends multiple memory read request packets, and the upper computer returns a memory read completion packet. After receiving the data in the completion packet, the entire DMA read operation is completed; if it is a DMA write, the terminal sends a memory write request packet through the sending module, and carries the load data of the corresponding request address after the packet header, and sends it to the link through the sending module. After the data packet is sent, an interrupt is initiated, and the corresponding interrupt register flag is written to end the DMA process. The data read out during DMA reading is sent to the asynchronous FIFO, and the data source during DMA writing is another asynchronous FIFO. These two asynchronous FIFOs are connected to the Aurora protocol and DDR3 storage control logic through the interface module. The implementation design of DMA transmission mainly includes TLP receiving module, sending module, DMA control logic, register array, interrupt control module, etc. The design and implementation of key modules are described below in combination with the PXIe transaction layer protocol;

[0072] Specifically, the signal streaming and playback system is based on the DMA mode of the PXIe protocol for high-speed data transmission. In the process of implementing DMA transmission, the core of the operation and calculation of the start, end, and length of each partial DMA transmission of the entire DMA is the DMA control logic. The most important function of the DMA control logic is to provide the TLP sending module with a series of information such as the DMA transmission length, physical address, and DMA start signal required for each partial DMA transmission, and then the TLP sending module performs TLP header encapsulation and TLP header and payload data transmission based on this information. Due to the segmentation mechanism of the parameter generation module in the TLP sending module for the payload data length Length variable, a DMA transmission can only transmit a maximum of 4KB at a time, and the total amount of data transmitted at high speed between the bottom layer and the host computer far exceeds 4KB, so the concept of partial DMA transmission is added here. Partial DMA transmission is relative to the entire DMA transmission, that is, a longer DMA transmission process is divided into multiple sub-transmission processes with an integer multiple of 4KB in length. For example, if the upper computer needs to send 30KB of data to the lower layer, after the lower layer initiates DMA read, the 30KB is divided into seven 4KB partial DMA transfers and one 2KB partial DMA transfer. The specific division method is performed using the DMA parameter statistical state machine.

[0073] Specifically, the total length of DMA transmission, the starting physical address and the intermediate frequency storage address are first read from the register array, and the overall DMA start signal is also first set by the register array. The DMA read and write parameter statistics state machine will divide and count according to the received parameter values, and send the obtained parameters to the TLP sending state machine, and set the partial DMA read and write start signal at the same time. After receiving these signals and parameters, the TLP sending module starts the transaction header encapsulation and the subsequent transaction packet sending. The TLP sending module also performs DMA remaining length statistics while encapsulating the transaction header, and returns a partial DMA write completion signal. The partial DMA read signal is returned after the TLP receiving module receives the completion packet. The overall DMA read and write is divided into such partial DMAs for multiple operations. When all are completed, the DMA parameter statistics state machine will no longer initiate partial DMA read and write signals, and the last DMA read and write signal of the TLP sending and receiving modules determines that the entire DMA transmission process is completed.

[0074] Specifically, the DMA read and write control logics are basically similar, and the write state control state machine and the DMA write parameter statistics state machine in the write control logic are interrelated and influence each other, so the two state machines will be described at the same time, collectively referred to as the DMA write control logic state machine.

[0075] Specifically, the signal streaming and playback system adopts the Xilinx7 series FPGA chip solution for DDR3 storage control. The DDR3 storage control IP performance provided by Xilinx has the highest integration and storage rate in the FPGA industry. Therefore, the DDR3 storage controller in this embodiment is implemented based on the free IP core MIG1.8 provided by the Xilinx Kintex-7 series FPGA. The first thing to do when using the MIG soft core is to customize the IP. The Clock Period option determines the transmission frequency of DDR3 for data transmission. The selected frequency is 533.3MHz, so the equivalent transmission rate of DDR3 is 1066MHz. The PHY to controller clock ratio determines the ratio of the transmission frequency to the user clock, and 4:1 is usually selected. The Memory Type option is used to select whether the DDR3 used is a particle or a memory bar in different forms. At the XC7K160T chip, this embodiment uses DDR3 particles, so select Components here. Select the DDR3 model used in Memory Part. The model can indicate the bit width and capacity of DDR3. If the selected part does not have the DDR3 model you use, you can use the Create Custom Part button to customize the parameters. The Memory Voltage is the default 1.5V voltage. The Data Width is the data bit width connected to the MIG physics. In the Memory The DDR3 particles we selected in the Part section are 16 bits, and here it can be set to 8-72 bits. If it is less than 16, some pins will not be used, and if it is more than 16, the number of particles will be increased to expand the total bit width; the rest of the options are selected according to the requirements, and finally the physical and clock pins are bound to generate the MIG soft core.

[0076] Specifically, users operate DDR3 SDRAM in the form of commands. DDR3 memory mainly has the following commands: Auto Refresh, Active, Precharge, Write, and Read. Since the DDR3 memory storage medium is a dynamic random access memory, it is necessary to refresh the charge of the storage unit regularly to maintain the stored data. The activation command is used to open a storage space, and the precharge command is used to close the row storage space that has been opened. After that, DDR3 enters the idle state. If the activation command arrives, it will open a new storage space for operation. When the customized MIG soft core is completed, the MIG soft core in the project will start the initialization operation of DDR3 power-on. After the initialization is completed, the DDR3 memory enters the normal working state and waits for the control command of the MIG user interface at any time. When the host computer wants to send reconfiguration data to the IF unit, the host computer configures the IF unit registers, initiates DMA reads through the IF unit, and transmits the returned data to the DDR3 control interface for storage and then processing; if the IF unit has a large amount of data uploaded to the host computer, it can also use DDR3 cache first, and then transmit it to the host computer through DMA; in real-time and trigger modes, the baseband signal output by the digital down-conversion module and the processed signal after FFT transformation need to be cached in the DDR3 memory bar; the above three situations all require the use of the DDR3 control module, and the control logic is basically the same. The IF unit implements DDR3 control by calling the official soft core MIG (Memory Interface Generator), so the control of DDR3 is actually completed by controlling the user interface of the MIG soft core.

[0077] Therefore, it can be seen from the above that a multi-channel high-speed sampling data storage system and control method provided by the present invention can quickly receive and record and store eight-channel analog signals of electromagnetic disturbance, as well as monitor and receive PXIe bus digital quantities, and can completely read back the data in the memory by recycling the memory, thereby supporting the data preservation, playback and statistical functions of the online monitoring system for electromagnetic disturbance of electronic transformers.

[0078] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The scheme in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming language Java and literal scripting language JavaScript, etc.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0083] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multi-channel high-speed sampling data storage system, characterized in that: The multi-channel high-speed sampling data storage system includes a disk array, a host computer, a memory particle cache module, a PXIe transmission protocol module, an Aurora transmission protocol module, a memory bar cache module, a data acquisition and signal processing module, and an A / D conversion module; The A / D conversion module, the data acquisition and signal processing module, the Aurora transmission protocol module, the PXIe transmission protocol module, the host computer and the disk array are connected in sequence, the PXIe transmission protocol module is also connected to the memory particle cache module, and the data acquisition and signal processing module is connected to the Aurora transmission protocol module through the memory bar cache module; The memory particle cache module and the PXIe transmission protocol module are integrated in the first FPGA chip, and the Aurora transmission protocol module, the memory bar cache module, and the data acquisition and signal processing module are integrated in the second FPGA chip.

2. The multi-channel high-speed sampling data storage system according to claim 1, characterized in that: The A / D conversion module is composed of a front-end signal conditioning circuit and an A / D converter; The front-end conditioning circuit is composed of a high-speed operational amplifier and an analog quantity driving circuit. The analog quantity is amplified by a high-speed operational amplifier whose input impedance is greater than a preset impedance threshold and sent to a high-speed differential operational amplifier to provide a differential input for the A / D converter.

3. A control method for a multi-channel high-speed sampling data storage system according to any one of claims 1 to 2, characterized in that: include: The host computer sends control instructions in PIO mode through the PXIe transmission protocol module and sends reconfiguration data in DMA read mode. The first FPGA chip stores the received reconfiguration data in the memory particle cache module, and reads the configuration data according to the corresponding instructions to initiate reconfiguration of the second FPGA chip. After the reconfiguration of the second FPGA chip is completed, the first FPGA chip transmits control commands and parameters to the second FPGA chip through the Aurora transmission protocol module. The second FPGA chip receives the digital intermediate frequency signal converted by the A / D conversion module according to the control command and performs corresponding signal processing and logic control in the three modes of single point, real-time and trigger according to the control instructions issued by the host computer.

4. The multi-channel high-speed sampling data storage control method according to claim 3, characterized in that: include: In the real-time and trigger mode, the data after signal processing is sent to the memory bar cache module for caching, and the data to be sent by the second FPGA chip is transmitted to the first FPGA chip through the Aurora transmission protocol module. The first FPGA chip receives the processed data, and then sends the processed data to the host computer memory by the PXIe bus in the DMA write mode, for real-time display and decides whether the host computer transfers the data in the memory to the disk array according to user needs; When the radio frequency signal is played back, the host computer reads the data in the disk array for real-time display, or sends it to the bottom layer for triggering judgment.

5. The multi-channel high-speed sampling data storage control method according to claim 4, characterized in that: include: When the host computer starts data acquisition, the FPGA chip initializes and configures the A / D converter via the SPI bus; The FPGA chip detects whether the internal FIFO storage state is full. When the FIFO storage reaches the full state, the FPGA chip generates a low-level external interrupt request signal. After the host computer responds to the interrupt, it reads the data in the FIFO through the PXI bus. The FPGA chip detects whether the internal FIFO storage status is empty. When the FPGA chip receives the FIFO output empty signal, it generates an interrupt request signal to the host computer through the PXI bus again. After responding to the interrupt, the host computer queries the interrupt source. After detecting that the FIFO is an empty signal, the host computer stops reading FIFO data through the bus, and an AD acquisition task is completed at this time.

6. The multi-channel high-speed sampling data storage control method according to claim 5, characterized in that: include: After completing an AD acquisition task, the host computer writes a reset signal to the FPGA chip, so that the FPGA chip stops configuring the A / D converter, the AD conversion process is terminated, and the control process is terminated.

7. The multi-channel high-speed sampling data storage control method according to claim 6, characterized in that: include: When the host computer initiates a DMA transmission operation, the DMA initialization information, control and status information are sent to the intermediate frequency unit terminal through the PIO mode, and the DMA controller of the terminal device receives the data packet, stores the DMA initialization information, control and status information in the register array space of the corresponding address, and then triggers the start of DMA transmission through the register value in the register array; The DMA control logic divides and assembles the data load or the requested data length according to the parameter value of the register array space, calculates the source and destination physical addresses, and performs successive calculations to parse the source or destination transaction ID to provide all the required coding values ​​for the TLP packet header assembly.

8. The multi-channel high-speed sampling data storage control method according to claim 7, characterized in that: Also includes: When the system performs a DMA read operation, the bottom PXIe terminal sending module sends multiple memory read request packets, and the host computer returns a memory read completion packet. After receiving the data carried in the completion packet, the entire DMA read operation is completed.

9. The multi-channel high-speed sampling data storage control method according to claim 8, characterized in that: Also includes: When the system performs a DMA write operation, the terminal writes a request packet through the sending module memory, and carries the payload data of the corresponding request address after the packet header, and sends it to the link through the sending module. After the packet is sent, an interrupt is initiated, and the corresponding interrupt register flag is written to end the DMA process.

10. The multi-channel high-speed sampling data storage control method according to claim 9, characterized in that: Also includes: The data read out during DMA read operation is sent to an asynchronous FIFO, and the data source during DMA write operation is another asynchronous FIFO. These two asynchronous FIFOs are connected to the Aurora protocol and storage control logic through an interface module.

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