Wide tuning range Class C inductance-capacitance voltage-controlled oscillator

Abstract

The invention provides a Class C inductance-capacitance voltage-controlled oscillator with a wide tuning range, which belongs to the technical field of voltage-controlled oscillators and is composed of an LC resonance circuit and a negative resistance area circuit which are connected in parallel. The LC resonant circuit comprises an on-chip symmetrical spiral inductor, a switched capacitor array, a first variable capacitance tube CV1 and a second variable capacitance tube CV2; the negative resistance area circuit comprises a tail current tube M, a first filter capacitor C1, a second filter capacitor C2, a first cross coupling triode Q0, a second cross coupling triode Q1, a first resistor R0, a second resistor R1, a first filter inductor L3 and a second filter inductor L4; the negative resistance area circuit is connected with the LC resonance circuit; through the switched capacitor array and the two variable capacitance tubes which are matched with each other, the wide tuning range frequency output is realized, and through improving the structure of the switched capacitor array, the anti-interference performance is enhanced, and the phase noise is optimized at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of voltage-controlled oscillators, and in particular relates to a Class C inductor-capacitor voltage-controlled oscillator with a wide tuning range. Background Art

[0002] The function of the frequency synthesizer is to generate the required local oscillation signal for the mixer, so as to receive and transmit at the specified frequency. Since modern communication systems transmit signals at specific frequencies, frequency synthesizers are an indispensable part. The generation of local oscillation signals by frequency synthesizers must meet at least three requirements. First, the frequency must be accurate. Second, it must have low phase noise and low spurious. The spectrum is a clean single-frequency signal. Third, the clock signal must be generated in a very short time, that is, the locking time of the frequency synthesizer must be as short as possible, and it is required to lock to the required frequency in a short time.

[0003] The frequency synthesizer consists of a voltage-controlled oscillator (VCO) and a phase-locked loop. The VCO is the control object of the phase-locked loop. The output frequency range and out-of-band phase noise of the frequency synthesizer are usually determined by the VCO. The VCO first generates a clock signal that meets the phase noise within a certain frequency range, and then locks its frequency through the phase-locked loop. Therefore, it is very important to design a VCO that meets the tuning range requirements and low phase noise requirements.

[0004] Phase noise indicators are generally given for the operating frequency range and operating bias frequency of the VCO. For example, the phase noise indicator of the VCO in GSM (Global System for Mobile Communications) is -120dBc / Hz at an oscillation frequency of 1850~1910MHz and a bias frequency of 400KHz. Compared with the ring VCO, the inductor-capacitor voltage-controlled oscillator (LC VCO) can achieve lower phase noise at a higher resonant frequency. And in the VCO circuit design, a multi-bit switched capacitor array is used to meet the wide tuning range.

[0005] The adjustment range of the VCO determines the frequency range of the phase-locked loop, and the wide tuning range is the difficulty in VCO design. The specific reason is that the wide tuning range has great restrictions on the selectable inductance value and requires a large capacitor for frequency adjustment, which will greatly reduce the Q value of the VCO and increase the difficulty of VCO design.

[0006] In 1918, the capacitor feedback oscillator - Colpitts oscillator was proposed. On this basis, various innovative circuit structures were developed, such as Class-B oscillator, Class-C oscillator, Class-A oscillator, Class-F oscillator, Class-D oscillator, etc.

[0007] Among them, the traditional Class C voltage-controlled oscillator can ensure that the cross-coupled pair does not enter the triode region by adding an additional bias to the gate, thereby avoiding the load effect, while reducing the conduction angle and reducing phase noise.

[0008] Aiming at the Class-C oscillator, the present invention designs an LC VCO with a wide tuning range and a high Q value. Summary of the invention

[0009] In view of the problem of low frequency tuning range in existing VCOs, the present invention provides a Class C LC voltage-controlled oscillator with a wide tuning range.

[0010] In order to achieve the above purpose, the technical method adopted by the present invention is as follows:

[0011] A Class C inductor-capacitor voltage-controlled oscillator with a wide tuning range, consisting of an LC resonant circuit and a negative resistance region circuit;

[0012] The LC resonant circuit includes an on-chip symmetrical spiral inductor, a switch capacitor array, a first variable capacitor tube C V1 and the second variable capacitor C V2 ; In which, the power supply voltage VDD is applied in the middle of the on-chip symmetrical spiral inductor; the switch capacitor array is connected in parallel at both ends of the on-chip symmetrical spiral inductor; the first variable capacitor tube C V1 and the second variable capacitor C V2 First connect in series, then connect in parallel at both ends of the switch capacitor array, and then connect in parallel at the first variable capacitor tube C V1 and the second variable capacitor C V2 Apply control voltage V control ;

[0013] The negative resistance region circuit includes a tail current tube M, a first filter capacitor C1, a second filter capacitor C2, a first cross-coupled transistor Q0, a second cross-coupled transistor Q1, a first resistor R0, a second resistor R1, a first filter inductor L3 and a second filter inductor L4; wherein the base of the first cross-coupled transistor Q0 is connected to the collector of the second cross-coupled transistor Q1 through the second filter capacitor C2, and the base of the second cross-coupled transistor Q1 is connected to the collector of the first cross-coupled transistor Q0 through the first filter capacitor C1; at the same time, a bias voltage V is applied to the base of the first cross-coupled transistor Q0 through the first filter inductor L3. b , a bias voltage V is applied to the base of the second cross-coupled transistor Q1 through the second filter inductor L4. b The emitter of the first cross-coupled transistor Q0 is connected to the drain of the tail current tube M through the first resistor R0, and the emitter of the second cross-coupled transistor Q1 is connected to the drain of the tail current tube M through the second resistor R1; the gate of the tail current tube M is applied with a bias voltage Vbias , the source is grounded; the collector of the first cross-coupled transistor Q0 is connected to the first variable capacitor tube C V1 The collector of the second cross-coupled transistor Q1 is connected to the second variable capacitor C V2 One end of the negative resistance region circuit is connected in parallel with the LC resonant circuit;

[0014] The first variable capacitor C V1 The first filter capacitor C1 is used as an output terminal Z of the Class C inductor-capacitor voltage-controlled oscillator, and the second variable capacitor C V2 The other output terminal ZN of the Class C LC voltage-controlled oscillator is used between the second filter capacitor C2.

[0015] Furthermore, the on-chip symmetrical spiral inductor adopts a double-layer nested polygonal structure, the first layer includes a polygonal structure and a first half-polygonal structure, and the second layer includes a second half-polygonal structure; wherein, one side of the polygonal structure is broken, one end at the break is connected to one end of the first half-polygonal structure, and the other end at the break is connected to one end of the second half-polygonal structure through a metal through hole; the other end of the first half-polygonal structure and the other end of the first half-polygonal structure respectively serve as two connection taps of the on-chip symmetrical spiral inductor; the side of the polygonal structure opposite to the broken side is arranged to be used to connect the center tap of the power supply voltage VDD; the two connection taps are located close to the center tap.

[0016] Furthermore, the double-layer nested polygonal structure is at least a double-layer nested octagonal structure.

[0017] Further, the switch capacitor array includes a plurality of array units connected in parallel, each array unit including a first NMOS tube M0, a second NMOS tube M1, a PMOS tube M2, a first switch capacitor, a second switch capacitor, a third resistor R3 and a fourth resistor R4; wherein, the drain of the first NMOS tube M0 is connected to the output terminal Z through the first switch capacitor, and the source is connected to the output terminal ZN through the second switch capacitor; the drain of the second NMOS tube M1 is connected to the drain of the first NMOS tube M0 through the third resistor R3, and the source is grounded; the drain of the PMOS tube M2 is connected to the source of the first NMOS tube M0 through the fourth resistor R4, and the source is connected to the power supply voltage VDD; the gates of the first NMOS tube M0, the second NMOS tube M1 and the PMOS tube M2 are all connected to the external control terminal A0; the drains of the second NMOS tube M1 and the PMOS tube M2 are connected.

[0018] Furthermore, the power supply voltage VDD connected to the on-chip symmetrical spiral inductor and the power supply voltage VDD connected to the switch capacitor array may be the same or different.

[0019] Furthermore, the first NMOS transistor M0, the second NMOS transistor M1, and the PMOS transistor M2 are controlled to be turned on or not through the external control terminal A0, thereby adjusting the working state of the array unit. Specifically:

[0020] When the external control terminal A0 is set to 1, the first NMOS tube M0 and the second NMOS tube M1 are turned on, the PMOS tube M2 is turned off, the potential B0 at the drain of the second NMOS tube M1 and the potential B1 at the drain of the PMOS tube M2 are grounded and are at a low potential; at this time, the gate of the first NMOS tube M0 is connected to a high potential, the source and the drain are connected to a low potential, and the first NMOS tube M0 is fully turned on; this method can reduce the on-resistance of the first NMOS tube M0, and reduce the influence of the parasitic resistance of the first NMOS tube M0 on the frequency modulation range of the circuit;

[0021] When the external control terminal A0 is set to 0, the first NMOS tube M0 and the second NMOS tube M1 are turned off, the PMOS tube M2 is turned on, and the potentials of the points B0 and B1 are connected to the power supply voltage VDD and are at a high potential; at this time, the gate of the first NMOS tube M0 is connected to a low potential, and the source and the drain are connected to a high potential, and the first NMOS tube M0 is completely turned off, making the frequency modulation range more accurate, thereby improving the Q value of the Class C LC voltage-controlled oscillator and optimizing the circuit phase noise.

[0022] Furthermore, the first variable capacitor C V1 and the second variable capacitor C V2 It is an accumulation type NMOS variable capacitor.

[0023] Furthermore, by controlling each array unit to set the corresponding external control terminal A0 to 0 or 1, and the first variable capacitor C V1 and the second variable capacitor C V2 The capacitance value adjusts the output frequency tuning range of the Class C LC VCO.

[0024] Furthermore, when all array units corresponding to the external control terminal A0 are set to 1, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value of the Class C LC VCO is at the maximum value, the output frequency of the Class C LC VCO is the lowest; when all array units corresponding to the external control terminal A0 are set to 0, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value is at its minimum, the Class C LC VCO outputs the highest frequency.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] 1. The present invention proposes a Class C LC voltage-controlled oscillator with a wide tuning range. Through a matched switched capacitor array and two variable capacitors, the output of a wide tuning range frequency is achieved, which not only achieves a wide frequency coverage, but also avoids the phenomenon of phase noise deterioration caused by excessive K value caused by using variable capacitors alone to achieve a wide tuning range;

[0027] 2. The present invention improves the switch capacitor array structure to enhance its anti-interference performance. At the same time, the phase noise is significantly optimized over the traditional switch capacitor array structure, specifically, at a 1KHz frequency deviation, it is optimized by 3dBm;

[0028] 3. Preferably, the on-chip symmetrical spiral inductor adopts a double-layer octagonal structure. When the inductance value is constant, the Q value of the on-chip symmetrical spiral inductor can be improved, thereby improving the total Q value of the Class C LC voltage-controlled oscillator, optimizing the overall phase noise, and improving the overall performance of the Class C LC voltage-controlled oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A circuit diagram of a Class C LC voltage-controlled oscillator with a wide tuning range proposed in Example 1;

[0031] Figure 2 Schematic diagram of the structure of the on-chip symmetrical spiral inductor in Example 1;

[0032] Figure 3 The Q value and inductance value of the on-chip symmetrical spiral inductor in Example 1 vary with frequency;

[0033] Figure 4 is a circuit schematic diagram of an array unit of the switched capacitor array in Example 1;

[0034] Figure 5 is a cross-sectional view of the structure of the accumulation type NMOS variable capacitor in Example 1;

[0035] Figure 6 The output noise curve of the Class C LC voltage-controlled oscillator with a wide tuning range proposed in Example 1;

[0036] Figure 7A frequency coverage diagram of a Class C LC voltage-controlled oscillator with a wide tuning range proposed in Example 1;

[0037] Figure 8 is a circuit schematic diagram of an array unit of a conventional switched capacitor array in Example 1;

[0038] Fig. 9 Phase noise comparison curve of the Class C LC VCO with wide tuning range proposed in Example 1 and the Class C LC VCO based on traditional switched capacitor array. DETAILED DESCRIPTION

[0039] In order to further understand the present invention, the preferred embodiments of the present invention are described below in conjunction with the examples, but it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the invention. All raw materials of the present invention are not particularly limited in their sources, and can be purchased on the market or prepared according to conventional methods well known to those skilled in the art.

[0040] Example 1

[0041] This embodiment provides a Class C LC voltage-controlled oscillator with a wide tuning range, the circuit structure of which is as follows: Figure 1 As shown, it is composed of an LC resonant circuit and a negative resistance zone circuit.

[0042] The LC resonant circuit includes an on-chip symmetrical spiral inductor ( Figure 1 L1 and L2 in the switch capacitor array, the first variable capacitor C V1 and the second variable capacitor C V2 ; In which, the power supply voltage VDD is applied in the middle of the on-chip symmetrical spiral inductor; the switch capacitor array is connected in parallel at both ends of the on-chip symmetrical spiral inductor; the first variable capacitor tube C V1 and the second variable capacitor C V2 First connect in series, then connect in parallel at both ends of the switch capacitor array, and then connect in parallel at the first variable capacitor tube C V1 and the second variable capacitor C V2 Apply control voltage V control .

[0043] The negative resistance region circuit includes a tail current tube M, a first filter capacitor C1, a second filter capacitor C2, a first cross-coupled transistor Q0, a second cross-coupled transistor Q1, a first resistor R0, a second resistor R1, a first filter inductor L3 and a second filter inductor L4; wherein, the base of the first cross-coupled transistor Q0 is connected to the collector of the second cross-coupled transistor Q1 through the second filter capacitor C2, and the base of the second cross-coupled transistor Q1 is connected to the collector of the first cross-coupled transistor Q0 through the first filter capacitor C1, forming a cross-coupled negative resistance region, which is connected in parallel to the circuit to supplement the energy consumed by the inductor and capacitor, so that the energy in the resonant cavity is conserved; at the same time, a bias voltage V is applied to the base of the first cross-coupled transistor Q0 through the first filter inductor L3. b , a bias voltage V is applied to the base of the second cross-coupled transistor Q1 through the second filter inductor L4. b The emitter of the first cross-coupled transistor Q0 is connected to the drain of the tail current tube M through the first resistor R0, and the emitter of the second cross-coupled transistor Q1 is connected to the drain of the tail current tube M through the second resistor R1; the gate of the tail current tube M is applied with a bias voltage V bias , the source is grounded, and the working current of the tail current tube M determines the power consumption of the entire circuit, where V bias The size of is generated by another bias circuit; the collector of the first cross-coupled transistor Q0 is connected to the first variable capacitor tube C V1 The collector of the second cross-coupled transistor Q1 is connected to the second variable capacitor C V2 One end of the negative resistance circuit is connected in parallel with the LC resonant circuit.

[0044] The first variable capacitor C V1 The first filter capacitor C1 is used as an output terminal Z of the Class C inductor-capacitor voltage-controlled oscillator, and the second variable capacitor C V2 The other output terminal ZN of the Class C LC voltage-controlled oscillator is used between the second filter capacitor C2.

[0045] like Figure 2As shown, the on-chip symmetrical spiral inductor adopts a double-layer octagonal structure, the first layer includes a polygonal structure and a first half-polygonal structure, and the second layer includes a second half-polygonal structure; wherein, one side of the polygonal structure is broken, one end of the broken part is connected to one end of the first half-polygonal structure, and the other end of the broken part is connected to one end of the second half-polygonal structure through a metal through hole; the other end of the first half-polygonal structure and the other end of the first half-polygonal structure are respectively used as two connection taps tap1 and tap2 of the on-chip symmetrical spiral inductor; the side of the polygonal structure opposite to the broken side is set to connect to the center tap tap0 of the power supply voltage VDD; the two connection taps tap1 and tap2 are located close to the center tap tap0.

[0046] Since the on-chip symmetrical spiral inductor has both inductance and capacitance characteristics, the frequency characteristics of the inductor are divided into two sections with the self-resonance frequency point as the boundary: below the self-resonance frequency, the inductance value is positive; above the self-resonance frequency, the inductance value is negative, and the overall capacitance is present. At the self-resonance frequency point, the inductance and quality factor are both zero. Therefore, the self-resonance frequency determines the frequency band of the inductor and is an important indicator in the design. At the same time, the performance of passive devices is usually measured by the quality factor Q. For inductors, it can be defined as: the ratio of the net magnetic energy stored in the system to the energy loss in each cycle. The quality factor Q of the on-chip spiral inductor is a crucial parameter. It can determine the loss of the related impedance matching network and affect the filtering performance, circuit bandwidth, effective power, noise, etc.

[0047] Figure 3 The Q value and inductance value of the on-chip symmetrical spiral inductor change with frequency. It can be seen that as the frequency changes, the inductor behaves as inductive at low frequencies. At this time, the Q value of the inductor is relatively high. By selecting a suitable inductance value to design the inductor within this frequency range, a relatively good Q value can be obtained. When a certain frequency is reached, the inductance value of the inductor becomes 0. This frequency is called the self-excited oscillation frequency of the inductor. At this frequency, the Q value of the inductor is also 0. After exceeding this frequency, the inductor becomes capacitive. This area is an area that needs to be avoided during design, which will seriously affect the use function of the inductor. Figure 3 When the medium frequency is 20GHz, the inductance of the inductor is 269.22p, and its corresponding Q value is 52.34.

[0048] The switch capacitor array includes 15 array units connected in parallel, such as Figure 4As shown, each array unit includes a first NMOS tube M0, a second NMOS tube M1, a PMOS tube M2, a first switch capacitor Cu, a second switch capacitor Cu, a third resistor R3 and a fourth resistor R4; wherein, the drain of the first NMOS tube M0 is connected to the output terminal Z through the first switch capacitor Cu, and the source is connected to the output terminal ZN through the second switch capacitor Cu; the drain of the second NMOS tube M1 is connected to the drain of the first NMOS tube M0 through the third resistor R3, and the source is grounded; the drain of the PMOS tube M2 is connected to the source of the first NMOS tube M0 through the fourth resistor R4, and the source is connected to the power supply voltage VDD; the gates of the first NMOS tube M0, the second NMOS tube M1 and the PMOS tube M2 are all connected to the external control terminal A0; the drains of the second NMOS tube M1 and the PMOS tube M2 are connected.

[0049] The first NMOS transistor M0, the second NMOS transistor M1, and the PMOS transistor M2 are controlled to be turned on or not through the external control terminal A0. Specifically, by controlling whether the first NMOS transistor M0 is turned on or not, it is selected whether to connect the first switch capacitor Cu and the second switch capacitor Cu to the LC resonant circuit, thereby adjusting the working state of the array unit. Specifically:

[0050] When the external control terminal A0 is set to 1, the first NMOS tube M0 and the second NMOS tube M1 are turned on, the PMOS tube M2 is turned off, the potential B0 at the drain of the second NMOS tube M1 and the potential B1 at the drain of the PMOS tube M2 are grounded and are at a low potential; at this time, the gate of the first NMOS tube M0 is connected to a high potential, the source and the drain are connected to a low potential, the first NMOS tube M0 is fully turned on, and the first switch capacitor Cu and the second switch capacitor Cu are connected to the LC resonant circuit; this method can reduce the on-resistance of the first NMOS tube M0, and reduce the influence of the parasitic resistance of the first NMOS tube M0 on the frequency modulation range of the circuit;

[0051] When the external control terminal A0 is set to 0, the first NMOS tube M0 and the second NMOS tube M1 are turned off, the PMOS tube M2 is turned on, and the potentials of the points B0 and B1 are connected to the power supply voltage VDD and are at a high potential; at this time, the gate of the first NMOS tube M0 is connected to a low potential, the source and the drain are connected to a high potential, the first NMOS tube M0 is completely turned off, and the first switch capacitor Cu and the second switch capacitor Cu are not connected to the LC resonant circuit, so that the frequency modulation range is more accurate, thereby improving the Q value of the Class C LC voltage-controlled oscillator and optimizing the circuit phase noise.

[0052] The third resistor R3 and the fourth resistor R4 are connected in series at the drain and source ends of the first NMOS tube M0, which can reduce parasitic capacitance and reduce the noise input of the control signal, thereby improving the anti-interference performance of the switched capacitor circuit. The phase noise is improved by 3dBc / Hz@1kHz compared with before.

[0053] The drain parasitic capacitance of the first NMOS tube M0 and the second NMOS tube M1 is C d , W / L is the width-to-length ratio of the switch MOS tube. The tuning range of the switch capacitor array is affected by the parasitic capacitance C d The quality factor of the parallel capacitor is restricted by the on-resistance of the switch, so under the premise of not affecting the quality factor of the oscillator, the W / L ratio of the first NMOS tube M0 is made relatively large.

[0054] The first variable capacitor C V1 and the second variable capacitor C V2 It is an accumulation type NMOS variable capacitor with a structure such as Figure 5 As shown, it can withstand positive and negative voltages. G <V S , the electrons in the N well are repelled by the silicon oxide interface, forming a depletion region. At this time, the equivalent capacitance is obtained by the series connection of the oxide and depletion layer capacitances. The Q value of the cumulative NMOS variable capacitor is determined by the resistance between the source and the drain. When the capacitance of the cumulative NMOS variable capacitor changes from the minimum to the maximum, its Q value decreases from the maximum to the minimum. By changing V control The size of the first variable capacitor C is adjusted V1 and the second variable capacitor C V2 The capacitance value can be changed from the minimum value to the maximum value, thereby limiting the output frequency of the Class C LC VCO. This will affect the K value of the Class C LC VCO, which will directly affect the phase noise and performance of the Class C LC VCO.

[0055] By controlling each array unit to set the corresponding external control terminal A0 to 0 or 1, and the first variable capacitor C V1 and the second variable capacitor C V2 The capacitance value adjusts the output frequency tuning range of the Class C LC VCO.

[0056] When all array units correspond to the external control terminal A0 is set to 1, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value of the Class C LC VCO is at the maximum value, the output frequency of the Class C LC VCO is the lowest; when all array units corresponding to the external control terminal A0 are set to 0, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value is at its minimum, the Class C LC VCO outputs the highest frequency.

[0057] In the cross-coupled negative resistance region, the negative resistance generated by the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1 must be less than or equal to the equivalent parallel resistance 2R of the LC resonant circuit. p , the Class C LC VCO starts to oscillate; since the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1 are not turned on yet, the sum of their transconductances is large. m R p ≥1, the Class C LC VCO can oscillate and maintain oscillation; then when the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1 are turned on, the transconductance of the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1 decreases and increases respectively, and the Class C LC VCO gradually enters the Class C working state, and the transconductance and decrease, thereby reducing the current and power consumption.

[0058] The bases of the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1 are respectively added with a first filter capacitor C1 and a second filter capacitor C2 to isolate the voltage of the power supply or the ground. b A bias voltage is provided for the base of the first cross-coupled transistor Q0 and the second cross-coupled transistor Q1, so that when the Class C LC VCO operates in the Class C state, its current and voltage overlap range is smaller and the power consumption is lower. In addition, V b When connected to the circuit, some interference signals are filtered out by the first filter inductor L3 and the second filter inductor L4, which can reduce the interference of the outside world to the circuit.

[0059] The design simulation software Cadence virtuoso is used to simulate and design the Class C inductor-capacitor voltage-controlled oscillator with a wide tuning range provided in this embodiment, wherein the inductor model is modeled and simulated using the EMX software. The moment method used by the EMX software solves the integral form of the Maxwell equation in the frequency domain, obtains the surface current distribution of the metal, and then performs numerical integration according to the Green's function to obtain the field distribution at any point in the solution space. For on-chip passive devices, especially spiral inductors, which have a typical 3D layered structure, the calculation speed of the moment method will be faster than the finite algorithm.

[0060] Figure 6 This is the output noise curve of the Class C LC voltage-controlled oscillator with a wide tuning range proposed in this embodiment. High and low temperature mode simulations are performed from three process angles: tt, ff, and ss. It can be seen that the phase noise of different process angles is not much different, indicating that the Class C LC voltage-controlled oscillator with a wide tuning range proposed in this embodiment has high reliability.

[0061] Figure 7The frequency coverage diagram of the Class C LC VCO with a wide tuning range proposed in this embodiment shows that the control voltage V control When changing from 0.5V to 2.8V, the frequency coverage range of the Class C LC voltage-controlled oscillator can be "fine-tuned". At the same time, with the access of the switched capacitor array, by controlling whether the first switched capacitor Cu and the second switched capacitor Cu of each array unit are connected to the LC resonant circuit, the frequency coverage range can be "coarsely adjusted", thereby completing the frequency output with a wide tuning range.

[0062] This embodiment improves the switch capacitor array structure, which helps to enhance its anti-interference performance, and at the same time, the phase noise is significantly optimized compared with the traditional switch capacitor array structure. Figure 8 is a schematic diagram of the array unit structure of a traditional switched capacitor array. By comparing the phase noise of the Class C LC VCO with a wide tuning range proposed in this embodiment with that of the Class C LC VCO based on the traditional switched capacitor array, as shown in FIG. Fig. 9 As shown, it can be seen that the improved switched capacitor array in this embodiment optimizes the phase noise of the Class C LC voltage-controlled oscillator, and its phase noise is optimized by about 3dBc / Hz at a frequency offset from 1KHz to 1MHz.

[0063] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas, including the best mode, and also enables any technician in the field to practice the present invention, including making and using any device or system, and implementing any combined method. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention. The scope of patent protection of the present invention is defined by the claims and may include other embodiments that can be thought of by those skilled in the art. If these other embodiments have structural elements that are not different from the text of the claims, or if they include equivalent structural elements that are not substantially different from the text of the claims, then these other embodiments should also be included in the scope of the claims.

Claims

1. A Class C LC voltage-controlled oscillator with a wide tuning range, characterized in that: It is composed of LC resonant circuit and negative resistance zone circuit; The LC resonant circuit includes an on-chip symmetrical spiral inductor, a switch capacitor array, a first variable capacitor tube C V1 and the second variable capacitor C V2 ; In which, the power supply voltage VDD is applied in the middle of the on-chip symmetrical spiral inductor; the switch capacitor array is connected in parallel at both ends of the on-chip symmetrical spiral inductor; the first variable capacitor tube C V1 and the second variable capacitor C V2 First connect in series, then connect in parallel at both ends of the switch capacitor array, and then connect in parallel at the first variable capacitor tube C V1 and the second variable capacitor C V2 Apply control voltage V control ; The negative resistance region circuit includes a tail current tube M, a first filter capacitor C1, a second filter capacitor C2, a first cross-coupled transistor Q0, a second cross-coupled transistor Q1, a first resistor R0, a second resistor R1, a first filter inductor L3 and a second filter inductor L4; wherein the base of the first cross-coupled transistor Q0 is connected to the collector of the second cross-coupled transistor Q1 through the second filter capacitor C2, and the base of the second cross-coupled transistor Q1 is connected to the collector of the first cross-coupled transistor Q0 through the first filter capacitor C1; at the same time, a bias voltage V is applied to the base of the first cross-coupled transistor Q0 through the first filter inductor L3. b , a bias voltage V is applied to the base of the second cross-coupled transistor Q1 through the second filter inductor L4. b The emitter of the first cross-coupled transistor Q0 is connected to the drain of the tail current tube M through the first resistor R0, and the emitter of the second cross-coupled transistor Q1 is connected to the drain of the tail current tube M through the second resistor R1; the gate of the tail current tube M is applied with a bias voltage V bias , the source is grounded; the collector of the first cross-coupled transistor Q0 is connected to the first variable capacitor tube C V1 The collector of the second cross-coupled transistor Q1 is connected to the second variable capacitor C V2 One end of the negative resistance region circuit is connected in parallel with the LC resonant circuit; The first variable capacitor C V1 The first filter capacitor C1 is used as an output terminal Z of the Class C inductor-capacitor voltage-controlled oscillator, and the second variable capacitor C V2 The other output terminal ZN of the Class C LC voltage-controlled oscillator is used between the second filter capacitor C2.

2. The Class C LC-VC oscillator with a wide tuning range according to claim 1, characterized in that: The switch capacitor array includes a plurality of array units connected in parallel, each array unit including a first NMOS tube M0, a second NMOS tube M1, a PMOS tube M2, a first switch capacitor, a second switch capacitor, a third resistor R3 and a fourth resistor R4; wherein, the drain of the first NMOS tube M0 is connected to the output terminal Z through the first switch capacitor, and the source is connected to the output terminal ZN through the second switch capacitor; the drain of the second NMOS tube M1 is connected to the drain of the first NMOS tube M0 through the third resistor R3, and the source is grounded; the drain of the PMOS tube M2 is connected to the source of the first NMOS tube M0 through the fourth resistor R4, and the source is connected to the power supply voltage VDD; the gates of the first NMOS tube M0, the second NMOS tube M1 and the PMOS tube M2 are all connected to the external control terminal A0; the drains of the second NMOS tube M1 and the PMOS tube M2 are connected.

3. The Class C LC-VC oscillator with a wide tuning range according to claim 2, characterized in that: The first NMOS transistor M0, the second NMOS transistor M1, and the PMOS transistor M2 are controlled to be turned on or off by the external control terminal A0, thereby adjusting the working state of the array unit. Specifically: When the external control terminal A0 is set to 1, the first NMOS tube M0 and the second NMOS tube M1 are turned on, the PMOS tube M2 is turned off, the potential B0 at the drain of the second NMOS tube M1 and the potential B1 at the drain of the PMOS tube M2 are grounded and are at a low potential; at this time, the gate of the first NMOS tube M0 is connected to a high potential, the source and the drain are connected to a low potential, and the first NMOS tube M0 is fully turned on; When the external control terminal A0 is set to 0, the first NMOS tube M0 and the second NMOS tube M1 are turned off, the PMOS tube M2 is turned on, and the potentials of points B0 and B1 are connected to the power supply voltage VDD and are at a high potential; at this time, the gate of the first NMOS tube M0 is connected to a low potential, the source and the drain are connected to a high potential, and the first NMOS tube M0 is completely turned off.

4. The Class C LC-VC oscillator with a wide tuning range according to claim 3, characterized in that: By controlling each array unit to set the corresponding external control terminal A0 to 0 or 1, and the first variable capacitor C V1 and the second variable capacitor C V2 The capacitance value adjusts the output frequency tuning range of the Class C LC VCO.

5. The Class C LC-VC oscillator with a wide tuning range according to claim 4, characterized in that: When all array units correspond to the external control terminal A0 is set to 1, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value of the Class C LC VCO is at the maximum value, the output frequency of the Class C LC VCO is the lowest; when all array units corresponding to the external control terminal A0 are set to 0, and the first variable capacitor C V1 and the second variable capacitor C V2 When the capacitance value is at its minimum, the Class C LC VCO outputs the highest frequency.

6. The Class C LC-VCO with a wide tuning range according to claim 1, characterized in that: The on-chip symmetrical spiral inductor adopts a double-layer nested polygonal structure, wherein the first layer includes a polygonal structure and a first half polygonal structure, and the second layer includes a second half polygonal structure; wherein one side of the polygonal structure is broken, one end of the broken side is connected to one end of the first half polygonal structure, and the other end of the broken side is connected to one end of the second half polygonal structure through a metal through hole; the other end of the first half polygonal structure and the other end of the first half polygonal structure are respectively used as two connection taps of the on-chip symmetrical spiral inductor; the side of the polygonal structure opposite to the broken side is arranged to be used for connecting the center tap of the power supply voltage VDD; the two connection taps are located close to the center tap.

7. The Class C LC-VCO with a wide tuning range according to claim 6, characterized in that: The double-layer nested polygonal structure is at least a double-layer nested octagonal structure.

8. The Class C LC-VCO with a wide tuning range according to claim 1, characterized in that: The first variable capacitor C V1 and the second variable capacitor C V2 It is an accumulation type NMOS variable capacitor.

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