Waveform data acquisition method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to a waveform data acquisition method, electronic equipment and a storage medium, target data of each processing unit is captured through a target node specified by a user and compressed and stored in a cache, and the target data in the cache is transferred to a memory in each equipment period; wherein the step of capturing the target data of the f-th processing unit and compressing and storing the target data in the cache comprises the following steps of: screening data streams continuously output by the f-th processing unit according to a target node to obtain a data block comprising target node data; when the changed data blocks are cached, the change mark positions of the data blocks with the changed data are valid, and the change mark positions of the data blocks with the unchanged data are invalid. A user is allowed to specify a large number of target nodes or change the target nodes, recompiling is not needed, and the debugging efficiency is improved; and moreover, the occupied cache and memory space is reduced, and the hardware simulation speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a method for acquiring waveform data, an electronic device and a storage medium. Background Art

[0002] In the current hardware simulation system based on Boolean Processor (BP), in order to achieve full visual debugging, the general method is to capture the operation results of some nodes (such as all triggers in the netlist) and upload them to the HOST, and then the HOST performs software simulation on the gate-level netlist of the device under test (DUT) based on the status of these partial nodes, so as to obtain the waveform of all nodes in the gate-level netlist. The operation results of some nodes are captured by dynamically configuring a set of MUXs to select the outputs of some BPs. For example, there are 64 processing units in a cluster, and the outputs of 8 processing units are selected to capture to obtain the status of some nodes. Then the hardware design needs to deploy 8 64-to-1 MUXs, and the input selection of these MUXs is controlled in real time by instructions. The problems caused by such a design include:

[0003] First, due to the number of MUXs and the selection mechanism, no matter how the control signal changes, only the outputs of 8 processing units can be selected and captured at the same time. When the outputs of more than 8 processing units in a cluster need to be captured, some information capture will fail. To avoid this, the user design needs to be recompiled and additional constraints are imposed on the processing unit compiler, thereby reducing the execution efficiency of the processing unit instructions. For example, more wait instructions need to be inserted to prevent the operations that need to be captured from being executed in the same device cycle.

[0004] Second, when the user needs to select different node signals for capture, recompile and generate new instructions. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is: a method for acquiring waveform data, the method comprising the following steps:

[0006] S100, obtaining a target node specified by a user.

[0007] S200, capturing target data of each processing unit according to the target node and compressing and storing it in a cache, and transferring the target data in the cache to a memory in each device cycle; wherein the step of capturing target data of the fth processing unit and compressing and storing it in a cache includes:

[0008] S210 , filtering the data stream continuously output by the f th processing unit according to the target node to obtain a data block including the target node data.

[0009] S220, if the target data of the i-th data block in the current device cycle is different from the target data of the i-th data block in the previous device cycle, the target data of the i-th data block in the current device cycle is stored in the data cache, and at the same time, the status information of the change flag of the i-th data block in the current device cycle is set to valid and saved to the flag cache; otherwise, the target data of the i-th data block in the current device cycle is not stored, and only the status information of the change flag of the i-th data block in the current device cycle is set to invalid and saved to the flag cache.

[0010] The present invention has at least the following beneficial effects:

[0011] A waveform data acquisition method, electronic device, and storage medium provided in the first embodiment of the present invention obtain target data by capturing data of all nodes and filtering according to the target node specified by the user. While caching the changed data blocks, the change flag position of the data blocks with changed data is set to valid, and the change flag position of the data blocks with unchanged data is set to invalid, so as to facilitate the recovery of waveform data. The number of target nodes specified by the user is not limited by hardware, which not only allows the user to specify a large number of target nodes or change the target nodes without recompiling, thereby improving debugging efficiency; but also reduces the occupied cache and memory space, thereby improving the hardware simulation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A schematic diagram of a debugging system based on hardware simulation provided in Embodiment 1 of the present invention;

[0014] Figure 2 A schematic diagram of another debugging system based on hardware simulation provided in the first embodiment of the present invention;

[0015] Figure 3 A flow chart of a method for acquiring waveform data provided in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0018] See also Figure 1 , which shows a schematic diagram of a debugging system based on hardware simulation, the system includes: M target modules, wherein the jth target module includes K processing units BPC j and a capture module ProB j , each processing unit includes at least one node. Among them, BPC j ={BPC j,1 ,BPC j,2 ,…,BPC j,r ,…,BPC j,K}, BPC j,r For BPC j The rth processing unit in , the value of r ranges from 1 to K.

[0019] In one embodiment, the processing unit is a Boolean processor (BP) or a Field-Programmable Gate Array (FPGA). Other types of processing units similar to simulation also fall within the protection scope of the present invention.

[0020] A node is any logical element in a circuit that produces an observable signal.

[0021] In one embodiment, the node is a trigger, a register, a combinational logic, a signal line, a module or a subsystem interface. In one embodiment, the combinational logic is an adder or a decoder. Other types of logic elements that are selected and observe their state changes also fall within the scope of the present invention.

[0022] Further, please refer again Figure 1 , ProB j Includes: a mask module Mask j , K filters j , a packaging module Pack j And a data cache module Pbuffer j Filterj ={Filter j,1 ,Filter j,2 ,…,Filter j,r ,…,Filter j,K}, Filter j,r Filter j The rth filter in .

[0023] Furthermore, the mask module Mask j , used to obtain the target node specified by the user.

[0024] It should be noted that in the prior art, if the user wants to view all waveforms, since only the information of some nodes is captured, in order to achieve visual debugging of all waveforms, the software needs to perform gate-level netlist simulation on the HOST side according to the captured node information to restore the waveforms of all nodes. This will cause the user to wait for a long time to get the waveform file during the debugging process. The system provided by the embodiment of the present invention allows the user to arbitrarily specify the target node, or specify all nodes as the target node. When the user specifies some target nodes or specifies all nodes, the system stores the data of all target nodes specified by the user into the memory to achieve waveform visualization, and there is no need to recompile or software simulation to restore the data. When the user changes the specified target node, the system does not need to recompile, and only needs to re-acquire the data of the changed part of the target node and re-store it into the memory.

[0025] Further, K filters j , respectively with the Mask j Connect, and each filter is connected to a processing unit; among them, the rth filter Filter j,r Connect the BPC j The rth processing unit BPC j,r , used to obtain BPC j,r Continuously output the data stream and filter the BPC j,r The data flow of the target node is obtained to obtain the target data.

[0026] Among them, in the ProB of the jth target module j Each filter is associated with a Mask j Connection, Mask j Send the acquired user-specified target nodes to ProB at the same time j All filters within.

[0027] Among them, ProB of the jth target module j Each filter is connected to its corresponding processor unit. j,rConnect BPC j,r For example, Filter j,r It is used to obtain the data stream continuously output by the processor, and then filter the target data of the target node specified by the user.

[0028] Further, the packaging module Pack j , and Filter j All filters in are connected to receive target data and package it.

[0029] Furthermore, the data cache module Pbuffer j , with the Pack j connection, used to cache target data, and each device cycle will be the Pbuffer j The target data in the memory is transferred to the memory, and the target data in the memory is used to present a full visible waveform.

[0030] That is, when the processing unit operation of a device cycle is completed, Pbuffer j It will be packaged into a data frame and then transferred to the memory. The device cycle is also called the DUT cycle. The frame header of the data frame contains timestamp and identity coding information, which is used to present a fully visible waveform.

[0031] Embodiment 1 of the present invention configures a capture module for each group of K processing units, and the capture module includes a mask module and a filter configured for each processing unit, wherein the mask module is used to obtain the target node specified by the user and send it to each filter, and each filter screens out the target data of the target node in the data stream continuously output by the corresponding processor, and finally the target data is packaged by the capture module and sent to the memory. In the system provided by the present invention, the number of target nodes specified by the user is not limited by hardware. When the user needs to specify more than 8 processing units or change the target node, there is no need to recompile. When the user needs to view the data of all nodes, there is no need to restore the waveform through software simulation, and the waveform data is obtained according to the target data, thereby improving the debugging efficiency.

[0032] In one embodiment, in order to solve the problem of storage space occupation and hardware simulation speed reduction due to data transmission bandwidth limitation, the packaging module and the Filter j There is also a change detection module connected between each filter.

[0033] It should be noted that the number of filters and change detection modules is the same, and each filter is configured with a change detection module.

[0034] Furthermore, the Pack j With the Filter j,rChange detection module connected between j,r , used to detect whether the target data in the current data block has changed compared to the target data of the corresponding data block in the previous device cycle. If the target data has changed, the current target data is sent to the packaging module; otherwise, it is not sent. For ease of understanding, please refer to Figure 2 , in ProB j It also includes K change detection modules. The first change detection module is change j,1 Connect in Pack j With the Filter j,1 Between, the second change detection module change j,2 Connect in Pack j With the Filter j,2 Between, and so on, the Kth change detection module change j,K Connect in Pack j With the Filter j,K between.

[0035] The change detection module only sends the changed data to the packaging module, that is, the packaging module only stores the data that has changed in adjacent cycles, which greatly reduces the cache and memory usage. At the same time, since the amount of data that needs to be uploaded to the memory is reduced, the pressure on the data transmission bandwidth is reduced and the hardware simulation speed is improved.

[0036] In one embodiment, the change j,r It is also used to generate status information of a change flag. When the target data changes, the status information of the change flag of the data block to which the target data belongs is set to be valid; otherwise, it is set to be invalid.

[0037] The status information of the change flag is used to identify the change of the data in the data block continuously output by the current processing unit, and is used to present the waveform in combination with the changed target data stored in the memory. That is, when the status information of the change flag is valid, the target data in the memory is sequentially obtained as the data information of the current data block; when the status information of the change flag is invalid, the data information of the corresponding data block in the previous device cycle is used as the data information of the current data block. When sequentially obtaining the target data in the memory, according to the Mask j The data width of the target node specified by the user is used to obtain the target data of the same width in the memory. For example, when the target node specified by the user is 16-bit data, the 16-bit target data is sequentially taken from the memory.

[0038] The data block is a fixed-size data segment divided from the data stream continuously output by the processing unit. For example, when the size of the data stream continuously output by the processing unit is 512 bits and the fixed size of the data block is 32 bits, 512 bits can be divided into 16 data blocks. If any bit in the current data block changes compared to the corresponding data block in the previous device cycle, the current data block is considered different from the previous data block, that is, the status information of the change flag bit is set to valid.

[0039] In one embodiment, please refer again to Figure 2 The j-th target module also includes: a flag buffer module Fbuffer j , Fbuffer j It is connected to each change detection module in the j-th target module, and is used to sequentially save the state information of the change flag bits of all data blocks in all processing units, and the state information of the change flag bits is used to restore the visualized waveform.

[0040] In one embodiment, the change j,r It also includes: current data cache, temporary storage module and comparison module. Among them, the current data cache is directly connected to the Filter j,r The temporary storage module is connected to the current data cache and is used to cache the target data of each data block in the previous device cycle. The comparison module is connected to the current data cache and the temporary storage module respectively, and is used to compare whether the target data of the current data block is the same as the target data of the corresponding data block in the previous device cycle. If they are the same, there is no change; otherwise, the target data changes.

[0041] In one embodiment, the system further comprises:

[0042] The upload control module is respectively connected to the flag cache module and the data cache module in each capture module, and is used to initiate an upload request when the flag cache module is full of data for a device cycle; and generate a stop clock request when the flag cache module and / or the data cache module reaches an overflow threshold.

[0043] The stop clock request is used to request the system to stop the clock, thereby stopping the further flow of data into the corresponding cache module until there is enough space in the cache module to store new data. By stopping the clock in time, data loss or system errors can be avoided, thereby ensuring the correctness and integrity of data processing.

[0044] Embodiment 2

[0045] Please refer to 3, which shows a method for acquiring waveform data, the method comprising the following steps:

[0046] S100, obtaining a target node specified by a user.

[0047] S200, capturing target data of each processing unit according to the target node and compressing and storing it in a cache, and transferring the target data in the cache to a memory in each device cycle.

[0048] It should be noted that the target node, processing unit, target data, device cycle, cache and memory in the first embodiment are all applicable to the second embodiment of the present invention and will not be described in detail.

[0049] The step of capturing the target data of the fth processing unit and compressing and storing it in the cache includes:

[0050] S210 , filtering the data stream continuously output by the f th processing unit according to the target node to obtain a data block including the target node data.

[0051] Among them, S210 also includes:

[0052] S211, obtaining a data stream continuously output by the f-th processing unit, wherein the data stream includes data of all nodes.

[0053] S212, dividing the data stream into a plurality of data blocks according to a preset size. It should be noted that each data block is bound to its own unique identification, and the unique identification of the data block is used to identify the order of data in the data stream to prevent data confusion.

[0054] S213, filtering out data that does not belong to the target node in each data block according to the target node, to obtain a data block including the target data of the target node.

[0055] It should be noted that the unique identifier bound to the data block including the target data obtained after filtering remains unchanged.

[0056] S220, if the target data of the i-th data block in the current device cycle is different from the target data of the i-th data block in the previous device cycle, the target data of the i-th data block in the current device cycle is stored in the data cache, and at the same time, the status information of the change flag of the i-th data block in the current device cycle is set to valid and saved to the flag cache; otherwise, the target data of the i-th data block in the current device cycle is not stored, and only the status information of the change flag of the i-th data block in the current device cycle is set to invalid and saved to the flag cache. The status information of the change flag is used to restore the waveform data.

[0057] Among them, it compresses data by storing the data blocks that have changed in the previous and next cycles, which not only reduces the occupied cache and memory space; but also reduces the pressure on data transmission bandwidth and improves the hardware simulation speed because the amount of data that needs to be uploaded to the memory is greatly reduced. While caching the data blocks that have changed in the previous and next cycles, the change flag position of the data block that has changed is valid, and the change flag position of the data block that has not changed is invalid. When presenting the waveform, it identifies whether the data of the current data block is the same as the previous cycle based on the status information of the change flag. If the same, the data of the corresponding data block in the previous cycle is directly used as the data of the current data block; if different, the corresponding data is sequentially retrieved from the memory.

[0058] In one embodiment, when the data stream continuously output by the processing unit in a device cycle is divided into T data blocks, the T data blocks of a device cycle are compared with the corresponding data blocks of the previous cycle T times in sequence, and T change flag status information is generated in sequence.

[0059] In one embodiment, the status information of the change flag is valid when it is set to 1. It is invalid when the status information of the change flag is set to 0. Other status information representations of the change flag defined as valid or invalid fall within the protection scope of the present invention.

[0060] In one implementation, S220 further includes:

[0061] S221, when the flag buffer is full of data for one device cycle, an upload request is initiated.

[0062] In one embodiment, in S200, the step of moving the target data in the cache to the memory in each device cycle further includes:

[0063] S230, receiving upload requests from each target module in the system.

[0064] S240, arbitrate all received upload requests, select a target upload request and authorize its corresponding target module to store the data in its flag buffer into the memory.

[0065] In one implementation, S220 further includes:

[0066] S222: When at least one of the data cache and the flag cache reaches an overflow threshold, a clock stop request is generated.

[0067] It should be noted that there is no order of precedence between S221 and S222, and they are treatment measures under two different conditions.

[0068] Furthermore, the method further comprises:

[0069] S300, presenting waveform data, wherein the step of recovering target data of the i-th data block in the waveform includes:

[0070] S310, when the status information of the change flag of the i-th data block is valid, the target data width of the target node included in the i-th data block is obtained, and the data of the target data width is sequentially retrieved from the memory. It should be noted that when the user specifies the target node, the data width of the target node is also specified.

[0071] S320: When the status information of the change flag is invalid, the data of the corresponding data block in the previous cycle is used as the data of the current database.

[0072] The method can quickly and losslessly restore waveform data. In the method provided by the present invention, it is not necessary to select some nodes for output through a multiplexer, but directly obtain the node data of all processors and grant the user the right to configure, and filter the data according to the target node specified by the user. That is, when the user wants to capture more target nodes or change the target node, the configuration can be performed directly without recompiling or restoring the waveforms of all nodes through gate-level netlist simulation. Not only does it reduce the memory usage, but it can also obtain the data of the target node more flexibly, thereby improving the debugging efficiency.

[0073] Embodiment 2 of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processing unit to implement the method provided in the above embodiment.

[0074] Embodiment 2 of the present invention further provides an electronic device, including a processing unit and the aforementioned non-transitory computer-readable storage medium.

[0075] Embodiment 2 of the present invention further provides a computer program product, which includes program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0076] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0077] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for acquiring waveform data, characterized in that: The method comprises the following steps: S100, obtaining a target node specified by a user; S200, capturing target data of each processing unit according to the target node and compressing and storing it in a cache, and transferring the target data in the cache to a memory in each device cycle; wherein the step of capturing target data of the fth processing unit and compressing and storing it in a cache includes: S210, filtering the data stream continuously output by the f-th processing unit according to the target node to obtain a data block including the target node data; S220, if the target data of the i-th data block in the current device cycle is different from the target data of the i-th data block in the previous device cycle, the target data of the i-th data block in the current device cycle is stored in the data cache, and at the same time, the status information of the change flag of the i-th data block in the current device cycle is set to valid and saved to the flag cache; otherwise, the target data of the i-th data block in the current device cycle is not stored, and only the status information of the change flag of the i-th data block in the current device cycle is set to invalid and saved to the flag cache.

2. The method according to claim 1, characterized in that The S210 also includes: S211, obtaining a data stream continuously output by the f-th processing unit, wherein the data stream includes data of all nodes; S212, dividing the data stream into a plurality of data blocks according to a preset size; S213, filtering out data that does not belong to the target node in each data block according to the target node, to obtain a data block including the target data of the target node.

3. The method according to claim 1, characterized in that The S220 also includes: S221, when the flag buffer is full of data for one device cycle, an upload request is initiated.

4. The method according to claim 3, characterized in that The step of moving the target data in the cache to the memory in each device cycle also includes: S230, receiving upload requests from various target modules in the system; S240, arbitrate all received upload requests, select a target upload request and authorize its corresponding target module to store the data in its flag buffer into the memory.

5. The method according to claim 1, characterized in that The S220 also includes: S222: When at least one of the data cache and the flag cache reaches an overflow threshold, a clock stop request is generated.

6. The method according to claim 1, characterized in that When the data stream continuously output by the processing unit is divided into T data blocks in a device cycle, the T data blocks of a device cycle are compared with the corresponding data blocks of the previous cycle T times in sequence, and the status information of T change flags are generated in sequence.

7. The method according to claim 1, characterized in that When the state information of the change flag bit is set to 1, it is valid. When the state information of the change flag bit is set to 0, it is invalid.

8. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by the processor to implement the method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The invention comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 8.

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