Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, relates to the technical field of display, and is used for improving the brightness consistency of the display panel. The first scanning driving unit is electrically connected with the first scanning control end of the first pixel driving circuit and the first scanning control end of the second pixel driving circuit. The working cycle of the pixel driving circuit comprises a data writing time period, and the data writing time period of the first pixel driving circuit is before the data writing time period of the second pixel driving circuit in the display time of one frame of picture; moreover, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, the potential VN11 of a first node in the first pixel driving circuit is greater than the potential VN12 of a first node in the second pixel driving circuit after respective data writing periods.

Description

[0001] This application is a divisional application with the application date of June 29, 2022, application number 202210757542.8, and invention name “Display panel, driving method thereof, and display device”.

Technical field

[0002] The present invention relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. [Background Technology]

[0003] Organic Light Emitting Diode (OLED) display panels have gradually become the mainstream display technology for mobile phones, televisions, computers and other displays due to their self-luminescence, fast response, wide color gamut, large viewing angle and high brightness.

[0004] OLED display panels include multiple sub-pixels in the display area and a driver circuit in the non-display area that illuminates the sub-pixels. Currently, display panels have issues with excessively large non-display areas and poor brightness consistency across the display area during display. [Summary of the invention]

[0005] In view of this, embodiments of the present invention provide a display panel, a driving method thereof, and a display device, so as to reduce the width of a non-display area of ​​the display panel and improve the brightness uniformity of the display panel.

[0006] In one aspect, an embodiment of the present invention provides a display panel, comprising:

[0007] A plurality of pixel groups, each pixel group including B pixel rows, where B is an integer and B is greater than or equal to 2; each pixel row including a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor being electrically connected to a first node, and a first electrode of each driving transistor being electrically connected to a second node;

[0008] a first scan driving unit electrically connected to a plurality of the first scan control terminals in the same pixel group;

[0009] The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level to the first scanning control terminal;

[0010] The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit. During the display time of one frame, a data writing period of the first pixel driving circuit is before a data writing period of the second pixel driving circuit. When the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the potential of the first node in the first pixel driving circuit is V N11 , the potential of the first node in the second pixel driving circuit is V N12 , V N11 >V N12 .

[0011] In another aspect, an embodiment of the present invention provides a display panel, including:

[0012] A plurality of pixel groups, each pixel group including B pixel rows, where B is an integer and B is greater than or equal to 2; each pixel row including a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor being electrically connected to a first node, and a first electrode of each driving transistor being electrically connected to a second node;

[0013] a first scan driving unit electrically connected to a plurality of the first scan control terminals in the same pixel group;

[0014] The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives an effective level and the first scanning driving unit provides an effective level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit, and within the display time of one frame of picture, the data writing period of the first pixel driving circuit is located before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage current speed of the first node in the first pixel driving circuit is v N11 , the leakage current speed of the first node in the second pixel driving circuit is v N12 , v N11 <v N12 .

[0015] In another aspect, an embodiment of the present invention provides a method for driving a display panel, the display panel comprising:

[0016] A plurality of pixel groups, each pixel group including B pixel rows, where B is an integer and B is greater than or equal to 2; each pixel row including a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor being electrically connected to a first node, and a first electrode of each driving transistor being electrically connected to a second node;

[0017] a first scan driving unit electrically connected to a plurality of the first scan control terminals in the same pixel group;

[0018] The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level and the first scanning driving unit provides a valid level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit;

[0019] The driving method includes:

[0020] During the display time of one frame, the data writing period of the first pixel driving circuit is controlled to be before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the potential of the first node in the first pixel driving circuit is controlled to be V N11 , the potential of the first node in the second pixel driving circuit is V N12 , V N11 >V N12 .

[0021] In another aspect, an embodiment of the present invention provides a method for driving a display panel, the display panel comprising:

[0022] A plurality of pixel groups, each pixel group including B pixel rows, where B is an integer and B is greater than or equal to 2; each pixel row including a plurality of pixel driving circuits, each pixel driving circuit including a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor being electrically connected to a first node, and a first electrode of each driving transistor being electrically connected to a second node;

[0023] a first scan driving unit electrically connected to a plurality of the first scan control terminals in the same pixel group;

[0024] The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level and the first scanning driving unit provides a valid level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit;

[0025] The driving method includes:

[0026] During the display time of one frame, the data writing period of the first pixel driving circuit is controlled to be before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage current speed of the first node in the first pixel driving circuit is controlled to be v N11 , the leakage current speed of the first node in the second pixel driving circuit is v N12 , v N11 <v N12 .

[0027] In yet another aspect, an embodiment of the present invention provides a display device including the above-mentioned display panel.

[0028] The display panel, its driving method, and display device provided by the embodiments of the present invention can reduce the number of first scan driving units required for the display panel by electrically connecting the first scan driving unit to multiple first scan control terminals in the same pixel group, thereby reducing the space occupied by the first scan driving circuit in the non-display area, which is beneficial to improving the screen-to-body ratio of the display panel.

[0029] Moreover, when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period of the first pixel driving circuit and the second pixel driving circuit, that is, when the data writing transistors of the first pixel driving circuit and the second pixel driving circuit are turned off, the embodiment of the present invention makes V N11 >V N12 , which can make up for or even eliminate the difference in leakage time between the first node of the first pixel driving circuit and the first node of the second pixel driving circuit. After entering the light-emitting stage, the potentials of the first nodes of the first pixel driving circuit and the second pixel driving circuit can be made consistent, which is beneficial to improving the brightness consistency of the light-emitting elements driven by the two.

Brief Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A schematic diagram of a partial area of ​​a display panel provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0033] Figure 3 An operation timing diagram of a first pixel driving circuit and a second pixel driving circuit provided by an embodiment of the present invention;

[0034] Figure 4 A schematic diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0035] Figure 5 for Figure 4 Corresponding working timing diagram;

[0036] Figure 6 A schematic diagram of a second scanning circuit provided by an embodiment of the present invention;

[0037] Figure 7 A circuit diagram of a second scan driving unit provided by an embodiment of the present invention;

[0038] Figure 8 for Figure 6 A corresponding working timing diagram;

[0039] Figure 9 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention;

[0040] Figure 10 for Figure 9 Corresponding working timing diagram;

[0041] Figure 11 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention;

[0042] Figure 12 for Figure 11 A corresponding working timing diagram;

[0043] Figure 13 for Figure 6 Another corresponding working timing diagram;

[0044] Figure 14 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention;

[0045] Figure 15 A schematic diagram of a connection relationship between a first pixel driving circuit and a second pixel driving circuit provided by an embodiment of the present invention;

[0046] Figure 16 A schematic diagram of a partial area of ​​another display panel provided by an embodiment of the present invention;

[0047] Figure 17 A circuit diagram of a light-emitting driving unit provided by an embodiment of the present invention;

[0048] Figure 18 A connection diagram of a light-emitting drive circuit provided by an embodiment of the present invention;

[0049] Figure 19 A schematic diagram of a method for driving a display panel provided by an embodiment of the present invention;

[0050] Figure 20 Schematic diagram of another display panel driving method provided by an embodiment of the present invention

[0051] Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0052] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0054] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0055] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0056] It should be understood that although the terms first, second, etc. may be used to describe pixel driving circuits in embodiments of the present invention, these pixel driving circuits should not be limited to these terms. These terms are only used to distinguish pixel driving circuits located in different pixel rows from each other. For example, without departing from the scope of embodiments of the present invention, a first pixel driving circuit may also be referred to as a second pixel driving circuit, and similarly, a second pixel driving circuit may also be referred to as a first pixel driving circuit.

[0057] An embodiment of the present invention provides a display panel, such as Figure 1 As shown, Figure 1This is a schematic diagram of a portion of a display panel provided in an embodiment of the present invention. The display panel includes a display area AA and a non-display area NA. The display area AA includes multiple pixel groups 1 arranged along a first direction h1. Each pixel group 1 includes B pixel rows 10 arranged along the first direction h1, where B ≥ 2 and B is an integer. The pixel rows 10 include multiple pixel driving circuits 100 arranged along a second direction h2. Figure 1 Assume that B=2, that is, one pixel group 1 includes two pixel rows 10 , one pixel row 10 includes a first pixel driving circuit 101 , and the other pixel row 10 includes a second pixel driving circuit 102 .

[0058] like Figure 2 As shown, Figure 2This is a schematic diagram of a pixel driving circuit provided by an embodiment of the present invention. The pixel driving circuit 100 includes a driving transistor M0, a data writing transistor M11, a threshold compensation transistor M12, a first node reset transistor M13, a light-emitting element reset transistor M14, a second light-emitting control transistor M15, a first light-emitting control transistor M16, and a storage capacitor Cst. The control electrode of the driving transistor M0 is electrically connected to the first node N11, the first electrode of the driving transistor M0 is electrically connected to the second node N12, and the second electrode of the driving transistor M0 is electrically connected to the third node N13. The control electrode of the data writing transistor M11 is electrically connected to the data writing control terminal S1, the first electrode of the data writing transistor M11 is electrically connected to the data voltage terminal Vdata, and the second electrode of the data writing transistor M11 is electrically connected to the second node N12. The control electrode of the threshold compensation transistor M12 is electrically connected to the first scanning control terminal S21, the first electrode of the threshold compensation transistor M12 is electrically connected to the third node N13, and the second electrode of the threshold compensation transistor M12 is electrically connected to the first node N11. The control electrode of the first-node reset transistor M13 is electrically connected to the second scan control terminal S22, the first electrode of the first-node reset transistor M13 is electrically connected to the first reset terminal Ref1, and the second electrode of the first-node reset transistor M13 is electrically connected to the first node N11. The control electrode of the light-emitting element reset transistor M14 is electrically connected to the data write control terminal S1, the first electrode of the light-emitting element reset transistor M14 is electrically connected to the second reset terminal Ref2, and the second electrode of the light-emitting element reset transistor M14 is electrically connected to the fourth node N14. The control electrode of the first light-emitting control transistor M16 is electrically connected to the light-emitting control terminal E, the first electrode of the first light-emitting control transistor M16 is electrically connected to the third node N13, and the second electrode of the first light-emitting control transistor M16 is electrically connected to the fourth node N14. The control electrode of the second light-emitting control transistor M15 is electrically connected to the light-emitting control terminal E, the first electrode of the second light-emitting control transistor M15 is electrically connected to the first power supply voltage terminal PVDD, and the second electrode of the second light-emitting control transistor M15 is electrically connected to the second node N12. The first plate of the storage capacitor Cst is electrically connected to the first node N11, and the second plate is electrically connected to the first power supply voltage terminal PVDD. One terminal of the light emitting element 200 is electrically connected to the fourth node N14, and the other terminal is electrically connected to the second power supply voltage terminal PVEE.

[0059] Exemplarily, the first node reset transistor M13 and the threshold compensation transistor M12 may be oxide transistors, such as indium gallium zinc oxide (IGZO) transistors, so that the first node reset transistor M13 and the threshold compensation transistor M12 have a smaller off-state leakage current, thereby improving the potential stability of the first node N11. In particular, when the display panel is operating in a low-frequency mode, the potential of the first node N11 needs to be maintained for a longer period of time. The first node reset transistor M13 and the threshold compensation transistor M12 electrically connected to the first node N11 are configured as IGZO transistors, thereby ensuring uniform brightness in low-frequency displays.

[0060] When the display panel is displaying, Figure 2 and Figure 3 As shown, Figure 3 This is a working timing diagram of a first pixel driving circuit and a second pixel driving circuit provided by an embodiment of the present invention. The working processes of the first pixel driving circuit 101 and the second pixel driving circuit 102 both include a first reset period TR1, a data writing period and a light emitting period TE. Figure 3 TW_101 in FIG. 1 represents a data writing period for the first pixel driving circuit 101 , and TW_102 represents a data writing period for the second pixel driving circuit 102 .

[0061] In the first reset period TR1, the second scan control terminal S22 controls the first node reset transistor M13 of the first pixel driving circuit 101 and the second pixel driving circuit 102 to be turned on, and the first reset terminal Ref1 resets the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 through the first node reset transistor M13.

[0062] In the data writing period TW_101 of the first pixel driving circuit 101, the data writing control terminal S1 of the first pixel driving circuit 101 controls the data writing transistor M11 of the first pixel driving circuit 101 to be turned on, and the data voltage terminal Vdata of the first pixel driving circuit 101 provides the data voltage V data The data is written into the second node N12 of the first pixel driving circuit 101 through the data writing transistor M11 of the first pixel driving circuit 101. The driving transistor M0 of the first pixel driving circuit 101 is turned on. In this stage, the first scanning control terminal S21 of the first pixel driving circuit 101 controls the threshold compensation transistor M12 of the first pixel driving circuit 101 to be turned on. In this process, the potential of the first node N11 of the first pixel driving circuit 101 changes continuously until the potential V N11 Change to V N11 =Vdata -|V th1 |, V th1 is the threshold voltage of the driving transistor M0 of the first pixel driving circuit 101 .

[0063] During the data writing period TW_102 of the second pixel driving circuit 102, the data writing control terminal S1 of the second pixel driving circuit 102 controls the data writing transistor M11 of the second pixel driving circuit 102 to be turned on, and the data voltage terminal Vdata of the second pixel driving circuit 102 provides the data voltage V data The data is written into the second node N12 of the second pixel driving circuit 102 through the data writing transistor M11. The driving transistor M0 of the second pixel driving circuit 102 is turned on. In this stage, the first scanning control terminal S21 of the second pixel driving circuit 102 controls the threshold compensation transistor M12 of the second pixel driving circuit 102 to be turned on. In this process, the potential of the first node N11 of the second pixel driving circuit 102 changes continuously until the potential V N11 Change to V N11 =V data -|V th2 |, V th2 is the threshold voltage of the driving transistor M0 of the second pixel driving circuit 102 .

[0064] During the light-emitting period TE, the second light-emitting control transistor M15, the first light-emitting control transistor M16 and the driving transistor M0 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are turned on, the first node reset transistor M13, the data writing transistor M11 and the threshold compensation transistor M12 are all turned off, the current path between the first power supply voltage terminal PVDD and the second power supply voltage terminal PVEE is turned on, and the light-emitting element 200 electrically connected to the first pixel driving circuit 101 and the second pixel driving circuit 102 is lit.

[0065] like Figure 1 As shown, the display panel further includes a first scan driving circuit 21 , a second scan driving circuit 22 and a light emitting driving circuit 23 .

[0066] The first scan driving circuit 21 includes a plurality of cascaded first scan driving units 210 . The first scan driving units 210 are electrically connected to the first scan control terminals S21 of a plurality of pixel rows 10 belonging to the same pixel group 1 .

[0067] The second scan drive circuit 22 includes multiple cascaded second scan drive unit groups 20, each of which includes B cascaded second scan drive units 220. Multiple cascaded second scan drive unit groups 20 mean that the output of the last-stage second scan drive unit 220 in the previous second scan drive unit group 20 is electrically connected to the input of the first-stage second scan drive unit 220 in the current second scan drive unit group 20. The second scan drive unit groups 20 are arranged corresponding to the pixel groups 1, and the B cascaded second scan drive units 220 in the same second scan drive unit group 20 are electrically connected in a one-to-one correspondence with the B pixel rows 10 in the same pixel group 1. The second scan drive units 220 are electrically connected to the data write control terminal S1 of the pixel drive circuit 100. When the display panel is operating, each stage of the second scan drive unit 220 sequentially outputs an active-level signal, causing each pixel row 10 to perform a data write operation in sequence.

[0068] Taking the multiple pixel driving circuits 100 in the same pixel group 1 including the first pixel driving circuit 101 and the second pixel driving circuit 102 located in different pixel rows as an example, within the display time of one frame, Figure 3 As shown, the active levels of the first scan control terminals S21 of the first pixel driving circuit 101 and the second pixel driving circuit 102 cover the data writing period TW_101 of the first pixel driving circuit 101 and the data writing period TW_102 of the second pixel driving circuit 102. The data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_101 of the second pixel driving circuit 102. When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the potential of the first node N11 in the first pixel driving circuit 101 is V N11 After the data writing period TW_102 of the second pixel driving circuit 102, the potential of the first node N11 in the second pixel driving circuit 102 is V N12 In the embodiment of the present invention, V N11 >V N12 .

[0069] The display panel provided by the embodiment of the present invention can reduce the number of first scan driving units 210 required for the display panel by electrically connecting the first scan driving unit 210 to multiple first scan control terminals S21 in the same pixel group 1, thereby reducing the space occupied by the first scan driving circuit 21 in the non-display area NA, which is beneficial to improving the screen-to-body ratio of the display panel.

[0070] When the second pixel driving circuit 102 performs a data write operation, that is, during the data write period TW_102 corresponding to the second pixel driving circuit 102, the threshold compensation transistor M12 of the first pixel driving circuit 101 remains in the on state. Since the fourth node N14 is electrically connected to the second reset terminal Ref2 via the light-emitting element reset transistor M14, the second reset terminal Ref2 provides a low-level reset signal. Therefore, during this period, the first node N11 of the first pixel driving circuit 101 leaks electricity to the fourth node N14 through the third node N13 and the first light-emitting control transistor M16 until the threshold compensation transistor M12 of the first pixel driving circuit 101 is turned off. The time between the turning off of the data write transistor M11 of the pixel driving circuit 100 and the turning off of the threshold compensation transistor M12 is defined as the leakage time of the first node N1. As mentioned above, the effective levels of the first scan control terminals S21 of the first pixel driving circuit 101 and the second pixel driving circuit 102 cover the data writing period TW_101 and the data writing period TW_102. The data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_101 of the second pixel driving circuit 102. Therefore, the leakage time of the first node N11 in the first pixel driving circuit 101 is greater than the leakage time of the first node N11 in the second pixel driving circuit 102.

[0071] When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing periods of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when the respective data writing transistors M11 are turned off, the embodiment of the present invention sets V N11 >V N12 , which can compensate for or even eliminate the difference in leakage duration between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potentials of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made consistent, which is beneficial to improving the brightness consistency of the light-emitting element 200 driven by the two.

[0072] For example, Figure 3 As shown, the working process of the first pixel driving circuit 101 and the second pixel driving circuit 102 also includes a second reset period TR2. In the second reset period TR2, combined with Figure 2As shown, the threshold compensation transistor M12 and the first node reset transistor M13 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are both turned on, and the first reset terminal Ref1 can reset the third node N13 through the threshold compensation transistor M12 and the first node reset transistor M13 to adjust the bias state of the driving transistor M0 of the first pixel driving circuit 101 and the second pixel driving circuit 102.

[0073] For example, Figure 1 As shown, the second scan control terminal S22 in the pixel driving circuit 100 can be electrically connected to the first scan driving unit 210 of the previous stage. That is, in addition to being electrically connected to the first scan control terminals S21 of the plurality of pixel driving circuits 100 in the corresponding pixel group 1, the first scan driving unit 210 can also be electrically connected to the second scan control terminals S22 of the plurality of pixel driving circuits 100 in the next pixel group 1.

[0074] For example, Figure 4 and Figure 5 As shown, Figure 4 A schematic diagram of another pixel driving circuit provided by an embodiment of the present invention, Figure 5 for Figure 4 In the corresponding working timing diagram, the pixel driving circuit 100 further includes a regulating transistor M11*, the control electrode of the regulating transistor M11* is electrically connected to the regulating control terminal S1*, the first electrode of the regulating transistor M11* is electrically connected to the regulating terminal DVH, and the second electrode of the regulating transistor M11* is electrically connected to the second node N12. Figure 5 The other structures except the regulating transistor M11* can be as follows Figure 2 The corresponding structures in the pixel driving circuit 100 are set, and the embodiments of the present invention are not described again here.

[0075] Combine Figure 5 As shown, the operation process of the pixel driving circuit 100 also includes a first bias adjustment phase TD1 and a second bias adjustment phase TD2. The first bias adjustment phase TD1 is located before the first reset period TR1, and the second bias adjustment phase TD2 is located after the corresponding data writing period of the pixel driving circuit 100. During the first bias adjustment phase TD1 and the second bias adjustment phase TD2, the pixel driving circuit 100 is in a non-luminous state. During the first bias adjustment phase TD1 and the second bias adjustment phase TD2, the adjustment terminal DVH writes a bias adjustment signal to the second node N12 through the adjustment transistor M11* to adjust the bias state of the driving transistor M0 in this phase.

[0076] Optionally, in an embodiment of the present invention, during the display time of a frame, the conduction time of the data writing transistor M11 in the first pixel driving circuit 101 is shorter than the conduction time of the data writing transistor M11 in the second pixel driving circuit 102. In this way, the threshold compensation time of the first pixel driving circuit 101 can be shorter than the threshold compensation time of the second pixel driving circuit 102, so that the threshold compensation of the first pixel driving circuit 101 is incomplete. After the pixel driving circuit performs threshold compensation, the potential of the first node N11 satisfies: V N11 =V data -|V th |. V th The threshold voltage of the driving transistor written to the first node N11 of the pixel driving circuit when the data writing transistor M11 of the corresponding pixel driving circuit is turned off. Therefore, using the method provided by the embodiment of the present invention, after each data writing transistor M11 is turned off, the potential of the first node N11 in the first pixel driving circuit 101 can be made higher than the potential of the first node N11 in the second pixel driving circuit 102, thereby compensating for the subsequent difference in leakage time between the two.

[0077] like Figure 6 、 Figure 7 and Figure 8 As shown, Figure 6 A schematic diagram of a second scanning circuit provided by an embodiment of the present invention, Figure 7 A circuit diagram of a second scan driving unit provided by an embodiment of the present invention is shown. Figure 8 for Figure 6In a corresponding operation timing diagram, the second scan driving unit 220 includes a first output transistor M21, a second output transistor M22, a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27, an eighth transistor M28, a first capacitor C21, and a second capacitor C22. A first electrode of the first output transistor M21 is electrically connected to the first clock terminal CK1, a second electrode of the first output transistor M21 is electrically connected to the output terminal OUT1 of the second scan driving unit 220, and a control electrode of the first output transistor M21 is electrically connected to the first node N21. A first electrode of the second output transistor M22 is electrically connected to the second level terminal VGH1, a second electrode of the second output transistor M22 is electrically connected to the output terminal OUT1 of the second scan driving unit 220, and a control electrode of the second output transistor M22 is electrically connected to the second node N22. The control electrodes of the fifth transistor M25 and the fourth transistor M24 are both electrically connected to the second clock terminal XCK1. The first electrode of the fifth transistor M25 is electrically connected to the input terminal IN1. The second electrode of the fifth transistor M25 is electrically connected to the control electrode of the seventh transistor M27, the first electrode of the sixth transistor M26, and the first electrode of the third transistor M23. The first electrode of the seventh transistor M27 is electrically connected to the second clock terminal XCK1. The second electrode of the seventh transistor M27 is electrically connected to the control electrode of the eighth transistor M28. The control electrode of the sixth transistor M26 is electrically connected to the first clock terminal CK1. The second electrode of the sixth transistor M26 is electrically connected to the first electrode of the eighth transistor M28. The second electrode of the eighth transistor M28 is electrically connected to the second voltage level terminal VGH1. The first electrode of the fourth transistor M24 is electrically connected to the first voltage level terminal VGL1. The second electrode of the fourth transistor M24 is electrically connected to the control electrode of the second output transistor M22. The control electrode of the third transistor M23 is electrically connected to the first voltage level terminal VGL1. The second electrode of the third transistor M23 is electrically connected to the control electrode of the first output transistor M21. The output terminal OUT1 of each second scan driving unit in the second scan driving circuit is electrically connected to the control electrode of the data writing transistor M11 of the corresponding pixel driving circuit 100 .

[0078] When the first output transistor M21 of the second scan driver unit 220 is turned on, the signal of the first clock terminal CK1 is output to the output terminal OUT1. The signal received by the first clock terminal CK1 is a pulse signal including an active level capable of turning on the data write transistor M11 in the pixel driver circuit 100. For example, when the data write transistor M11 is a P-type transistor, the active level is a low-level signal VGL. When the data write transistor M1 is an N-type transistor, the active level is a high-level signal VGH.

[0079] In an embodiment of the present invention, the display panel further includes Class B clock signal lines, which are electrically connected to the first clock terminals CK1 of the Class B second scan drive units 220 in the same second scan drive unit group 20. Each type of clock signal line is used to transmit a periodic pulse signal. The pulse signal includes an effective level that controls the conduction of the data write transistor M11 of the pixel drive circuit 100. In an embodiment of the present invention, the effective levels of any two types of clock signal lines in the Class B clock signal lines are staggered. Moreover, the pulse widths of the effective levels transmitted by the Class B clock signal lines are different from each other. The pulse widths of the effective levels output by the Class B clock signal lines increase in sequence according to the order in which the Class B clock signal lines output effective levels.

[0080] For example, the B cascaded second scan driver units 220 in the same second scan driver unit group 20 include at least an m-th second scan driver unit 220_m and an n-th second scan driver unit 220_n. The output terminal of the m-th second scan driver unit 220_m is electrically connected to the data write control terminal S1 of the first pixel driver circuit 101, and the output terminal of the n-th second scan driver unit 220_n is electrically connected to the data write control terminal S1 of the second pixel driver circuit 102. Accordingly, the B-type clock signal lines included in the display panel include at least an m-th clock signal line and an n-th clock signal line. The m-th clock signal line is electrically connected to the first clock terminal CK1 of the m-th second scan driver unit 220_m, and the n-th clock signal line is electrically connected to the first clock terminal CK1 of the n-th second scan driver unit 220_n. The mth-stage second scan drive unit 220_m outputs a valid level first, and the nth-stage second scan drive unit 220_n outputs a valid level later, so that within the display time of a frame, the first pixel drive circuit 101 writes data first, and the second pixel drive circuit 102 writes data later. In an embodiment of the present invention, the pulse width of the valid level of the mth-stage clock signal line is shorter than the pulse width of the valid level of the nth-stage clock signal line. Wherein, m and n are both integers, and 1≤m<n≤B. For example, when B=2, m=1, n=2; when B=3, m=1, n=2; or, m=1, n=3; or, m=2, n=3.

[0081] Take B=2 as an example, Figure 6As shown, two cascaded second scan driver unit groups 20 are used as an example. The two cascaded second scan driver unit groups 20 correspond to the first second scan driver unit group 20 and the second second scan driver unit group 20 of the display panel, respectively. The input terminal IN1 of the first-stage second scan driver unit 220_1 in the first scan driver unit group 20 is electrically connected to the scan frame start signal line LS1. The output terminal OUT1 of the second-stage second scan driver unit 220_2 in the first second scan driver unit group 20 is connected to the input terminal IN1 of the first-stage second scan driver unit in the second second scan driver unit group 20 (corresponding to the third-stage second scan driver unit 220_3 of the display panel).

[0082] Taking the two-stage second scan driving unit in the first scan driving unit group 20 as an example, the first clock terminal CK1 of the first-stage second scan driving unit 220_1 is electrically connected to the first-type clock signal line LC11; the first clock terminal CK1 of the second-stage second scan driving unit 220_2 is electrically connected to the second-type clock signal line LC12. Figure 8 As shown, the pulse width e1 of the effective level transmitted by the first-type clock signal line LC11 is smaller than the pulse width f1 of the effective level transmitted by the second-type clock signal line LC12.

[0083] In the embodiment of the present invention, different second scan driving units 220 in the same second scan driving unit group 20 are respectively connected to different types of clock signal lines, and the pulse widths of the effective levels transmitted by the various clock signal lines are increased in sequence according to the order of the effective levels output by the various clock signal lines. This can make the turn-on times of the data writing transistors M11 in different pixel rows 10 in the same pixel group 1 different, thereby balancing the differences in the leakage times of the first nodes N11 of different pixel driving circuits 100 in the same pixel group 1.

[0084] In specific implementation, the difference in pulse width of the effective level transmitted by various clock signal lines can be adjusted according to the leakage conditions of the first nodes N11 of different pixel driving circuits in the same pixel group, which is not limited in the embodiment of the present invention.

[0085] For example, for the first type of clock signal lines in the aforementioned B-type clock signal lines, in addition to being electrically connected to the first clock terminal CK1 of the first-stage second scan driver unit 220 in the second scan driver unit group 20, they can also be electrically connected to the second clock terminal XCK1 of the B-th-stage second scan driver unit 220 in the same second scan driver unit group 20. For the i-th type of clock signal lines in the aforementioned B-type clock signal lines, where i is an integer and 2≤i≤B, in addition to being electrically connected to the first clock terminal CK1 of the i-th-stage second scan driver unit 220 in the second scan driver unit group 20, they can also be electrically connected to the second clock terminal XCK1 of the i-1-th-stage second scan driver unit 220 in the same second scan driver unit group 20. This configuration helps reduce the number of required signal lines while ensuring the normal operation of the second scan driver circuit 22.

[0086] Take B=2 as an example, Figure 6 As shown, the first-type clock signal line LC11 is electrically connected to the first clock terminal CK1 of the first-stage second scan driving unit 220_1, and is also electrically connected to the second clock terminal XCK1 of the second-stage second scan driving unit 220_2 in the same second scan driving unit group 20. The second-type clock signal line LC12 is electrically connected to the first clock terminal CK1 of the second-stage second scan driving unit 220_2, and is also electrically connected to the second clock terminal XCK1 of the first-stage second scan driving unit 220_1 in the same second scan driving unit group 20.

[0087] Take B=3 as an example, Figure 9 and Figure 10 As shown, Figure 9 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention is shown. Figure 10 for Figure 9 The corresponding working timing diagram, in which two second scan drive unit groups 20 are used as an example, the display panel includes three types of clock signal lines. Figure 9 and Figure 10LC11, LC12, and LC13, respectively. The pulse width e2 of the active level transmitted by the first-type clock signal line LC11 is smaller than the pulse width f2 of the active level transmitted by the second-type clock signal line LC12. The pulse width f2 of the active level transmitted by the second-type clock signal line LC12 is smaller than the pulse width f3 of the active level transmitted by the third-type clock signal line LC13. For the first second scan driver unit group 20, the first-type clock signal line LC11 is electrically connected to the first clock terminal CK1 of the first-stage second scan driver unit 220_1 and the second clock terminal XCK1 of the third-stage second scan driver unit 220_3. The second-type clock signal line LC12 is electrically connected to the first clock terminal CK1 of the second-stage second scan driver unit 220_2 and the second clock terminal XCK1 of the first-stage second scan driver unit 220_1. The third-type clock signal line LC13 is electrically connected to the first clock terminal CK1 of the third-stage second scan driving unit 220_3 and is also electrically connected to the second clock terminal XCK1 of the second-stage second scan driving unit 220_2.

[0088] Exemplarily, the first clock terminals CK1 of the second scan driving units 220 of corresponding stages in different second scan driving unit groups 20 are connected to the same clock signal line. Figure 6 For example, in addition to being electrically connected to the first clock terminal CK1 of the first-level second scan driving unit 220_1 in the first second scan driving unit group 20, the first-type clock signal line LC11 is also electrically connected to the first clock terminal CK1 of the first-level second scan driving unit 220 in the second second scan driving unit group 20 (that is, the fourth-level second scan driving unit 220_4 of the display panel).

[0089] Optionally, in an embodiment of the present invention, a Class B first clock signal line and a Class B second clock signal line may be separately provided in the display panel, wherein the Class B first clock signal lines are electrically connected to the first clock terminal CK1 of each level of the second scan driver unit 220 in the same second scan driver unit group 20; and the Class B second clock signal lines are electrically connected to the second clock terminal XCK1 of each level of the second scan driver unit 220 in the same second scan driver unit group 20. In accordance with the order of the active levels transmitted by the Class B first clock signal lines, the pulse width of the active level transmitted by the Class B first clock signal lines becomes narrower, and accordingly, the pulse width of the active level transmitted by the Class B second clock signal lines also becomes narrower.

[0090] For example, the frequency of the signal transmitted by the second clock signal line is the same as the frequency of the signal transmitted by the first clock signal line. For example, the frequency of the signal transmitted by the first clock signal line and the second clock signal line can be less than Figure 8 and Figure 10The frequency of the signal transmitted by the clock signal line shown.

[0091] Taking B=2 as an example, for example, Figure 11 and Figure 12 As shown, Figure 11 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention is shown. Figure 12 for Figure 11 A corresponding working sequence diagram, Figure 11 In the figure, two cascaded second scan drive unit groups 20 in the display panel are used as an example. Figure 11 As shown, the display panel includes a first-type first clock signal line LC111, a second-type first clock signal line LC112, a first-type second clock signal line LX11, and a second-type second clock signal line LX12. The first-type first clock signal line LC111 is electrically connected to the first clock terminal CK1 of the first-stage second scan driver unit 220_1, and the second-type first clock signal line LC112 is electrically connected to the first clock terminal CK1 of the second-stage second scan driver unit 220_2. The first-type second clock signal line LX11 is electrically connected to the second clock terminal XCK1 of the first-stage second scan driver unit 220_1, and the second-type second clock signal line LX12 is electrically connected to the second clock terminal XCK1 of the second-stage second scan driver unit 220_2. The pulse width e3 of the active level transmitted by the first-type first clock signal line LC111 is smaller than the pulse width f3 of the active level transmitted by the second-type first clock signal line LC112. The pulse width of the active level transmitted by the first-category first clock signal line LC111 and the pulse width of the active level transmitted by the first-category second clock signal line LX11 are both e3. The pulse width of the active level transmitted by the second-category first clock signal line LC112 and the pulse width of the active level transmitted by the second-category second clock signal line LX12 are both f3. The active level transmitted by the second-category first clock signal line LC112 is between the active level transmitted by the first-category first clock signal line LC111 and the active level transmitted by the first-category second clock signal line LX11. The active level transmitted by the first-category second clock signal line LX11 is between the active level transmitted by the second-category first clock signal line LC112 and the active level transmitted by the second-category second clock signal line LX12. The active level transmitted by the second-category second clock signal line LX12 is between the active level transmitted by the first-category first clock signal line LC111 and the active level transmitted by the first-category second clock signal line LX11. With this configuration, the frequencies of the signals transmitted by the various first clock signal lines and the various second clock signal lines can be lowered while ensuring the normal operation of the second scan driving circuit 220, which is beneficial to reducing the power consumption of the display panel.

[0092] For example, in the embodiment of the present invention, various first clock signal lines are alternately connected to the first clock terminal CK1 and the second clock terminal XCK1 of the second scan driving unit 220 of the corresponding stage in two adjacent second scan driving unit groups 20. Figure 11 As shown, for the first-type first clock signal line LC111, it is electrically connected to the first clock terminal CK1 of the first-level second scan driving unit 220_1 in the first second scan driving unit group 20 and the first-level second scan driving unit 220 in the second second scan driving unit group 20, that is, the second clock terminal XCK1 of the third-level second scan driving unit 220_3 of the display panel.

[0093] Similarly, various types of second clock signal lines are alternately connected to the second clock terminals XCK1 and the first clock terminals CK1 of the second scan driving units 220 of corresponding stages in two adjacent second scan driving unit groups 20. Figure 11 As shown, for the first-type second clock signal line LX11, it is electrically connected to the second clock terminal XCK1 of the first-level second scan driving unit 220_1 in the first second scan driving unit group 20 and the first-level second scan driving unit 220 in the second second scan driving unit group 20, that is, the first clock terminal CK1 of the third-level second scan driving unit 220_3 of the display panel.

[0094] Combine Figure 7 As shown, the width-to-length ratio of the channel of the first output transistor M21 of the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 is W11 / L11, and the width-to-length ratio of the channel of the first output transistor M21 of the second scan driving unit 220 electrically connected to the second pixel driving circuit 102 is W21 / L21. In the embodiment of the present invention, W11 / L11<W21 / L21. This configuration can make the output delay of the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 greater than the output delay of the second scan driving unit 220 electrically connected to the second pixel driving circuit 102. As a result, the time when the data of the first pixel driving circuit 101 is written to the valid level received by the control terminal S1 is shorter than the time when the data of the second pixel driving circuit 102 is written to the valid level received by the control terminal S1, thereby compensating for the difference in subsequent leakage time between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102.

[0095] Optionally, an embodiment of the present invention may further make the on-state current of the data write transistor M11 in the first pixel driving circuit 101 smaller than the on-state current of the data write transistor M11 in the second pixel driving circuit 102, thereby making the threshold compensation degree of the first pixel driving circuit 101 weaker than the threshold compensation degree of the second pixel driving circuit 102, so that after the corresponding data write transistor M11 is turned off, the potential of the first node N11 of the first pixel driving circuit 101 is higher than the potential of the first node N11 of the second pixel driving circuit 102.

[0096] Exemplarily, the data writing transistor M11 includes a P-type transistor or an N-type transistor.

[0097] When the data writing transistors M11 of the above-mentioned first pixel driving circuit 101 and the second pixel driving circuit 102 are both set to include P-type transistors, the P-type transistors are turned on at a low level. In this embodiment of the present invention, the effective level output by the second scanning driving unit 220 electrically connected to the first pixel driving circuit 101 can be greater than the effective level output by the second scanning driving unit 220 electrically connected to the second pixel driving circuit 102, so that the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is less than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0098] When the data writing transistors M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are both configured to include N-type transistors, the N-type transistors are turned on at a high level. In this embodiment of the present invention, the effective level output by the second scanning driving unit 220 electrically connected to the first pixel driving circuit 101 can be lower than the effective level output by the second scanning driving unit 220 electrically connected to the second pixel driving circuit 102. This configuration enables the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 to be lower than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0099] Exemplarily, when the data writing transistors M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are set to include P-type transistors, the embodiment of the present invention can make the effective level Vm transmitted by the m-th type clock signal line electrically connected to the first clock terminal CK1 of the m-th level second scanning driving unit 220_m greater than the effective level Vn transmitted by the n-th type clock signal line electrically connected to the first clock terminal CK1 of the n-th level second scanning driving unit 220_n. As mentioned above, the effective level output by the second scanning driving unit 220 is the effective level of the signal received by its first clock terminal CK1. By making Vm>Vn, the embodiment of the present invention can make the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102. Taking B=2 as an example, combined with Figure 6 and Figure 13 As shown, Figure 13 for Figure 6 In another corresponding working timing diagram, the effective level V1 transmitted by the first-type clock signal line LC11 is greater than the effective level V2 transmitted by the second-type clock signal line LC12.

[0100] It should be noted that while the magnitudes of the effective levels transmitted by various clock signal lines are set differently, the pulse widths of the effective levels transmitted by various clock signal lines may also be adjusted in the aforementioned manner.

[0101] Optionally, when the data writing transistor M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 is set to include an N-type transistor, an embodiment of the present invention can make the effective level Vm transmitted by the m-th type clock signal line electrically connected to the first clock terminal CK1 of the m-th level second scanning driving unit 220_m smaller than the effective level Vn transmitted by the n-th type clock signal line electrically connected to the first clock terminal CK1 of the n-th level second scanning driving unit 220_n, so that the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102.

[0102] The display panel further includes type B first level signal lines. The type B first level signal lines are electrically connected to the first level terminals VGL1 of the type B second scan driving units in the same second scan driving unit group 20 .

[0103] When the data writing transistors M11 of each pixel driving circuit in the same pixel group 1 are all P-type transistors, the potential of the signal transmitted by the B-type first-level signal line gradually decreases according to the output order of the effective levels of the second scanning driving units of each level in the same second scanning driving unit group 20.

[0104] When the data writing transistors M11 of each pixel driving circuit in the same pixel group 1 are all N-type transistors, the potential of the signal transmitted by the B-type first-level signal line gradually increases according to the output order of the effective levels of the second scanning driving units of each level in the same second scanning driving unit group 20.

[0105] Taking the example that the Class B first-level signal line includes at least the m-th Class first-level signal line and the n-th Class first-level signal line, the m-th Class first-level signal line is electrically connected to the first level end VGL1 of the m-th level second scan driving unit; and the n-th Class first-level signal line is electrically connected to the first level end VGL1 of the n-th level second scan driving unit, in an embodiment of the present invention, when the data writing transistors M11 of each pixel driving circuit in the same pixel group 1 are all P-type transistors, the level transmitted by the m-th Class first-level signal line is greater than the level transmitted by the n-th Class first-level signal line.

[0106] Take B=2 as an example, Figure 14 As shown, Figure 14 A connection diagram of another second scan driving circuit provided by an embodiment of the present invention is shown, using two second scan driving unit groups 20 in a display panel as an example. For the two second scan driving units 220 in the same second scan driving unit group 20, the first level terminal VGL1 of the first-stage second scan driving unit 220_1 is electrically connected to the first-type first-level signal line LL11; and the first level terminal VGL1 of the second-stage second scan driving unit 220_2 is electrically connected to the second-type first-level signal line LL12. The voltage level transmitted by the first-type first-level signal line LL11 is greater than the voltage level transmitted by the second-type first-level signal line LL12.

[0107] For the second scanning driving unit 220, combined with Figure 7 As shown, when the potential of the second clock terminal XCK1 is low, the fifth transistor M25 and the fourth transistor M24 are turned on. When the signal input by the input terminal IN1 is also low, the control electrode of the seventh transistor M27 is written low by the input terminal IN through the fifth transistor M25, so that the seventh transistor M27 is turned on, and the low level of the second clock terminal XCK1 is written into the control electrode of the eighth transistor M28. At the same time, the control electrode of the eighth transistor M28 is also written low by the first level terminal VGL1 through the fourth transistor M24. The embodiment of the present invention can make the potential connected to the first level terminal VGL1 of the second scan driving unit 220 of each level in the same second scan driving unit group 20 match the potential connected to the second clock terminal XCK1 of the corresponding second scan driving unit 220 by differentially setting the potential connected to the first level terminal VGL1 of the second scan driving unit 220 of each level, which is beneficial to avoid the path formed by the second clock terminal XCK1, the seventh transistor M27 and the first level terminal VGL1 (such as Figure 7 The display effect of the display panel can be guaranteed by short-circuiting the display panel (indicated by the dotted arrow).

[0108] The embodiment of the present invention further provides a display panel, Figure 1 and Figure 2 As shown, the display panel includes multiple pixel groups 1, each of which includes B pixel rows 10, where B ≥ 2 and B is a positive integer. The pixel rows 10 include multiple pixel driving circuits 100, each of which includes a driving transistor M0, a data write control terminal S1, and a first scan control terminal S21. The control electrode of the driving transistor M0 is electrically connected to a first node N11, and the first electrode of the driving transistor M0 is electrically connected to a second node N12. A first scan driving circuit 21 includes multiple cascaded first scan driving units 210, each of which is electrically connected to multiple first scan control terminals S21 in the same pixel group 1.

[0109] The working cycle of the pixel driving circuit 100 includes a data writing period. During the data writing period, the data writing control terminal S1 and the first scanning control terminal S21 receive an effective level. The multiple pixel driving circuits 100 in the same pixel group 1 include a first pixel driving circuit 101 and a second pixel driving circuit 102. During the display time of a frame, Figure 3 As shown, the data writing period TW_101 of the first pixel driving circuit 101 is located before the data writing period TW_102 of the second pixel driving circuit 102; and, in an embodiment of the present invention, when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101, the leakage current speed of the first node N11 in the first pixel driving circuit 101 is v N11 After the data writing period TW_102 of the second pixel driving circuit 102, the leakage current speed of the first node N11 in the second pixel driving circuit 102 is v N12 .v N11 <v N12 .

[0110] The display panel provided by the embodiment of the present invention can reduce the number of first scan driving units 210 required for the display panel by electrically connecting the first scan driving unit 210 to multiple first scan control terminals S21 in the same pixel group 1, thereby reducing the space occupied by the first scan driving circuit 21 in the non-display area NA, which is beneficial to improving the screen-to-body ratio of the display panel.

[0111] When the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing periods of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when the respective data writing transistors M11 are turned off, the embodiment of the present invention sets v N11 <v N12 , which can compensate for or even eliminate the difference in leakage duration between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potentials of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made consistent, which is beneficial to improving the brightness consistency of the light-emitting element 200 driven by the two.

[0112] For example, the width-to-length ratio of the channel of the first light-emitting control transistor M16 in the first pixel driving circuit 101 is W12 / L12, and the width-to-length ratio of the channel of the first light-emitting control transistor M16 in the second pixel driving circuit 102 is W22 / L22, where W12 / L12<W22 / L22. With this configuration, during the process in which the potential of the first node N11 of the first pixel driving circuit 101 leaks to the fourth node N14 through the threshold compensation transistor M12, the third node N13, and the first light-emitting control transistor M16, since the width-to-length ratio W12 / L12 of the channel of the first light-emitting control transistor M16 in the first pixel driving circuit 101 is less than the width-to-length ratio W22 / L22 of the channel of the first light-emitting control transistor M16 in the second pixel driving circuit 102, the leakage current velocity v of the first node N11 in the first pixel driving circuit 101 can be reduced. N11 is smaller than the leakage current velocity v of the first node N11 in the second pixel driving circuit 102 N12 .

[0113] Optionally, the first light emission control transistor M16 in the first pixel driving circuit 101 and the second pixel driving circuit 102 includes a plurality of sub-transistors connected in series, such as Figure 15 As shown, Figure 15A schematic diagram of the connection relationship between a first pixel driving circuit and a second pixel driving circuit provided in an embodiment of the present invention, wherein the first light-emitting control transistor M16 in the first pixel driving circuit 101 includes three sub-transistors connected in series, namely M161, M162 and M163, sub-transistors M161 and M162 are electrically connected to the fifth node N15, and sub-transistors M162 and M163 are electrically connected to the sixth node N16. The first light-emitting control transistor M16 in the second pixel driving circuit 102 is configured to include two sub-transistors connected in series, namely M164 and M165. Among them, sub-transistor M164 and sub-transistor M165 are electrically connected to the seventh node N17. The configuration of multiple sub-transistors connected in series can slow down the leakage speed from the third node N13 to the fourth node N14. Taking the first pixel driving circuit 101 as an example, the voltage difference between the third node N13 and the fifth node N15 will be less than Figure 2 The voltage difference between the third node N13 and the fourth node N14 is shown, therefore, based on Figure 15 With the setting, the leakage current between the third node N13 and the fourth node N14 will be slowed down.

[0114] In the embodiment of the present invention, the number of sub-transistors included in the first light emission control transistor M16 in the first pixel driving circuit 101 is greater than the number of sub-transistors included in the first light emission control transistor M16 in the second pixel driving circuit 102. This configuration can make the leakage rate of the first node N11 in the first pixel driving circuit 101 lower than the leakage rate of the first node N11 in the second pixel driving circuit 102.

[0115] When setting up the light-emitting drive circuit, for example, Figure 1 As shown, one light-emitting driving unit 230 can be electrically connected to the light-emitting control terminals E of B pixel driving circuit rows in the above-mentioned one pixel group 1.

[0116] Alternatively, the embodiment of the present invention may also electrically connect the light-emitting driving unit 230 to the pixel rows 10 in a one-to-one correspondence. Figure 16 As shown, Figure 16This is a connection diagram of a light-emitting drive circuit provided in an embodiment of the present invention. The light-emitting drive circuit 23 includes multiple cascaded light-emitting drive unit groups 30, each of which includes B cascaded light-emitting drive units 230. Multiple cascaded light-emitting drive unit groups 30 mean that the output end of the last stage of light-emitting drive unit 230 in the previous light-emitting drive unit group 30 is electrically connected to the input end of the first stage of light-emitting drive unit 230 in the current light-emitting drive unit group 30. Multiple cascaded light-emitting drive units 230 in the same light-emitting drive unit group 30 are respectively electrically connected to the light-emitting control end E of the pixel drive circuit in different pixel rows 10 in the same pixel group 1.

[0117] like Figure 17 As shown, Figure 17 This is a circuit diagram of a light-emitting driving unit provided in an embodiment of the present invention. The light-emitting driving unit 230 includes a first transistor M31, a second transistor M32, a third transistor M33, a fourth transistor M34, a fifth transistor M35, a sixth transistor M36, a seventh transistor M37, an eighth transistor M38, a ninth transistor M39, a tenth transistor M30, a first capacitor C31, a second capacitor C32, and a third capacitor C33.

[0118] The control electrode of the first transistor M31 is electrically connected to the first clock terminal CK2, the first terminal of the first transistor M31 is electrically connected to the input terminal IN2, and the second terminal of the first transistor M31 is electrically connected to the first node N31. Under the control of the signal provided by the first clock terminal CK2, the first transistor M31 controls the electrical connection between the input terminal IN2 and the first node N31, thereby adjusting the potential of the first node N31. The control electrode of the second transistor M32 is electrically connected to the second clock terminal XCK2, the first terminal of the second transistor M32 is electrically connected to the first node N31, and the second terminal of the second transistor M32 is electrically connected to the first terminal of the third transistor M33. The control electrode of the third transistor M33 is electrically connected to the third node N33, and the second terminal of the third transistor M33 is electrically connected to the input terminal IN2. Under the control of the signal provided by the second clock terminal XCK2 and the third node N33, the second transistor M32 and the third transistor M33 control the electrical connection between the input terminal IN2 and the first node N31, thereby adjusting the potential of the first node N31. The control electrode of the fourth transistor M34 is electrically connected to the first node N31, the first terminal of the fourth transistor M34 is electrically connected to the first clock terminal CK2, and the second terminal of the fourth transistor M34 is electrically connected to the third node N33. Under the control of the first node N31, the fourth transistor M34 controls the electrical connection between the first clock terminal CK2 and the third node N33, thereby adjusting the potential of the third node N33 according to the signal of the first clock terminal CK2. The control electrode of the fifth transistor M35 is electrically connected to the first clock terminal CK2, the first terminal of the fifth transistor M35 is electrically connected to the first level terminal VGL2, and the second terminal of the fifth transistor M35 is electrically connected to the third node N33. Under the control of the signal provided by the first clock terminal CK2, the fifth transistor M35 controls the electrical connection between the first level terminal VGL2 and the third node N33, thereby adjusting the potential of the third node N33 according to the signal of the first level terminal VGL2. The control electrode of the sixth transistor M36 is electrically connected to the third node N33, the first terminal of the sixth transistor M36 is electrically connected to the second clock terminal XCK2, and the second terminal of the sixth transistor M36 is electrically connected to the fourth node N34. Under the control of the third node N33, the sixth transistor M36 controls the electrical connection between the second clock terminal XCK2 and the fourth node N34, thereby adjusting the potential of the fourth node N34 via the signal of the second clock terminal XCK2. The control electrode of the seventh transistor M37 is electrically connected to the second clock terminal XCK2, the first terminal of the seventh transistor M37 is electrically connected to the fourth node N34, and the second terminal of the seventh transistor M37 is electrically connected to the second node N32. Under the control of the signal provided by the second clock terminal XCK2, the seventh transistor M37 controls the electrical connection between the fourth node N34 and the second node N32, thereby adjusting the potential of the second node N32 via the signal of the fourth node N34.The eighth transistor M38 has a control electrode electrically connected to the first node N31, a first end electrically connected to the second level terminal VGH2, and a second end electrically connected to the second node N32. Under the control of the first node N31, the eighth transistor M38 controls the electrical connection between the second level terminal VGH2 and the second node N32, thereby adjusting the potential of the second node N32 via the signal at the second level terminal VGH2. The ninth transistor M39 has a control electrode electrically connected to the first node N31, a first end electrically connected to the first level terminal VGL2, and a second end electrically connected to the output terminal OUT2. Under the control of the first node N31, the ninth transistor M39 controls the electrical connection between the first level terminal VGL2 and the output terminal OUT2, thereby adjusting the output signal of the output terminal OUT2 via the first level terminal VGL2. The tenth transistor M30 has a control electrode electrically connected to the second node N32, a first end electrically connected to the second level terminal VGH2, and a second end electrically connected to the output terminal OUT2. Under the control of the second node N32 , the tenth transistor M30 controls the electrical connection between the second level terminal VGH2 and the output terminal OUT2 , so as to adjust the output signal of the output terminal OUT2 through the second level terminal VGH2 .

[0119] A first end of the first capacitor C21 is electrically connected to the first node N21, and a second end of the first capacitor C21 is electrically connected to the second clock terminal XCK2. A first end of the second capacitor C22 is electrically connected to the third node N23, and a second end of the second capacitor C22 is electrically connected to the fourth node N24. A first end of the third capacitor C23 is electrically connected to the second voltage level terminal VGH2, and a second end of the third capacitor C23 is electrically connected to the second node N22.

[0120] The first level terminal VGL2 is used to transmit a signal to turn on the first emission control transistor M16 in the pixel driving circuit 100. The second level terminal VGH2 is used to transmit a signal to turn off the first emission control transistor M16 in the pixel driving circuit 100. Exemplarily, when the first emission control transistor M16 is a P-type transistor, the first level terminal VGL2 receives a low-level signal VGL, and the second level terminal VGH2 receives a high-level signal VGH.

[0121] In an embodiment of the present invention, the display panel further includes a Class B second-level signal line. The Class B second-level signal lines are respectively electrically connected to the second level terminal VGH2 of the Class B light-emitting drive unit 230 in the same light-emitting drive unit group 30. Exemplarily, each class of second-level signal lines is used to transmit a constant signal. The constant signal includes a signal capable of controlling the first light-emitting control transistor M16 of the corresponding pixel drive circuit 100 to be cut off. The levels transmitted by the Class B second-level signal lines are different in magnitude. The voltage of the level transmitted by the Class M second-level signal lines gradually decreases according to the data writing order of the corresponding connected pixel drive circuits.

[0122] For example, the B-class light-emitting driver unit 230 in the same light-emitting driver unit group 30 includes at least a p-th light-emitting driver unit 30_p and a q-th light-emitting driver unit 30_q. Both p and q are integers, and 1≤p<q≤B. The B-class second-level signal lines include a p-th second-level signal line and a q-th second-level signal line. The p-th second-level signal line is electrically connected to the second level terminal VGH2 of the p-th light-emitting driver unit 30_p, and the q-th second-level signal line is electrically connected to the second level terminal VGH2 of the q-th light-emitting driver unit 30_q. The voltage of the p-th second-level signal line is greater than the voltage of the q-th second-level signal line.

[0123] Take B=2 as an example, Figure 18 As shown, Figure 18 A connection diagram of a light-emitting driving circuit provided in an embodiment of the present invention is provided. Taking two light-emitting driving unit groups 30 in a display panel as an example, the input terminal IN2 of the first-stage light-emitting driving unit 230_1 in the first light-emitting driving unit group 30 is electrically connected to the light-emitting frame start signal line LS2, the first-type second-level signal line LH21 is electrically connected to the second-level terminal VGH2 of the first-stage light-emitting driving unit 230_1; the second-type second-level signal line LH22 is electrically connected to the second-level terminal VGH2 of the second-stage light-emitting driving unit_2; and the voltage of the signal provided by the first-type second-level signal line LH21 is greater than the voltage of the signal provided by the second-type second-level signal line LH22.

[0124] In an embodiment of the present invention, a parasitic capacitance exists between the light-emission control signal line connecting the light-emission driving unit 230 and the pixel driving circuit and the first node N11 in the pixel driving circuit. When the signal on the light-emission control signal line connected to the pixel driving circuit 100 changes from a non-enable level (e.g., a high level) to an enable level (e.g., a low level), causing the corresponding light-emitting element to begin emitting light, the signal transition on the corresponding light-emission control signal line affects the potential of the first node N11 in the corresponding pixel driving circuit through coupling, causing the potential of the corresponding first node N11 to decrease. In an embodiment of the present invention, by connecting different light-emission driving units 230 in the same light-emission driving unit group 30 to different types of second-level signal lines, and by decreasing the voltage of the signals transmitted by each type of second-level signal line in accordance with the data writing order of the corresponding electrically connected pixel driving circuit, within a pixel group, the first nodes in the pixel driving circuits in different pixel rows can be coupled to different degrees by the light-emission control signal when entering the light-emission phase, thereby balancing the difference in leakage time of the first nodes of the pixel driving circuits.

[0125] The embodiment of the present invention further provides a method for driving a display panel. The display panel has been described in detail above and will not be described again here. Figure 3 and Figure 19 As shown, Figure 19 A schematic diagram of a method for driving a display panel provided in an embodiment of the present invention, the method comprising:

[0126] During the display time of one frame, the data writing period TW_101 of the first pixel driving circuit 101 is controlled to be before the data writing period TW_102 of the second pixel driving circuit 102; and when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101 is controlled, the potential of the first node N11 in the first pixel driving circuit 101 is V N11 After the data writing period TW_102 of the second pixel driving circuit 102, the potential of the first node N11 in the second pixel driving circuit 102 is V N12 , V N11 >V N12 .

[0127] The driving method of the display panel provided by the embodiment of the present invention is that when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the respective data writing periods of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when the respective data writing transistors M11 are turned off, the embodiment of the present invention sets V N11 >V N12, which can compensate for or even eliminate the difference in leakage duration between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potentials of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made consistent, which is beneficial to improving the brightness consistency of the light-emitting element 200 driven by the two.

[0128] For example, combined Figure 2 As shown, the above control V N11 >V N12 The methods include:

[0129] The on-time of the data writing transistor M11 in the first pixel driving circuit 101 is controlled to be shorter than the on-time of the data writing transistor M11 in the second pixel driving circuit 102 .

[0130] Optional, combined Figure 1 As shown, the display panel further includes a second scan driving circuit 22, which includes a plurality of cascaded second scan driving unit groups 20, each of which includes B cascaded second scan driving units 220; the B second scan driving units 220 in the same second scan driving unit group 20 include at least an m-th stage second scan driving unit and an n-th stage second scan driving unit, where m and n are both integers and 1≤m<n≤B; an output terminal of the m-th stage second scan driving unit is electrically connected to the data write control terminal S1 of the first pixel driving circuit 101, and an output terminal of the n-th stage second scan driving unit is electrically connected to the data write control terminal S1 of the second pixel driving circuit 102;

[0131] Combine Figure 6 and Figure 7 As shown, the second scan driving unit 220 includes a clock terminal; the display panel further includes a B-type clock signal line, the B-type clock signal line includes at least an m-th clock signal line and an n-th clock signal line, the m-th clock signal line is electrically connected to the clock terminal of the m-th stage second scan driving unit; the n-th clock signal line is electrically connected to the clock terminal of the n-th stage second scan driving unit;

[0132] The method for controlling the on-time of the data writing transistor M11 in the first pixel driving circuit 101 to be shorter than the on-time of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0133] The duration of the effective level transmitted by the m-th type clock signal line is controlled to be shorter than the duration of the effective level transmitted by the n-th type clock signal line.

[0134] Optionally, the above control V N11 >V N12 methods, including:

[0135] The on-state current of the data writing transistor M11 in the first pixel driving circuit 101 is controlled to be smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102 .

[0136] Exemplarily, the data writing transistor M11 in the first pixel driving circuit 101 and the second pixel driving circuit 102 includes a P-type transistor; the method for controlling the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 to be smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0137] Controlling the effective level output by the second scanning driving unit 220 electrically connected to the first pixel driving circuit 101 to be greater than the effective level output by the second scanning driving unit 220 electrically connected to the second pixel driving circuit 102;

[0138] Alternatively, in an embodiment of the present invention, the data writing transistors M11 in the first pixel driving circuit 101 and the second pixel driving circuit 102 may both be configured to include N-type transistors. The method of controlling the on-state current of the data writing transistor M11 in the first pixel driving circuit 101 to be smaller than the on-state current of the data writing transistor M11 in the second pixel driving circuit 102 includes:

[0139] The effective level output by the second scan driving unit 220 electrically connected to the first pixel driving circuit 101 is controlled to be lower than the effective level output by the second scan driving unit 220 electrically connected to the second pixel driving circuit 102 .

[0140] The B cascaded second scan driving units 220 in the same second scan driving unit group 20 mentioned above include an m-th level second scan driving unit 220 and an n-th level second scan driving unit 220, the output end of the m-th level second scan driving unit 220 is electrically connected to the data write control end S1 of the first pixel driving circuit 101, and the output end of the n-th level second scan driving unit 220 is electrically connected to the data write control end S1 of the second pixel driving circuit 102; the second scan driving unit 220 includes a clock end CK1; the display panel also includes an m-th clock signal line and an n-th clock signal line, the m-th clock signal line is electrically connected to the clock end CK1 of the m-th level second scan driving unit 220; the n-th clock signal line is electrically connected to the clock end CK1 of the n-th level second scan driving unit 220.

[0141] Exemplarily, an embodiment of the present invention can set the data writing transistor M1 in the first pixel driving circuit 101 and the second pixel driving circuit 102 to include a P-type transistor; the above-mentioned method of controlling the effective level output by the second scanning driving unit 220 electrically connected to the first pixel driving circuit 101 to be greater than the effective level output by the second scanning driving unit 220 electrically connected to the second pixel driving circuit 102 includes: controlling the effective level transmitted by the mth type clock signal line to be greater than the effective level transmitted by the nth type clock signal line.

[0142] Exemplarily, an embodiment of the present invention may also set the data writing transistors M11 in the above-mentioned first pixel driving circuit 101 and the second pixel driving circuit 102 to include N-type transistors; the above-mentioned method of controlling the effective level output by the second scanning driving unit 220 electrically connected to the first pixel driving circuit 101 to be less than the effective level output by the second scanning driving unit 220 electrically connected to the second pixel driving circuit 102 includes: controlling the effective level transmitted by the mth type clock signal line to be less than the effective level transmitted by the nth type clock signal line.

[0143] The embodiment of the present invention further provides a method for driving a display panel, such as Figure 20 As shown, Figure 20 A schematic diagram of another display panel driving method provided in an embodiment of the present invention, the driving method comprising:

[0144] During the display time of one frame, the data writing period TW_101 of the first pixel driving circuit 101 is controlled to be before the data writing period TW_102 of the second pixel driving circuit 102; and when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period TW_101 of the first pixel driving circuit 101 is controlled, the leakage current speed of the first node in the first pixel driving circuit 101 is v N11 After the data writing period TW_102 of the second pixel driving circuit 102, the leakage current speed of the first node in the second pixel driving circuit 102 is v N12 , v N11 <v N12 .

[0145] The driving method of the display panel provided by the embodiment of the present invention is that when the first pixel driving circuit 101 and the second pixel driving circuit 102 receive the same data voltage, after the data writing period of the first pixel driving circuit 101 and the second pixel driving circuit 102, that is, when the data writing transistors M11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 are turned off, the embodiment of the present invention sets v N11 <v N12, which can compensate for or even eliminate the difference in leakage duration between the first node N11 of the first pixel driving circuit 101 and the first node N11 of the second pixel driving circuit 102. After entering the light-emitting stage, the potentials of the first node N11 of the first pixel driving circuit 101 and the second pixel driving circuit 102 can be made consistent, which is beneficial to improving the brightness consistency of the light-emitting element 200 driven by the two.

[0146] Combine Figure 16 As shown, the display panel further includes a light-emitting driving circuit 23, which includes a plurality of cascaded light-emitting driving unit groups 30, and the light-emitting driving unit group 30 includes B cascaded light-emitting driving units 230. Figure 17 As shown, the light-emitting driving unit 230 includes a second level terminal VGH2; the display panel also includes a Class B second level signal line. The Class B second level signal lines are respectively electrically connected to the second level terminal VGH2 of the Class B light-emitting driving units 230 in the same light-emitting driving unit group 30. The levels transmitted by these Class B second level signal lines are different from each other. According to the data writing order of the corresponding connected pixel driving circuits, the voltage of the level transmitted by the above-mentioned Class M second level signal lines gradually decreases. Taking the example that the Class B light-emitting driving unit 230 in the same light-emitting driving unit group 30 includes at least the p-th level light-emitting driving unit and the q-th level light-emitting driving unit, the output end of the p-th level light-emitting driving unit is electrically connected to the light-emitting control end of the first pixel driving circuit, and the output end of the q-th level light-emitting driving unit is electrically connected to the light-emitting control end of the second pixel driving circuit; p and q are both integers, and 1≤p<q≤B. Correspondingly, the Class B second-level signal line includes at least a p-th class second-level signal line and a q-th class second-level signal line, the p-th class second-level signal line is electrically connected to the second-level end of the p-th level light-emitting driving unit; the q-th class second-level signal line is electrically connected to the second-level end of the q-th level light-emitting driving unit.

[0147] For example, the above control v N11 <v N12 The method includes controlling the voltage of the p-th type second-level signal line to be greater than the voltage of the q-th type second-level signal line.

[0148] The embodiment of the present invention further provides a display device, such as Figure 21 As shown, Figure 21 Schematic diagram of a display device provided by an embodiment of the present invention, the display device includes the above-mentioned display panel 1000. The specific structure of the display panel 1000 has been described in detail in the above embodiment and will not be repeated here. Figure 21 The display device shown is for illustrative purposes only. The display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: A plurality of pixel groups, each pixel group comprising B pixel rows, B≥2, and B is an integer; each pixel row comprises a plurality of pixel driving circuits, each pixel driving circuit comprises a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor is electrically connected to a first node, and a first electrode of each driving transistor is electrically connected to a second node; A first scan driving unit, electrically connected to a plurality of the first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level, and the first scanning driving unit provides a valid level to the first scanning control terminal; The plurality of pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit, and within the display time of one frame of picture, a data writing period of the first pixel driving circuit is before a data writing period of the second pixel driving circuit; The display panel further comprises a second scan driving circuit, wherein the second scan driving circuit comprises a plurality of cascaded second scan driving unit groups, and the second scan driving unit group comprises B cascaded second scan driving units; The B second scan driving units in the same second scan driving unit group include at least an m-th level second scan driving unit and an n-th level second scan driving unit, where m and n are both integers, and 1≤m<n≤B; an output end of the m-th level second scan driving unit is electrically connected to the data writing control end of the first pixel driving circuit, and an output end of the n-th level second scan driving unit is electrically connected to the data writing control end of the second pixel driving circuit; The second scan driving unit includes a clock terminal; the display panel also includes a B-type clock signal line, the B-type clock signal line includes at least an m-th clock signal line and an n-th clock signal line, and the m-th clock signal line is electrically connected to the clock terminal of the m-th level second scan driving unit; The n-th type clock signal line is electrically connected to the clock terminal of the n-th level second scanning driving unit; The pulse width of the effective level transmitted by the m-th type clock signal line is smaller than the pulse width of the effective level transmitted by the n-th type clock signal line; Alternatively, the second scanning driving unit includes a first output transistor, which is used to electrically connect a clock terminal and an output terminal of the second scanning driving unit; the width-to-length ratio of the channel of the first output transistor of the second scanning driving unit electrically connected to the first pixel driving circuit is W11 / L11, and the width-to-length ratio of the channel of the first output transistor of the second scanning driving unit electrically connected to the second pixel driving circuit is W21 / L21, and W11 / L11<W21 / L21.

2. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes a data writing transistor, a control electrode of the data writing transistor is electrically connected to the data writing control terminal, a first electrode of the data writing transistor is electrically connected to the data voltage terminal, and a second electrode of the data writing transistor is electrically connected to the second node; During a display time of one frame, a turn-on time of the data writing transistor in the first pixel driving circuit is shorter than a turn-on time of the data writing transistor in the second pixel driving circuit.

3. The display panel according to claim 1, characterized in that: An on-state current of the data writing transistor in the first pixel driving circuit is smaller than an on-state current of the data writing transistor in the second pixel driving circuit.

4. The display panel according to claim 3, characterized in that: The display panel further includes a second scan driving circuit, the second scan driving circuit includes a plurality of cascaded second scan driving unit groups, the second scan driving unit group includes B cascaded second scan driving units; the second scan driving unit is electrically connected to the data writing control terminal of the pixel driving circuit; The data writing transistor comprises a P-type transistor; the effective level output by the second scanning driving unit electrically connected to the first pixel driving circuit is greater than the effective level output by the second scanning driving unit electrically connected to the second pixel driving circuit; or, The data writing transistor comprises an N-type transistor; the effective level outputted by the second scanning driving unit electrically connected to the first pixel driving circuit is lower than the effective level outputted by the second scanning driving unit electrically connected to the second pixel driving circuit.

5. The display panel according to claim 4, characterized in that: The B second scan driving units in the same second scan driving unit group include at least an m-th level second scan driving unit and an n-th level second scan driving unit, the output end of the m-th level second scan driving unit is electrically connected to the data writing control end of the first pixel driving circuit, and the output end of the n-th level second scan driving unit is electrically connected to the data writing control end of the second pixel driving circuit; m and n are both integers, and 1≤m<n≤B; The second scan driving unit includes a clock terminal; the display panel also includes a B-type clock signal line, the B-type clock signal line includes at least an m-th clock signal line and an n-th clock signal line, and the m-th clock signal line is electrically connected to the clock terminal of the m-th level second scan driving unit; The n-th type clock signal line is electrically connected to the clock terminal of the n-th level second scanning driving unit; The data writing transistor comprises a P-type transistor; the effective level transmitted by the m-th type clock signal line is greater than the effective level transmitted by the n-th type clock signal line; or, The data writing transistor comprises an N-type transistor; The effective level transmitted by the m-th type clock signal line is smaller than the effective level transmitted by the n-th type clock signal line.

6. The display panel according to claim 5, characterized in that: The second scan driving unit further includes a first level end; the display panel further includes a B-type first level signal line, the B-type first level signal line includes at least an m-th type first level signal line and an n-th type first level signal line, and the m-th type first level signal line is electrically connected to the first level end of the m-th level second scan driving unit; The n-th type first level signal line is electrically connected to the first level end of the n-th level second scanning driving unit; The data writing transistor comprises a P-type transistor; the level transmitted by the m-th type first level signal line is greater than the level transmitted by the n-th type first level signal line; or, The data writing transistor comprises an N-type transistor; The level transmitted by the m-th type first level signal line is lower than the level transmitted by the n-th type first level signal line.

7. A display panel, characterized in that: include: A plurality of pixel groups, each pixel group comprising B pixel rows, B≥2, and B is an integer; each pixel row comprises a plurality of pixel driving circuits, each pixel driving circuit comprises a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor is electrically connected to a first node, and a first electrode of each driving transistor is electrically connected to a second node; A first scan driving unit, electrically connected to a plurality of the first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level and the first scanning driving unit provides a valid level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit, and within the display time of a frame of picture, the data writing period of the first pixel driving circuit is located before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage speed of the first node in the first pixel driving circuit is v N11 , the leakage current speed of the first node in the second pixel driving circuit is v N12 , v N11 <v N12 .

8. The display panel according to claim 7, characterized in that: The pixel driving circuit further comprises a light emitting control transistor, wherein a control electrode of the light emitting control transistor is electrically connected to a light emitting control terminal, a first electrode of the light emitting control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the light emitting control transistor is electrically connected to a light emitting element; The width-to-length ratio of the channel of the light emitting control transistor in the first pixel driving circuit is W12 / L12, and the width-to-length ratio of the channel of the light emitting control transistor in the second pixel driving circuit is W22 / L22, W12 / L12<W22 / L22.

9. The display panel according to claim 7, characterized in that: The pixel driving circuit further comprises a first light emitting control transistor, wherein a control electrode of the first light emitting control transistor is electrically connected to a light emitting control terminal, a first electrode of the first light emitting control transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the light emitting control transistor is electrically connected to a light emitting element; The first light emission control transistor includes a plurality of sub-transistors connected in series, and the number of the sub-transistors in the first pixel driving circuit is greater than the number of the sub-transistors in the second pixel driving circuit.

10. The display panel according to claim 7, characterized in that: The display panel further includes a light-emitting driving circuit, the light-emitting driving circuit includes a plurality of cascaded light-emitting driving unit groups, the light-emitting driving unit group includes B cascaded light-emitting driving units; the B light-emitting driving units in the same light-emitting driving unit group include at least a p-th level light-emitting driving unit and a q-th level light-emitting driving unit, the output end of the p-th level light-emitting driving unit is electrically connected to the light-emitting control end of the first pixel driving circuit, and the output end of the q-th level light-emitting driving unit is electrically connected to the light-emitting control end of the second pixel driving circuit; p and q are both integers, and 1≤p<q≤B; The light-emitting driving unit includes a second level end; the display panel also includes a B-type second level signal line, the B-type second level signal line includes at least a p-th type second level signal line and a q-th type second level signal line, and the p-th type second level signal line is electrically connected to the second level end of the p-th level light-emitting driving unit; The qth type second level signal line is electrically connected to the second level end of the qth level light emitting driving unit; The voltage of the p-th type second level signal line is greater than the voltage of the q-th type second level signal line.

11. A method for driving a display panel, characterized in that: The display panel comprises: A plurality of pixel groups, each pixel group comprising B pixel rows, B≥2, and B is an integer; each pixel row comprises a plurality of pixel driving circuits, each pixel driving circuit comprises a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor is electrically connected to a first node, and a first electrode of each driving transistor is electrically connected to a second node; A first scan driving unit, electrically connected to a plurality of the first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level and the first scanning driving unit provides a valid level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit; The driving method comprises: During the display time of one frame of picture, controlling the data writing period of the first pixel driving circuit to be before the data writing period of the second pixel driving circuit; The display panel further comprises a second scan driving circuit, wherein the second scan driving circuit comprises a plurality of cascaded second scan driving unit groups, and the second scan driving unit group comprises B cascaded second scan driving units; The B second scan driving units in the same second scan driving unit group at least include an m-th level second scan driving unit and an n-th level second scan driving unit, m and n are both integers, and 1≤m<n≤B; the output end of the m-th level second scan driving unit is electrically connected to the data writing control end of the first pixel driving circuit, and the output end of the n-th level second scan driving unit is electrically connected to the data writing control end of the second pixel driving circuit; the second scan driving unit includes a clock end; the display panel also includes a B-type clock signal line, the B-type clock signal line includes at least an m-th type clock signal line and an n-th type clock signal line, the m-th type clock signal line is electrically connected to the clock end of the m-th level second scan driving unit; the n-th type clock signal line is electrically connected to the clock end of the n-th level second scan driving unit; the pulse width of the effective level transmitted by the m-th type clock signal line is smaller than the pulse width of the effective level transmitted by the n-th type clock signal line; Alternatively, the second scanning driving unit includes a first output transistor, which is used to electrically connect a clock terminal and an output terminal of the second scanning driving unit; the width-to-length ratio of the channel of the first output transistor of the second scanning driving unit electrically connected to the first pixel driving circuit is W11 / L11, and the width-to-length ratio of the channel of the first output transistor of the second scanning driving unit electrically connected to the second pixel driving circuit is W21 / L21, and W11 / L11<W21 / L21.

12. The driving method according to claim 11, characterized in that: The pixel driving circuit further includes a data writing transistor, a control electrode of the data writing transistor is electrically connected to the data writing control terminal, a first electrode of the data writing transistor is electrically connected to the data voltage terminal, and a second electrode of the data writing transistor is electrically connected to the second node; Control V N11 >V N12 The methods include: The conduction time of the data writing transistor in the first pixel driving circuit is controlled to be shorter than the conduction time of the data writing transistor in the second pixel driving circuit.

13. The driving method according to claim 11, characterized in that: Control V N11 >V N12 The methods include: The on-state current of the data writing transistor in the first pixel driving circuit is controlled to be smaller than the on-state current of the data writing transistor in the second pixel driving circuit.

14. The driving method according to claim 13, characterized in that: The display panel further comprises a second scan driving circuit, wherein the second scan driving circuit comprises a plurality of cascaded second scan driving unit groups, and the second scan driving unit group comprises B cascaded second scan driving units; The data writing transistor comprises a P-type transistor; and the method for controlling the on-state current of the data writing transistor in the first pixel driving circuit to be smaller than the on-state current of the data writing transistor in the second pixel driving circuit comprises: Controlling the effective level output by the second scanning driving unit electrically connected to the first pixel driving circuit to be greater than the effective level output by the second scanning driving unit electrically connected to the second pixel driving circuit; Alternatively, the data writing transistor includes an N-type transistor; and the method of controlling the on-state current of the data writing transistor in the first pixel driving circuit to be smaller than the on-state current of the data writing transistor in the second pixel driving circuit includes: The effective level output by the second scanning driving unit electrically connected to the first pixel driving circuit is controlled to be lower than the effective level output by the second scanning driving unit electrically connected to the second pixel driving circuit.

15. The driving method according to claim 13, characterized in that: The B second scan driving units in the same second scan driving unit group include at least an m-th level second scan driving unit and an n-th level second scan driving unit, the output end of the m-th level second scan driving unit is electrically connected to the data writing control end of the first pixel driving circuit, and the output end of the n-th level second scan driving unit is electrically connected to the data writing control end of the second pixel driving circuit; m and n are both integers, and 1≤m<n≤B; The second scan driving unit includes a clock terminal; the display panel also includes a B-type clock signal line, the B-type clock signal line includes at least an m-th clock signal line and an n-th clock signal line, and the m-th clock signal line is electrically connected to the clock terminal of the m-th level second scan driving unit; The n-th type clock signal line is electrically connected to the clock terminal of the n-th level second scanning driving unit; The data writing transistor includes a P-type transistor; and the method for controlling the effective level output by the second scanning driving unit electrically connected to the first pixel driving circuit to be greater than the effective level output by the second scanning driving unit electrically connected to the second pixel driving circuit comprises: Controlling the effective level transmitted by the m-th type clock signal line to be greater than the effective level transmitted by the n-th type clock signal line; The data writing transistor includes an N-type transistor; and the method of controlling the effective level output by the second scanning driving unit electrically connected to the first pixel driving circuit to be less than the effective level output by the second scanning driving unit electrically connected to the second pixel driving circuit comprises: The effective level transmitted by the m-th clock signal line is controlled to be smaller than the effective level transmitted by the n-th clock signal line.

16. A method for driving a display panel, characterized in that: The display panel comprises: A plurality of pixel groups, each pixel group comprising B pixel rows, B≥2, and B is an integer; each pixel row comprises a plurality of pixel driving circuits, each pixel driving circuit comprises a driving transistor, a data writing control terminal, and a first scanning control terminal; a control electrode of each driving transistor is electrically connected to a first node, and a first electrode of each driving transistor is electrically connected to a second node; A first scan driving unit, electrically connected to a plurality of the first scan control terminals in the same pixel group; The working cycle of the pixel driving circuit includes a data writing period, during which the data writing control terminal receives a valid level and the first scanning driving unit provides a valid level; the multiple pixel driving circuits in the same pixel group include a first pixel driving circuit and a second pixel driving circuit; The driving method comprises: During the display time of one frame, the data writing period of the first pixel driving circuit is controlled to be before the data writing period of the second pixel driving circuit; and when the first pixel driving circuit and the second pixel driving circuit receive the same data voltage, after the data writing period, the leakage current speed of the first node in the first pixel driving circuit is controlled to be v N11 , the leakage current speed of the first node in the second pixel driving circuit is v N12 , v N11 <v N12 .

17. The driving method according to claim 16, characterized in that: The display panel further includes a light-emitting driving circuit, the light-emitting driving circuit includes a plurality of cascaded light-emitting driving unit groups, the light-emitting driving unit group includes B cascaded light-emitting driving units; the B light-emitting driving units in the same light-emitting driving unit group include at least a p-th level light-emitting driving unit and a q-th level light-emitting driving unit, the output end of the p-th level light-emitting driving unit is electrically connected to the light-emitting control end of the first pixel driving circuit, and the output end of the q-th level light-emitting driving unit is electrically connected to the light-emitting control end data writing control end of the second pixel driving circuit; p and q are both integers, and 1≤p<q≤B; The light-emitting driving unit includes a second level end; the display panel also includes a B-type second level signal line, the B-type second level signal line includes at least a p-th type second level signal line and a q-th type second level signal line, and the p-th type second level signal line is electrically connected to the second level end of the p-th level light-emitting driving unit; The qth type second level signal line is electrically connected to the second level end of the qth level light emitting driving unit; Control N11 <v N12 The methods include: The voltage of the p-th type second level signal line is controlled to be greater than the voltage of the q-th type second level signal line.

18. A display device, characterized in that: A display panel comprising any one of claims 1 to 10.

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